JP5392985B2 - 半導体装置及びその動作制御方法 - Google Patents
半導体装置及びその動作制御方法 Download PDFInfo
- Publication number
- JP5392985B2 JP5392985B2 JP2006550539A JP2006550539A JP5392985B2 JP 5392985 B2 JP5392985 B2 JP 5392985B2 JP 2006550539 A JP2006550539 A JP 2006550539A JP 2006550539 A JP2006550539 A JP 2006550539A JP 5392985 B2 JP5392985 B2 JP 5392985B2
- Authority
- JP
- Japan
- Prior art keywords
- inversion
- gate
- voltage
- inversion gate
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 74
- 238000000034 method Methods 0.000 title claims description 12
- 230000015654 memory Effects 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 41
- 239000000872 buffer Substances 0.000 claims description 21
- 230000000694 effects Effects 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 239000003795 chemical substances by application Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0491—Virtual ground arrays
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Description
Claims (17)
- 半導体基板と、
ワード線と、
グローバルビット線と、
前記半導体基板にローカルビット線となる反転層を形成して該反転層を前記グローバルビット線に電気的に接続する反転ゲートであって、ソースとなる反転層を形成する第1の反転ゲートと、ドレインとなる反転層を形成する第2の反転ゲートと、該第1の反転ゲートと該第2の反転ゲート間に設けられた第3の反転ゲートとを含む反転ゲートと、
書込み時、前記第1乃至第3の反転ゲートに所定の電圧を供給して、書込みを行うメモリセルを選択する選択回路と、
前記第1、第2及び第3の反転ゲートと前記半導体基板とを覆い、窒化膜が絶縁膜を構成するONO膜と、
隣接する前記反転ゲート間に形成され、前記反転層をソース及びドレインとして用い、前記反転ゲート間の絶縁膜の両端に1ビットづつ記憶させることによって1セル当たり2ビットを記憶するメモリセルと、
を備える、半導体装置。 - 前記選択回路は、書込み時、前記第3の反転ゲートに、前記半導体基板中のソース及びドレイン間に形成されるチャネル領域のうち前記第3の反転ゲート下のチャネル領域を小さく形成するための電圧を供給する、請求項1に記載の半導体装置。
- 前記反転ゲートは更に、前記第1の反転ゲートから見て前記第3の反転ゲートとは反対側の位置に設けられた第4の反転ゲートを含み、
前記選択回路は、書込み時、前記第4の反転ゲートに前記半導体基板中に形成されるチャネルをカットするための電圧を供給する、請求項1に記載の半導体装置。 - 書込み時、前記反転層に書込み電圧を供給する書込電圧供給回路を更に含む、請求項1から請求項3のいずれか一項に記載の半導体装置。
- 消去時、前記メモリセルに注入された電子をFNトンネル効果を用いて前記半導体基板側に引き抜くための電圧を前記ワード線に供給する電圧供給回路を更に含む、請求項1に記載の半導体装置。
- 消去時、前記メモリセルに注入された電子をFNトンネル効果を用いて前記ワード線側に引き抜くための電圧を前記ワード線に供給する電圧供給回路を更に含む、請求項1に記載の半導体装置。
- 消去時、前記メモリセルに注入された電子をFNトンネル効果を用いて引き抜くための電圧を前記反転ゲートに供給する電圧供給回路を更に含む、請求項1に記載の半導体装置。
- 複数本の前記グローバルビット線からなるコラムセットを複数有し、共通の選択信号によって該コラムセット内の所定のグローバルビット線をそれぞれに対応するページバッファに接続するデコーダを更に含む、請求項1に記載の半導体装置。
- 前記反転層は、複数のメモリセルで共有される、請求項1に記載の半導体装置。
- 前記メモリセルは、SONOS型である、請求項1から請求項9のいずれか一項に記載の半導体装置。
- 前記半導体装置は、半導体記憶装置である、請求項1から請求項10のいずれか一項に記載の半導体装置。
- 半導体基板とワード線とグローバルビット線とを備える半導体装置に書き込みを行う方法であって、
反転ゲートに所定の電圧を供給してローカルビット線となる反転層を半導体基板に形成することにより該反転層をグローバルビット線に電気的に接続する第1のステップであって、該反転ゲートが、ソースとなる反転層を形成する第1の反転ゲートと、ドレインとなる反転層を形成する第2の反転ゲートと、該第1の反転ゲートと該第2の反転ゲート間に設けられた第3の反転ゲートとを含む、第1のステップと、
ワード線を選択する第2のステップと、
前記第3の反転ゲートの両端にある窒化膜にプログラム動作を行なうことによりメモリセルに書き込む第3のステップとを備え、
前記窒化膜は、前記第1、第2及び第3の反転ゲートと前記半導体基板とを覆うONO膜の中間層であり、前記窒化膜の両端に1ビットずつ記憶する、方法。 - 前記第1のステップは、前記第3の反転ゲートに、前記半導体基板中のソース及びドレイン間に形成されるチャネル領域のうち前記第3の反転ゲート下のチャネル領域を小さく形成するための電圧を供給するステップを含む、請求項12に記載の方法。
- 前記反転ゲートは更に、前記第1の反転ゲートから見て第3の反転ゲートとは反対の位置に設けられた第4の反転ゲートを含み、
前記第1のステップは、書込み時、前記半導体基板に形成されるチャネルをカットするための電圧を前記第4の反転ゲートに供給するステップを更に含む、請求項12に記載の方法。 - 書込み時、前記第3の反転ゲートの両端の前記窒化膜で構成される絶縁膜に1ビットづつ記憶させるステップを更に含む、請求項12に記載の方法。
- 書込み時、前記グローバルビット線を介して、書込み電圧を前記反転層に供給するステップを更に含む、請求項12から請求項15のいずれか一項に記載の方法。
- 消去時、メモリセルに注入された電子をFNトンネル効果を用いて前記半導体基板側に引き抜くための電圧を前記ワード線に供給するステップを更に含む、請求項12に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/019645 WO2006070473A1 (ja) | 2004-12-28 | 2004-12-28 | 半導体装置及びその動作制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006070473A1 JPWO2006070473A1 (ja) | 2008-06-12 |
JP5392985B2 true JP5392985B2 (ja) | 2014-01-22 |
Family
ID=36614600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006550539A Expired - Fee Related JP5392985B2 (ja) | 2004-12-28 | 2004-12-28 | 半導体装置及びその動作制御方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7321511B2 (ja) |
EP (1) | EP1833091A4 (ja) |
JP (1) | JP5392985B2 (ja) |
CN (1) | CN101091252B (ja) |
TW (1) | TWI420649B (ja) |
WO (1) | WO2006070473A1 (ja) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
JP2007281137A (ja) * | 2006-04-05 | 2007-10-25 | Sharp Corp | 不揮発性半導体記憶装置およびその製造方法、前記不揮発性半導体記憶装置を備えてなる携帯電子機器 |
US7838920B2 (en) * | 2006-12-04 | 2010-11-23 | Micron Technology, Inc. | Trench memory structures and operation |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
KR101749351B1 (ko) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8363491B2 (en) * | 2011-01-28 | 2013-01-29 | Freescale Semiconductor, Inc. | Programming a non-volatile memory |
WO2017151628A1 (en) * | 2016-02-29 | 2017-09-08 | Washington University | Self-powered sensors for long-term monitoring |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156275A (ja) * | 1999-09-17 | 2001-06-08 | Hitachi Ltd | 半導体集積回路 |
JP2004152977A (ja) * | 2002-10-30 | 2004-05-27 | Renesas Technology Corp | 半導体記憶装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4422791C2 (de) * | 1993-06-29 | 2001-11-29 | Toshiba Kawasaki Kk | Halbleitervorrichtungen mit einem eine Inversionsschicht in einem Oberflächenbereich eines Halbleitersubstrats induzierenden leitenden Film |
WO1998047151A1 (en) * | 1997-04-11 | 1998-10-22 | Programmable Silicon Solutions | Electrically erasable nonvolatile memory |
JPH11110967A (ja) * | 1997-10-01 | 1999-04-23 | Nec Corp | 半導体メモリ装置 |
JPH11328957A (ja) * | 1998-05-19 | 1999-11-30 | Oki Micro Design:Kk | 半導体記憶装置 |
US7190023B2 (en) * | 1999-09-17 | 2007-03-13 | Renesas Technology Corp. | Semiconductor integrated circuit having discrete trap type memory cells |
US6809949B2 (en) * | 2002-05-06 | 2004-10-26 | Symetrix Corporation | Ferroelectric memory |
JP2005056889A (ja) * | 2003-08-04 | 2005-03-03 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP2005191542A (ja) * | 2003-12-01 | 2005-07-14 | Renesas Technology Corp | 半導体記憶装置 |
JP2006060030A (ja) * | 2004-08-20 | 2006-03-02 | Renesas Technology Corp | 半導体記憶装置 |
US7158420B2 (en) * | 2005-04-29 | 2007-01-02 | Macronix International Co., Ltd. | Inversion bit line, charge trapping non-volatile memory and method of operating same |
-
2004
- 2004-12-28 JP JP2006550539A patent/JP5392985B2/ja not_active Expired - Fee Related
- 2004-12-28 WO PCT/JP2004/019645 patent/WO2006070473A1/ja active Application Filing
- 2004-12-28 EP EP04808000A patent/EP1833091A4/en not_active Withdrawn
- 2004-12-28 CN CN2004800447293A patent/CN101091252B/zh not_active Expired - Fee Related
-
2005
- 2005-12-22 US US11/316,800 patent/US7321511B2/en not_active Expired - Fee Related
- 2005-12-27 TW TW094146638A patent/TWI420649B/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156275A (ja) * | 1999-09-17 | 2001-06-08 | Hitachi Ltd | 半導体集積回路 |
JP2004152977A (ja) * | 2002-10-30 | 2004-05-27 | Renesas Technology Corp | 半導体記憶装置 |
Non-Patent Citations (2)
Title |
---|
JPN6011034861; H.Kurata, et al: 'Self-Boosted Charge Injection for 90-nm-Node 4-Gb Multilevel AG-AND Flash Memories Programmable at 1' 2004 Symposium on VLSI Circuits Digest of Technical Papers , 20040617, p.72-73 * |
JPN6011034864; Y. Sasago, et al: '90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming thro' IEDM 2003 , 20031208, 34.2.1-34.2.4 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006070473A1 (ja) | 2006-07-06 |
EP1833091A4 (en) | 2008-08-13 |
CN101091252A (zh) | 2007-12-19 |
EP1833091A1 (en) | 2007-09-12 |
JPWO2006070473A1 (ja) | 2008-06-12 |
CN101091252B (zh) | 2012-09-05 |
US20060256617A1 (en) | 2006-11-16 |
TW200636974A (en) | 2006-10-16 |
TWI420649B (zh) | 2013-12-21 |
US7321511B2 (en) | 2008-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5392985B2 (ja) | 半導体装置及びその動作制御方法 | |
JP4791868B2 (ja) | Fin−NAND型フラッシュメモリ | |
US8045385B2 (en) | Methods of operating nonvolatile memory devices to inhibit parasitic charge accumulation therein | |
KR100960352B1 (ko) | 선 소거 단계를 이용하여 플래시 메모리를 소거하는 방법 | |
US6567305B2 (en) | Semiconductor memory device in which source line potential is controlled in accordance with data programming mode | |
JP3625383B2 (ja) | 不揮発性半導体メモリ装置 | |
JP4709867B2 (ja) | 半導体記憶装置 | |
JP3584494B2 (ja) | 半導体不揮発性記憶装置 | |
KR100746292B1 (ko) | 비휘발성 메모리 장치 | |
KR100639827B1 (ko) | Eeprom 응용을 위한 1 트랜지스터 셀 | |
US6760254B2 (en) | Semiconductor memory device | |
WO2006059375A1 (ja) | 半導体装置および半導体装置の制御方法 | |
JP3843869B2 (ja) | 不揮発性半導体記憶装置 | |
JP2004199738A (ja) | 不揮発性記憶装置 | |
JP4545056B2 (ja) | 不揮発性半導体記憶装置 | |
JP3871049B2 (ja) | 不揮発性半導体記憶装置 | |
JP3985689B2 (ja) | 不揮発性半導体記憶装置 | |
JP3692664B2 (ja) | 不揮発性半導体記憶装置 | |
JP7297977B1 (ja) | フラッシュメモリ | |
WO2004109806A1 (ja) | 不揮発性半導体メモリ | |
JPH06325582A (ja) | 不揮発性記憶装置 | |
KR20070086719A (ko) | 반도체 장치 및 그 동작 제어 방법 | |
JP2011216169A (ja) | 半導体メモリ | |
JP4382168B2 (ja) | ベリファイ機能を有する不揮発性記憶装置 | |
JP2002208287A (ja) | 不揮発性半導体記憶装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100204 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100616 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100805 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20100922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110705 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111004 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111012 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111102 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111129 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120228 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120306 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120328 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120404 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120426 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120508 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120528 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120626 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20120830 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121026 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20121207 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20130208 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130906 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131015 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5392985 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |