TWI420649B - 半導體裝置及控制其操作之方法 - Google Patents

半導體裝置及控制其操作之方法 Download PDF

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Publication number
TWI420649B
TWI420649B TW094146638A TW94146638A TWI420649B TW I420649 B TWI420649 B TW I420649B TW 094146638 A TW094146638 A TW 094146638A TW 94146638 A TW94146638 A TW 94146638A TW I420649 B TWI420649 B TW I420649B
Authority
TW
Taiwan
Prior art keywords
reverse gate
inversion layer
bit line
semiconductor substrate
voltage
Prior art date
Application number
TW094146638A
Other languages
English (en)
Chinese (zh)
Other versions
TW200636974A (en
Inventor
Masaru Yano
Hideki Arakawa
Hidehiko Shiraiwa
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc filed Critical Spansion Llc
Publication of TW200636974A publication Critical patent/TW200636974A/zh
Application granted granted Critical
Publication of TWI420649B publication Critical patent/TWI420649B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
TW094146638A 2004-12-28 2005-12-27 半導體裝置及控制其操作之方法 TWI420649B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2004/019645 WO2006070473A1 (ja) 2004-12-28 2004-12-28 半導体装置及びその動作制御方法

Publications (2)

Publication Number Publication Date
TW200636974A TW200636974A (en) 2006-10-16
TWI420649B true TWI420649B (zh) 2013-12-21

Family

ID=36614600

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094146638A TWI420649B (zh) 2004-12-28 2005-12-27 半導體裝置及控制其操作之方法

Country Status (6)

Country Link
US (1) US7321511B2 (ja)
EP (1) EP1833091A4 (ja)
JP (1) JP5392985B2 (ja)
CN (1) CN101091252B (ja)
TW (1) TWI420649B (ja)
WO (1) WO2006070473A1 (ja)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
JP2007281137A (ja) * 2006-04-05 2007-10-25 Sharp Corp 不揮発性半導体記憶装置およびその製造方法、前記不揮発性半導体記憶装置を備えてなる携帯電子機器
US7838920B2 (en) * 2006-12-04 2010-11-23 Micron Technology, Inc. Trench memory structures and operation
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8363491B2 (en) * 2011-01-28 2013-01-29 Freescale Semiconductor, Inc. Programming a non-volatile memory
US11041764B2 (en) * 2016-02-29 2021-06-22 Washington University Self-powered sensors for long-term monitoring

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW409250B (en) * 1997-10-01 2000-10-21 Nippon Electric Co A semiconductor memory device
TW411465B (en) * 1998-05-19 2000-11-11 Oki Micro Design Kk Semiconductor memory device
US6531735B1 (en) * 1999-09-17 2003-03-11 Hitachi, Ltd. Semiconductor integrated circuit
TW200400509A (en) * 2002-05-06 2004-01-01 Symetrix Corp Ferroelectric memory

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Publication number Priority date Publication date Assignee Title
KR0167874B1 (ko) * 1993-06-29 1999-01-15 사토 후미오 반도체 기억장치
KR20010006135A (ko) * 1997-04-11 2001-01-26 프로그래머블 실리콘 솔루션즈 전기적 소거가능 비휘발성 메모리
US7190023B2 (en) * 1999-09-17 2007-03-13 Renesas Technology Corp. Semiconductor integrated circuit having discrete trap type memory cells
JP2004152977A (ja) * 2002-10-30 2004-05-27 Renesas Technology Corp 半導体記憶装置
JP2005056889A (ja) * 2003-08-04 2005-03-03 Renesas Technology Corp 半導体記憶装置およびその製造方法
JP2005191542A (ja) * 2003-12-01 2005-07-14 Renesas Technology Corp 半導体記憶装置
JP2006060030A (ja) * 2004-08-20 2006-03-02 Renesas Technology Corp 半導体記憶装置
US7158420B2 (en) * 2005-04-29 2007-01-02 Macronix International Co., Ltd. Inversion bit line, charge trapping non-volatile memory and method of operating same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW409250B (en) * 1997-10-01 2000-10-21 Nippon Electric Co A semiconductor memory device
TW411465B (en) * 1998-05-19 2000-11-11 Oki Micro Design Kk Semiconductor memory device
US6531735B1 (en) * 1999-09-17 2003-03-11 Hitachi, Ltd. Semiconductor integrated circuit
TW200400509A (en) * 2002-05-06 2004-01-01 Symetrix Corp Ferroelectric memory

Also Published As

Publication number Publication date
CN101091252A (zh) 2007-12-19
EP1833091A1 (en) 2007-09-12
WO2006070473A1 (ja) 2006-07-06
JPWO2006070473A1 (ja) 2008-06-12
US7321511B2 (en) 2008-01-22
CN101091252B (zh) 2012-09-05
JP5392985B2 (ja) 2014-01-22
TW200636974A (en) 2006-10-16
EP1833091A4 (en) 2008-08-13
US20060256617A1 (en) 2006-11-16

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