US20160225652A1 - Low temperature chuck for plasma processing systems - Google Patents

Low temperature chuck for plasma processing systems Download PDF

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Publication number
US20160225652A1
US20160225652A1 US14/612,857 US201514612857A US2016225652A1 US 20160225652 A1 US20160225652 A1 US 20160225652A1 US 201514612857 A US201514612857 A US 201514612857A US 2016225652 A1 US2016225652 A1 US 2016225652A1
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US
United States
Prior art keywords
wafer
puck
top surface
chuck
chuck assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/612,857
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English (en)
Inventor
Toan Q. Tran
Zilu Weng
Dmitry Lubomirsky
Satoru Kobayashi
Tae Seung Cho
Soonam Park
Son M. Phi
Shankar Venkataraman
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Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to US14/612,857 priority Critical patent/US20160225652A1/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOBAYASHI, SATORU, PHI, SON M., WENG, ZILU, CHO, TAE SEUNG, LUBOMIRSKY, DMITRY, PARK, SOONAM, TRAN, TOAN Q., VENKATARAMAN, SHANKAR
Priority to TW105101391A priority patent/TWI726860B/zh
Priority to KR1020177024655A priority patent/KR102553118B1/ko
Priority to CN201680008395.7A priority patent/CN107533945B/zh
Priority to JP2017540697A priority patent/JP6710217B2/ja
Priority to PCT/US2016/014106 priority patent/WO2016126425A1/en
Publication of US20160225652A1 publication Critical patent/US20160225652A1/en
Priority to US15/581,497 priority patent/US11594428B2/en
Priority to US18/175,104 priority patent/US12009228B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • H—ELECTRICITY
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68792—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the construction of the shaft
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

Definitions

  • the present disclosure applies broadly to the field of plasma processing equipment. More specifically, systems and methods for providing spatially uniform plasma processing on a workpiece are disclosed.
  • wafers Integrated circuits and other semiconductor products are often fabricated on surfaces of substrates called “wafers.” Sometimes processing is performed on groups of wafers held in a carrier, while other times processing and testing are performed on one wafer at a time. When single wafer processing or testing is performed, the wafer may be positioned on a wafer chuck. Other workpieces may also be processed on similar chucks.
  • a wafer chuck assembly includes a puck, a shaft and a base.
  • the puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material.
  • the puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element.
  • the shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes.
  • the base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.
  • a method of plasma processing includes stabilizing temperature of a chuck by a heat exchange fluid through an inner puck element of the chuck, the chuck having an electrically insulating top surface in thermal communication with the inner puck element, loading a workpiece onto the chuck, and providing a DC voltage differential across two spatially separated electrodes within the electrically insulating top surface, to clamp the workpiece to the chuck.
  • the method further includes providing process gases in a chamber surrounding the chuck, and providing an RF voltage between a conductive plate beneath the chuck, and one or more walls of the chamber, to ignite a plasma from the process gases.
  • FIG. 1 schematically illustrates major elements of a wafer processing system, according to an embodiment.
  • FIG. 2 is a schematic illustration of a wafer chuck shown in FIG. 1 , showing exemplary component parts thereof, according to an embodiment.
  • FIG. 3 is a schematic illustration of a plasma wafer processing system including a wafer chuck, showing exemplary component parts thereof, according to an embodiment.
  • FIG. 4 is a schematic illustration of part of the plasma wafer processing system of FIG. 3 , including portions of a wafer chuck and a diffuser therein, and illustrating exemplary power supply connections thereto.
  • FIG. 5 illustrates a portion of a wafer in process, according to an embodiment.
  • FIG. 6 illustrates a hypothetical result when the wafer portion of FIG. 5 is exposed to a plasma that does not steer ions.
  • FIG. 7 illustrates the result when the wafer of FIG. 5 is exposed to a plasma that steers ions, according to an embodiment.
  • Embodiments herein provide new and useful functionality for wafer processing systems.
  • Semiconductor wafer sizes have increased while feature sizes have decreased significantly over the years, so that more integrated circuits with greater functionality can be harvested per wafer processed.
  • Typical wafer diameters increased from about 2 or 3 inches in the 1970s to 12 inches or more in the 2010s.
  • typical minimum feature sizes of commercial integrated circuits decreased from about 5 microns to about 0.015 microns. Processing smaller features while wafers grow larger requires significant improvements in processing uniformity. Because chemical reaction rates are often temperature sensitive, point to point temperature control across wafers during processing is becoming more important.
  • chucks for holding “wafers” should be understood as equivalent to “chucks” for holding “workpieces” of any sort, and “wafer processing systems” as similarly equivalent to “processing systems.”
  • FIG. 1 schematically illustrates major elements of a wafer processing system 100 .
  • System 100 is depicted as a single wafer, semiconductor wafer processing system, but it will be apparent to one skilled in the art that the techniques and principles herein are applicable to plasma processing systems of any type (e.g., systems that process workpieces of other types, not necessarily semiconductors or wafers).
  • FIG. 1 is a diagram that only schematically illustrates selected, major elements of system 100 ; an actual processing system will accordingly look different and likely contain additional elements as compared with system 100 .
  • Wafer processing system 100 is serviced by one or more utilities such as process fluid(s) 10 , external power 20 , vacuum 30 and heat exchange fluid(s) 35 .
  • Wafer processing system 100 includes a housing 110 and a wafer interface 115 that receives wafers 50 from external sources and positions them within a processing location 160 .
  • Wafer processing system 100 may also include a user interface 145 , and a controller 135 that typically includes a microprocessor, memory and the like, may take input from user interface 145 and/or other sources, and provides computer based control over the hardware elements of wafer processing system 100 .
  • Controller 135 may interface with external networks and/or computers over one or more data links 40 that may be physical (wires or optical connectors) or wireless connections.
  • Wafer processing system 100 may also include one or more internal power supplies 150 that transform or condition power supplied by external power 20 for use by the hardware elements of the system.
  • Processing location 160 receives each wafer 50 onto a wafer chuck 170 that, in embodiments, includes three portions: a puck 175 , a shaft 180 that supports puck 175 , and a base 185 that supports shaft 180 .
  • Wafer 50 is physically positioned on, and in embodiments is heated, cooled and/or mechanically held by, puck 175 .
  • Wafer chuck 170 is also configured to couple radio frequency (RF) and/or direct current (DC) voltages to wafer 50 , for electrostatic clamping of wafer 50 to puck 175 , for generating a plasma within processing location 160 and/or for directing reactive ions from the plasma to wafer 50 .
  • RF radio frequency
  • DC direct current
  • Processing location 160 thus exposes wafer 50 to “plasma products,” defined herein as any material that is, or has at one time been, part of a plasma.
  • Plasma products may include any or all of ions, radicals, molecular fragments of source gases, other activated species, and/or source gas atoms or molecules that were part of a plasma but were not transformed into ions, radicals and so forth. Gases that have not formed part of a plasma at any time are defined herein as “unactivated gases.”
  • Puck 175 and/or shaft 180 are also, in embodiments, configured to manipulate wafer 50 for access to wafer handling tools.
  • shaft 180 may raise puck 175 for a wafer 50 to be received thereon, and subsequently lower puck 175 to another height for processing, or the reverse.
  • puck 175 and/or shaft 180 may include actuators that raise or lower wafer 50 relative to a top surface of puck 175 , such as lift pins that can extend from or retract within puck 175 , such that a wafer tool may be inserted between wafer 50 and the top surface.
  • Shaft 180 may also facilitate electrical and/or fluid connections with puck 175 .
  • Base 185 mechanically anchors shaft 180 within housing 110 and, in embodiments, provides interfaces for electrical utilities and/or fluids to shaft 180 .
  • Portions of base 185 , shaft 180 and puck 175 , or any combination thereof, may be formed monolithically with one another, or may be assembled partially or completely from component parts, as further described below.
  • FIG. 2 is a schematic illustration of wafer chuck 170 , showing exemplary component parts thereof.
  • FIG. 2 is not drawn to scale, certain components of wafer chuck 170 are exaggerated or diminished in size, not every instance of each component is labeled, and not all internal connections among components are shown, for illustrative clarity.
  • Regions of wafer chuck 170 are identified as puck 175 , shaft 180 and base 185 , as per FIG. 1 , although certain components of wafer chuck 170 may overlap two or more of these regions.
  • Puck 175 includes an insulating top 205 in which are embedded electrodes 210 .
  • Top 205 may be formed of ceramic or other electrically insulating material; for example, in embodiments, top 205 is formed of aluminum nitride or alumina. Electrodes 210 may be formed of conductive and/or resistive materials that can withstand moderate to high temperatures, such as tungsten oxide, for example.
  • An optional channel 207 within top 205 brings a heat transfer gas such as helium into contact with a backside of wafer 50 to improve heat transfer between top 205 and wafer 50 .
  • the improved heat transfer can help in cases where a wafer is not perfectly flat, and thus is not in uniform contact with the top surface of top 205 , and/or to improve thermal uniformity from the range of a few degrees point-to-point on a wafer, to the range of one degree or less.
  • Optional channels 208 interconnect with channel 207 and with one another within a top surface of top 205 , so that the heat transfer gas can spread between the bottom surface of wafer 50 and top 205 until the gas passes an outer edge of wafer 50 .
  • An electrically conductive plate 220 that may be formed of metal, for example, of aluminum or alloys thereof, is disposed beneath top 205 .
  • Plate 220 supports an inner puck element 212 in which one or more heat exchange channels 215 are defined.
  • Heat exchange channels 215 may, for example, be defined in a spiral configuration within inner puck element 212 .
  • Heat exchange channels 215 may define internal fins 218 , as shown, to improve thermal coupling between heat exchange fluid 35 (see FIG. 1 ) flowing within channels 215 , and inner puck element 212 .
  • Connective element 214 is advantageously formed of a material that has both high thermal conductivity and reasonably high ductility, to accommodate mechanical stresses and/or thermal expansion mismatch with adjacent components during temperature changes.
  • fabrication of connective element 214 is advantageously fabricated of aluminum silicon carbide (AlSiC), which features high thermal conductivity and at least higher ductility than puck inner element 212 and top 205 .
  • AlSiC aluminum silicon carbide
  • Connective element 214 may fasten to plate 220 using bolts 219 , as shown.
  • top 205 is held in place over connective element 214 with a ring 211 , made for example of ceramic.
  • Ring 211 may be press-fit over top 205 and about connective element 214 , as shown, to provide mechanical stability and good thermal coupling, while not fastening ring 211 and/or top 205 rigidly with connective element 214 or plate 220 . Attaching top 205 in this manner advantageously accommodates slight thermal expansion mismatches among top 205 , ring 211 and connective element 214 during heating or cooling.
  • Ring 211 also protects bolts 219 from exposure to plasma and/or plasma products outside chuck 170 .
  • an electrically conductive shaft housing 222 is below top 205 and forms a housing for shaft 180 .
  • Shaft housing 222 may also be made, for example, of aluminum; plate 220 and shaft housing 222 are electrically coupled and may be integrally formed, as shown in FIG. 2 , or assembled by fastening or joining component parts.
  • Shaft housing 222 houses an optional insulating liner 225 , made for example of a ceramic material such as AlN or Al 2 O 3 , that helps keep internal components from shorting or arcing to shaft housing 222 .
  • Insulating liner 225 may be integrally formed with inner puck element 212 , as shown in FIG. 2 , or may be formed separately therefrom.
  • Interior surfaces of insulating liner 225 may, optionally, be flushed with inert gases such as helium or nitrogen to remove heat or to dilute and remove process gases that may enter the chuck surface as wafers are transferred to and from chuck 170 .
  • inert gases such as helium or nitrogen to remove heat or to dilute and remove process gases that may enter the chuck surface as wafers are transferred to and from chuck 170 .
  • Shaft 180 also houses a variety of connectors 230 between power supplies and other facilities of equipment in which chuck 170 is located, and features of puck 175 .
  • Exemplary connectors 230 shown in FIG. 2 include radio-frequency/direct current (RF/DC) connectors 230 ( 1 ), 230 ( 2 ); a heat exchange fluid inlet and outlet 230 ( 3 ), 230 ( 4 ); a probe center-tap terminal 230 ( 5 ); and a thermocouple (TC) or resistance temperature detector (RTD) wire 230 ( 6 ) (e.g., a two-element wire, shown schematically as a single connector in FIG. 2 ).
  • RF/DC radio-frequency/direct current
  • TC thermocouple
  • RTD resistance temperature detector
  • Other connectors 230 are possible, in embodiments.
  • Connectors 230 may be single or twisted pair wires, rods, coaxial or other connectors, insulated or uninsulated wires, or fluid conduits.
  • radio-frequency/direct current (RF/DC) connectors 230 ( 1 ), 230 ( 2 ) include an inner conductor, an insulating layer about the inner conductor, a ground tube about the insulating layer, and a ceramic tube about the ground tube.
  • Connectors 230 that are fluid conduits may be integrally formed with puck and/or base elements, such as heat exchange fluid inlet and outlet 230 ( 3 ), 230 ( 4 ) integrally formed with inner puck element 212 , as shown in FIG. 2 .
  • TCs or RTDs may be implemented in any number and may optionally be organized for sensitivity to temperature variations caused by temperature and flow rate of heat exchange fluid 35 , heating by plasma or plasma products, heating or cooling caused by interaction with flowing gases or plasma products, or other causes.
  • characterization of chuck 170 may lead to a determination that temperature is uniform across a given configuration of chuck 170 , such that a single TC or RTD accurately represents the temperature of chuck 170 .
  • multiple TCs or RTDs can be used to monitor temperature uniformity across chuck 170 , providing information that can be used to automatically and/or manually adjust operation of heat exchange fluids 35 or other aspects of a plasma processing system in which chuck 170 is located, to promote temperature uniformity.
  • Connectors 230 may also be fluid conduits. Additionally, or instead of connectors 230 being configured as fluid conduits, shaft housing 222 , insulating liner 225 and/or spaces among or between them may be configured with fluid passages. For example, a backside gas source 285 supplies He or other inert gas to channel 207 , for improved thermal control across wafer 50 .
  • heat exchange fluid(s) 35 to heat and/or cool puck 175 simplifies thermal management of chuck 170 , and a wafer 50 processed thereon, in a relatively low temperature regime, such as the range of about 20 C to 150 C.
  • an external heat exchanger may be set to provide a heating/cooling fluid such as a mixture of 50% water, 50% ethylene or propylene glycol at the desired chuck temperature.
  • Puck 175 is provided with a high thermal mass that wafer 50 loaded onto puck 175 rapidly comes into thermal equilibrium with puck 175 at the desired temperature; inclusion of a connective element 214 formed of AlSiC helps to provide the high thermal mass.
  • Thermal conductivity of puck 175 and flow rate of the heat exchange fluid are great enough that puck 175 and wafer 50 remain at the desired temperature despite heating and/or cooling effects of plasma generation, gas flows within processing location 160 , and the like.
  • connectors 230 in FIG. 2 are schematic only; connectors 230 may, and usually will, be arranged differently for purposes such as minimizing size of shaft 180 , maximizing space between adjacent connectors 230 , improving temperature uniformity and/or heat dissipation, and other reasons.
  • Base 185 of chuck 170 includes an electrically conductive base housing 270 that may be made of metal (for example, of aluminum) and may be may be integrally formed with shaft housing 222 or assembled to it by fasteners, welding or the like.
  • base housing 270 includes an electrically insulating terminal block 275 through which connectors 230 pass.
  • Terminal block 275 serves to align connectors 230 - 265 such that their respective distal ends are arranged to mate with corresponding sockets within puck 175 .
  • Terminal block 275 may be formed of an insulator such as polyether ether ketone (PEEK) or ceramic, which both provide good electrical resistance and stability at high temperatures.
  • PEEK polyether ether ketone
  • Base housing 270 may include channels such as channel 280 therein for heat exchange fluid 35 ( FIG. 1 ), as shown.
  • Heat exchange fluid 35 passing through channel 280 may be either a gas or a liquid.
  • heat exchange fluid 35 passed through channel 280 is a mixture of water and ethylene glycol or propylene glycol, having a mix ratio of approximately 50% water, 50% glycol.
  • cooling provided through channel 280 cools not only base housing 270 , but also shaft housing 222 and conductive plate 220 mechanically connected therewith.
  • Base 185 may be fixed within an associated piece of wafer processing equipment, or may be movably mounted using slides, hinges, stages or other devices to position puck 175 to send or receive a wafer or other workpiece, and/or to align the wafer or workpiece as needed.
  • FIG. 3 is a schematic illustration of a plasma wafer processing system 300 including wafer chuck 170 , showing exemplary component parts thereof.
  • FIG. 3 is not drawn to scale, certain components of plasma wafer processing system 300 are exaggerated or diminished in size, not every instance of each component is labeled, and not all internal connections among components are shown, for illustrative clarity.
  • Plasma wafer processing system 300 is an example of wafer processing system 100 , FIG. 1 .
  • Plasma wafer processing system 300 processes a wafer 50 within a process chamber 305 using plasma products and/or unactivated gases;
  • FIG. 3 shows flows of plasma products as open arrows and of unactivated gases as solid arrows.
  • An optional remote plasma source 310 generates a first plasma (not shown) from a first input gas stream 10 ( 1 ) and optionally mixes resulting plasma products with a second input gas stream 10 ( 2 ), passing the plasma products toward a diffuser 320 .
  • the plasma products may pass through further, optional diffusers 320 , 325 and 340 that serve at least to distribute the plasma products uniformly before they are introduced into process chamber 305 .
  • a first power supply 150 ( 1 ) provides RF energy across a space 330 between diffusers 325 and 340 , forming a second plasma 335 in space 330 .
  • Plasma products from the first and second plasmas may optionally mix with a further input gas stream 10 ( 3 ) through a further diffuser 350 (sometimes referred to as a “showerhead”).
  • Diffuser 350 is configured with large ports for passing the plasma products therethrough, and gas passages 360 that transmit input gas stream 10 ( 3 ) through only the side of diffuser 350 that faces process chamber 305 . It will be appreciated that the use of any or all of remote plasma source 310 and diffusers 320 , 325 , 340 and 350 is optional.
  • a second power supply 150 ( 2 ) is controllably configured to provide RF energy and/or DC bias to electrodes 210 ( 1 ) and 210 ( 2 ) within chuck 170 , through connectors 230 ( 1 ) and 230 ( 2 ), as schematically shown, and to other parts of processing system 300 .
  • Specific connections of the RF energy and/or DC bias may vary, as discussed further below.
  • Power supply 150 ( 2 ) may provide, for example, DC bias across electrodes 210 ( 1 ) and 210 ( 2 ), and may provide RF energy and/or DC bias between electrodes 210 ( 1 ) and 210 ( 2 ) and other parts of processing system 300 , as indicated by connection 151 between power supply 150 ( 2 ) and diffuser 350 .
  • Providing both RF energy and DC bias is especially useful for both electrostatically clamping wafer 50 (or any other workpiece) to chuck 170 , for generating a plasma within process chamber 305 , and for directing ions of the plasma to certain processing sites on wafer 50 , as discussed further below.
  • Typical DC clamping voltages are ⁇ 200V delivered to opposite electrodes 210 ( 1 ) and 210 ( 2 ), while typical RF voltages are ⁇ 75V across process chamber 305 , corresponding to power delivery of about 100-500 W to the plasma.
  • a portion of processing system 300 is shown in greater detail in FIG. 4 .
  • FIG. 4 is a schematic illustration of part of plasma wafer processing system 300 including portions of wafer chuck 170 and diffuser 350 , and illustrating exemplary power supply connections thereto.
  • FIG. 4 is not drawn to scale, certain components of plasma wafer processing system 300 are exaggerated or diminished in size, not every instance of each component is labeled, and not all internal connections among components are shown, for illustrative clarity.
  • FIG. 4 shows a portion of process chamber 305 bounded by respective portions of diffuser 350 and chuck 170 , wafer 50 , a plasma 355 within process chamber 305 , and exemplary details of power supply 150 ( 2 ).
  • Plasma 355 is generated from gas streams 10 ( 1 ), 10 ( 2 ) and/or 10 ( 3 ), either in their original, unactivated forms, or as plasma products formed in remote plasma source 310 or within space 330 ( FIG. 3 ).
  • RF energy for forming plasma 355 is supplied by RF source 390 within power supply 150 ( 2 ).
  • power supply 150 ( 2 ) also provides a DC bias 370 across electrodes 210 ( 1 ) and 210 ( 2 ), that serves to electrostatically clamp wafer 50 to wafer chuck 170 .
  • DC electric fields are shown in FIG. 4 with dotted arrows.
  • the embodiment shown in FIG. 4 also includes an optional DC bias 380 between electrodes 210 and diffuser 350 .
  • DC bias 380 can steer ions formed in plasma 355 (or existing in plasma products from other locations, as discussed above) toward wafer 50 to influence directionality of plasma processing on wafer 50 (see FIG. 5 ).
  • FIG. 4 also shows a center tap DC probe 395 that can be monitored to determine the actual backside DC voltage of wafer 50 .
  • Voltage measured on DC probe 395 can be measured and used to control DC bias 380 , in order to control and optimize process results on wafer 50 .
  • reactive species within the plasma products are often negatively charged ions, which can transfer negative charge to wafer 50 when they react. This leads to charging of wafer 50 ; a typical DC voltage acquired by wafer 50 during processing may be about ⁇ 50V.
  • Center tap DC probe 395 allows this voltage to be sensed and thus compensated by adjusting DC bias 380 accordingly.
  • DC probe 395 couples with a high impedance circuit 398 that measures the voltage on DC probe 395 and provides appropriate information for power supply 150 ( 2 ) to adjust DC bias 380 .
  • All of the components of, and integrated with, wafer chuck 170 are compatible with operation in a temperature range of about 20 C to 150 C, in contrast to earlier systems that may utilize materials that are not compatible with the 20 C to 150 C temperature range, such as certain polymers or plastics, rubber, and the like.
  • the components that are exposed to plasma are also capable of surviving very harsh plasma environments, such as H* or F* radicals, and others, produced when NH 3 or NF 3 respectively are utilized as source gases.
  • O 2 is also commonly added as a source gas (to supply electrons, facilitating plasma initiation) creating further ionic species and radicals.
  • Earlier systems often used stainless steel chucks, but stainless generally corrodes in such environments, causing particulate contamination.
  • wafer chuck 170 within processing system 300 is unique in that it allows for processing to take place at a uniform temperature while also providing firm electrostatic clamping for heat transfer, and the ability to steer reactive ionic species toward the workpiece, without corrosion or thermal degradation.
  • embodiments herein are capable of plasma etching of certain metallic and/or ceramic materials on wafer 50 .
  • FIGS. 5, 6 and 7 illustrate exemplary processing results obtainable with the wafer chucks and wafer processing systems described herein.
  • FIG. 5 illustrates a portion of a wafer 50 ( 1 ) in process. Wafer 50 ( 1 ) has already been processed to form deep trenches 410 therein, and a film 400 ( 1 ) has been deposited on both top surfaces of wafer 50 ( 1 ) and in trenches 410 . Subsequent processing is intended to remove film 400 ( 1 ) from certain regions of wafer 50 ( 1 ) but leave film 400 ( 1 ) on other regions; photoresist 420 is therefore provided in the regions where film 400 ( 1 ) is to remain.
  • FIG. 6 illustrates a hypothetical result when wafer 50 ( 1 ) is exposed to a plasma that does not steer ions, for example by exposing wafer 50 ( 1 ) to a plasma where reactive species are simply directed randomly by diffusion. Surfaces of film 400 ( 1 ) that are readily exposed to the reactive species are etched, while wafer 50 ( 1 ) does not react with the reactive species. This process leaves the resulting wafer 50 ( 2 ) with film 400 ( 4 ) protected by photoresist 420 , but also leaving residual material 400 ( 3 ) within trenches 410 . This occurs because the reactive species simply travel until they meet something, then react where they land. Few reactive species happen to be traveling in the exact direction required to penetrate deeply into trenches 410 . It may or may not be possible, and is usually impractical, to etch wafer 50 ( 1 ) long enough to remove residual material 400 ( 3 ) using randomly directed reactive species.
  • FIG. 7 illustrates the result when wafer 50 ( 1 ) is exposed to a plasma that steers ions by providing an electric field that directs ions toward wafer 50 ( 1 ); that is, as shown in FIGS. 3 and 4 using wafer chuck 170 .
  • the electric field indicated in FIG. 4 directs negatively charged reactive species downward in the orientation of FIG. 7 , such that more of the reactive species reach lower regions of film 400 ( 1 ) within trenches 410 .
  • the resulting wafer 50 ( 3 ) retains film 400 ( 4 ) only in locations where original film 400 ( 1 ) is protected by photoresist 420 , as shown.
  • wafer chucks have often been quite simple affairs ranging from mere slabs of metal to slightly more complicated systems that provide vacuum or electrostatic clamping, adjustable wafer alignment/positioning, and the like. Designs that retain all of these functions and yet operate with precise cross-wafer temperature control in highly corrosive plasma environments without degradation, are not known.

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TW105101391A TWI726860B (zh) 2015-02-03 2016-01-18 用於電漿處理系統的低溫晶圓夾具總成及電漿處理的方法
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CN201680008395.7A CN107533945B (zh) 2015-02-03 2016-01-20 用于等离子体处理系统的低温夹具
JP2017540697A JP6710217B2 (ja) 2015-02-03 2016-01-20 プラズマ処理システム用の低温チャック
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