JP2015149491A - 半導体チップ、定義方法および設計方法 - Google Patents
半導体チップ、定義方法および設計方法 Download PDFInfo
- Publication number
- JP2015149491A JP2015149491A JP2015059324A JP2015059324A JP2015149491A JP 2015149491 A JP2015149491 A JP 2015149491A JP 2015059324 A JP2015059324 A JP 2015059324A JP 2015059324 A JP2015059324 A JP 2015059324A JP 2015149491 A JP2015149491 A JP 2015149491A
- Authority
- JP
- Japan
- Prior art keywords
- dynamic array
- das
- array section
- manufacturing
- shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 101
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000013461 design Methods 0.000 title description 63
- 238000004519 manufacturing process Methods 0.000 claims abstract description 190
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 189
- 230000002411 adverse Effects 0.000 claims abstract description 28
- 230000002093 peripheral effect Effects 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims description 377
- 238000003491 array Methods 0.000 claims description 16
- 239000011295 pitch Substances 0.000 description 149
- 239000002184 metal Substances 0.000 description 115
- 238000009792 diffusion process Methods 0.000 description 105
- 238000010586 diagram Methods 0.000 description 83
- 239000000758 substrate Substances 0.000 description 59
- 230000006870 function Effects 0.000 description 36
- 230000008569 process Effects 0.000 description 34
- 230000003993 interaction Effects 0.000 description 33
- 230000002787 reinforcement Effects 0.000 description 23
- 230000011218 segmentation Effects 0.000 description 22
- 230000003287 optical effect Effects 0.000 description 18
- 238000000926 separation method Methods 0.000 description 18
- 230000008859 change Effects 0.000 description 16
- 238000001459 lithography Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 9
- 238000005457 optimization Methods 0.000 description 9
- 101150067325 DAS1 gene Proteins 0.000 description 8
- 101100516268 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NDT80 gene Proteins 0.000 description 8
- 238000012937 correction Methods 0.000 description 8
- 230000001066 destructive effect Effects 0.000 description 8
- 238000005192 partition Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000003014 reinforcing effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 101100008874 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DAS2 gene Proteins 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007792 addition Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000010363 phase shift Effects 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000003335 Production assurance Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000037237 body shape Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 102100022117 Abnormal spindle-like microcephaly-associated protein Human genes 0.000 description 1
- 101000900939 Homo sapiens Abnormal spindle-like microcephaly-associated protein Proteins 0.000 description 1
- ZPCCSZFPOXBNDL-ZSTSFXQOSA-N [(4r,5s,6s,7r,9r,10r,11e,13e,16r)-6-[(2s,3r,4r,5s,6r)-5-[(2s,4r,5s,6s)-4,5-dihydroxy-4,6-dimethyloxan-2-yl]oxy-4-(dimethylamino)-3-hydroxy-6-methyloxan-2-yl]oxy-10-[(2r,5s,6r)-5-(dimethylamino)-6-methyloxan-2-yl]oxy-5-methoxy-9,16-dimethyl-2-oxo-7-(2-oxoe Chemical compound O([C@H]1/C=C/C=C/C[C@@H](C)OC(=O)C[C@H]([C@@H]([C@H]([C@@H](CC=O)C[C@H]1C)O[C@H]1[C@@H]([C@H]([C@H](O[C@@H]2O[C@@H](C)[C@H](O)[C@](C)(O)C2)[C@@H](C)O1)N(C)C)O)OC)OC(C)=O)[C@H]1CC[C@H](N(C)C)[C@@H](C)O1 ZPCCSZFPOXBNDL-ZSTSFXQOSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005923 long-lasting effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11811—Basic cell P to N transistor count
- H01L2027/1182—8-T CMOS basic cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11859—Connectibility characteristics, i.e. diffusion and polysilicon geometries
- H01L2027/11866—Gate electrode terminals or contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11883—Levels of metallisation
- H01L2027/11888—More than 3 levels of metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
【解決手段】ダイナミックアレイ・セクションの周辺境界を定義するステップ3101と、ダイナミックアレイ・セクションの境界外側に製造保証ハロを定義するステップ3103と、製造保証ハロ内のチップ・レイアウト形状によってダイナミックアレイ・セクションの境界内側に導電体形状を製造するステップが悪影響を受けないことを確実にするように、製造保証ハロ内のチップ・レイアウト形状をコントロールするステップ3105と、を備える。
【選択図】図31
Description
ある。
拡散コンタクトの中心のx座標=I*0.36μm,ここでIはグリッド番号;
ゲート電極形状の中心のx座標=0.18μm+I*0.36μm,
ここでIはグリッド番号。
・少なくとも2つのメタル1トラックがnチャンネルデバイス領域を横切って設けられる;
・少なくとも2つのメタル1トラックがpチャンネルデバイス領域を横切って設けられる;
・少なくとも2つのゲート電極トラックがnチャンネルデバイスに設けられる;及び
・少なくとも2つのゲート電極トラックがpチャンネルデバイスに設けられる。
式1は、あるDAS実施形態における第3の配線レベルの仮想格子と第1の配線レベルの仮想格子間の関係を定義しているが、その他のDAS実施形態では、第3の配線レベルの仮想格子と第1の配線レベルの仮想格子間で異なる関係を用いてもよいことは認識されるべきである。特定の実施形態にかかわらず、ピッチと配列の観点からの特定の間隔関係は、第3の配線レベルの仮想格子と第1の配線レベルの仮想格子間に存在することは理解されるべき点である。
一実施形態では、多くの製造保証ハロ・セグメントを、同じ製造適合性識別子を有する1つまたは複数の周辺のダイナミックアレイ・セクションの多くの製造保証ハロ・セグメントから分離し、これによって、選択されたダイナミックアレイ・セクションと1つまたは複数の周辺のダイナミックアレイ・セクションとの間にスペースを設けるように、選択されたダイナミックアレイ・セクションをチップの一部のレイアウト内に配置することによって、操作3203が行われる。さらに、この実施形態の例では、ダイナミックアレイ・セクションに関連しないチップ・レイアウト形状は、選択されたダイナミックアレイ・セクションと1つまたは複数の周辺のダイナミックアレイ・セクションとの間のスペース内に定義される。
Claims (20)
- ダイナミックアレイ・セクションの周辺境界を定義するステップと、
前記ダイナミックアレイ・セクションの境界外側に製造保証ハロを定義するステップと、
前記製造保証ハロ内のチップ・レイアウト形状によって前記ダイナミックアレイ・セクションの境界内側に導電体形状を製造するステップが悪影響を受けないことを確実にするように、前記製造保証ハロ内のチップ・レイアウト形状をコントロールするステップと、
を備え、
前記ダイナミックアレイ・セクションの前記周辺境界から垂直方向に離れる前記製造保証ハロの範囲は、前記ダイナミックアレイ・セクションの境界内側に導電体形状を製造するステップに対して前記製造保証ハロの外側に定義された各チップ・レイアウト形状が悪影響を与える能力を有しないことを確実にするように定義される、半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。 - 前記ダイナミックアレイ・セクションの境界内側の導電体形状の多くは、前記製造保証ハロを通って前記ダイナミックアレイ・セクションの境界を越えて延びるように定義される請求項1に記載の半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。
- 前記ダイナミックアレイ・セクションは、前記ダイナミックアレイ・セクションの境界内のチップの複数のレベルによって定義され、
個々の製造保証ハロは、前記ダイナミックアレイ・セクションの前記複数のレベルのそれぞれに対して、独立してそれぞれ定義される請求項1に記載の半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。 - 前記製造保証ハロ内のチップ・レイアウト形状をコントロールするステップは、前記ダイナミックアレイ・セクションに関連しないチップ・レイアウト形状の前記製造保証ハロ内への侵入が前記ダイナミックアレイ・セクションの境界内側に導電体形状を製造するステップに悪影響を与えない場合にのみ許容されるようにして、前記チップ上に前記ダイナミックアレイ・セクションを配置することにより実行される請求項1に記載の半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。
- 前記ダイナミックアレイ・セクションの前記周辺境界は、ダイナミックアレイ・セクション・グリッドのグリッド・ラインと一致するように定義され、
前記製造保証ハロの外周は、前記ダイナミックアレイ・セクション・グリッドのグリッド・ラインと一致する請求項1に記載の半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。 - 前記ダイナミックアレイ・セクションの境界は、境界セグメントの遠回りの配置によって定義され、各境界セグメントは、関連する製造保証ハロ・セグメントを有し、
各製造保証ハロ・セグメントは、製造適合性識別子を割り当てられる請求項1に記載の半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。 - 前記製造保証ハロ内のチップ・レイアウト形状をコントロールステップは、各製造保証ハロ・セグメントが同じ製造適合性識別子を有する隣接したダイナミックアレイ・セクションの製造保証ハロ・セグメントに重なることが許容されるように、かつ、各製造保証ハロ・セグメントが異なる製造適合性識別子を有する隣接したダイナミックアレイ・セクションの製造保証ハロ・セグメントに重なることが許容されないようにして、前記チップ上に前記ダイナミックアレイ・セクションを配置することにより実行される請求項6に記載の半導体チップ上に製造されるべきダイナミックアレイ・セクションの定義方法。
- チップの一部上に定義されるべきダイナミックアレイ・セクションを選択するステップであって、選択されたダイナミックアレイ・セクションが前記選択されたダイナミックアレイ・セクションの境界外側に定義された関連する製造保証ハロを有するステップと、
前記選択されたダイナミックアレイ・セクションの製造可能性に悪影響を与えないように、前記選択されたダイナミックアレイ・セクションに関連せずに前記製造保証ハロ内に含まれるレイアウト形状が前記製造保証ハロに適合するようにして、前記選択されたダイナミックアレイ・セクションを前記チップの一部のレイアウト内に配置するステップと、
を備え、
前記選択されたダイナミックアレイ・セクションの境界から垂直方向に離れる前記製造保証ハロの範囲は、前記製造保証ハロの外側で定義された各チップ・レイアウト形状が前記選択されたダイナミックアレイ・セクションの境界内側の導電体形状の製造に悪影響を与える能力を有しないことを確実にするように定義される、一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。 - 前記選択されたダイナミックアレイ・セクションは、前記選択されたダイナミックアレイ・セクションの境界内の前記チップの複数のレベルによって定義され、
個々の製造保証ハロは、前記選択されたダイナミックアレイ・セクションの前記複数のレベルのそれぞれに、独立してそれぞれ関連する請求項8に記載の一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。 - 前記選択されたダイナミックアレイ・セクションは、前記選択されたダイナミックアレイ・セクションの境界が前記チップの一部上に投影されたダイナミックアレイ・セクション・グリッドのグリッド・ラインと一致するようにして配置される請求項8に記載の一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。
- 前記選択されたダイナミックアレイ・セクションの境界は、境界セグメントの遠回りの配置によって定義され、各境界セグメントは、関連する製造保証ハロ・セグメントを有し、
各製造保証ハロ・セグメントは、製造適合性識別子を割り当てられる請求項8に記載の一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。 - 前記選択されたダイナミックアレイ・セクションを前記チップの一部のレイアウト内に配置するステップは、各製造保証ハロ・セグメントが同じ製造適合性識別子を有する隣接したダイナミックアレイ・セクションの製造保証ハロ・セグメントに重なることが許容されるように、かつ、各製造保証ハロ・セグメントが異なる製造適合性識別子を有する隣接したダイナミックアレイ・セクションの製造保証ハロ・セグメントに重なることが許容されないようにして実行される請求項11に記載の一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。
- 前記選択されたダイナミックアレイ・セクションを前記チップの一部のレイアウト内に配置するステップは、多くの製造保証ハロ・セグメントが同じ製造適合性識別子を有する一以上の隣接したダイナミックアレイ・セクションの製造保証ハロの多くから分離され、前記選択されたダイナミックアレイ・セクションと前記一以上の隣接したダイナミックアレイ・セクションとの間にスペースが空くようにして実行される請求項11に記載の一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。
- 前記選択されたダイナミックアレイ・セクションと前記一以上の隣接したダイナミックセクション・アレイとの間のスペース内に、ダイナミックアレイ・セクションに関連しないチップ・レイアウト形状を定義するステップをさらに備える請求項13に記載の一以上の機能的にインターフェースされたダイナミックアレイ・セクションを有する半導体チップの設計方法。
- 周辺境界を有するダイナミックアレイ・セクションであって、前記ダイナミックアレイ・セクションが前記周辺境界内のチップの複数のレベルにより定義され、前記ダイナミックアレイ・セクションが前記チップの複数のレベルのそれぞれ内に定義される多くの線形導電体形状を含み、各線形導電体形状がその線形導電体形状が定義される前記チップのレベルに関連する仮想格子のラインに沿って定義されるダイナミックアレイ・セクションと、
前記ダイナミックアレイ・セクションの周囲に定義される製造保証ハロと、を備え、
前記ダイナミックアレイ・セクション内に定義される前記線形導電体形状の多くが、前記製造保証ハロを通って前記ダイナミックアレイ・セクションの前記周辺境界の外側に延びるように定義され、
前記ダイナミックアレイ・セクションの前記周辺境界から垂直方向に離れる前記製造保証ハロの範囲は、前記ダイナミックアレイ・セクションの前記周辺境界の内側に導電体形状を製造することに対して前記製造保証ハロの外側で定義された各チップ・レイアウト形状が悪影響を与える能力を有しないことを確実にするように定義される半導体チップ。 - 個々の製造保証ハロは、前記ダイナミックアレイ・セクションの前記複数のレベルのそれぞれに対して、独立してそれぞれ定義される請求項15に記載の半導体チップ。
- 前記ダイナミックアレイ・セクションの前記周辺境界の内側に導電体形状を製造することに対して前記製造保証ハロの外側で定義された各チップ・レイアウト形状が悪影響を与える能力を有しないことを確実にするようにして、前記ダイナミックアレイ・セクションの前記周辺境界から垂直方向に離れる前記製造保証ハロの範囲が定義される請求項15に記載の半導体チップ。
- 前記ダイナミックアレイ・セクションの製造可能性に悪影響を与えないように、前記ダイナミックアレイ・セクションに関連せずに前記製造保証ハロ内に含まれるチップレイアウト形状が前記製造保証ハロに適合するようにして、前記ダイナミックアレイ・セクションが前記チップ上に配置される請求項15に記載の半導体チップ。
- 前記ダイナミックアレイ・セクションの前記周辺境界は、境界セグメントの遠回り配置によって定義され、各境界セグメントは関連する製造保証ハロ・セグメントを有し、
各製造保証ハロ・セグメントは、製造適合性識別子を割り当てられる請求項15に記載の半導体チップ。 - 各製造保証ハロ・セグメントが同じ製造適合性識別子を有する隣接したダイナミックアレイ・セクションの製造保証ハロ・セグメントに重なることが許容されるように、かつ、各製造保証ハロ・セグメントが異なる製造適合性識別子を有する隣接したダイナミックアレイ・セクションの製造保証ハロ・セグメントに重なることが許容されないようにして、前記ダイナミックアレイ・セクションが前記チップ上に配置される請求項18に記載の半導体チップ。
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US96336407P | 2007-08-02 | 2007-08-02 | |
US60/963,364 | 2007-08-02 | ||
US97239407P | 2007-09-14 | 2007-09-14 | |
US60/972,394 | 2007-09-14 | ||
US12/013,342 US7917879B2 (en) | 2007-08-02 | 2008-01-11 | Semiconductor device with dynamic array section |
US12/013,356 US7908578B2 (en) | 2007-08-02 | 2008-01-11 | Methods for designing semiconductor device with dynamic array section |
US12/013,366 | 2008-01-11 | ||
US12/013,366 US7888705B2 (en) | 2007-08-02 | 2008-01-11 | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
US12/013,342 | 2008-01-11 | ||
US12/013,356 | 2008-01-11 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012015484A Division JP5758815B2 (ja) | 2007-08-02 | 2012-01-27 | 集積回路デバイス |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016171635A Division JP6289567B2 (ja) | 2007-08-02 | 2016-09-02 | 集積回路デバイス |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015149491A true JP2015149491A (ja) | 2015-08-20 |
JP6093794B2 JP6093794B2 (ja) | 2017-03-08 |
Family
ID=40337325
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010526886A Expired - Fee Related JP4991938B2 (ja) | 2007-08-02 | 2008-07-31 | ダイナミックアレイ・セクションを有する半導体デバイス |
JP2012015484A Expired - Fee Related JP5758815B2 (ja) | 2007-08-02 | 2012-01-27 | 集積回路デバイス |
JP2015059324A Expired - Fee Related JP6093794B2 (ja) | 2007-08-02 | 2015-03-23 | 半導体チップ、定義方法および設計方法 |
JP2016171635A Expired - Fee Related JP6289567B2 (ja) | 2007-08-02 | 2016-09-02 | 集積回路デバイス |
JP2017227099A Pending JP2018050072A (ja) | 2007-08-02 | 2017-11-27 | 集積回路デバイス |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010526886A Expired - Fee Related JP4991938B2 (ja) | 2007-08-02 | 2008-07-31 | ダイナミックアレイ・セクションを有する半導体デバイス |
JP2012015484A Expired - Fee Related JP5758815B2 (ja) | 2007-08-02 | 2012-01-27 | 集積回路デバイス |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016171635A Expired - Fee Related JP6289567B2 (ja) | 2007-08-02 | 2016-09-02 | 集積回路デバイス |
JP2017227099A Pending JP2018050072A (ja) | 2007-08-02 | 2017-11-27 | 集積回路デバイス |
Country Status (5)
Country | Link |
---|---|
US (9) | US7908578B2 (ja) |
EP (1) | EP2186136A4 (ja) |
JP (5) | JP4991938B2 (ja) |
TW (1) | TWI389298B (ja) |
WO (1) | WO2009017828A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019526170A (ja) * | 2016-07-12 | 2019-09-12 | エーティーアイ・テクノロジーズ・ユーエルシーAti Technologies Ulc | セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 |
Families Citing this family (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8286107B2 (en) * | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
KR101749351B1 (ko) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
JP2010061547A (ja) * | 2008-09-05 | 2010-03-18 | Nec Electronics Corp | 半導体デバイス設計支援装置及び基板ネットリスト作成方法 |
JP2010278189A (ja) * | 2009-05-28 | 2010-12-09 | Renesas Electronics Corp | 半導体集積回路の設計方法及び設計システム |
US8495583B2 (en) | 2009-09-11 | 2013-07-23 | International Business Machines Corporation | System and method to determine defect risks in software solutions |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US7969199B1 (en) * | 2010-05-10 | 2011-06-28 | Pdf Solutions, Inc. | Pattern controlled IC layout |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8513978B2 (en) * | 2011-03-30 | 2013-08-20 | Synopsys, Inc. | Power routing in standard cell designs |
US9123562B2 (en) * | 2011-09-19 | 2015-09-01 | Texas Instruments Incorporated | Layout method to minimize context effects and die area |
CN103094251B (zh) * | 2011-10-28 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | 用于评价opc效果的测试结构 |
US8581348B2 (en) | 2011-12-13 | 2013-11-12 | GlobalFoundries, Inc. | Semiconductor device with transistor local interconnects |
US9355910B2 (en) * | 2011-12-13 | 2016-05-31 | GlobalFoundries, Inc. | Semiconductor device with transistor local interconnects |
CN102663147B (zh) * | 2012-02-28 | 2014-02-05 | 上海华力微电子有限公司 | 一种用于铜互连冗余金属图形的插入算法 |
US8533651B1 (en) * | 2012-07-18 | 2013-09-10 | Globalfoundries Inc. | Providing conversion of a planar design to a FinFET design |
US20140040847A1 (en) * | 2012-08-01 | 2014-02-06 | Lsi Corporation | System and method for generating physical deterministic boundary interconnect features for dual patterning technologies |
US9147029B2 (en) * | 2013-03-11 | 2015-09-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stretch dummy cell insertion in FinFET process |
US8869090B2 (en) * | 2013-03-11 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stretch dummy cell insertion in FinFET process |
KR20140128619A (ko) | 2013-04-29 | 2014-11-06 | 에스케이하이닉스 주식회사 | 차동 증폭기를 구비한 반도체 집적 회로 장치 |
US9501600B2 (en) * | 2013-05-02 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cells for predetermined function having different types of layout |
US9245076B2 (en) * | 2013-06-03 | 2016-01-26 | International Business Machines Corporation | Orthogonal circuit element routing |
US9331016B2 (en) * | 2013-07-25 | 2016-05-03 | Qualcomm Incorporated | SOC design with critical technology pitch alignment |
US9141744B2 (en) | 2013-08-15 | 2015-09-22 | United Microelectronics Corp. | Method for generating layout pattern |
TWI588596B (zh) * | 2013-08-15 | 2017-06-21 | 聯華電子股份有限公司 | 產生佈局圖案的方法 |
EP3050085B1 (en) | 2013-09-27 | 2021-02-24 | Intel Corporation | Self-aligned via and plug patterning for back end of line (beol) interconnects |
US9793163B2 (en) | 2013-09-27 | 2017-10-17 | Intel Corporation | Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects |
CN105493249B (zh) * | 2013-09-27 | 2019-06-14 | 英特尔公司 | 用于后段(beol)互连的先前层自对准过孔及插塞图案化 |
US9653413B2 (en) * | 2014-06-18 | 2017-05-16 | Arm Limited | Power grid conductor placement within an integrated circuit |
US9690892B2 (en) * | 2014-07-14 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks based on gate pad layout patterns of standard cell having different gate pad pitches |
CN105719688B (zh) * | 2014-12-04 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | Sram存储器和形成sram存储器的方法 |
US10204920B2 (en) | 2015-04-09 | 2019-02-12 | Samsung Electronics Co., Ltd. | Semiconductor device including polygon-shaped standard cell |
US9690896B2 (en) | 2015-04-09 | 2017-06-27 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor device and semiconductor device manufactured by the same |
US9698056B2 (en) | 2015-04-09 | 2017-07-04 | Samsung Electronics., Ltd. | Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same |
KR102321605B1 (ko) | 2015-04-09 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치의 레이아웃 설계 방법 및 그를 이용한 반도체 장치의 제조 방법 |
US9773772B2 (en) | 2015-04-09 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9640480B2 (en) | 2015-05-27 | 2017-05-02 | Qualcomm Incorporated | Cross-couple in multi-height sequential cells for uni-directional M1 |
KR102483254B1 (ko) | 2016-03-21 | 2022-12-29 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US10275560B2 (en) * | 2016-05-26 | 2019-04-30 | Synopsys, Inc. | Placement of circuit elements in regions with customized placement grids |
FR3053156B1 (fr) * | 2016-06-28 | 2018-11-16 | Stmicroelectronics (Rousset) Sas | Composant a faible dispersion dans une puce electronique |
US10147714B2 (en) * | 2016-10-10 | 2018-12-04 | Globalfoundries Inc. | Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell |
US9837398B1 (en) * | 2016-11-23 | 2017-12-05 | Advanced Micro Devices, Inc. | Metal track cutting in standard cell layouts |
KR102630392B1 (ko) * | 2016-12-06 | 2024-01-29 | 삼성전자주식회사 | 반도체 장치, 반도체 장치의 레이아웃 설계 방법, 및 반도체 장치의 제조 방법 |
US10923425B2 (en) * | 2017-01-20 | 2021-02-16 | Arm Limited | Power distribution |
KR102308779B1 (ko) | 2017-04-10 | 2021-10-05 | 삼성전자주식회사 | 이종 컨택들을 구비하는 집적 회로 및 이를 포함하는 반도체 장치 |
US11347925B2 (en) | 2017-05-01 | 2022-05-31 | Advanced Micro Devices, Inc. | Power grid architecture and optimization with EUV lithography |
US11211330B2 (en) | 2017-05-01 | 2021-12-28 | Advanced Micro Devices, Inc. | Standard cell layout architectures and drawing styles for 5nm and beyond |
US10489548B2 (en) * | 2017-05-26 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit and method for manufacturing the same |
US11334703B2 (en) * | 2017-06-29 | 2022-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit layouts with fill feature shapes |
US11271010B2 (en) * | 2017-09-20 | 2022-03-08 | Intel Corporation | Multi version library cell handling and integrated circuit structures fabricated therefrom |
CN107803230B (zh) * | 2017-11-16 | 2019-10-08 | 北京工业大学 | 不同交汇角度的多层微流控芯片的制作方法 |
US10360337B2 (en) * | 2017-11-22 | 2019-07-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of forming conductive grid of integrated circuit |
US10916498B2 (en) * | 2018-03-28 | 2021-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for logic circuit |
KR102387946B1 (ko) * | 2018-05-21 | 2022-04-18 | 삼성전자주식회사 | 클럽풋 구조의 도전 패턴을 포함하는 집적 회로 |
US10748889B2 (en) | 2018-06-15 | 2020-08-18 | Samsung Electronics Co., Ltd. | Power grid and standard cell co-design structure and methods thereof |
US10769342B2 (en) * | 2018-10-31 | 2020-09-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Pin access hybrid cell height design |
US10796061B1 (en) | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
US20210134783A1 (en) * | 2019-10-30 | 2021-05-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure |
US11901286B2 (en) | 2021-01-28 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diagonal via pattern and method |
US12001772B2 (en) * | 2021-09-24 | 2024-06-04 | International Business Machines Corporation | Ultra-short-height standard cell architecture |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09282349A (ja) * | 1996-04-17 | 1997-10-31 | Shinko Electric Ind Co Ltd | データ変換処理装置 |
JP2001166452A (ja) * | 1999-12-03 | 2001-06-22 | Toshiba Microelectronics Corp | パターンの自動設計方法 |
JP2001351981A (ja) * | 2000-06-06 | 2001-12-21 | Asahi Kasei Microsystems Kk | セルの配置方法およびその配置装置 |
JP2005123537A (ja) * | 2003-10-20 | 2005-05-12 | Sony Corp | 半導体装置及び製造方法 |
JP2007123682A (ja) * | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム |
US20070113216A1 (en) * | 2005-11-14 | 2007-05-17 | Youping Zhang | Photolithographic mask correction |
JP2007141971A (ja) * | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法 |
Family Cites Families (677)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4069493A (en) * | 1970-10-02 | 1978-01-17 | Thomson-Csf | Novel integrated circuit and method of manufacturing same |
US4197555A (en) * | 1975-12-29 | 1980-04-08 | Fujitsu Limited | Semiconductor device |
JPS5746536A (en) | 1980-09-04 | 1982-03-17 | Matsushita Electric Ind Co Ltd | Gate circuit |
US4424460A (en) | 1981-07-14 | 1984-01-03 | Rockwell International Corporation | Apparatus and method for providing a logical exclusive OR/exclusive NOR function |
JPS5943824B2 (ja) | 1982-03-03 | 1984-10-24 | 三菱電機株式会社 | 半導体集積回路装置 |
JPS58182242A (ja) * | 1982-04-19 | 1983-10-25 | Nec Corp | 半導体集積回路装置 |
JPS58182242U (ja) | 1982-05-28 | 1983-12-05 | パイオニア株式会社 | スライドロツク付プツシユボタン |
JPS58215827A (ja) | 1982-06-09 | 1983-12-15 | Toshiba Corp | 論理回路 |
JPS5943548A (ja) | 1982-09-06 | 1984-03-10 | Hitachi Ltd | 半導体集積回路装置 |
US4613940A (en) | 1982-11-09 | 1986-09-23 | International Microelectronic Products | Method and structure for use in designing and building electronic systems in integrated circuits |
JPS6035532A (ja) | 1983-07-29 | 1985-02-23 | Fujitsu Ltd | マスタスライス集積回路装置 |
US4575648A (en) | 1983-12-23 | 1986-03-11 | At&T Bell Laboratories | Complementary field effect transistor EXCLUSIVE OR logic gates |
US5121186A (en) | 1984-06-15 | 1992-06-09 | Hewlett-Packard Company | Integrated circuit device having improved junction connections |
US5545904A (en) * | 1986-01-17 | 1996-08-13 | Quick Technologies Ltd. | Personalizable gate array devices |
JPH0695570B2 (ja) * | 1985-02-07 | 1994-11-24 | 三菱電機株式会社 | 半導体集積回路装置 |
US4657628A (en) | 1985-05-01 | 1987-04-14 | Texas Instruments Incorporated | Process for patterning local interconnects |
US4804636A (en) | 1985-05-01 | 1989-02-14 | Texas Instruments Incorporated | Process for making integrated circuits having titanium nitride triple interconnect |
US4975756A (en) | 1985-05-01 | 1990-12-04 | Texas Instruments Incorporated | SRAM with local interconnect |
JPH0216605Y2 (ja) | 1985-05-02 | 1990-05-08 | ||
US4602270A (en) | 1985-05-17 | 1986-07-22 | United Technologies Corporation | Gate array with reduced isolation |
US5097422A (en) | 1986-10-10 | 1992-03-17 | Cascade Design Automation Corporation | Method and apparatus for designing integrated circuits |
US4745084A (en) | 1986-11-12 | 1988-05-17 | Vlsi Technology, Inc. | Method of making a customized semiconductor integrated device |
US4884115A (en) | 1987-02-27 | 1989-11-28 | Siemens Aktiengesellschaft | Basic cell for a gate array arrangement in CMOS Technology |
US4801986A (en) | 1987-04-03 | 1989-01-31 | General Electric Company | Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method |
JP2742052B2 (ja) | 1987-06-12 | 1998-04-22 | 日本電信電話株式会社 | 相補型misマスタスライス論理集積回路 |
US5119313A (en) | 1987-08-04 | 1992-06-02 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
KR100212098B1 (ko) | 1987-09-19 | 1999-08-02 | 가나이 쓰도무 | 반도체 집적회로 장치 및 그 제조 방법과 반도체 집적 회로 장치의 배선기판 및 그 제조 방법 |
US5068603A (en) | 1987-10-07 | 1991-11-26 | Xilinx, Inc. | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
US4812688A (en) | 1987-12-30 | 1989-03-14 | International Business Machines Corporation | Transistor delay circuits |
JPH01284115A (ja) | 1988-05-11 | 1989-11-15 | Sharp Corp | 論理回路 |
US5268319A (en) | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
JP2617217B2 (ja) * | 1988-11-24 | 1997-06-04 | シャープ株式会社 | 半導体装置の製造方法 |
US4928160A (en) | 1989-01-17 | 1990-05-22 | Ncr Corporation | Gate isolated base cell structure with off-grid gate polysilicon pattern |
JPH02198154A (ja) | 1989-01-27 | 1990-08-06 | Hitachi Ltd | 配線の形成方法及びこれを利用した半導体装置 |
US5224057A (en) | 1989-02-28 | 1993-06-29 | Kabushiki Kaisha Toshiba | Arrangement method for logic cells in semiconductor IC device |
US5351197A (en) | 1989-04-13 | 1994-09-27 | Cascade Design Automation Corporation | Method and apparatus for designing the layout of a subcircuit in an integrated circuit |
JPH03165061A (ja) * | 1989-11-22 | 1991-07-17 | Hitachi Ltd | 半導体集積回路装置 |
US5298774A (en) | 1990-01-11 | 1994-03-29 | Mitsubishi Denki Kabushiki Kaisha | Gate array system semiconductor integrated circuit device |
US5483104A (en) | 1990-01-12 | 1996-01-09 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
KR100199258B1 (ko) | 1990-02-09 | 1999-06-15 | 가나이 쓰도무 | 반도체집적회로장치 |
US6100025A (en) | 1990-04-20 | 2000-08-08 | Cold Spring Harbor Laboratory | Cloning by complementation and related processes |
US5977305A (en) | 1990-04-20 | 1999-11-02 | Cold Spring Harbor Laboratories | Cloning by complementation and related processes |
US5047979A (en) | 1990-06-15 | 1991-09-10 | Integrated Device Technology, Inc. | High density SRAM circuit with ratio independent memory cells |
US5208765A (en) * | 1990-07-20 | 1993-05-04 | Advanced Micro Devices, Inc. | Computer-based method and system for product development |
US5079614A (en) * | 1990-09-26 | 1992-01-07 | S-Mos Systems, Inc. | Gate array architecture with basic cell interleaved gate electrodes |
JP3017789B2 (ja) | 1990-10-18 | 2000-03-13 | 三菱電機株式会社 | 半導体集積回路装置のレイアウト設計方法 |
JP2851447B2 (ja) | 1991-03-08 | 1999-01-27 | 三菱電機株式会社 | 形状シミュレーション方法 |
JPH04350954A (ja) * | 1991-05-28 | 1992-12-04 | Hitachi Ltd | 半導体装置 |
JPH05152937A (ja) | 1991-11-26 | 1993-06-18 | Hitachi Ltd | 論理ゲート回路 |
JP3129336B2 (ja) | 1991-12-09 | 2001-01-29 | 沖電気工業株式会社 | 半導体記憶装置 |
US7071060B1 (en) | 1996-02-28 | 2006-07-04 | Sandisk Corporation | EEPROM with split gate source side infection with sidewall spacers |
US5242770A (en) | 1992-01-16 | 1993-09-07 | Microunity Systems Engineering, Inc. | Mask for photolithography |
JP2760195B2 (ja) | 1992-01-20 | 1998-05-28 | 日本電気株式会社 | 論理回路 |
US5526307A (en) | 1992-01-22 | 1996-06-11 | Macronix International Co., Ltd. | Flash EPROM integrated circuit architecture |
JPH05218362A (ja) | 1992-02-04 | 1993-08-27 | Sharp Corp | ゲートアレイのベーシックセル |
JPH0669470A (ja) * | 1992-08-18 | 1994-03-11 | Mitsubishi Electric Corp | 半導体装置 |
JP2776180B2 (ja) * | 1992-12-18 | 1998-07-16 | 株式会社日立製作所 | 超電導マグネット、超電導マグネットコイル及びその製造方法 |
US5367187A (en) | 1992-12-22 | 1994-11-22 | Quality Semiconductor, Inc. | Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions |
IT1257184B (it) | 1992-12-22 | 1996-01-10 | Applied Research Systems | Preparato ad attivita' antinfiammatoria, anticoagulante e antitumorale |
US5420447A (en) | 1993-01-29 | 1995-05-30 | Sgs-Thomson Microelectronics, Inc. | Double buffer base gate array cell |
US5359226A (en) | 1993-02-02 | 1994-10-25 | Paradigm Technology, Inc. | Static memory with self aligned contacts and split word lines |
US5497334A (en) * | 1993-02-19 | 1996-03-05 | International Business Machines Corporation | Application generator for use in verifying a hierarchical circuit design |
US5410107A (en) | 1993-03-01 | 1995-04-25 | The Board Of Trustees Of The University Of Arkansas | Multichip module |
FR2702595B1 (fr) | 1993-03-11 | 1996-05-24 | Toshiba Kk | Structure de câblage multicouche. |
US5536955A (en) | 1993-03-29 | 1996-07-16 | Toppan Electronics (Usa) Inc. | Electronic devices for use in generating integrated circuit structures and method therefor |
US5338963A (en) | 1993-04-05 | 1994-08-16 | International Business Machines Corporation | Soft error immune CMOS static RAM cell |
US5691218A (en) | 1993-07-01 | 1997-11-25 | Lsi Logic Corporation | Method of fabricating a programmable polysilicon gate array base cell structure |
US5396128A (en) | 1993-09-13 | 1995-03-07 | Motorola, Inc. | Output circuit for interfacing integrated circuits having different power supply potentials |
JP3144967B2 (ja) | 1993-11-08 | 2001-03-12 | 株式会社日立製作所 | 半導体集積回路およびその製造方法 |
JP2746087B2 (ja) | 1993-12-01 | 1998-04-28 | 日本電気株式会社 | 半導体集積回路 |
US5625568A (en) | 1993-12-22 | 1997-04-29 | Vlsi Technology, Inc. | Method and apparatus for compacting integrated circuits with standard cell architectures |
JP2684980B2 (ja) | 1993-12-24 | 1997-12-03 | 日本電気株式会社 | 半導体記憶装置及びその製造方法 |
US5378649A (en) | 1994-04-08 | 1995-01-03 | United Microelectronics Corporation | Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas |
US5636002A (en) | 1994-04-29 | 1997-06-03 | Lucent Technologies Inc. | Auxiliary mask features for enhancing the resolution of photolithography |
JP3463180B2 (ja) | 1994-05-02 | 2003-11-05 | Necトーキン株式会社 | 磁性ガーネット酸化物粉末の製造方法及び磁性ガーネット酸化物膜の製造方法 |
US5591995A (en) | 1994-05-10 | 1997-01-07 | Texas Instruments, Incorporated | Base cell for BiCMOS and CMOS gate arrays |
TW297158B (ja) | 1994-05-27 | 1997-02-01 | Hitachi Ltd | |
JP3202490B2 (ja) | 1994-07-22 | 2001-08-27 | 株式会社東芝 | 集積回路のレイアウト方法及び集積回路のレイアウト装置 |
JP3469362B2 (ja) | 1994-08-31 | 2003-11-25 | 株式会社東芝 | 半導体記憶装置 |
US5528177A (en) | 1994-09-16 | 1996-06-18 | Research Foundation Of State University Of New York | Complementary field-effect transistor logic circuits for wave pipelining |
US5497337A (en) * | 1994-10-21 | 1996-03-05 | International Business Machines Corporation | Method for designing high-Q inductors in silicon technology without expensive metalization |
US5852562A (en) | 1994-12-13 | 1998-12-22 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones |
JPH08292938A (ja) | 1995-02-24 | 1996-11-05 | Fujitsu Ltd | 有限要素メッシュ発生方法及び装置、並びに解析方法及び装置 |
JP2647045B2 (ja) | 1995-02-28 | 1997-08-27 | 日本電気株式会社 | 半導体記憶装置及びその製造方法 |
US5682323A (en) | 1995-03-06 | 1997-10-28 | Lsi Logic Corporation | System and method for performing optical proximity correction on macrocell libraries |
US5581098A (en) | 1995-05-05 | 1996-12-03 | Circuit Integration Technology, Inc. | Circuit routing structure using fewer variable masks |
JP3708168B2 (ja) * | 1995-06-13 | 2005-10-19 | 富士通株式会社 | 遅延装置 |
JP3535615B2 (ja) | 1995-07-18 | 2004-06-07 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US5774367A (en) | 1995-07-24 | 1998-06-30 | Motorola, Inc. | Method of selecting device threshold voltages for high speed and low power |
US5764533A (en) | 1995-08-01 | 1998-06-09 | Sun Microsystems, Inc. | Apparatus and methods for generating cell layouts |
JPH0951083A (ja) * | 1995-08-10 | 1997-02-18 | Mitsubishi Electric Corp | ゲートアレイ型半導体集積回路装置及びその製造方法 |
US5841663A (en) | 1995-09-14 | 1998-11-24 | Vlsi Technology, Inc. | Apparatus and method for synthesizing integrated circuits using parameterized HDL modules |
JPH0993118A (ja) | 1995-09-22 | 1997-04-04 | Kawasaki Steel Corp | パストランジスタ論理回路 |
US5789776A (en) | 1995-09-22 | 1998-08-04 | Nvx Corporation | Single poly memory cell and array |
JPH0997885A (ja) | 1995-09-28 | 1997-04-08 | Denso Corp | ゲートアレイ |
US5723883A (en) | 1995-11-14 | 1998-03-03 | In-Chip | Gate array cell architecture and routing scheme |
US5640342A (en) | 1995-11-20 | 1997-06-17 | Micron Technology, Inc. | Structure for cross coupled thin film transistors and static random access memory cell |
JP3400215B2 (ja) | 1995-11-21 | 2003-04-28 | 沖電気工業株式会社 | 半導体装置 |
JP3486725B2 (ja) | 1995-11-28 | 2004-01-13 | 株式会社ルネサステクノロジ | 可変論理集積回路 |
JP3934719B2 (ja) | 1995-12-22 | 2007-06-20 | 株式会社東芝 | 光近接効果補正方法 |
US6043562A (en) | 1996-01-26 | 2000-03-28 | Micron Technology, Inc. | Digit line architecture for dynamic memory |
KR100229577B1 (ko) | 1996-01-31 | 1999-11-15 | 포만 제프리 엘 | 게이트 어레이 셀 및 이것을 포함한 집적 회로 칩 |
US5798298A (en) | 1996-02-09 | 1998-08-25 | United Microelectronics Corporation | Method of automatically generating dummy metals for multilevel interconnection |
US6269472B1 (en) | 1996-02-27 | 2001-07-31 | Lsi Logic Corporation | Optical proximity correction method and apparatus |
US5705301A (en) * | 1996-02-27 | 1998-01-06 | Lsi Logic Corporation | Performing optical proximity correction with the aid of design rule checkers |
US5698873A (en) | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
JP2914292B2 (ja) * | 1996-04-25 | 1999-06-28 | 日本電気株式会社 | 半導体装置 |
US5740068A (en) | 1996-05-30 | 1998-04-14 | International Business Machines Corporation | Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction |
US5935763A (en) | 1996-06-11 | 1999-08-10 | International Business Machines Corporation | Self-aligned pattern over a reflective layer |
US6026223A (en) | 1996-06-28 | 2000-02-15 | Scepanovic; Ranko | Advanced modular cell placement system with overlap remover with minimal noise |
JP3311244B2 (ja) * | 1996-07-15 | 2002-08-05 | 株式会社東芝 | 基本セルライブラリ及びその形成方法 |
US5796128A (en) | 1996-07-25 | 1998-08-18 | Translogic Technology, Inc. | Gate array with fully wired multiplexer circuits |
US5920486A (en) | 1996-08-16 | 1999-07-06 | International Business Machines Corporation | Parameterized cells for generating dense layouts of VLSI circuits |
JP3152635B2 (ja) | 1996-09-09 | 2001-04-03 | 三洋電機株式会社 | マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器 |
US5858580A (en) | 1997-09-17 | 1999-01-12 | Numerical Technologies, Inc. | Phase shifting circuit manufacture method and apparatus |
US5790417A (en) | 1996-09-25 | 1998-08-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of automatic dummy layout generation |
US5923060A (en) | 1996-09-27 | 1999-07-13 | In-Chip Systems, Inc. | Reduced area gate array cell design based on shifted placement of alternate rows of cells |
US5684733A (en) | 1996-09-30 | 1997-11-04 | Holtek Microelectronics, Inc. | Fixed resistance high density parallel ROM device |
JP3529563B2 (ja) | 1996-10-09 | 2004-05-24 | 株式会社東芝 | 半導体集積回路の再レイアウト方法及び半導体集積回路の再レイアウトプログラムを記録した媒体 |
US6209123B1 (en) * | 1996-11-01 | 2001-03-27 | Motorola, Inc. | Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors |
US6099584A (en) | 1996-12-06 | 2000-08-08 | Vsli Technology, Inc. | System to fix post-layout timing and design rules violations |
JP3523762B2 (ja) | 1996-12-19 | 2004-04-26 | 株式会社東芝 | 半導体記憶装置 |
JP3352895B2 (ja) | 1996-12-25 | 2002-12-03 | 株式会社東芝 | 半導体集積回路、半導体集積回路の設計方法および製造方法 |
JP3420694B2 (ja) | 1996-12-27 | 2003-06-30 | 株式会社東芝 | スタンダードセル方式の集積回路 |
JPH10189746A (ja) | 1996-12-27 | 1998-07-21 | Oki Electric Ind Co Ltd | Lsi論理回路の配線レイアウト方法 |
JP3036588B2 (ja) | 1997-02-03 | 2000-04-24 | 日本電気株式会社 | 半導体記憶装置 |
JP3180700B2 (ja) | 1997-02-03 | 2001-06-25 | 日本電気株式会社 | 半導体集積回路装置 |
JP3352349B2 (ja) | 1997-02-24 | 2002-12-03 | シャープ株式会社 | 双方向サイリスタ素子 |
US5900340A (en) * | 1997-03-03 | 1999-05-04 | Motorola, Inc. | One dimensional lithographic proximity correction using DRC shape functions |
US5977574A (en) | 1997-03-28 | 1999-11-02 | Lsi Logic Corporation | High density gate array cell architecture with sharing of well taps between cells |
US5880991A (en) | 1997-04-14 | 1999-03-09 | International Business Machines Corporation | Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure |
US6393601B1 (en) | 1997-04-14 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method |
JP3178799B2 (ja) | 1997-04-18 | 2001-06-25 | シャープ株式会社 | Mos論理回路及びこのmos論理回路を備えた半導体装置 |
KR100227621B1 (ko) | 1997-05-22 | 1999-11-01 | 김영환 | 반도체 소자의 트랜지스터 제조방법 |
US6005296A (en) | 1997-05-30 | 1999-12-21 | Stmicroelectronics, Inc. | Layout for SRAM structure |
US6445049B1 (en) | 1997-06-30 | 2002-09-03 | Artisan Components, Inc. | Cell based array comprising logic, transfer and drive cells |
US6282696B1 (en) * | 1997-08-15 | 2001-08-28 | Lsi Logic Corporation | Performing optical proximity correction with the aid of design rule checkers |
US6370679B1 (en) * | 1997-09-17 | 2002-04-09 | Numerical Technologies, Inc. | Data hierarchy layout correction and verification method and apparatus |
US6470489B1 (en) | 1997-09-17 | 2002-10-22 | Numerical Technologies, Inc. | Design rule checking system and method |
US6009251A (en) | 1997-09-30 | 1999-12-28 | Synopsys, Inc. | Method and system for layout verification of an integrated circuit design with reusable subdesigns |
US6114071A (en) | 1997-11-24 | 2000-09-05 | Asml Masktools Netherlands B.V. | Method of fine feature edge tuning with optically-halftoned mask |
DE69727581D1 (de) | 1997-11-28 | 2004-03-18 | St Microelectronics Srl | RAM-Speicherzelle mit niedriger Leistungsaufnahme |
JP3701781B2 (ja) | 1997-11-28 | 2005-10-05 | 株式会社ルネサステクノロジ | 論理回路とその作成方法 |
JP3926011B2 (ja) * | 1997-12-24 | 2007-06-06 | 株式会社ルネサステクノロジ | 半導体装置の設計方法 |
JP3777768B2 (ja) | 1997-12-26 | 2006-05-24 | 株式会社日立製作所 | 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法 |
KR100278273B1 (ko) * | 1997-12-30 | 2001-02-01 | 김영환 | 반도체장치의콘택홀형성방법 |
US6249902B1 (en) | 1998-01-09 | 2001-06-19 | Silicon Perspective Corporation | Design hierarchy-based placement |
US6571140B1 (en) | 1998-01-15 | 2003-05-27 | Eutech Cybernetics Pte Ltd. | Service-oriented community agent |
JPH11214662A (ja) | 1998-01-29 | 1999-08-06 | Mitsubishi Electric Corp | 半導体装置 |
US6091845A (en) | 1998-02-24 | 2000-07-18 | Micron Technology, Inc. | Inspection technique of photomask |
US6378110B1 (en) | 1998-03-31 | 2002-04-23 | Synopsys, Inc. | Layer-based rule checking for an integrated circuit layout |
US6230299B1 (en) | 1998-03-31 | 2001-05-08 | Mentor Graphics Corporation | Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design |
JPH11297856A (ja) | 1998-04-16 | 1999-10-29 | Mitsubishi Electric Corp | スタティック半導体記憶装置 |
US5915199A (en) | 1998-06-04 | 1999-06-22 | Sharp Microelectronics Technology, Inc. | Method for manufacturing a CMOS self-aligned strapped interconnection |
US6262487B1 (en) | 1998-06-23 | 2001-07-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method |
JP3964575B2 (ja) * | 1998-06-23 | 2007-08-22 | 株式会社東芝 | 半導体集積回路装置、半導体集積回路配線方法およびセル配置方法 |
US6063132A (en) | 1998-06-26 | 2000-05-16 | International Business Machines Corporation | Method for verifying design rule checking software |
US6480989B2 (en) | 1998-06-29 | 2002-11-12 | Lsi Logic Corporation | Integrated circuit design incorporating a power mesh |
US6714903B1 (en) | 1998-07-10 | 2004-03-30 | Lsi Logic Corporation | Placement and routing of circuits using a combined processing/buffer cell |
US6240542B1 (en) * | 1998-07-14 | 2001-05-29 | Lsi Logic Corporation | Poly routing for chip interconnects with minimal impact on chip performance |
US6182272B1 (en) * | 1998-07-16 | 2001-01-30 | Lsi Logic Corporation | Metal layer assignment |
JP3562975B2 (ja) | 1998-09-29 | 2004-09-08 | 株式会社東芝 | 集積回路設計方法及び集積回路設計装置 |
US20020008257A1 (en) | 1998-09-30 | 2002-01-24 | John P. Barnak | Mosfet gate electrodes having performance tuned work functions and methods of making same |
JP2000114262A (ja) * | 1998-10-05 | 2000-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3852729B2 (ja) * | 1998-10-27 | 2006-12-06 | 富士通株式会社 | 半導体記憶装置 |
US6275973B1 (en) * | 1998-10-30 | 2001-08-14 | Lsi Logic Corporation | Integrated circuit design with delayed cell selection |
US6174742B1 (en) | 1998-10-30 | 2001-01-16 | Lsi Logic Corporation | Off-grid metal layer utilization |
US6166415A (en) | 1998-11-02 | 2000-12-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with improved noise resistivity |
JP3680594B2 (ja) | 1998-11-10 | 2005-08-10 | 株式会社日立製作所 | 半導体集積回路 |
TW476069B (en) | 1998-11-20 | 2002-02-11 | Via Tech Inc | Placement and routing for array device |
AU1913500A (en) | 1998-11-25 | 2000-06-13 | Nanopower, Inc. | Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits |
US6477695B1 (en) | 1998-12-09 | 2002-11-05 | Artisan Components, Inc. | Methods for designing standard cell transistor structures |
WO2000036466A1 (fr) | 1998-12-11 | 2000-06-22 | Hitachi, Ltd. | Dispositif a circuit integre a semiconducteurs et procede de fabrication |
KR100291384B1 (ko) | 1998-12-31 | 2001-07-12 | 윤종용 | 반도체장치의레이아웃방법 |
US6159839A (en) | 1999-02-11 | 2000-12-12 | Vanguard International Semiconductor Corporation | Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections |
US6691297B1 (en) | 1999-03-04 | 2004-02-10 | Matsushita Electric Industrial Co., Ltd. | Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI |
US6480032B1 (en) | 1999-03-04 | 2002-11-12 | Intel Corporation | Gate array architecture |
US6974978B1 (en) | 1999-03-04 | 2005-12-13 | Intel Corporation | Gate array architecture |
US6194912B1 (en) | 1999-03-11 | 2001-02-27 | Easic Corporation | Integrated circuit device |
US6331733B1 (en) | 1999-08-10 | 2001-12-18 | Easic Corporation | Semiconductor device |
US6044007A (en) * | 1999-03-24 | 2000-03-28 | Advanced Micro Devices, Inc. | Modification of mask layout data to improve writeability of OPC |
JP3986036B2 (ja) | 1999-04-16 | 2007-10-03 | 株式会社日立製作所 | 半導体集積回路装置 |
US6505328B1 (en) | 1999-04-27 | 2003-01-07 | Magma Design Automation, Inc. | Method for storing multiple levels of design data in a common database |
US6507941B1 (en) * | 1999-04-28 | 2003-01-14 | Magma Design Automation, Inc. | Subgrid detailed routing |
JP4565700B2 (ja) * | 1999-05-12 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6492066B1 (en) | 1999-05-28 | 2002-12-10 | Advanced Micro Devices, Inc. | Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion |
US6425112B1 (en) | 1999-06-17 | 2002-07-23 | International Business Machines Corporation | Auto correction of error checked simulated printed images |
US6381730B1 (en) | 1999-07-09 | 2002-04-30 | Sequence Design, Inc. | Method and system for extraction of parasitic interconnect impedance including inductance |
US6525350B1 (en) * | 1999-07-16 | 2003-02-25 | Kawasaki Steel Corporation | Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same |
JP2001056463A (ja) | 1999-08-20 | 2001-02-27 | Casio Comput Co Ltd | 液晶表示装置 |
JP2001068558A (ja) | 1999-08-30 | 2001-03-16 | Hitachi Ltd | 半導体集積回路装置 |
US6436805B1 (en) | 1999-09-01 | 2002-08-20 | Micron Technology, Inc. | Local interconnect structures and methods for making the same |
US6496965B1 (en) | 1999-09-20 | 2002-12-17 | Magma Design Automation, Inc. | Automated design of parallel drive standard cells |
TW423218B (en) | 1999-10-06 | 2001-02-21 | Ind Tech Res Inst | Charge-redistribution low-swing differential logic circuit |
US6194104B1 (en) | 1999-10-12 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Optical proximity correction (OPC) method for improving lithography process window |
US6737347B1 (en) | 1999-10-20 | 2004-05-18 | Texas Instruments Incorporated | Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device |
US6426269B1 (en) | 1999-10-21 | 2002-07-30 | International Business Machines Corporation | Dummy feature reduction using optical proximity effect correction |
US6255845B1 (en) | 1999-11-16 | 2001-07-03 | Advanced Micro Devices, Inc. | Efficient use of spare gates for post-silicon debug and enhancements |
WO2001037345A1 (en) | 1999-11-17 | 2001-05-25 | Aeroflex Utmc Microelectronic Systems Inc. | Radiation resistant integrated circuit design |
JP2001144603A (ja) | 1999-11-18 | 2001-05-25 | Oki Micro Design Co Ltd | レベルシフタ回路およびそれを含むデータ出力回路 |
WO2001037322A2 (en) | 1999-11-18 | 2001-05-25 | Pdf Solutions, Inc. | System and method for product yield prediction using a logic characterization vehicle |
JP2001168707A (ja) | 1999-12-03 | 2001-06-22 | Sony Corp | 論理回路およびそれを用いた全加算器 |
US6421820B1 (en) * | 1999-12-13 | 2002-07-16 | Infineon Technologies Ag | Semiconductor device fabrication using a photomask with assist features |
US6303252B1 (en) | 1999-12-27 | 2001-10-16 | United Microelectronics Corp. | Reticle having assist feature between semi-dense lines |
KR100346832B1 (ko) | 2000-01-12 | 2002-08-03 | 삼성전자 주식회사 | 스태틱 랜덤 억세스 메모리 소자 및 그 제조 방법 |
US6737199B1 (en) | 2000-01-31 | 2004-05-18 | Taiwan Semiconductor Manufacturing Company | Using new pattern fracturing rules for optical proximity correction mask-making to improve critical dimension uniformity |
US6408427B1 (en) | 2000-02-22 | 2002-06-18 | The Regents Of The University Of California | Wire width planning and performance optimization for VLSI interconnects |
US6756811B2 (en) | 2000-03-10 | 2004-06-29 | Easic Corporation | Customizable and programmable cell array |
US6331790B1 (en) | 2000-03-10 | 2001-12-18 | Easic Corporation | Customizable and programmable cell array |
US6399972B1 (en) * | 2000-03-13 | 2002-06-04 | Oki Electric Industry Co., Ltd. | Cell based integrated circuit and unit cell architecture therefor |
US6536028B1 (en) | 2000-03-14 | 2003-03-18 | Ammocore Technologies, Inc. | Standard block architecture for integrated circuit design |
JP2001272228A (ja) | 2000-03-24 | 2001-10-05 | Railway Technical Res Inst | 相対変位量計測システム及び相対変位量計測方法 |
US6356112B1 (en) * | 2000-03-28 | 2002-03-12 | Translogic Technology, Inc. | Exclusive or/nor circuit |
US6553544B2 (en) * | 2000-04-04 | 2003-04-22 | Matsushita Electric Industrial Co., Ltd. | Method for design of partial circuit |
US6416907B1 (en) * | 2000-04-27 | 2002-07-09 | Micron Technology, Inc. | Method for designing photolithographic reticle layout, reticle, and photolithographic process |
TW512424B (en) | 2000-05-01 | 2002-12-01 | Asml Masktools Bv | Hybrid phase-shift mask |
US6583041B1 (en) | 2000-05-01 | 2003-06-24 | Advanced Micro Devices, Inc. | Microdevice fabrication method using regular arrays of lines and spaces |
JP4885365B2 (ja) | 2000-05-16 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6509952B1 (en) | 2000-05-23 | 2003-01-21 | Silicon Valley Group, Inc. | Method and system for selective linewidth optimization during a lithographic process |
US6610607B1 (en) | 2000-05-25 | 2003-08-26 | International Business Machines Corporation | Method to define and tailor process limited lithographic features using a modified hard mask process |
US6445065B1 (en) * | 2000-06-06 | 2002-09-03 | In-Chip Systems, Inc. | Routing driven, metal programmable integrated circuit architecture with multiple types of core cells |
US6617621B1 (en) | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
US6425113B1 (en) | 2000-06-13 | 2002-07-23 | Leigh C. Anderson | Integrated verification and manufacturability tool |
US6889370B1 (en) | 2000-06-20 | 2005-05-03 | Unisys Corporation | Method and apparatus for selecting and aligning cells using a placement tool |
JP2002026296A (ja) | 2000-06-22 | 2002-01-25 | Internatl Business Mach Corp <Ibm> | 半導体集積回路装置 |
JP2002009160A (ja) | 2000-06-26 | 2002-01-11 | Nec Microsystems Ltd | 半導体集積回路の自動レイアウト方法、この方法で製造した半導体集積回路及びこの方法を記録した記録媒体 |
US7225423B2 (en) | 2000-06-30 | 2007-05-29 | Zenasis Technologies, Inc. | Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks |
US6787271B2 (en) | 2000-07-05 | 2004-09-07 | Numerical Technologies, Inc. | Design and layout of phase shifting photolithographic masks |
US6978436B2 (en) | 2000-07-05 | 2005-12-20 | Synopsys, Inc. | Design data format and hierarchy management for phase processing |
US7028285B2 (en) | 2000-07-05 | 2006-04-11 | Synopsys, Inc. | Standard cell design incorporating phase information |
US6733929B2 (en) | 2000-07-05 | 2004-05-11 | Numerical Technologies, Inc. | Phase shift masking for complex patterns with proximity adjustments |
US6516459B1 (en) | 2000-07-10 | 2003-02-04 | Mentor Graphics Corporation | Integrated circuit design correction using fragment correspondence |
JP4794030B2 (ja) | 2000-07-10 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6632741B1 (en) | 2000-07-19 | 2003-10-14 | International Business Machines Corporation | Self-trimming method on looped patterns |
US6574786B1 (en) | 2000-07-21 | 2003-06-03 | Aeroflex UTMC Microelectronics Systems, Inc. | Gate array cell generator using cadence relative object design |
US20050136340A1 (en) | 2000-07-21 | 2005-06-23 | Asml Netherlands B.V. | Lithographic apparatus and methods, patterning structure and method for making a patterning structure, device manufacturing method, and device manufactured thereby |
US6523162B1 (en) | 2000-08-02 | 2003-02-18 | Numerical Technologies, Inc. | General purpose shape-based layout processing scheme for IC layout modifications |
JP4764987B2 (ja) | 2000-09-05 | 2011-09-07 | 富士電機株式会社 | 超接合半導体素子 |
AU2001290937A1 (en) | 2000-09-13 | 2002-04-02 | Massachusetts Institute Of Technology | Method of design and fabrication of integrated circuits using regular arrays and gratings |
US6800883B2 (en) | 2000-09-21 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | CMOS basic cell and method for fabricating semiconductor integrated circuit using the same |
US6625801B1 (en) | 2000-09-29 | 2003-09-23 | Numerical Technologies, Inc. | Dissection of printed edges from a fabrication layout for correcting proximity effects |
US6557162B1 (en) | 2000-09-29 | 2003-04-29 | Numerical Technologies, Inc. | Method for high yield reticle formation |
US6453457B1 (en) | 2000-09-29 | 2002-09-17 | Numerical Technologies, Inc. | Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout |
US6794677B2 (en) | 2000-10-02 | 2004-09-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for fabricating the same |
US6555450B2 (en) | 2000-10-04 | 2003-04-29 | Samsung Electronics Co., Ltd. | Contact forming method for semiconductor device |
US6566720B2 (en) | 2000-10-05 | 2003-05-20 | United Memories, Inc. | Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits |
US6978437B1 (en) | 2000-10-10 | 2005-12-20 | Toppan Photomasks, Inc. | Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same |
KR20020034313A (ko) | 2000-10-31 | 2002-05-09 | 박종섭 | 에스램셀의 제조 방법 |
US6703170B1 (en) | 2000-12-13 | 2004-03-09 | Dupont Photomasks, Inc. | Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process |
JP2002184870A (ja) | 2000-12-18 | 2002-06-28 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
US6992394B2 (en) | 2000-12-28 | 2006-01-31 | Infineon Technologies Ag | Multi-level conductive lines with reduced pitch |
US6553559B2 (en) | 2001-01-05 | 2003-04-22 | International Business Machines Corporation | Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions |
US6578190B2 (en) | 2001-01-11 | 2003-06-10 | International Business Machines Corporation | Process window based optical proximity correction of lithographic images |
JP2002289703A (ja) | 2001-01-22 | 2002-10-04 | Nec Corp | 半導体記憶装置およびその製造方法 |
JP2002252161A (ja) | 2001-02-23 | 2002-09-06 | Hitachi Ltd | 半導体製造システム |
US6792591B2 (en) | 2001-02-28 | 2004-09-14 | Asml Masktools B.V. | Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs |
JP4928675B2 (ja) | 2001-03-01 | 2012-05-09 | エルピーダメモリ株式会社 | 半導体装置 |
JP4736206B2 (ja) | 2001-03-05 | 2011-07-27 | 大日本印刷株式会社 | フォトマスクパタン欠陥検査方法および微細図形パタンの検出方法 |
US6881523B2 (en) | 2001-03-14 | 2005-04-19 | Asml Masktools B.V. | Optical proximity correction method utilizing ruled ladder bars as sub-resolution assist features |
US6732334B2 (en) | 2001-04-02 | 2004-05-04 | Matsushita Electric Industrial Co., Ltd. | Analog MOS semiconductor device, manufacturing method therefor, manufacturing program therefor, and program device therefor |
US6514849B1 (en) * | 2001-04-02 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of forming smaller contact size using a spacer hard mask |
US6574779B2 (en) | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Hierarchical layout method for integrated circuits |
US6505327B2 (en) * | 2001-04-13 | 2003-01-07 | Numerical Technologies, Inc. | Generating an instance-based representation of a design hierarchy |
US6524870B2 (en) | 2001-04-24 | 2003-02-25 | Pell, Iii Edwin A. | Method and apparatus for improving resolution of objects in a semiconductor wafer |
JP4187947B2 (ja) | 2001-04-26 | 2008-11-26 | 株式会社東芝 | パターン補正方法、パターン補正装置、およびパターン補正プログラムを記録した記録媒体 |
US6781170B2 (en) * | 2001-05-01 | 2004-08-24 | Lattice Semiconductor Corporation | Integrated circuit base transistor structure and associated programmable cell library |
US6936908B2 (en) | 2001-05-03 | 2005-08-30 | Ixys Corporation | Forward and reverse blocking devices |
US6553562B2 (en) | 2001-05-04 | 2003-04-22 | Asml Masktools B.V. | Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques |
US6590289B2 (en) | 2001-05-17 | 2003-07-08 | Lsi Logic Corporation | Hexadecagonal routing |
US6523156B2 (en) | 2001-06-08 | 2003-02-18 | Library Technologies, Inc. | Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries |
US6759282B2 (en) | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
JP2002368135A (ja) | 2001-06-12 | 2002-12-20 | Hitachi Ltd | 半導体記憶装置 |
JP4798881B2 (ja) * | 2001-06-18 | 2011-10-19 | 富士通セミコンダクター株式会社 | 半導体集積回路装置 |
JP4746770B2 (ja) | 2001-06-19 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6609235B2 (en) * | 2001-06-22 | 2003-08-19 | Bae Systems Information And Electronic Systems Integration, Inc. | Method for providing a fill pattern for an integrated circuit design |
US7079989B2 (en) | 2001-06-29 | 2006-07-18 | Shmuel Wimer | Arrangements for automatic re-legging of transistors |
US6835591B2 (en) * | 2001-07-25 | 2004-12-28 | Nantero, Inc. | Methods of nanotube films and articles |
DE10137830A1 (de) | 2001-08-02 | 2003-02-27 | Infineon Technologies Ag | Verfahren zum Herstellen einer selbstjustierten Struktur auf einem Halbleiter-Wafer |
US6684382B2 (en) | 2001-08-31 | 2004-01-27 | Numerical Technologies, Inc. | Microloading effect correction |
DE10143723B4 (de) | 2001-08-31 | 2006-09-28 | Infineon Technologies Ag | Verfahren zur Optimierung eines Layouts für eine Maske zur Verwendung bei der Halbleiterherstellung |
US6633182B2 (en) | 2001-09-05 | 2003-10-14 | Carnegie Mellon University | Programmable gate array based on configurable metal interconnect vias |
JP4786836B2 (ja) | 2001-09-07 | 2011-10-05 | 富士通セミコンダクター株式会社 | 配線接続部設計方法及び半導体装置 |
JP2003092250A (ja) | 2001-09-18 | 2003-03-28 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3989213B2 (ja) | 2001-09-25 | 2007-10-10 | シャープ株式会社 | パストランジスタ論理回路 |
JP3637299B2 (ja) | 2001-10-05 | 2005-04-13 | 松下電器産業株式会社 | 半導体記憶装置 |
TWI228642B (en) | 2001-10-09 | 2005-03-01 | Asml Masktools Inc | Method of two dimensional feature model calibration and optimization |
JP2003124339A (ja) | 2001-10-11 | 2003-04-25 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3526450B2 (ja) | 2001-10-29 | 2004-05-17 | 株式会社東芝 | 半導体集積回路およびスタンダードセル配置設計方法 |
JP2003142584A (ja) | 2001-11-05 | 2003-05-16 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置の設計方法 |
US6673638B1 (en) | 2001-11-14 | 2004-01-06 | Kla-Tencor Corporation | Method and apparatus for the production of process sensitive lithographic features |
JP3789351B2 (ja) | 2001-11-30 | 2006-06-21 | 株式会社日立製作所 | 反射型液晶表示装置及びその製造方法 |
JP2003168640A (ja) | 2001-12-03 | 2003-06-13 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003188361A (ja) | 2001-12-20 | 2003-07-04 | Mitsubishi Electric Corp | ゲートアレイ構造の半導体集積回路 |
JP3828419B2 (ja) | 2001-12-25 | 2006-10-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6787469B2 (en) | 2001-12-28 | 2004-09-07 | Texas Instruments Incorporated | Double pattern and etch of poly with hard mask |
US7159197B2 (en) | 2001-12-31 | 2007-01-02 | Synopsys, Inc. | Shape-based geometry engine to perform smoothing and other layout beautification operations |
US6817000B2 (en) | 2002-01-02 | 2004-11-09 | International Business Machines Corporation | Delay correlation analysis and representation for vital complaint VHDL models |
US7085701B2 (en) | 2002-01-02 | 2006-08-01 | International Business Machines Corporation | Size reduction techniques for vital compliant VHDL simulation models |
JP2003203993A (ja) | 2002-01-10 | 2003-07-18 | Mitsubishi Electric Corp | 半導体記憶装置及びその製造方法 |
US6749972B2 (en) | 2002-01-15 | 2004-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Optical proximity correction common process window maximization over varying feature pitch |
US6721926B2 (en) | 2002-01-25 | 2004-04-13 | Intel Corporation | Method and apparatus for improving digital circuit design |
US6662350B2 (en) | 2002-01-28 | 2003-12-09 | International Business Machines Corporation | FinFET layout generation |
US6820248B1 (en) | 2002-02-14 | 2004-11-16 | Xilinx, Inc. | Method and apparatus for routing interconnects to devices with dissimilar pitches |
US6877144B1 (en) * | 2002-02-28 | 2005-04-05 | Dupont Photomasks, Inc. | System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit |
JP2003258109A (ja) * | 2002-03-07 | 2003-09-12 | Hitachi Ltd | 半導体集積回路装置 |
JP2003264231A (ja) | 2002-03-11 | 2003-09-19 | Mitsubishi Electric Corp | レイアウト設計方法および半導体装置 |
TWI252516B (en) | 2002-03-12 | 2006-04-01 | Toshiba Corp | Determination method of process parameter and method for determining at least one of process parameter and design rule |
US7386433B2 (en) | 2002-03-15 | 2008-06-10 | Synopsys, Inc. | Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout |
US6732338B2 (en) | 2002-03-20 | 2004-05-04 | International Business Machines Corporation | Method for comprehensively verifying design rule checking runsets |
US6765245B2 (en) * | 2002-03-25 | 2004-07-20 | Bae Systems Information And Electronic Systems Integration Inc. | Gate array core cell for VLSI ASIC devices |
US6754121B2 (en) | 2002-03-29 | 2004-06-22 | Stmicroelectronics, Inc. | Sense amplifying circuit and method |
US6745372B2 (en) * | 2002-04-05 | 2004-06-01 | Numerical Technologies, Inc. | Method and apparatus for facilitating process-compliant layout optimization |
US6789246B1 (en) | 2002-04-07 | 2004-09-07 | Barcelona Design, Inc. | Method and apparatus for automatic layout of circuit structures |
US7252909B2 (en) | 2002-04-18 | 2007-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to reduce CD non-uniformity in IC manufacturing |
JP4190796B2 (ja) | 2002-04-24 | 2008-12-03 | Necエレクトロニクス株式会社 | 露光原版の作成方法 |
US6992925B2 (en) | 2002-04-26 | 2006-01-31 | Kilopass Technologies, Inc. | High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline |
US6826738B2 (en) | 2002-05-10 | 2004-11-30 | Pdf Solutions, Inc. | Optimization of die placement on wafers |
US6794914B2 (en) | 2002-05-24 | 2004-09-21 | Qualcomm Incorporated | Non-volatile multi-threshold CMOS latch with leakage control |
JP2004013920A (ja) | 2002-06-03 | 2004-01-15 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6980211B2 (en) | 2002-06-04 | 2005-12-27 | Springsoft, Inc. | Automatic schematic diagram generation using topology information |
US7712056B2 (en) | 2002-06-07 | 2010-05-04 | Cadence Design Systems, Inc. | Characterization and verification for integrated circuit designs |
US7774726B2 (en) | 2002-06-07 | 2010-08-10 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
WO2003104921A2 (en) | 2002-06-07 | 2003-12-18 | Praesagus, Inc. | Characterization adn reduction of variation for integrated circuits |
US7124386B2 (en) | 2002-06-07 | 2006-10-17 | Praesagus, Inc. | Dummy fill for integrated circuits |
US7152215B2 (en) | 2002-06-07 | 2006-12-19 | Praesagus, Inc. | Dummy fill for integrated circuits |
US20030229875A1 (en) | 2002-06-07 | 2003-12-11 | Smith Taber H. | Use of models in integrated circuit fabrication |
US7363099B2 (en) | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Integrated circuit metrology |
US6795953B2 (en) | 2002-06-11 | 2004-09-21 | Hpl Technologies, Inc. | Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design |
JP3879063B2 (ja) | 2002-06-11 | 2007-02-07 | 富士通株式会社 | 半導体装置およびその製造方法 |
US7039882B2 (en) | 2002-06-17 | 2006-05-02 | Amar Pal Singh Rana | Technology dependent transformations for Silicon-On-Insulator in digital design synthesis |
JP2004022070A (ja) | 2002-06-17 | 2004-01-22 | Renesas Technology Corp | 半導体記憶装置 |
JP4036688B2 (ja) | 2002-06-18 | 2008-01-23 | 松下電器産業株式会社 | 自動配置配線用スタンダードセルライブラリ及び半導体集積装置 |
EP1376676A3 (en) | 2002-06-24 | 2008-08-20 | Interuniversitair Microelektronica Centrum Vzw | Multibit non-volatile memory device and method |
JP4462528B2 (ja) | 2002-06-24 | 2010-05-12 | 株式会社日立製作所 | 半導体集積回路装置 |
US6687895B2 (en) | 2002-07-03 | 2004-02-03 | Numerical Technologies Inc. | Method and apparatus for reducing optical proximity correction output file size |
US6998722B2 (en) | 2002-07-08 | 2006-02-14 | Viciciv Technology | Semiconductor latches and SRAM devices |
JP2004040042A (ja) | 2002-07-08 | 2004-02-05 | Fujitsu Ltd | 半導体記憶装置 |
US20040009409A1 (en) | 2002-07-11 | 2004-01-15 | Jiunn-Ren Hwang | Optical proximity correction method |
US7063923B2 (en) * | 2002-07-11 | 2006-06-20 | United Electronics Corp. | Optical proximity correction method |
US7231628B2 (en) | 2002-07-12 | 2007-06-12 | Cadence Design Systems, Inc. | Method and system for context-specific mask inspection |
JP4416384B2 (ja) | 2002-07-19 | 2010-02-17 | 株式会社ルネサステクノロジ | 半導体集積回路 |
KR100445638B1 (ko) | 2002-07-26 | 2004-08-25 | 삼성전자주식회사 | 전기적으로 분리된 영역들을 연결하는 상호 연결 구조 및그 제조방법 |
US7739624B2 (en) | 2002-07-29 | 2010-06-15 | Synopsys, Inc. | Methods and apparatuses to generate a shielding mesh for integrated circuit devices |
US7171645B2 (en) | 2002-08-06 | 2007-01-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device |
KR100493025B1 (ko) | 2002-08-07 | 2005-06-07 | 삼성전자주식회사 | 반도체 메모리 장치의 제조 방법 |
US6789244B1 (en) | 2002-08-08 | 2004-09-07 | Xilinx, Inc. | Placement of clock objects under constraints |
US7143380B1 (en) | 2002-08-08 | 2006-11-28 | Xilinx, Inc. | Method for application of network flow techniques under constraints |
US6785875B2 (en) | 2002-08-15 | 2004-08-31 | Fulcrum Microsystems, Inc. | Methods and apparatus for facilitating physical synthesis of an integrated circuit design |
US6854100B1 (en) | 2002-08-27 | 2005-02-08 | Taiwan Semiconductor Manufacturing Company | Methodology to characterize metal sheet resistance of copper damascene process |
JP3795846B2 (ja) | 2002-08-29 | 2006-07-12 | 富士通株式会社 | 半導体装置 |
US7345511B2 (en) | 2002-08-29 | 2008-03-18 | Technion Research & Development Foundation Ltd. | Logic circuit and method of logic circuit design |
US6734521B2 (en) | 2002-08-30 | 2004-05-11 | Texas Instruments Incorporated | Integrated circuit cells |
DE10241170A1 (de) | 2002-09-05 | 2004-03-18 | Infineon Technologies Ag | Hochdichter NROM-FINFET |
US20040049754A1 (en) | 2002-09-06 | 2004-03-11 | Sun Microsystems, Inc. | Method and apparatus for filling and connecting filler material in a layout |
TWI274969B (en) | 2002-09-11 | 2007-03-01 | Asml Masktools Bv | Method and computer program product of generating masks and mask generated thereby, device manufacturing method and device manufactured thereby, and method of printing pattern |
US6807663B2 (en) | 2002-09-23 | 2004-10-19 | Numerical Technologies, Inc. | Accelerated layout processing using OPC pre-processing |
US6928635B2 (en) * | 2002-09-25 | 2005-08-09 | Numerical Technologies, Inc. | Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits |
US7327597B1 (en) | 2002-10-02 | 2008-02-05 | Cisco Technology, Inc. | Static random access memory architecture |
WO2004034463A1 (ja) | 2002-10-10 | 2004-04-22 | Fujitsu Limited | レイアウト方法及び装置並びにそのプログラム及び記録媒体 |
US7214579B2 (en) | 2002-10-24 | 2007-05-08 | Nxp Bv. | Self-aligned 2-bit “double poly CMP” flash memory cell |
US6994939B1 (en) | 2002-10-29 | 2006-02-07 | Advanced Micro Devices, Inc. | Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types |
US7053424B2 (en) | 2002-10-31 | 2006-05-30 | Yamaha Corporation | Semiconductor integrated circuit device and its manufacture using automatic layout |
US7219326B2 (en) | 2002-12-16 | 2007-05-15 | Intrinsity, Inc. | Physical realization of dynamic logic using parameterized tile partitioning |
JP3848248B2 (ja) | 2002-12-17 | 2006-11-22 | 株式会社東芝 | Sramセルおよびそれを用いたメモリ集積回路 |
US6953956B2 (en) | 2002-12-18 | 2005-10-11 | Easic Corporation | Semiconductor device having borderless logic array and flexible I/O |
US7093228B2 (en) * | 2002-12-20 | 2006-08-15 | Lsi Logic Corporation | Method and system for classifying an integrated circuit for optical proximity correction |
EP1434264A3 (en) | 2002-12-27 | 2017-01-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method using the transfer technique |
JP4202120B2 (ja) | 2002-12-27 | 2008-12-24 | セイコーインスツル株式会社 | 集積回路の最適化設計装置 |
US6898770B2 (en) | 2003-01-09 | 2005-05-24 | Lsi Logic Corporation | Split and merge design flow concept for fast turnaround time of circuit layout design |
JP4136684B2 (ja) | 2003-01-29 | 2008-08-20 | Necエレクトロニクス株式会社 | 半導体装置及びそのダミーパターンの配置方法 |
US6996790B2 (en) | 2003-01-30 | 2006-02-07 | Synopsys, Inc. | System and method for generating a two-dimensional yield map for a full layout |
JP2004241529A (ja) | 2003-02-05 | 2004-08-26 | Matsushita Electric Ind Co Ltd | 半導体回路装置及びその回路シミュレーション方法 |
US6884712B2 (en) | 2003-02-07 | 2005-04-26 | Chartered Semiconductor Manufacturing, Ltd. | Method of manufacturing semiconductor local interconnect and contact |
JP4274814B2 (ja) * | 2003-02-20 | 2009-06-10 | Necエレクトロニクス株式会社 | 半導体集積回路の設計方法、設計装置、セルライブラリのデータ構造および自動レイアウトプログラム |
JP2004253730A (ja) | 2003-02-21 | 2004-09-09 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
US6777146B1 (en) * | 2003-02-21 | 2004-08-17 | International Business Machines Corporation | Method of optical proximity correction with sub-resolution assists |
US7149999B2 (en) | 2003-02-25 | 2006-12-12 | The Regents Of The University Of California | Method for correcting a mask design layout |
CN100498532C (zh) | 2003-02-27 | 2009-06-10 | 香港大学 | 将部件成像到晶片上的方法和用于成像晶芯的掩膜组 |
JP4531340B2 (ja) | 2003-02-27 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | マルチプレクサセルのレイアウト構造 |
JP4290457B2 (ja) | 2003-03-31 | 2009-07-08 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP3920804B2 (ja) | 2003-04-04 | 2007-05-30 | 松下電器産業株式会社 | 半導体記憶装置 |
US6931617B2 (en) * | 2003-04-21 | 2005-08-16 | Synopsys, Inc. | Mask cost driven logic optimization and synthesis |
US7065731B2 (en) | 2003-05-07 | 2006-06-20 | Cadence Design Systems, Inc. | Removal of acute angles in a design layout |
US7051306B2 (en) | 2003-05-07 | 2006-05-23 | Mosaid Technologies Corporation | Managing power on integrated circuits using power islands |
US7093208B2 (en) | 2003-05-12 | 2006-08-15 | International Business Machines Corporation | Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices |
JP2004342757A (ja) | 2003-05-14 | 2004-12-02 | Toshiba Corp | 半導体集積回路及びその設計方法 |
US7063920B2 (en) | 2003-05-16 | 2006-06-20 | Asml Holding, N.V. | Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems |
JP4233381B2 (ja) | 2003-05-21 | 2009-03-04 | 株式会社ルネサステクノロジ | 半導体装置とその製造方法 |
US7770144B2 (en) * | 2003-05-28 | 2010-08-03 | Eric Dellinger | Modular array defined by standard cell logic |
US7107551B1 (en) | 2003-05-30 | 2006-09-12 | Prolific, Inc. | Optimization of circuit designs using a continuous spectrum of library cells |
US7183611B2 (en) | 2003-06-03 | 2007-02-27 | Micron Technology, Inc. | SRAM constructions, and electronic systems comprising SRAM constructions |
US7400627B2 (en) | 2003-06-05 | 2008-07-15 | Brooktree Broadband Holding, Inc. | ATM header compression using hash tables |
US6992916B2 (en) | 2003-06-13 | 2006-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
JP4245418B2 (ja) | 2003-06-25 | 2009-03-25 | 富士通マイクロエレクトロニクス株式会社 | 斜め方向配線を有する半導体集積回路装置及びそのレイアウト方法 |
US20050009312A1 (en) | 2003-06-26 | 2005-01-13 | International Business Machines Corporation | Gate length proximity corrected device |
US6900999B1 (en) | 2003-06-30 | 2005-05-31 | Integrated Device Technology, Inc. | Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio |
KR100577610B1 (ko) * | 2003-07-15 | 2006-05-10 | 삼성전자주식회사 | 반도체 장치, 반도체 장치의 제조 방법 및 에스램 장치,에스램 장치 제조 방법. |
US6993741B2 (en) | 2003-07-15 | 2006-01-31 | International Business Machines Corporation | Generating mask patterns for alternating phase-shift mask lithography |
EP1519421A1 (en) | 2003-09-25 | 2005-03-30 | Interuniversitair Microelektronica Centrum Vzw | Multiple gate semiconductor device and method for forming same |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
EP1503411A1 (fr) | 2003-07-30 | 2005-02-02 | St Microelectronics S.A. | Lignes conductrices enterrées dans des zones d'isolement |
JP4398195B2 (ja) | 2003-08-08 | 2010-01-13 | パナソニック株式会社 | 半導体記憶装置 |
US6924560B2 (en) | 2003-08-08 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Compact SRAM cell with FinFET |
JP4620942B2 (ja) | 2003-08-21 | 2011-01-26 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク |
TWI220268B (en) | 2003-09-17 | 2004-08-11 | Faraday Tech Corp | Method for programming a routing layout design through one via layer |
US7345909B2 (en) | 2003-09-24 | 2008-03-18 | Yen-Jen Chang | Low-power SRAM memory cell |
US6957402B2 (en) | 2003-09-24 | 2005-10-18 | Artisan Components, Inc. | Yield maximization in the manufacture of integrated circuits |
KR100516226B1 (ko) * | 2003-09-25 | 2005-09-23 | 동부아남반도체 주식회사 | 에스램 테스트용 셀 및 에스램 셀 테스트 방법 |
JP2005114752A (ja) | 2003-10-02 | 2005-04-28 | Yamaha Corp | 演奏装置 |
JP4599048B2 (ja) | 2003-10-02 | 2010-12-15 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク |
JP4632287B2 (ja) | 2003-10-06 | 2011-02-16 | 株式会社日立製作所 | 半導体集積回路装置 |
US7155689B2 (en) | 2003-10-07 | 2006-12-26 | Magma Design Automation, Inc. | Design-manufacturing interface via a unified model |
FR2860920A1 (fr) | 2003-10-14 | 2005-04-15 | St Microelectronics Sa | Procede de realisation de connexions conductrices de circuits integres, et circuit integre mettant en oeuvre des telles connexions |
JP2005123524A (ja) | 2003-10-20 | 2005-05-12 | Toshiba Corp | 半導体装置及びその製造方法 |
US6867073B1 (en) | 2003-10-21 | 2005-03-15 | Ziptronix, Inc. | Single mask via method and device |
JP4346410B2 (ja) | 2003-10-28 | 2009-10-21 | 東芝メモリシステムズ株式会社 | 半導体集積回路の配線設計方法及び半導体集積回路 |
US7329953B2 (en) | 2003-10-29 | 2008-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same |
JP2005149265A (ja) | 2003-11-18 | 2005-06-09 | Olympus Corp | 演算処理システム及び演算処理装置 |
US7269803B2 (en) | 2003-12-18 | 2007-09-11 | Lsi Corporation | System and method for mapping logical components to physical locations in an integrated circuit design environment |
US7052972B2 (en) | 2003-12-19 | 2006-05-30 | Micron Technology, Inc. | Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus |
JP4585197B2 (ja) | 2003-12-22 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | レイアウト設計方法およびフォトマスク |
KR100702552B1 (ko) * | 2003-12-22 | 2007-04-04 | 인터내셔널 비지네스 머신즈 코포레이션 | 이중 게이트 FinFET 디자인을 위한 자동화 레이어생성 방법 및 장치 |
JP2005197345A (ja) | 2004-01-05 | 2005-07-21 | Hitachi Ltd | 半導体装置 |
JP2005203447A (ja) | 2004-01-13 | 2005-07-28 | Toshiba Corp | 半導体集積回路、半導体集積回路設計システム及び半導体集積回路設計方法 |
US7064068B2 (en) * | 2004-01-23 | 2006-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to improve planarity of electroplated copper |
JP2005229061A (ja) * | 2004-02-16 | 2005-08-25 | Matsushita Electric Ind Co Ltd | スタンダードセル、セル列および複合セル列 |
KR100564612B1 (ko) | 2004-02-19 | 2006-03-28 | 삼성전자주식회사 | 하드 디스크 드라이브 |
US7523429B2 (en) | 2004-02-20 | 2009-04-21 | Takumi Technology Corporation | System for designing integrated circuits with enhanced manufacturability |
WO2005081066A1 (en) | 2004-02-24 | 2005-09-01 | The University Of Hong Kong | Rectangular contact lithography for circuit performance improvement |
US7335966B2 (en) | 2004-02-26 | 2008-02-26 | Triad Semiconductor, Inc. | Configurable integrated circuit capacitor array using via mask layers |
US7084476B2 (en) | 2004-02-26 | 2006-08-01 | International Business Machines Corp. | Integrated circuit logic with self compensating block delays |
JP2005243928A (ja) | 2004-02-26 | 2005-09-08 | Fujitsu Ltd | トレンチアイソレーションで分離されたトランジスタ対を有する半導体装置 |
US7353492B2 (en) | 2004-02-26 | 2008-04-01 | International Business Machines Corporation | Method of IC fabrication, IC mask fabrication and program product therefor |
US7115343B2 (en) | 2004-03-10 | 2006-10-03 | International Business Machines Corporation | Pliant SRAF for improved performance and manufacturability |
US7423298B2 (en) | 2004-03-17 | 2008-09-09 | Sharp Kabushiki Kaisha | Bidirectional photothyristor chip, optical lighting coupler, and solid state relay |
JP2005268610A (ja) | 2004-03-19 | 2005-09-29 | Matsushita Electric Ind Co Ltd | スタンダードセルの設計方法及び半導体集積回路 |
DE102004014472B4 (de) * | 2004-03-24 | 2012-05-03 | Infineon Technologies Ag | Anwendungsspezifischer integrierter Halbleiter-Schaltkreis |
US7126837B1 (en) | 2004-03-26 | 2006-10-24 | Netlogic Microsystems, Inc. | Interlocking memory/logic cell layout and method of manufacture |
EP1730777B1 (en) | 2004-04-01 | 2007-09-19 | Soisic | Improved layout of a sram memory cell |
US7449371B2 (en) | 2004-04-02 | 2008-11-11 | Triad Semiconductor | VIA configurable architecture for customization of analog circuitry in a semiconductor device |
WO2005098686A2 (en) | 2004-04-02 | 2005-10-20 | Clear Shape Technologies, Inc. | Modeling resolution enhancement processes in integrated circuit fabrication |
US7404173B2 (en) | 2004-04-07 | 2008-07-22 | Aprio Technologies, Inc. | Intermediate layout for resolution enhancement in semiconductor fabrication |
US20050229130A1 (en) * | 2004-04-07 | 2005-10-13 | Aprio Technologies, Inc. | Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements |
US7115920B2 (en) | 2004-04-12 | 2006-10-03 | International Business Machines Corporation | FinFET transistor and circuit |
JP2007534258A (ja) | 2004-04-20 | 2007-11-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 低スキューの対称差動出力信号を有するレールツーレール同相モード動作を有する高速差動レシーバ |
EP1747520B1 (en) | 2004-05-07 | 2018-10-24 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
US7194712B2 (en) | 2004-05-12 | 2007-03-20 | Synopsys, Inc. | Method and apparatus for identifying line-end features for lithography verification |
US7053668B2 (en) | 2004-05-25 | 2006-05-30 | Kabushiki Kaisha Toshiba | SOI sense amplifier with cross-coupled body terminal |
US7426710B2 (en) | 2004-05-27 | 2008-09-16 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |
US6975133B1 (en) | 2004-05-27 | 2005-12-13 | International Business Machines Corporation | Logic circuits having linear and cellular gate transistors |
US7257017B2 (en) | 2004-05-28 | 2007-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cell for soft-error rate reduction and cell stability improvement |
KR100591158B1 (ko) | 2004-06-01 | 2006-06-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 게이트 전극의 제조 방법 |
US20070257277A1 (en) | 2004-06-04 | 2007-11-08 | Nec Corporation | Semiconductor Device and Method for Manufacturing the Same |
JP4834853B2 (ja) | 2004-06-10 | 2011-12-14 | シャープ株式会社 | 薄膜トランジスタ回路、薄膜トランジスタ回路の設計方法、薄膜トランジスタ回路の設計プログラム、設計プログラム記録媒体、及び表示装置 |
JP4248451B2 (ja) | 2004-06-11 | 2009-04-02 | パナソニック株式会社 | 半導体装置およびそのレイアウト設計方法 |
JP4778689B2 (ja) | 2004-06-16 | 2011-09-21 | パナソニック株式会社 | 標準セル、標準セルライブラリおよび半導体集積回路 |
US7327591B2 (en) | 2004-06-17 | 2008-02-05 | Texas Instruments Incorporated | Staggered memory cell array |
US7003068B2 (en) | 2004-06-21 | 2006-02-21 | Kenet, Inc. | Device for subtracting or adding a constant amount of charge in a charge-coupled device at high operating frequencies |
JP4405865B2 (ja) | 2004-06-24 | 2010-01-27 | 富士通マイクロエレクトロニクス株式会社 | 多層配線構造の製造方法及びfib装置 |
JP4175649B2 (ja) | 2004-07-22 | 2008-11-05 | 松下電器産業株式会社 | 半導体装置 |
AU2005269568A1 (en) | 2004-07-27 | 2006-02-09 | Easic Corporation | Structured integrated circuit device |
US7176508B2 (en) | 2004-07-27 | 2007-02-13 | International Business Machines Corporation | Temperature sensor for high power very large scale integration circuits |
JP2006049780A (ja) | 2004-08-09 | 2006-02-16 | Elpida Memory Inc | 半導体集積回路装置 |
US7093213B2 (en) | 2004-08-13 | 2006-08-15 | International Business Machines Corporation | Method for designing an integrated circuit defect monitor |
US7365432B2 (en) | 2004-08-23 | 2008-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell structure |
JP2006073696A (ja) | 2004-09-01 | 2006-03-16 | Matsushita Electric Ind Co Ltd | スタンダードセルを用いた半導体集積回路とその設計方法 |
US7632610B2 (en) | 2004-09-02 | 2009-12-15 | Intel Corporation | Sub-resolution assist features |
US7227183B2 (en) | 2004-09-17 | 2007-06-05 | International Business Machines Corporation | Polysilicon conductor width measurement for 3-dimensional FETs |
US20060063334A1 (en) | 2004-09-17 | 2006-03-23 | International Business Machines Corporation | Fin FET diode structures and methods for building |
US7185294B2 (en) | 2004-09-23 | 2007-02-27 | Verisilicon Holdings, Co Ltd | Standard cell library having globally scalable transistor channel length |
DE102004047263B4 (de) | 2004-09-24 | 2010-04-22 | Qimonda Ag | Verfahren zum Erzeugen eines Abbildungsfehler vermeidenden Maskenlayouts für eine Maske |
US7337421B2 (en) | 2004-09-30 | 2008-02-26 | Cadence Design Systems, Inc. | Method and system for managing design corrections for optical and process effects based on feature tolerances |
US7466607B2 (en) | 2004-09-30 | 2008-12-16 | Analog Devices, Inc. | Memory access system and method using de-coupled read and write circuits |
JP2006100718A (ja) | 2004-09-30 | 2006-04-13 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置の動作解析方法、これに用いられる解析装置およびこれを用いた最適化設計方法 |
JP2006114668A (ja) | 2004-10-14 | 2006-04-27 | Sony Corp | 半導体集積回路およびその製造方法 |
US7487475B1 (en) | 2004-10-15 | 2009-02-03 | Cadence Design Systems, Inc. | Systems, methods, and apparatus to perform statistical static timing analysis |
JP2006119195A (ja) | 2004-10-19 | 2006-05-11 | Nec Electronics Corp | 配線のレイアウト方法 |
US7302651B2 (en) | 2004-10-29 | 2007-11-27 | International Business Machines Corporation | Technology migration for integrated circuits with radical design restrictions |
US7458045B2 (en) | 2004-10-29 | 2008-11-25 | Synopsys, Inc. | Silicon tolerance specification using shapes as design intent markers |
US7278118B2 (en) | 2004-11-04 | 2007-10-02 | Pdf Solutions, Inc. | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features |
KR100587692B1 (ko) | 2004-11-05 | 2006-06-08 | 삼성전자주식회사 | 반도체 메모리 장치에서의 회로 배선 배치구조와 그에따른 배치방법 |
US7350183B2 (en) | 2004-11-05 | 2008-03-25 | International Business Machines Corporation | Method for improving optical proximity correction |
JP2006156778A (ja) | 2004-11-30 | 2006-06-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びそのレイアウト設計方法 |
US7424696B2 (en) | 2004-12-03 | 2008-09-09 | Lsi Corporation | Power mesh for multiple frequency operation of semiconductor products |
US7465973B2 (en) * | 2004-12-03 | 2008-12-16 | International Business Machines Corporation | Integrated circuit having gates and active regions forming a regular grating |
JP2006165365A (ja) | 2004-12-09 | 2006-06-22 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
US7345330B2 (en) | 2004-12-09 | 2008-03-18 | Omnivision Technologies, Inc. | Local interconnect structure and method for a CMOS image sensor |
JP4357409B2 (ja) * | 2004-12-17 | 2009-11-04 | 株式会社東芝 | 半導体集積回路装置及びその設計方法 |
US7396732B2 (en) | 2004-12-17 | 2008-07-08 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Formation of deep trench airgaps and related applications |
JP2007043049A (ja) | 2004-12-20 | 2007-02-15 | Matsushita Electric Ind Co Ltd | セル、スタンダードセル、スタンダードセル配置方法、スタンダードセルライブラリ、ならびに半導体集積回路 |
FR2879816B1 (fr) | 2004-12-20 | 2007-06-08 | Atmel Nantes Sa Sa | Circuit electronique comprenant au moins une premiere et une seconde paires differentielles dont les transistors partagent un meme caisson |
EP1833091A4 (en) | 2004-12-28 | 2008-08-13 | Spansion Llc | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING CONTROL |
US7106620B2 (en) | 2004-12-30 | 2006-09-12 | International Business Machines Corporation | Memory cell having improved read stability |
US7509621B2 (en) | 2005-01-03 | 2009-03-24 | Synopsys, Inc. | Method and apparatus for placing assist features by identifying locations of constructive and destructive interference |
US7366997B1 (en) | 2005-01-11 | 2008-04-29 | Synplicity, Inc. | Methods and apparatuses for thermal analysis based circuit design |
JP2006196627A (ja) | 2005-01-12 | 2006-07-27 | Nec Electronics Corp | 半導体装置、及び半導体装置の設計プログラム |
DE102005002533B4 (de) | 2005-01-14 | 2007-09-13 | Infineon Technologies Ag | Verfahren zum Erzeugen eines Abbildungsfehler vermeidenden Maskenlayouts für eine Maske |
JP4455356B2 (ja) | 2005-01-28 | 2010-04-21 | Necエレクトロニクス株式会社 | 半導体装置 |
KR20060092408A (ko) * | 2005-02-17 | 2006-08-23 | 삼성전자주식회사 | 고성능 배타적 오아 및 배타적 노아 회로 및 방법 |
JP4602112B2 (ja) | 2005-02-17 | 2010-12-22 | 株式会社東芝 | 半導体集積回路の製造方法及び半導体集積回路 |
JP5018475B2 (ja) | 2005-02-23 | 2012-09-05 | 富士通セミコンダクター株式会社 | 半導体回路装置及びその半導体回路装置の製造方法 |
US7266787B2 (en) | 2005-02-24 | 2007-09-04 | Icera, Inc. | Method for optimising transistor performance in integrated circuits |
US7200835B2 (en) | 2005-02-24 | 2007-04-03 | Texas Instruments Incorporated | Method of locating sub-resolution assist feature(s) |
US7287237B2 (en) | 2005-02-24 | 2007-10-23 | Icera Inc. | Aligned logic cell grid and interconnect routing architecture |
US7721246B2 (en) | 2005-02-24 | 2010-05-18 | Synopsys, Inc. | Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout |
US7421678B2 (en) | 2005-02-24 | 2008-09-02 | Synopsys, Inc. | Assist feature placement using a process-sensitivity model |
US7188322B2 (en) | 2005-02-25 | 2007-03-06 | International Business Machines Corporation | Circuit layout methodology using a shape processing application |
TWI281317B (en) | 2005-03-07 | 2007-05-11 | Sunplus Technology Co Ltd | Self DC-bias high frequency logic gate, NAND gate, and NOR gate using the same |
JP4309360B2 (ja) * | 2005-03-10 | 2009-08-05 | エルピーダメモリ株式会社 | 回路セル及び半導体装置 |
US7992122B1 (en) | 2005-03-25 | 2011-08-02 | Gg Technology, Inc. | Method of placing and routing for power optimization and timing closure |
US7563701B2 (en) * | 2005-03-31 | 2009-07-21 | Intel Corporation | Self-aligned contacts for transistors |
US7882456B2 (en) | 2005-04-09 | 2011-02-01 | Cadence Design Systems, Inc. | Optical lithography correction process |
CN1908812B (zh) | 2005-04-12 | 2012-02-22 | Asml蒙片工具有限公司 | 执行双重曝光光刻的方法、程序产品和设备 |
JP4634849B2 (ja) | 2005-04-12 | 2011-02-16 | 株式会社東芝 | 集積回路のパターンレイアウト、フォトマスク、半導体装置の製造方法、及びデータ作成方法 |
JP4921723B2 (ja) | 2005-04-18 | 2012-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
TWI297101B (en) | 2005-04-20 | 2008-05-21 | Nanya Technology Corp | Phase shifting mask for equal line/space dense line patterns |
CN101213489B (zh) * | 2005-04-26 | 2015-05-13 | 瑞萨电子株式会社 | 半导体装置及其制造方法和半导体制造用掩模、光接近处理方法 |
US7480891B2 (en) * | 2005-04-29 | 2009-01-20 | Cadence Design Systems, Inc. | Method and apparatus of model-based photomask synthesis |
US7506300B2 (en) | 2005-04-29 | 2009-03-17 | Cadence Design Systems, Inc. | Apparatus and method for breaking up and merging polygons |
US7441211B1 (en) | 2005-05-06 | 2008-10-21 | Blaze Dfm, Inc. | Gate-length biasing for digital circuit optimization |
US8044437B1 (en) | 2005-05-16 | 2011-10-25 | Lsi Logic Corporation | Integrated circuit cell architecture configurable for memory or logic elements |
JP4936418B2 (ja) | 2005-05-17 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置とその製造方法、及び半導体装置の設計プログラム |
US7308669B2 (en) | 2005-05-18 | 2007-12-11 | International Business Machines Corporation | Use of redundant routes to increase the yield and reliability of a VLSI layout |
JP4912016B2 (ja) | 2005-05-23 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP2006332348A (ja) * | 2005-05-26 | 2006-12-07 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法およびライブラリの設計方法 |
WO2006126125A1 (en) | 2005-05-26 | 2006-11-30 | Nxp B.V. | Electronic device |
US7411252B2 (en) | 2005-06-21 | 2008-08-12 | International Business Machines Corporation | Substrate backgate for trigate FET |
US7960791B2 (en) | 2005-06-24 | 2011-06-14 | International Business Machines Corporation | Dense pitch bulk FinFET process by selective EPI and etch |
US7492013B2 (en) | 2005-06-27 | 2009-02-17 | International Business Machines Corporation | Systems and arrangements to interconnect components of a semiconductor device |
US8405216B2 (en) * | 2005-06-29 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for integrated circuits |
WO2007002799A1 (en) * | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
US7236396B2 (en) * | 2005-06-30 | 2007-06-26 | Texas Instruments Incorporated | Area efficient implementation of small blocks in an SRAM array |
JP2007012855A (ja) | 2005-06-30 | 2007-01-18 | Matsushita Electric Ind Co Ltd | 半導体集積回路、標準セル、標準セルライブラリ、半導体集積回路の設計方法および半導体集積回路の設計装置 |
JP2007013060A (ja) | 2005-07-04 | 2007-01-18 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007018588A (ja) * | 2005-07-06 | 2007-01-25 | Toshiba Corp | 半導体記憶装置および半導体記憶装置の駆動方法 |
US7235424B2 (en) | 2005-07-14 | 2007-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for enhanced CMP planarization using surrounded dummy design |
JP2007027643A (ja) * | 2005-07-21 | 2007-02-01 | Matsushita Electric Ind Co Ltd | 半導体回路装置及びそのシミュレーション方法 |
EP1917715A2 (en) | 2005-07-22 | 2008-05-07 | Nanopower Technologies, Inc. | High sensitivity rfid tag integrated circuits |
CN101228478B (zh) | 2005-07-22 | 2012-08-08 | 富士通半导体股份有限公司 | 光掩模图形数据生成方法、用此数据生成的光掩模及用此掩模的半导体器件制造方法 |
US7404154B1 (en) | 2005-07-25 | 2008-07-22 | Lsi Corporation | Basic cell architecture for structured application-specific integrated circuits |
US7934172B2 (en) | 2005-08-08 | 2011-04-26 | Micronic Laser Systems Ab | SLM lithography: printing to below K1=.30 without previous OPC processing |
US7568174B2 (en) | 2005-08-19 | 2009-07-28 | Cadence Design Systems, Inc. | Method for checking printability of a lithography target |
JP2007073885A (ja) * | 2005-09-09 | 2007-03-22 | Renesas Technology Corp | 半導体集積回路 |
JP2007093861A (ja) | 2005-09-28 | 2007-04-12 | Renesas Technology Corp | マスクパターン設計方法および半導体装置の製造方法 |
US7749662B2 (en) | 2005-10-07 | 2010-07-06 | Globalfoundries Inc. | Process margin using discrete assist features |
US7485934B2 (en) | 2005-10-25 | 2009-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated semiconductor structure for SRAM cells |
US7397260B2 (en) | 2005-11-04 | 2008-07-08 | International Business Machines Corporation | Structure and method for monitoring stress-induced degradation of conductive interconnects |
US20070106971A1 (en) | 2005-11-04 | 2007-05-10 | Lizotech, Inc. | Apparatus for a routing system |
US7569309B2 (en) | 2005-11-09 | 2009-08-04 | Texas Instruments Incorporated | Gate critical dimension variation by use of ghost features |
US7527900B2 (en) | 2005-11-10 | 2009-05-05 | United Microelectronics Corp. | Reticle and optical proximity correction method |
US7543262B2 (en) | 2005-12-06 | 2009-06-02 | Cadence Design Systems, Inc. | Analog layout module generator and method |
US7569310B2 (en) | 2005-12-07 | 2009-08-04 | Intel Corporation | Sub-resolution assist features for photolithography with trim ends |
US7512017B2 (en) | 2005-12-21 | 2009-03-31 | Intel Corporation | Integration of planar and tri-gate devices on the same substrate |
JP4774294B2 (ja) | 2005-12-26 | 2011-09-14 | 富士通株式会社 | 集積回路レイアウト装置、その方法及びプログラム |
EP1804282A1 (en) | 2005-12-29 | 2007-07-04 | Interuniversitair Microelektronica Centrum vzw ( IMEC) | Methods for manufacturing dense integrated circuits |
US7640522B2 (en) | 2006-01-14 | 2009-12-29 | Tela Innovations, Inc. | Method and system for placing layout objects in a standard-cell layout |
US7614030B2 (en) | 2006-01-17 | 2009-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Scattering bar OPC application method for mask ESD prevention |
JP4347304B2 (ja) * | 2006-01-24 | 2009-10-21 | Sriスポーツ株式会社 | ゴルフボール |
JP4675249B2 (ja) | 2006-02-07 | 2011-04-20 | パナソニック株式会社 | 位置依存変動量計算方法並びに回路解析方法 |
US7480880B2 (en) | 2006-02-21 | 2009-01-20 | International Business Machines Corporation | Method, system, and program product for computing a yield gradient from statistical timing |
US7469401B2 (en) | 2006-02-22 | 2008-12-23 | International Business Machines Corporation | Method for using partitioned masks to build a chip |
US8225261B2 (en) * | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US7943967B2 (en) * | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US7932545B2 (en) * | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
JP2007265179A (ja) | 2006-03-29 | 2007-10-11 | Fujitsu Ltd | レイアウト検証方法、レイアウト検証装置 |
JP4882455B2 (ja) | 2006-03-31 | 2012-02-22 | 富士通セミコンダクター株式会社 | 半導体集積回路のユニットセルおよびユニットセルを使用した配線方法および配線プログラム |
US7437691B2 (en) | 2006-04-11 | 2008-10-14 | International Business Machines Corporation | VLSI artwork legalization for hierarchical designs with multiple grid constraints |
US7484197B2 (en) | 2006-04-14 | 2009-01-27 | International Business Machines Corporation | Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs |
US7509622B2 (en) | 2006-04-17 | 2009-03-24 | Synopsys, Inc. | Dummy filling technique for improved planarization of chip surface topography |
JP5579959B2 (ja) * | 2006-04-18 | 2014-08-27 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
US7407890B2 (en) | 2006-04-21 | 2008-08-05 | International Business Machines Corporation | Patterning sub-lithographic features with variable widths |
US7355906B2 (en) | 2006-05-24 | 2008-04-08 | International Business Machines Corporation | SRAM cell design to improve stability |
US7941776B2 (en) | 2006-05-26 | 2011-05-10 | Open-Silicon Inc. | Method of IC design optimization via creation of design-specific cells from post-layout patterns |
WO2007149004A1 (en) | 2006-06-13 | 2007-12-27 | Freescale Semiconductor, Inc. | Methods and apparatus for simulating distributed effects |
US7317339B1 (en) | 2006-06-16 | 2008-01-08 | Via Technologies, Inc. | N-domino register with accelerated non-discharge path |
US7459792B2 (en) | 2006-06-19 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via layout with via groups placed in interlocked arrangement |
US7992117B2 (en) | 2006-06-20 | 2011-08-02 | Adtran, Inc. | System and method for designing a common centroid layout for an integrated circuit |
JP2008004796A (ja) | 2006-06-23 | 2008-01-10 | Matsushita Electric Ind Co Ltd | 半導体装置および回路素子レイアウト方法 |
US7444609B2 (en) | 2006-06-29 | 2008-10-28 | International Business Machines Corporation | Method of optimizing customizable filler cells in an integrated circuit physical design process |
US7763932B2 (en) | 2006-06-29 | 2010-07-27 | International Business Machines Corporation | Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices |
US7739627B2 (en) | 2006-07-05 | 2010-06-15 | Chew Marko P | System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells |
JP2008027940A (ja) | 2006-07-18 | 2008-02-07 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法および回路シミュレーション方法 |
DE102006037162B4 (de) | 2006-08-01 | 2008-08-21 | Qimonda Ag | Verfahren und Vorrichtung und deren Verwendung zur Prüfung des Layouts einer elektronischen Schaltung |
JP5080578B2 (ja) | 2006-08-04 | 2012-11-21 | サガンテック イスラエル リミテッド | 回路レイアウトを所定のグリッドに適応させるための方法及びシステム |
US7966579B2 (en) | 2006-08-04 | 2011-06-21 | Infineon Technologies Ag | Methods of optical proximity correction |
US7873929B2 (en) * | 2006-08-14 | 2011-01-18 | The Regents Of The University Of California | Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction |
US7886262B2 (en) | 2006-08-15 | 2011-02-08 | Chew Marko P | System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization |
TW200811704A (en) | 2006-08-31 | 2008-03-01 | Univ Nat Yunlin Sci & Tech | Full adder of complementary type carry logic voltage compensator |
US7434185B2 (en) | 2006-09-27 | 2008-10-07 | International Business Machines Corporation | Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data |
JP4362785B2 (ja) | 2006-09-28 | 2009-11-11 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US20080082952A1 (en) | 2006-09-29 | 2008-04-03 | Texas Instruments Incorporated | Method of inclusion of sub-resolution assist feature(s) |
JP4814044B2 (ja) | 2006-10-05 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | パターン設計方法 |
JP2008103610A (ja) | 2006-10-20 | 2008-05-01 | Matsushita Electric Ind Co Ltd | 半導体集積回路の配線構造およびその設計方法と設計装置 |
US8230379B2 (en) | 2006-10-20 | 2012-07-24 | Kabushiki Kaisha Toshiba | Layout generating method for semiconductor integrated circuits |
US7624369B2 (en) | 2006-10-31 | 2009-11-24 | International Business Machines Corporation | Closed-loop design for manufacturability process |
US7802219B2 (en) | 2006-11-30 | 2010-09-21 | Cadence Design Systems, Inc. | Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout |
US7774739B2 (en) | 2006-11-30 | 2010-08-10 | Texas Instruments Incorporated | Methods for adjusting shifter width of an alternating phase shifter having variable width |
US8378407B2 (en) | 2006-12-07 | 2013-02-19 | Tower Semiconductor, Ltd. | Floating gate inverter type memory cell and array |
US8156450B2 (en) | 2006-12-18 | 2012-04-10 | Cadence Design Systems, Inc. | Method and system for mask optimization |
US7814447B2 (en) | 2006-12-29 | 2010-10-12 | Cadence Design Systems, Inc. | Supplant design rules in electronic designs |
US8178905B2 (en) | 2007-01-12 | 2012-05-15 | Panasonic Corporation | Layout structure of semiconductor device |
JP5217180B2 (ja) | 2007-02-20 | 2013-06-19 | 富士通セミコンダクター株式会社 | 静電放電保護装置の製造方法 |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US20080216207A1 (en) | 2007-03-09 | 2008-09-11 | Shen-Hai Tsai | Finger pressing massage glove |
KR100911187B1 (ko) * | 2007-03-13 | 2009-08-06 | 주식회사 하이닉스반도체 | 래치 구조 및 그것을 포함하는 비트라인 센스앰프 구조 |
US7575973B2 (en) | 2007-03-27 | 2009-08-18 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7543252B2 (en) | 2007-03-28 | 2009-06-02 | International Business Machines Corporation | Migration of integrated circuit layout for alternating phase shift masks |
US7791109B2 (en) | 2007-03-29 | 2010-09-07 | International Business Machines Corporation | Metal silicide alloy local interconnect |
US7757196B2 (en) | 2007-04-04 | 2010-07-13 | Cisco Technology, Inc. | Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards |
US7723786B2 (en) | 2007-04-11 | 2010-05-25 | Ronald Kakoschke | Apparatus of memory array using FinFETs |
US7964267B1 (en) | 2007-04-13 | 2011-06-21 | Bae Systems Tensylon H.P.M., Inc. | Ballistic-resistant panel including high modulus ultra high molecular weight polyethylene tape |
US7453125B1 (en) | 2007-04-24 | 2008-11-18 | Infineon Technologies Ag | Double mesh finfet |
JP4461154B2 (ja) | 2007-05-15 | 2010-05-12 | 株式会社東芝 | 半導体装置 |
US20080283910A1 (en) | 2007-05-15 | 2008-11-20 | Qimonda Ag | Integrated circuit and method of forming an integrated circuit |
US7911830B2 (en) | 2007-05-17 | 2011-03-22 | Integrated Magnetoelectronics | Scalable nonvolatile memory |
JP4445521B2 (ja) | 2007-06-15 | 2010-04-07 | 株式会社東芝 | 半導体装置 |
US7898040B2 (en) | 2007-06-18 | 2011-03-01 | Infineon Technologies Ag | Dual gate FinFET |
US7923337B2 (en) | 2007-06-20 | 2011-04-12 | International Business Machines Corporation | Fin field effect transistor devices with self-aligned source and drain regions |
US7759194B2 (en) | 2008-07-25 | 2010-07-20 | Semiconductor Manufacturing International (Shanghai) Corporation | Electrically programmable device with embedded EEPROM and method for making thereof |
JP2009025914A (ja) | 2007-07-17 | 2009-02-05 | Nec Electronics Corp | 半導体集積回路の設計方法及び設計プログラム |
US7625790B2 (en) | 2007-07-26 | 2009-12-01 | International Business Machines Corporation | FinFET with sublithographic fin width |
US7700466B2 (en) | 2007-07-26 | 2010-04-20 | International Business Machines Corporation | Tunneling effect transistor with self-aligned gate |
US20090057780A1 (en) | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Finfet structure including multiple semiconductor fin channel heights |
US8156451B2 (en) | 2007-09-14 | 2012-04-10 | Renesas Electronics Corporation | Method of manufacturing photomask |
KR100905157B1 (ko) | 2007-09-18 | 2009-06-29 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
JP2009088085A (ja) | 2007-09-28 | 2009-04-23 | Tokyo Electron Ltd | 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びプログラム記憶媒体 |
US20090101940A1 (en) | 2007-10-19 | 2009-04-23 | Barrows Corey K | Dual gate fet structures for flexible gate array design methodologies |
US8042070B2 (en) | 2007-10-23 | 2011-10-18 | International Business Machines Corporation | Methods and system for analysis and management of parametric yield |
JP2009130238A (ja) | 2007-11-27 | 2009-06-11 | Fujitsu Microelectronics Ltd | 半導体装置 |
JP5193582B2 (ja) | 2007-12-12 | 2013-05-08 | 株式会社東芝 | 半導体装置の製造方法 |
WO2009078069A1 (ja) | 2007-12-14 | 2009-06-25 | Fujitsu Limited | 半導体装置 |
US7825437B2 (en) | 2007-12-28 | 2010-11-02 | Intel Corporation | Unity beta ratio tri-gate transistor static random access memory (SRAM) |
PL2235453T3 (pl) * | 2007-12-31 | 2017-02-28 | Arçelik Anonim Sirketi | Urządzenie chłodzące |
US7816740B2 (en) | 2008-01-04 | 2010-10-19 | Texas Instruments Incorporated | Memory cell layout structure with outer bitline |
US7934173B2 (en) | 2008-01-14 | 2011-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reverse dummy insertion algorithm |
US7926001B2 (en) | 2008-01-16 | 2011-04-12 | Cadence Design Systems, Inc. | Uniformity for semiconductor patterning operations |
US7984395B2 (en) | 2008-01-17 | 2011-07-19 | Synopsys, Inc. | Hierarchical compression for metal one logic layer |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8866254B2 (en) | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
US8423947B2 (en) | 2008-03-13 | 2013-04-16 | International Business Machines Corporation | Gridded glyph geometric objects (L3GO) design method |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US8173544B2 (en) | 2008-05-02 | 2012-05-08 | Texas Instruments Incorporated | Integrated circuit having interleaved gridded features, mask set and method for printing |
US7958465B2 (en) | 2008-05-08 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy pattern design for reducing device performance drift |
EP2117045A1 (en) | 2008-05-09 | 2009-11-11 | Imec | Design Methodology for MuGFET ESD Protection Devices |
US7917877B2 (en) | 2008-05-09 | 2011-03-29 | Cadence Design Systems, Inc. | System and method for circuit schematic generation |
US7853915B2 (en) | 2008-06-24 | 2010-12-14 | Synopsys, Inc. | Interconnect-driven physical synthesis using persistent virtual routing |
US8516819B2 (en) * | 2008-07-16 | 2013-08-27 | Siemens Energy, Inc. | Forward-section resonator for high frequency dynamic damping |
KR101749351B1 (ko) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US8136072B2 (en) | 2008-11-03 | 2012-03-13 | Arm Limited | Standard cell placement |
US8363455B2 (en) | 2008-12-04 | 2013-01-29 | David Rennie | Eight transistor soft error robust storage cell |
US8116121B2 (en) | 2009-03-06 | 2012-02-14 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing methods with using non-planar type of transistors |
WO2010099673A1 (en) | 2009-03-06 | 2010-09-10 | Kaixin Inc. | Leadless integrated circuit package having high density contacts |
US8184472B2 (en) | 2009-03-13 | 2012-05-22 | International Business Machines Corporation | Split-gate DRAM with lateral control-gate MuGFET |
US8004042B2 (en) | 2009-03-20 | 2011-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Static random access memory (SRAM) cell and method for forming same |
US8053299B2 (en) | 2009-04-17 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
US8076236B2 (en) | 2009-06-01 | 2011-12-13 | Globalfoundries Inc. | SRAM bit cell with self-aligned bidirectional local interconnects |
US8294212B2 (en) | 2009-09-18 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed |
US8675397B2 (en) | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
US8860107B2 (en) | 2010-06-03 | 2014-10-14 | International Business Machines Corporation | FinFET-compatible metal-insulator-metal capacitor |
US8839162B2 (en) | 2010-07-14 | 2014-09-16 | International Business Machines Corporation | Specifying circuit level connectivity during circuit design synthesis |
US8796759B2 (en) | 2010-07-15 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8402397B2 (en) | 2011-07-26 | 2013-03-19 | Mentor Graphics Corporation | Hotspot detection based on machine learning |
US8689164B2 (en) | 2011-10-18 | 2014-04-01 | National Taiwan University | Method of analytical placement with weighted-average wirelength model |
US9006841B2 (en) | 2011-12-30 | 2015-04-14 | Stmicroelectronics International N.V. | Dual port SRAM having reduced cell size and rectangular shape |
FR2996950B1 (fr) | 2012-10-11 | 2016-01-01 | Dolphin Integration Sa | Réseau de mémoire base sur des bascules |
-
2008
- 2008-01-11 US US12/013,356 patent/US7908578B2/en not_active Expired - Fee Related
- 2008-01-11 US US12/013,366 patent/US7888705B2/en not_active Expired - Fee Related
- 2008-01-11 US US12/013,342 patent/US7917879B2/en not_active Expired - Fee Related
- 2008-07-31 EP EP08794989A patent/EP2186136A4/en not_active Withdrawn
- 2008-07-31 WO PCT/US2008/009335 patent/WO2009017828A2/en active Application Filing
- 2008-07-31 JP JP2010526886A patent/JP4991938B2/ja not_active Expired - Fee Related
- 2008-08-01 TW TW097129267A patent/TWI389298B/zh not_active IP Right Cessation
-
2011
- 2011-01-14 US US13/007,584 patent/US8283701B2/en not_active Expired - Fee Related
- 2011-01-14 US US13/007,582 patent/US8759882B2/en not_active Expired - Fee Related
- 2011-03-14 US US13/047,474 patent/US8756551B2/en not_active Expired - Fee Related
- 2011-03-28 US US13/073,994 patent/US8356268B2/en active Active
-
2012
- 2012-01-27 JP JP2012015484A patent/JP5758815B2/ja not_active Expired - Fee Related
-
2014
- 2014-05-13 US US14/276,528 patent/US9595515B2/en active Active
-
2015
- 2015-03-23 JP JP2015059324A patent/JP6093794B2/ja not_active Expired - Fee Related
-
2016
- 2016-09-02 JP JP2016171635A patent/JP6289567B2/ja not_active Expired - Fee Related
-
2017
- 2017-03-13 US US15/457,997 patent/US20170186772A1/en not_active Abandoned
- 2017-11-27 JP JP2017227099A patent/JP2018050072A/ja active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09282349A (ja) * | 1996-04-17 | 1997-10-31 | Shinko Electric Ind Co Ltd | データ変換処理装置 |
JP2001166452A (ja) * | 1999-12-03 | 2001-06-22 | Toshiba Microelectronics Corp | パターンの自動設計方法 |
JP2001351981A (ja) * | 2000-06-06 | 2001-12-21 | Asahi Kasei Microsystems Kk | セルの配置方法およびその配置装置 |
JP2005123537A (ja) * | 2003-10-20 | 2005-05-12 | Sony Corp | 半導体装置及び製造方法 |
JP2007123682A (ja) * | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム |
US20070113216A1 (en) * | 2005-11-14 | 2007-05-17 | Youping Zhang | Photolithographic mask correction |
JP2007141971A (ja) * | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019526170A (ja) * | 2016-07-12 | 2019-09-12 | エーティーアイ・テクノロジーズ・ユーエルシーAti Technologies Ulc | セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 |
JP7015824B2 (ja) | 2016-07-12 | 2022-02-03 | エーティーアイ・テクノロジーズ・ユーエルシー | セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 |
Also Published As
Publication number | Publication date |
---|---|
JP6093794B2 (ja) | 2017-03-08 |
JP2018050072A (ja) | 2018-03-29 |
US20090032967A1 (en) | 2009-02-05 |
TWI389298B (zh) | 2013-03-11 |
TW200924163A (en) | 2009-06-01 |
US7888705B2 (en) | 2011-02-15 |
JP2012124510A (ja) | 2012-06-28 |
US20170186772A1 (en) | 2017-06-29 |
US9595515B2 (en) | 2017-03-14 |
US20090037864A1 (en) | 2009-02-05 |
US20110108891A1 (en) | 2011-05-12 |
JP2011501876A (ja) | 2011-01-13 |
US20110175144A1 (en) | 2011-07-21 |
US8356268B2 (en) | 2013-01-15 |
JP4991938B2 (ja) | 2012-08-08 |
US7917879B2 (en) | 2011-03-29 |
US20110108890A1 (en) | 2011-05-12 |
US20110161909A1 (en) | 2011-06-30 |
WO2009017828A2 (en) | 2009-02-05 |
WO2009017828A3 (en) | 2009-04-30 |
JP2016225648A (ja) | 2016-12-28 |
US7908578B2 (en) | 2011-03-15 |
JP6289567B2 (ja) | 2018-03-07 |
EP2186136A4 (en) | 2011-09-07 |
US8759882B2 (en) | 2014-06-24 |
US20140246733A1 (en) | 2014-09-04 |
US8283701B2 (en) | 2012-10-09 |
EP2186136A2 (en) | 2010-05-19 |
US20090032898A1 (en) | 2009-02-05 |
JP5758815B2 (ja) | 2015-08-05 |
US8756551B2 (en) | 2014-06-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6289567B2 (ja) | 集積回路デバイス | |
JP5260325B2 (ja) | ダイナミックアレイ・アーキテクチャ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160407 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160412 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20160711 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160902 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20161004 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161222 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170124 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170213 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6093794 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |