JP7015824B2 - セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 - Google Patents
セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 Download PDFInfo
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- JP7015824B2 JP7015824B2 JP2019500874A JP2019500874A JP7015824B2 JP 7015824 B2 JP7015824 B2 JP 7015824B2 JP 2019500874 A JP2019500874 A JP 2019500874A JP 2019500874 A JP2019500874 A JP 2019500874A JP 7015824 B2 JP7015824 B2 JP 7015824B2
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- 239000002184 metal Substances 0.000 title claims description 216
- 238000003860 storage Methods 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 238000013461 design Methods 0.000 description 77
- 238000013459 approach Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 16
- 230000007717 exclusion Effects 0.000 description 15
- 230000008901 benefit Effects 0.000 description 11
- 230000006870 function Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000005291 magnetic effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 230000002730 additional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000012942 design verification Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11875—Wiring region, routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
Claims (16)
- 半導体基板の直交する第1方向及び第2方向に沿って延在し、セル境界を有する第1セルと、
前記第1方向及び第2方向に沿って延在し、前記第1セルの前記セル境界の第1端部に隣接する第2端部を有するセル境界を含む第2セルと、を備え、
前記第1セルは、
M1金属層の第1金属トラックにおける第1金属セグメントであって、前記第1方向に沿って延在し、前記セル境界の第1端部を越えた所定の第1距離の位置において終端する第1金属セグメントと、
前記第1セルの前記セル境界の外側に延在するピンであって、前記第1金属セグメントに接続されたピンと、を含み、
前記第1金属セグメントは、前記M1金属層の前記第2セルの第1金属トラック内に延在する、
集積回路構造。 - 前記第1セルは、
前記第1方向に沿って延在し、前記第1端部の前方の少なくとも所定の第2距離の位置において終端する第2金属セグメントを、前記M1金属層の第2金属トラックに含む、
請求項1の集積回路構造。 - 前記所定の第1距離と前記所定の第2距離とが等しい、
請求項2の集積回路構造。 - 前記第1金属セグメントは、前記セル境界の第2端部の前方の少なくとも前記所定の第2距離の位置において終端し、前記第2端部は前記第1端部の反対側にある、
請求項2の集積回路構造。 - 前記第2金属セグメントは、前記セル境界の前記第2端部の前方の少なくとも前記所定の第2距離の位置において終端する、
請求項4の集積回路構造。 - 前記所定の第1距離と前記所定の第2距離とが等しい、
請求項5の集積回路構造。 - 前記第2セルは、
前記第1方向に沿って延在し、前記第2端部を越えた前記所定の第1距離の位置において終端する第2金属セグメントを、前記M1金属層の第2金属トラックに含み、
前記第2金属セグメントは、前記M1金属層の前記第1セルの第2金属トラック内に延在する、
請求項1の集積回路構造。 - 前記第1セルの前記第1金属トラックの残りの部分は、前記M1金属層で金属が欠けている、
請求項1の集積回路構造。 - 前記第1セルの前記第1金属トラックの残りの部分は、前記M1金属層においてスタブ配線を含む、
請求項1の集積回路構造。 - 集積回路構造を製造するための実行可能な命令のセットを具現化するコンピュータ可読記憶媒体であって、
前記実行可能な命令のセットは、
第1セルのセル境界を直交する第1方向及び第2方向に沿って延在させることによって、集積回路構造を構築することと、
第1金属セグメントを第1金属層の第1金属トラックに形成することであって、前記第1金属セグメントは、第1方向に沿って延在し、前記セル境界の第1端部を越えた所定の第1距離の位置において終端する、ことと、
前記第1セルの前記セル境界の外側の前記第1金属層のピンを、前記第1金属セグメントに接続することと、
第2セルのセル境界の第2端部を、前記第1セルの前記セル境界の前記第1端部に当接させることと、を行い、
前記第1金属セグメントは、前記第1金属層の第2セルの第1金属トラック内に延在する、
コンピュータ可読記憶媒体。 - 前記実行可能な命令のセットは、
前記第1方向に沿って延在し、前記第1端部の前方の所定の第2距離の位置において終端する第2金属セグメントを、前記第1金属層の第2金属トラックに形成することを行う、
請求項10のコンピュータ可読記憶媒体。 - 前記第1金属セグメントは、前記セル境界の第2端部の前方の前記所定の第2距離の位置において終端し、前記第2端部は前記第1端部の反対側にある、
請求項11のコンピュータ可読記憶媒体。 - 前記第2金属セグメントは、前記セル境界の前記第2端部の前方の前記所定の第2距離の位置において終端する、
請求項12のコンピュータ可読記憶媒体。 - 前記所定の第1距離と前記所定の第2距離とが等しい、
請求項13のコンピュータ可読記憶媒体。 - 前記第2セルは、前記第1方向に沿って延在し、前記第2端部を越えた前記所定の第1距離の位置において終端する第2金属セグメントを、前記第1金属層の第2金属トラックに含み、
前記第2金属セグメントは、前記第1金属層の前記第1セルの第2金属トラック内に延在する、
請求項10のコンピュータ可読記憶媒体。 - 前記実行可能な命令のセットは、
前記第1金属トラックの残りの部分を使用して、前記第1金属層にスタブを配線することを行う、
請求項10のコンピュータ可読記憶媒体。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US15/207,691 US9977854B2 (en) | 2016-07-12 | 2016-07-12 | Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary |
US15/207,691 | 2016-07-12 | ||
PCT/US2017/041349 WO2018013472A1 (en) | 2016-07-12 | 2017-07-10 | Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary |
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JP2019526170A JP2019526170A (ja) | 2019-09-12 |
JP2019526170A5 JP2019526170A5 (ja) | 2020-08-13 |
JP7015824B2 true JP7015824B2 (ja) | 2022-02-03 |
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US (1) | US9977854B2 (ja) |
EP (1) | EP3270414A1 (ja) |
JP (1) | JP7015824B2 (ja) |
KR (1) | KR102294210B1 (ja) |
CN (1) | CN109791930B (ja) |
TW (1) | TWI732900B (ja) |
WO (1) | WO2018013472A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102458446B1 (ko) * | 2016-03-03 | 2022-10-26 | 삼성전자주식회사 | 스탠다드 셀을 포함하는 반도체 장치 및 그것의 전자 설계 자동화 방법 |
US10691849B2 (en) * | 2017-09-28 | 2020-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal cut optimization for standard cells |
US10559558B2 (en) | 2017-09-29 | 2020-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pin modification for standard cells |
TWI681309B (zh) * | 2018-05-10 | 2020-01-01 | 瑞昱半導體股份有限公司 | 電子裝置測試資料庫產生方法 |
US10784869B2 (en) * | 2018-07-16 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit and method of manufacturing the same |
US10997348B2 (en) | 2018-09-28 | 2021-05-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal cut region location method and system |
US10769342B2 (en) * | 2018-10-31 | 2020-09-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Pin access hybrid cell height design |
US11011417B2 (en) | 2019-05-31 | 2021-05-18 | International Business Machines Corporation | Method and structure of metal cut |
US10909297B1 (en) * | 2019-08-15 | 2021-02-02 | Taiwan Semiconductor Manufacturing Company Limited | Deterministic system for device layout optimization |
CN114730353A (zh) * | 2019-12-09 | 2022-07-08 | 美商新思科技有限公司 | 使用具有金属线的单元进行电路设计 |
US11290109B1 (en) * | 2020-09-23 | 2022-03-29 | Qualcomm Incorporated | Multibit multi-height cell to improve pin accessibility |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007123682A (ja) | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム |
JP2015149491A (ja) | 2007-08-02 | 2015-08-20 | テラ イノヴェイションズ インク | 半導体チップ、定義方法および設計方法 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04216668A (ja) * | 1990-12-15 | 1992-08-06 | Sharp Corp | 半導体集積回路 |
US6174742B1 (en) | 1998-10-30 | 2001-01-16 | Lsi Logic Corporation | Off-grid metal layer utilization |
US7036103B2 (en) * | 1999-10-14 | 2006-04-25 | Synopsys, Inc. | Detailed placer for optimizing high density cell placement in a linear runtime |
US6351841B1 (en) | 2000-03-21 | 2002-02-26 | Cadence Design Systems, Inc. | Method and apparatus for creating multi-gate transistors with integrated circuit polygon compactors |
US7089521B2 (en) * | 2004-01-27 | 2006-08-08 | International Business Machines Corporation | Method for legalizing the placement of cells in an integrated circuit layout |
US6903389B1 (en) | 2004-06-15 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Variable layout design for multiple voltage applications |
US7194717B2 (en) * | 2004-09-08 | 2007-03-20 | Lsi Logic Corporation | Compact custom layout for RRAM column controller |
US7640522B2 (en) * | 2006-01-14 | 2009-12-29 | Tela Innovations, Inc. | Method and system for placing layout objects in a standard-cell layout |
US7564077B2 (en) * | 2006-05-05 | 2009-07-21 | Texas Instruments Incorporated | Performance and area scalable cell architecture technology |
JP5599395B2 (ja) * | 2008-07-16 | 2014-10-01 | テラ イノヴェイションズ インコーポレイテッド | 動的アレイアーキテクチャにおけるセル位相整合及び配置の方法及びその実施 |
US8136072B2 (en) * | 2008-11-03 | 2012-03-13 | Arm Limited | Standard cell placement |
US7919792B2 (en) | 2008-12-18 | 2011-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell architecture and methods with variable design rules |
US8661392B2 (en) * | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
JP5325162B2 (ja) * | 2010-05-18 | 2013-10-23 | パナソニック株式会社 | 半導体装置 |
US8423946B1 (en) * | 2010-05-25 | 2013-04-16 | Marvell International Ltd. | Circuitry having programmable power rails, architectures, apparatuses, and systems including the same, and methods and algorithms for programming and/or configuring power rails in an integrated circuit |
US8431968B2 (en) | 2010-07-28 | 2013-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electromigration resistant standard cell device |
US8742464B2 (en) | 2011-03-03 | 2014-06-03 | Synopsys, Inc. | Power routing in standard cells |
US8612914B2 (en) * | 2011-03-23 | 2013-12-17 | Synopsys, Inc. | Pin routing in standard cells |
US8513978B2 (en) * | 2011-03-30 | 2013-08-20 | Synopsys, Inc. | Power routing in standard cell designs |
US8451026B2 (en) * | 2011-05-13 | 2013-05-28 | Arm Limited | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells |
US8987831B2 (en) | 2012-01-12 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cells and arrays |
US9659129B2 (en) | 2013-05-02 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell having cell height being non-integral multiple of nominal minimum pitch |
CN104134657B (zh) * | 2013-05-02 | 2018-01-26 | 台湾积体电路制造股份有限公司 | 单元高度为标称最小间距的非整数倍的标准单元 |
KR102152772B1 (ko) * | 2013-11-18 | 2020-09-08 | 삼성전자 주식회사 | 레이아웃 디자인 시스템, 레이아웃 디자인 방법, 및 이를 이용하여 제조된 반도체 장치 |
US9876017B2 (en) * | 2014-12-03 | 2018-01-23 | Qualcomm Incorporated | Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells |
US9727685B2 (en) * | 2015-05-14 | 2017-08-08 | Globalfoundries Inc. | Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability |
KR102504289B1 (ko) * | 2016-04-07 | 2023-02-28 | 삼성전자 주식회사 | 인접 핀들 사이의 라우팅 간섭을 제거하는 구조를 갖는 표준 셀과 이를 포함하는 장치 |
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2016
- 2016-07-12 US US15/207,691 patent/US9977854B2/en active Active
- 2016-12-20 EP EP16205250.0A patent/EP3270414A1/en active Pending
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2017
- 2017-07-10 CN CN201780043776.3A patent/CN109791930B/zh active Active
- 2017-07-10 WO PCT/US2017/041349 patent/WO2018013472A1/en active Application Filing
- 2017-07-10 JP JP2019500874A patent/JP7015824B2/ja active Active
- 2017-07-10 KR KR1020197003688A patent/KR102294210B1/ko active IP Right Grant
- 2017-07-12 TW TW106123326A patent/TWI732900B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007123682A (ja) | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム |
JP2015149491A (ja) | 2007-08-02 | 2015-08-20 | テラ イノヴェイションズ インク | 半導体チップ、定義方法および設計方法 |
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Publication number | Publication date |
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US20180018419A1 (en) | 2018-01-18 |
TWI732900B (zh) | 2021-07-11 |
US9977854B2 (en) | 2018-05-22 |
CN109791930B (zh) | 2021-08-27 |
TW201813050A (zh) | 2018-04-01 |
JP2019526170A (ja) | 2019-09-12 |
CN109791930A (zh) | 2019-05-21 |
EP3270414A1 (en) | 2018-01-17 |
KR102294210B1 (ko) | 2021-08-27 |
KR20190018542A (ko) | 2019-02-22 |
WO2018013472A1 (en) | 2018-01-18 |
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