TW201814835A - 積體電路中採用之自對準局部互連線用之方法、結構與設計 - Google Patents
積體電路中採用之自對準局部互連線用之方法、結構與設計 Download PDFInfo
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- TW201814835A TW201814835A TW106145373A TW106145373A TW201814835A TW 201814835 A TW201814835 A TW 201814835A TW 106145373 A TW106145373 A TW 106145373A TW 106145373 A TW106145373 A TW 106145373A TW 201814835 A TW201814835 A TW 201814835A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000013461 design Methods 0.000 title abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 145
- 125000006850 spacer group Chemical group 0.000 claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 claims description 30
- 238000000465 moulding Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 abstract description 38
- 238000002955 isolation Methods 0.000 abstract description 7
- 239000002184 metal Substances 0.000 description 62
- 229910052751 metal Inorganic materials 0.000 description 62
- 229920000642 polymer Polymers 0.000 description 25
- 230000008569 process Effects 0.000 description 22
- 238000005530 etching Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 15
- 229910021332 silicide Inorganic materials 0.000 description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 14
- 230000008901 benefit Effects 0.000 description 12
- 230000003993 interaction Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000001459 lithography Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- 238000005452 bending Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000012937 correction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000001066 destructive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007792 addition Methods 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000009194 climbing Effects 0.000 description 2
- 238000001125 extrusion Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/62—Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
提供自對準局部互連線的方法、結構與設計。此方法包括於一基板中設計不同擴散區。複數個閘極中的若干個係設計為有效閘極,而複數個閘極中的若干個係設計為於隔絕區上形成。此方法包括沿著相同方向以規則且重複的排列方式設計複數個閘極,且此複數個閘極中的每一個係設計為具有介電間隔部。此方法也包括於複數個閘極之間或毗鄰複數個閘極而設計一局部互連層。此局部互連層有導電性且設置於基板上以允許與有效閘極之若干擴散區的電性接觸或互連。藉由此複數個閘極的介電間隔部而使此局部互連層自我對準。
Description
本發明係關於積體電路,尤有關於用於積體電路中互連半導體裝置的自對準局部互連線的設計與製造,但非限之。
隨著半導體技術持續進步,持續的趨勢係朝向帶有越來越小積體電路之製造的超大規模積集度,其於單一半導體晶片上包含越來越多的裝置。
裝置的尺寸縮小長久來係用以增加邏輯與記憶功能的密度。因光刻與其它處理步驟的改進,此尺寸縮小已是可行的。然而,隨著光學微影達到成本效益改善曲線之末端,需要其它方法以改善密度。
在半導體晶片中,互連線提供NMOS及PMOS電晶體與其它如電阻及電容的單元之間的連接。通常藉由於半導體裝置與被動單元上首先沉積介電層與使其平坦化而製造互連線。接著,在介電層中形成連通線(feed-thrus)。最後,在介電層上形成與定義導線路徑以連接連通線。層疊係由多層介電質、連通線,與導線所形成,以完成電路節點互連。製造互連線的此過程通常稱『金屬噴敷』(metallization)。隨著半導體晶片上裝置之密度的增加,金屬噴敷的複雜性也隨之增加。
局部互連線為互連線之一特殊形式。局部互連線通常用以短距離,如功能單元(functional cell)內。對於局部與總體連接兩者,習知的電路使用相同的互連層。
傳統上,擴散區至Vdd與Vss的接觸需要製造自PMOS與NMOS擴散區個別地朝Vdd與Vss線延伸的L形或T形彎曲擴散區。因為此彎曲區需要更昂貴的光刻設備而製造,故不是最佳的。另外,可在矩形擴散區上延伸Vdd與Vss軌條,而可形成至擴散區的接觸。然而,因為電力軌條佔據了可用於訊號的徑跡,且電力軌條不再坐落於單元邊界,無法於垂直毗連單元之間共享之,故於擴散區上具有電力軌條係無效益的。
於此背景下產生了本發明的實施例。
廣義而言,本發明的實施例定義製造方法、結構、佈局、設計方法,與傳導結構,以定義電路的局部互連線。依據本發明之實施例,當此局部互連線於閘極電極之間或旁邊的通道或區域中對準(做為製造過程的回應)時,本文則稱其為『自對準』局部互連線。此局部互連線係以自對準傾向(self-aligned orientation)所定義之物,可使其圖形化以移除若干材料,僅留下需要完成所選局部互連線的那些部分。
許多有益特徵中的一個係於矩形或實質矩形的擴散區附近著手電路佈局。以優於帶有彎曲或延伸部分之擴散區的精確度製造這些矩形擴散區。此外,此自對準局部互連線係用以製作與電晶體之源極與汲極的電力連接(即Vdd與Vss),而不需擴散區延伸部分。自對準局部互連線也可消除電晶體擴散區之特定接觸的需求。如下文將更詳細描述,此局部互連線製作與擴散區的直接且整合接觸。因此,此局部互連線於基板平面上提供以前不可得之金屬路線訂定,此舉用於消除特定第一金屬徑跡、特定介層孔,與在若干例中的第二金屬徑跡(如用以連接NMOS電晶體源極/汲極與PMOS電晶體源極/汲極)之需求。
進一步,藉由消除有效電晶體通道中的傳統擴散區接觸,不用變更此擴散區中的應變層。此舉改善加強應變層之移動率的效益。此外,允許擴散區接觸點與許多供選擇的第一金屬徑跡連接在電路設計中給予更多彈性,從而加強佈局且有利於更有效的放置與路線訂定。
在一實施例中,揭露用以定義局部互連結構的方法。此方法包括於基板上設計不同擴散區。複數個閘極中的若干個係設計為有效閘極,而複數個閘極中的若干個係設計為於隔絕區上形成。此方法包括沿著相同方向以規則且重複對準地設計複數個閘極,且複數個閘極中的每一個係設計為具有介電間隔部。此方法也包括於複數個閘極之間或毗鄰複數個閘極而設計一局部互連層。此局部互連層有導電性且設置於基板上以允許與有效閘極之若干擴散區的電性接觸或互連。藉由此複數個閘極的介電間隔部而使此局部互連層自我對準。
本發明的優點有許多個。最明顯的是,此自對準局部互連線容許帶有較少的彎曲、延伸部分等。此自對準局部互連線也降低所需接觸點的數量、第一金屬徑跡使用、製作擴散區之接觸所需的介層孔數量,與metal-2徑跡使用。因此,呈現更多的徑跡用以訂立路線。此外,自對準局部互連線的使用降低擴散區接觸之金屬的使用,此舉於基板上降低對應變材料的干預。因此,藉著消除擴散區的大部分金屬,在相當大的程度上提高裝置效益。此自對準局部互連線也於用以在一單元或單元內相連的第一金屬徑跡分配中提供更多彈性,改善密度與簡化後續放置與路線訂定。
於光學對位處理上用以製造局部互連線的自對準過程之另一優點係此自對準局部互連線的製造不需依靠用以使此局部互連線與閘極之側壁間隔部對準的微影技術。眾所週知,由於微影技術具有誤差幅度,因此即使於積體電路中局部互連層朝向閘極之側壁間隔部的微小偏移也可能引起裝置短路或導致不欲之結果。
本發明之其他實施態樣及優點由隨後之舉例說明本發明原理的詳細說明及隨附之相對應圖式當可更加明白。
揭露用以於積體電路中設計、佈局、製作、製造與執行『自對準局部互連線』的方法與製程之發明的實施例。在下文描述中,為提供本發明之徹底了解而闡明眾多的具體描述。在一實施例中,提供製造自對準局部互連線的過程。在其它實施例中,揭露方法與佈局技術,其說明使用此自對準局部互連線的方式。下文也特別參照一特殊邏輯單元而概述使用這些自對準局部互連線的益處與優點。然而,應了解到,在自對準局部互連線的使用上,此示範邏輯單元非限制性。可使自對準局部互連線的使用延伸至任何電路佈局、邏輯裝置、邏輯單元、邏輯基元(logic primitive)、內連結構、設計光罩等。因此,在下文描述中,為提供本發明之徹底了解而闡明眾多的具體描述。然而,對於熟悉本技藝者,明顯的是,不用這些特定細節的部分或全部即可實行本發明。在其他例子中,為了避免非必要地搞混本發明而沒有詳盡地描述眾所皆知的處理操作。
此自對準局部互連線於積體電路的製造中具有許多應用。既使是積體電路上局部互連線的微小錯位可能導致電性短路與/或致使裝置不能運作,積體電路中局部互連線的自我對準也消除了微影誤差幅度(lithography error margins)與由此產生的裝置損耗。
此外,自對準局部互連線可用於各式其它用途。一種這樣的用途係使用此自對準局部互連線而自電晶體的擴散區中移開金屬接觸點。
此外,於積體電路中製造『自對準』局部互連線的過程較需要經由微影處理而精確對位的其它技術係有利的。眾所週知,隨著特徵尺寸持續縮小,精確對準光罩的能力難以齊頭並進。此外,來自鄰近形狀的干涉圖案產生建設性或破壞性干涉。以建設性干涉而言,可能不注意地產生不必要的形狀。以破壞性干涉而言,可能不注意地移除所需的形狀。在任一例中,以異於計畫的方式印刷出特殊形狀可能引起裝置故障。如光學鄰近修正術(optical proximity correction,OPC)的修正方法企圖預測來自鄰近形狀的影響,而修正光罩使印刷形狀如所需地被製造。然而,如前所述,隨著製程幾何拓撲結構(process geometries)縮小與隨著光交互作用變得更複雜,光交互作用預測的品質也隨之每況愈下。
隨著此概要銘記於心,下文圖表將說明範例結構、製程步驟、佈局幾何拓撲、遮罩,與互連線佈局。上述種種可以佈局、光罩、具有光罩定義的電腦檔案,與半導體基板上由此產生的層別而表達。因此,應了解到,下文所述的製造過程僅為示範性,且只要維持『自對準』局部互連線的精神與定義,就可省略若干步驟或藉其它步驟而代之。
在一實施例中,本發明的方法與結構利用一致的特徵方向,此舉定義實質一致的特徵方向的畫布(canvas)。在畫布中,於基板內定義若干擴散區以定義電晶體裝置的有效區。此畫布也包括於基板上以共同方向所定向的若干線性閘極電極段。此線性閘極電極段中的一些係設置於擴散區上。擴散區上所設置的每一線性閘極電極段包括於擴散區上所定義之必須的有效區,與定義為於基板上超過擴散區的均勻延伸部分。此外,此線性閘極電極段係定義為具有可變長度而使邏輯閘運作。此畫布更包括於閘極電極段上的平面內所設置的若干線性導線段,其以實質垂直的方向跨越閘極電極段的共同方向。線性導線段的數目係定義為使基板上一共同線內毗鄰線性導線段之間的端間間隔減至最小。
在描述圖式與解釋實施例中,省略本技藝中眾所皆知的製造過程之各式細節,用以提供易懂且聚焦於待述的實施例。此外,因為與製造過程相關的許多項目於本技藝中係眾所皆知的,故不再細說之。
I. 執行一致相對特徵定向之畫布設計的概要
圖1係一說明,依據本發明之一實施例顯示用以定義動態陣列架構的通用層疊。應理解到,如有關圖1所描述的,用以定義動態陣列架構的通用層疊並不旨在窮舉CMOS製造過程的描述。然而此動態陣列係依據標準CMOS製造過程而建立。一般而言,此動態陣列架構包括此動態陣列之下層結構的定義,與用以針對區域利用與可製造性之最優化而組合此動態陣列的技術兩者。因此,此動態陣列係設計為使半導體製造能力最優化。
關於動態陣列之下層結構的定義,於基底基板(如半導體晶圓)201上,例如於矽質基板或絕緣層上覆矽(silicon-on-insulator,SOI)的基板上,以成層方式逐漸建立此動態陣列。擴散區203界定於基底基板201中。通常藉由隔絕區或淺層溝渠隔離(Shallow Trench Isolation,STI)區隔開擴散區203。此擴散區203表示基底基板201的所選區域,其係為改良基底基板201之電性特性的目的而於區內引進雜質。於擴散區203之上,擴散接觸點205係定義為連接擴散區203與導線。例如,此擴散接觸點205係定義為連接源極及汲極擴散區203與其個別的導線網。此外,於擴散區203之上定義閘極電極特徵207以形成電晶體閘極。閘極電極接觸點209係定義為連接閘極電極特徵207與導線。例如,此閘極電極接觸點209係定義為連接電晶體閘極與其個別導線網。
於擴散接觸點205層與閘極電極接觸點209層上定義互連層。此互連層包括第一金屬(metal 1)層211,、第一介層孔(via 1)層213、第二金屬(metal 2)層215、第二介層孔(via 2)層217、第三金屬(metal 3)層219、第三介層孔(via 3)層221,與第四金屬(metal 4)層223。此金屬與介層孔層定義所需的電路連接性。例如,此金屬與介層孔層電性上連接各式擴散接觸點205與閘極電極接觸點209,而實現電路的邏輯功能。應理解到,此動態陣列架構不限制互連層(即金屬與介層孔層)的特定數目。在一實施例中,此動態陣列除了第四金屬(metal 4)層223以外可包括額外的互連層225。另外,在另一實施例中,此動態陣列可包括少於四層金屬層。
定義此定義動態陣列而使層別(除了擴散區層203以外)受限於關於層中所定義的佈局特徵形狀。具體地說,在非擴散區層203的每一層別中,允許實質線性成型(linear-shaped)佈局特徵。在一既定層中線性成型佈局特徵的特點係具有一致的垂直截面形狀,且於基板上以單一方向延伸。然而,假設對若干線路需要做接觸點,則允許若干微小的垂直擠壓,但這些微小的垂直擠壓不應在方向上構成實質改變。因此,此線性成型佈局特徵定義一維變化的結構。儘管若必要時允許擴散區203係一維變化,但其係不需如此。具體地說,關於與基板之頂端表面一致的一平面,基板內的擴散區203係定義為具有任何二維變化形狀。在一實施例中,限制擴散彎曲拓撲的數目而使擴散區的彎曲與形成電晶體之閘極電極的導電材料(如多晶矽)之間的交互作用係可預期且可精確地建模。既定層中的線性成型佈局特徵係定位為彼此平行。因此,既定層中的線性成型佈局特徵於基板上以一共同方向延伸且平行於此基板。
在一實施例中,於微影處理中動態陣列的下層佈局方法可(但非必須)使用光波之建設性光干涉,以於既定層中加強鄰近形狀的曝光。因此,在駐光波的建設性光干涉周圍定義既定層中的平行線性成型佈局特徵之間隔,而使光學修正(例如OPC/RET)減至最小量或消除之。因此,對照習知以OPC/RET為基底的微影處理,本文所定義的動態陣列利用鄰近特徵之間的光交互作用,而非企圖針對鄰近特徵之間的光交互作用進行補償。
因為可精確地建立既定線性成型佈局特徵之駐光波的模型,有可能預測與既定層中平行所設置的鄰近線性成型佈局特徵有關的駐光波將如何交互作用。因此,有可能預測用以照射一線性成型特徵的駐光波將如何促成其鄰近線性成型特徵的曝光。鄰近線性成型特徵之間的光交互作用之預測可確認最佳特徵間間隔(feature-to-feature spacing),而使用以顯現既定形狀的光將加強其鄰近形狀。既定層中的特徵間間隔係定義為特徵間距,其中此間距係既定層中毗鄰線性成型特徵之間的中心間(center-to-center)相隔距離。
在一實施例中,為提供鄰近特徵之間所需的曝光增強,將既定層中的線性成型佈局特徵均勻分開而使自鄰近特徵的光之建設性與破壞性干涉最佳化,以產生鄰近區中所有特徵的最佳成像(rendering)。既定層中的特徵間間隔係正比於用以照射此特徵的光波長。用以照射離既定特徵約五倍波長距離內的每一特徵的光將用於使既定特徵的曝光增強至若干程度。充分利用用以照射鄰近特徵的光波之建設性干涉可使製造設備能力於微影處理期間能夠最大化且不被關於光交互作用之考量而限制。
如上述,動態陣列加入限制拓樸,其中需要每一層(非擴散層)內的特徵在形狀上為實質線性,且以平行方式定向而以一共同方向橫越基板。帶著此動態陣列的拓樸,可使光刻處理中的光交互作用最佳化而完成佈局之精確移轉至光阻上。
圖2A係一說明,依據本發明之一實施例顯示欲投射至動態陣列上的示範性基底座標格(base grid),以便於定義此限制拓樸。此基底座標格可用以便於以適當最佳間距而於每一動態陣列層中平行排列線性成型特徵。儘管基底座標格非實體上定義為動態陣列之一部分,此基底座標格可認為是每一動態陣列層上的投影。此外,應了解到,以關於每一動態陣列層上之位置的實質一致方式投影此基底座標格,從而使精確的特徵便於堆疊與對準。
在圖2A的示範性實施例中,此基底座標格係依據第一參考方向(x)與第二參考方向(y)定義為矩形座標格,即笛卡耳座標格(Cartesian grid)。第一與第二參考方向中的座標格點間間隔(gridpoint-to-gridpoint spacing)必要時係定義為以最佳特徵間間隔定義線性成型特徵。此外,第一參考方向(x)中的座標格點間隔可異於第二參考方向(y)中的座標格點間隔。在一實施例中,橫越整個晶粒(die)投影單一基底座標格以於橫越整個晶粒的每一層中設立各式線性成型特徵。然而,在其它實施例中,橫越晶粒的不同區投影不同的基底座標格,以於晶粒的不同區內支持不同特徵間間隔需求。圖2B係一說明,依據本發明之示範實施例顯示橫越晶粒之不同區所投影的不同基底座標格。
此動態陣列的佈局架構跟隨此基底座標格圖案。因此,有可能使用座標格點表示於閘極電極與金屬線性成型特徵所設置的擴散區中哪裡發生方向上的改變、那裡設置接觸點、於線性成型閘極電極與金屬特徵中開孔在哪裡等。對於既定特徵線寬應設定座標格點的間距,即座標格點間間隔,而使既定特徵線寬之鄰近線性成型特徵的曝光將彼此加強,其中此線性成型特徵係集中於座標格點上。參照圖1的動態陣列層疊與圖2A的示範基底座標格,在一實施例中,藉由所要求的閘極電極間距而設定第一參考方向(x)中的座標格點間隔。在此相同的實施例中,藉由第一金屬間距而設定第二參考方向(y)中的座標格點間距。例如,在90nm邏輯製程技術中,第二參考方向(y)中的座標格點間距約為0.24微米。在一實施例中,第一金屬與第二金屬層具有共同的間隔與間距。可於此第二金屬層上使用不同間隔與間距。
定義此動態陣列的各式層別而使毗鄰層中的線性成型特徵彼此以相互交叉的方式延伸。例如,毗鄰層的線性成型特徵可正交地延伸,即彼此相互垂直。此外,一層的線性成型特徵可以如約45度的角度延伸橫越毗鄰層的線性成型特徵。例如,在一實施例中,一層的線性成型特徵在第一參考方向(x)上延伸,而毗鄰層的線性成型特徵在相對於第一(x)與第二(y)參考方向上對角地延伸。應理解到,為在具有於毗鄰層中以相互交叉方式設置的線性成型特徵之動態陣列中訂定路線設計,在線性成型特徵中定義開口,且如必要時定義接觸點與介層孔。
此動態陣列使佈局形狀中的彎曲(或方向上實質改變)使用減至最小,以消除不可預期的微影交互作用。具體地說,在OPC或其它RET處理之前,動態陣列允許擴散層中的彎曲以控制裝置大小,但不允許擴散層上之層別中的實質彎曲(或方向上實質改變)。
關於圖3與4係描述自擴散層至第二金屬層之動態陣列的示範性增長。應理解到,僅經由範例方式提供關於圖3與4所描述的動態陣列,並不旨在傳達此動態陣列架構的限制性。可依據本文所呈現的原理使用此動態陣列,以根本上定義任何積體電路設計、任何邏輯單元、基本單元、架構,或設計佈局。設計可在實體晶片、晶圓、基板上或畫在紙、薄膜上,或存在檔案中。假設存在檔案中,此檔案可存於任何電腦可讀裝置。此電腦可讀裝置可存於區域電腦上、網路電腦上,且可經由網際或區域網路傳輸、分享或使用此檔案。
圖3依據本發明之一實施例顯示示範性動態陣列的擴散層佈局。圖3的擴散層顯示p擴散區401與n擴散區403。當依據下層的基底座標格定義此擴散區時,此擴散區係不受與擴散層上方層別有關的線性成型特徵限制之影響。然而,應注意到,佈植區佈局係較先前技藝設計更為簡單,其先前技藝設計另外需要更多形狀延伸與彎曲。如所示,n+佈植區(412)與p+佈植區(414)係定義為(x)與(y)座標格上不帶有外來的差階(jogs)與凹口之矩形。此樣式容許使用更大的佈植區,降低OPC/RET的需求,且能使用較低解析度與較低成本的微影系統,如365nm的i-line曝光系統。
圖4係一說明,依據本發明之一實施例顯示於圖3的擴散層之上且與其毗鄰的閘極電極層。如熟悉CMOS技藝者的理解,閘極電極特徵501定義電晶體閘極。此閘極電極特徵501係定義為於第二參考方向(y)上以平行關係延伸橫越於動態陣列的線性成型特徵。在一實施例中,此閘極電極特徵501係定義為具有共同的寬度。然而,在其它實施例,閘極電極特徵中一或多個係定義為具有不同的寬度。當確保鄰近閘極電極特徵501所提供的微影增強,即共振成像,最優化時,此閘極電極特徵501的間距(中心間間隔)減至最小量。為討論目的,在既定線條上延伸橫越於動態陣列的閘極電極特徵501稱為閘極電極徑跡。
當閘極電極特徵501橫越擴散區403與401時,個別地形成n-通道與p-通道電晶體。僅管在若干座標格位置上無呈現擴散區,但藉由在每一座標格位置上繪製閘極電極特徵501而完成最佳的閘極電極特徵501印刷。此外,於動態陣列的內部之內,長形連續閘極電極特徵501於其端點上有助於改善線端縮短效應。另外,當自此閘極電極特徵501中實質移除所有的彎曲時,在相當大的程度上改善閘極電極印刷。
在線性橫越動態陣列中,可數次打斷(即斷開)每一閘極電極徑跡以提供欲執行之特定邏輯功能的所要求電性連通性。當要求打斷既定閘極電極徑跡時,使此閘極電極徑跡線段之末端於斷開點處之間的分隔減小至考慮到製造能力與電性效應的可能寬度。在一實施例中,當於特定層內特徵之間使用共同端間間隔時,達成最佳化的可製造性。
II. 在畫布上使用自對準局部互連線的邏輯單元設計
圖5A說明示範性邏輯反相器的電路表示法。然而,如上所述,僅顯示及討論此邏輯反相器以傳達製作自對準局部互連線的過程,此過程可執行任何其它基元、單元、邏輯裝置,或處理方法。如所示,連結PMOS電晶體110與NMOS電晶體112以製作一邏輯反相器。PMOS電晶體110的源極係連接於Vdd 118,而PMOS電晶體110的汲極係連接於NMOS電晶體112的汲極。NMOS電晶體112的源極係接地(Vss)120。為電晶體設置共同的輸入116,且在PMOS電晶體110的汲極與NMOS電晶體112的汲極之連接處設置輸出114。再者,使用此邏輯反相器為例子以提供本發明之實施例的了解。然而,熟悉本技藝者將理解此實施例也可用於任何其它形式之邏輯單元、裝置,與積體電路的製造。
圖5B說明示範性邏輯反相器的平面圖,其具有將P 64及N 68擴散區分別連接至Vdd 50及Vss 54的自對準局部互連線58/60。也使用自對準局部互連線62連接PMOS電晶體的汲極與NMOS電晶體的汲極。在一實施例中,於基板上積體電路中的所有自對準局部互連線係平行於閘極電極通道。使局部互連線舖設為一方向的許多優點之一係此局部互連層可取代另外需要使用自對準局部互連線製作連接點的一金屬層。第一金屬線50、72、70,與54係對準垂直於閘極電極線74的一方向。在其它實施例中,金屬線的對位可為不同。
仍參照圖5B,使用自對準局部互連線有許多優點。在一實施例中,連接P擴散區64與Vdd線50的自對準局部互連線58消除製造朝向Vdd線50延伸之L形擴散區的需要。在若干設計中,此自對準局部互連線58消除連接擴散區64與Vdd線50之金屬帶的需要。此金屬帶與相關接觸點之消除提高裝置效能與縮小裝置尺寸。因為連接擴散區的金屬帶需要一或多個連接點,其干預矽的有益應變,而降低了效能。因此,除非若干設計組態的需要,減少擴散區的金屬接觸點將促進裝置效能。
圖6A說明部分已製成積體電路之平面圖,顯示於P擴散區64與N擴散區68上的P擴散區64、N擴散區68與閘極電極線74。在此部分視圖例子中,其它的閘極電極線74a與74b係舖設於淺層溝渠隔離(STI)區上。閘極電極線74、74a與74b包括兩邊的間隔部(或閘極側壁間隔部)。
儘管為討論之便易而未顯示,閘極電極的端點也具有介電間隔部。既然於基板上藉由設計而均勻放置閘極電極線,若干閘極電極線係形成於STI區上。因此,於STI區上所形成的閘極係無效閘極(inactive gates)。當於擴散區上放置閘極電極時,形成有效閘極,且定義了電晶體。在一實施例中,使用標準CMOS製造過程製造此部分已製成積體電路。
圖6B說明圖6A的部分已製成積體電路之橫剖面。應了解到,此圖不意味提供精確的維度呈現或精確的相對維度。另一方面,此圖應被理解為通常傳達特徵與層別的安排,與處理的範例順序。此外,應了解到,當若干順序步驟為熟悉本技藝者所知悉,且對本文所說明的處理及順序流程係不重要時,不用圖畫地說明之。
將此銘記於心,此部分已製成積體電路係於矽晶圓上形成,且包括阱182與淺層溝渠隔離(STI)區180,以於積體電路中提供毗鄰有效裝置之間的隔絕。阱182包括擴散區184與閘極電極74。此閘極電極包括沿著閘極電極線之側所形成的介電間隔部(也稱為側壁間隔部)230。如上文討論,為使設計最佳化,以平行方向彼此相對地製造此閘極電極(或線)。因此,如本文所述,『通道』係定義於個別閘極電極之間。藉由閘極電極線的規則間隔而因此指定介於兩毗鄰閘極電極通道之間的間隔。如下文更詳細地討論,由此產生的自對準局部互連線將存在於毗鄰閘極電極(或若無鄰近閘極電極時,於閘極電極旁邊)之間的通道。因為自對準局部互連線主要留存在通道中,其將可自我對準。
在圖7A與7B中,於擴散區184、閘極電極74、74a與74b,與間隔部上形成局部互連層196。舉例來說,可經由金屬沉積處理形成局部互連層196。為透視之便易,圖7A中以半透明層顯示此局部互連層196。圖7B的橫剖面顯示圖6B之特徵上所沉積的局部互連層196。
在一實施例中,此局部互連層196通常為金屬。在更具體的實施例中,此金屬主要為鎳(Ni)。在其它實施例中,此金屬為鈦、鉑,或鈷。在另一實施例中,使用鎳與鉑的合金。最好,局部互連層中所用的金屬之純度遵守工業標準金屬。在一實施例中,使用物理氣相沉積(PVD)技術沉積此局部互連層。在其它實施例中,經由化學氣相沉積(CVD)或原子層沉積(ALD)而沉積此局部互連層。
在沉積局部互連層196之後,互連層的金屬與下層的矽反應,且若互連層出現在閘極電極中,則與多晶矽反應。在一實施例中,經由熱處理步驟而促進此反應。在若干處理條件下可實現此反應,以鎳層做為一例子,溫度的範圍係於約攝氏200至400度之間、運作的時間範圍約5至約60秒;更高溫可用於其它金屬。在另一實施例中,溫度係設定為約攝氏300度,運作約30秒。通常在使用氮氣或其它惰性氣體的腔室中執行此反應步驟。
如圖8A所示,做為反應過程的結果,於裸露矽質區上形成矽化物196’。因此,此矽化作用(即矽化物196’的形成)發生於裸露矽基板部分與裸露多晶矽閘極(若存在時)上。如眾所週知,儘管矽化物196’係薄的,其提供良好導電。當然,在反應過程之後,未觸及矽質的部份局部互連層196依然係金屬。在圖示中,圖8A以陰影顯示矽化物196’,對照於未反應之局部互連層196的金屬。
圖8B說明於局部互連層196上沉積硬式遮罩199後的結果。在一實施例中,此硬式遮罩199為氧化物(如SiO2等)。在其它實施例中,此硬式遮罩199為氮化物(如氮化矽等)。在另一實施例中,此硬式遮罩199為非晶碳(APC)。可以若干方法形成硬式遮罩199,且一種如此的示範方法係藉由使用CVD、ALD,與PECVD處理中的一種。在此實施例中,此硬式遮罩199係用以於後續移除步驟期間保護局部互連層196,此移除步驟移除不需導電連接的部分局部互連層196。
圖9A依據本發明之一實施例顯示於硬式遮罩199上形成聚合物層210之後圖8B的橫剖面。以本技藝中所知悉的若干方法塗佈聚合物層210。在一實施例中,於硬式遮罩199的表面上最好是旋塗聚合物層210。在另一實施例中,聚合物層210為光阻材料,正型或負型,取決於所需顯影處理。例如,其他形式的光阻包括未敏化光阻(unsensitized photoresists)、聚甲基丙烯酸甲酯(PMMA)抗蝕劑等。如圖9B所示,一經塗佈,部分且均勻地移除聚合物層210直至裸露硬式遮罩199。最好使用電漿蝕刻處理執行此移除。一個範例蝕刻處理發生在氧氣電漿中。在此步驟中,此蝕刻處理實質上最好係非等向性而完成實質均勻移除輪廓深至首先裸露的硬式遮罩199。可使用標準端點偵測(end-point detection)技術判定何時停止圖9B中所說明的蝕刻操作。圖9C係一平面圖,顯示裸露的硬式遮罩199與留存的聚合物層210。在此階段,閘極側壁間隔部(即介電間隔部)230仍被聚合物層210所覆蓋。
應注意到,以一致的規則間隔放置閘極電極的另一優點為聚合物層210係一致地定義為具有實質相等厚度。若無如此一致間隔,聚合物層210將在厚度上顯出變化,其係所不欲之事。例如,假設此聚合物層210之厚度無法實質均勻覆蓋基板,帶有相對少量聚合物材料的若干閘極電極將首先裸露,於特定閘極上引起硬式遮罩之可能的過蝕刻。
一旦裸露閘極電極74、74a與74b之頂部上的硬式遮罩199,便執行等向蝕刻。此等向蝕刻係設計為移除聚合物層210之側部238,如閘極電極介電間隔部230上的聚合物層210。如圖10A與10B所示,在完成此等向蝕刻後,聚合物層210應以帶狀形式留存在閘極電極74、74a與74b之間,水平錯斷(offset)且自我對準於閘極介電間隔部230。因此,除閘極電極線74、74a與74b與閘極電極介電間隔部230上之外,聚合物層210將留存在基板上各處。
圖11A說明移除未被除聚合物層210所覆蓋的硬式遮罩199之後基板的橫剖面。取決於所選硬式遮罩的材料,使用若干已知的濕式或乾式蝕刻處理執行此移除。在一實施例中,一旦移除裸露的硬式遮罩199,繼續蝕刻以自介電間隔部230上移除部分局部互連層196。此部分局部互連層196之移除將為局部互連層196/矽化物196’與介電間隔部230之間的輕微分開做準備。在這一點上,留存的局部互連層196材料、矽化物196’材料與仍被聚合物層210所覆蓋的硬式遮罩199將存於介電間隔部230之間且為其所對準的通道中。
圖11B說明執行另外選擇性蝕刻操作以自局部互連層196(包括矽化物部分196’)上移除聚合物層210與硬式遮罩199之後基板的橫剖面。可以看出,此局部互連層196材料與矽化物部分196’將於介電間隔部230之間自我對準。圖12顯示圖11B中基板的平面圖。如所示,此局部互連層196存於閘極介電間隔部230之間的通道中。如上所述,做為蝕刻的結果,此自對準局部互連線196也與介電間隔部230間隔一距離231。圖12也說明P 64與N 68擴散區(在橫剖面中此兩區係說明為擴散區184)。
圖13依據本發明之一實施例說明使蝕刻便利的圖形化操作。在一實施例中,旋塗一光阻,接著使用標準光刻曝光以定義遮罩300。如所示,此遮罩300係定義為覆蓋執行蝕刻操作後所留存的部分局部互連層196。既使於裸露矽質或多晶矽(若存在的話)上形成矽化物196’的反應材料不被遮罩300所覆蓋,其也將在蝕刻後留存下來。在一實施例中,因為此遮罩300係定義為寬鬆地舖設於閘極電極74、74a與74b上,故無需嚴格佈局限制即可輕易定義之。
應理解到,當局部互連層196材料僅舖設於通道中,且於介電間隔部230之間已自對準時,不需要嚴格的佈局限制。再者,在執行蝕刻以移除局部互連層196的未受保護部份之後,矽化物196’材料仍留存著。電性上,此局部互連層196與矽化物196’材料將定義導電連結或連接或導線,相似於常例的互連金屬線。
圖14說明蝕刻與後續移除遮罩300之後基板的平面圖。如所示,局部互連層196將留存在遮罩300保護材料的通道中,從而形成實際的自對準局部互連特徵。因此,留存的局部互連層196將於介電間隔部230之間所定義的通道內機能上完成任何所需的互連。在移除遮罩300之後,執行退火操作。例如,此退火可為快速熱退火(RTA)法,其針對鎳係於約攝氏450度下操作約30秒。
回頭參照圖5B,如圖15所示垂直於閘極電極線74、74a與74b而製造第一金屬線。此外,於所需處形成接觸點以提供各式層別之間的電性連接,此舉對形成示範性邏輯電路係必要的。
在一實施例中,彼此緊靠地製造第一金屬徑跡702,此舉可更輕易地訂定路線與所需連接。當然,線間的間距將取決於製造能力、特殊電路、佈局,與設計與/或電路之形式的佈局限制。隨著垂直於第一金屬徑跡702而對準自對準局部互連線196,將提供更大的空間自由度用以定義/選擇自對準局部互連線196與所選第一金屬徑跡之間的接觸點。因此,除了先前所討論的自對準局部互連線之優點之外,自對準局部互連線也可在上述層面訂定金屬徑跡中幫助提供更多自由度,轉而提供設計與製造的彈性。
圖16說明示範性反相器邏輯單元,其係使用本發明之自對準局部互連線所製造。除了閘極電極線74a係分成兩段以提供閘極電極空隙703之外,此電路相似於圖5A中所說明者。應注意到,僅為說明之便易而僅顯示一個空隙。在其它實施例中,一或多條閘極電極線具有一或多個閘極電極空隙。在一實施例中,此閘極電極空隙703係用以製造自對準局部互連線,其係垂直於閘極電極線74a而對準。在這些閘極電極空隙703中的自對準局部互連線係用以連接二或多個裝置,或連接平行於閘極電極線74a的兩條自對準局部互連線。在這些閘極電極空隙703中的自對準局部互連線也可使金屬徑跡路線排定容易且消除若干第一金屬徑跡的需求。
圖17A-17D依據本發明之另一實施例說明用以使用局部互連層196製造連接的處理操作,以製作與閘極電極74的接觸。為了解之便易,請參考橫剖面400,其也於顯示於圖18中。圖17A呈現相似於演變成圖10B所述的處理中的一階段。然而,於區402上也形成遮罩404,其實質位於閘極電極74之間隔部230的側壁上。只要於沿著間隔部230的材料上提供保護,精確的尺寸就非格外重要。遮罩404於此區保護局部互連線材料196免於隨後的蝕刻。取決於所選的製造過程,可自硬式遮罩或光阻遮罩定義此遮罩404。
圖17B顯示在使用蝕刻操作移除裸露的硬式遮罩199之後的處理。如所示,移除裸露的硬式遮罩199與局部互連層196,其相似於圖11A的處理。現在,移除遮罩404、聚合物層210,與硬式遮罩199,如圖17C所示,留下局部互連層196。圖17C也顯示遮罩300’,其用以於欲留存局部互連層196之處保護局部互連層196。顯示遮罩300’於區域402中覆蓋局部互連層196且保護之。因此,因為使用遮罩404,局部互連層196將留存在間隔部230之側壁上,從而允許局部互連層196與閘極電極74之矽化物196’材料產生連接。因此,無需上層金屬層與接觸點,於基板之層面上製作連接用以與閘極電極74連接。
圖18顯示使用局部互連層196的例子,其攀上介電間隔部230以於區域402中製作與閘極電極74的連接。在此例中,此局部互連層196(其跨上介電間隔部230)與閘極電極電性上相連。然而,應了解到,用以形成攀上間隔部230之連接的結構與方法可用於許多不同的設計、電路、單元,與邏輯互連。
已揭露方法、設計、佈局,與結構,其定義使用自對準局部互連線的方式。應銘記於心,使用這些自對準局部互連線的益處與優點並不限於任一特定電路、單元或邏輯。相反地,這些自對準局部互連方法與結構的揭露可延伸至任一電路佈局、邏輯裝置、邏輯單元、邏輯基元、互連結構、設計光罩等。而且,由此產生用以定義此自對準局部互連線(於晶片、較大之完整系統或實施之任一部分或區域中)的佈局、設計、組態或資料可電子式地存於檔案中。此檔案可存於電腦可讀媒體,且此電腦可讀媒體可於如網際網路的網路上分享、傳送或交流。
因此,隨著上述實施例銘記於心,應了解到,本發明在製造過程、製造步驟、製造步驟之順序、製造中所用的化學劑、製造中所用的處理、組態與各式單元的相對位置中可採用其它的變化。雖然已按照數個較佳實施例而敘述本發明,應理解熟悉本技藝者研讀具體說明及研究圖式時可在其中做各式替換、增加、交換及等價動作。因此,意味著本發明包含落入本發明的真實精神及範圍內之所有如替代、增加、交換及等價動作。
50‧‧‧第一金屬線/Vdd
54‧‧‧第一金屬線/Vss
58‧‧‧自對準局部互連線
60‧‧‧自對準局部互連線
62‧‧‧自對準局部互連線
64‧‧‧P擴散區
68‧‧‧N擴散區
64(184)‧‧‧(P)擴散區
68(184)‧‧‧(N)擴散區
70‧‧‧第一金屬線
72‧‧‧第一金屬線
74‧‧‧閘極電極(線)
74a‧‧‧閘極電極(線)
74b‧‧‧閘極電極(線)
110‧‧‧PMOS電晶體
112‧‧‧NMOS電晶體
114‧‧‧輸出
116‧‧‧輸入
118‧‧‧Vdd
120‧‧‧接地/Vss
180‧‧‧淺層溝渠隔離區
182‧‧‧阱
184‧‧‧擴散區
196‧‧‧局部互連層
196'‧‧‧矽化物
199‧‧‧硬式遮罩
201‧‧‧基底基板
203‧‧‧擴散區
205‧‧‧擴散接觸點
207‧‧‧閘極電極特徵
209‧‧‧閘極電極接觸點
210‧‧‧聚合物層
211‧‧‧第一金屬層
213‧‧‧第一介層孔層
215‧‧‧第二金屬層
217‧‧‧第二介層孔層
219‧‧‧第三金屬層
221‧‧‧第三介層孔層
223‧‧‧第四金屬層
225‧‧‧額外的互連層
230‧‧‧(閘極電極)介電間隔部
231‧‧‧距離
238‧‧‧側部
300‧‧‧遮罩
300'‧‧‧遮罩
400‧‧‧橫剖面
401‧‧‧p擴散區
402‧‧‧區域
403‧‧‧n擴散區
404‧‧‧遮罩
412‧‧‧N+佈植區
414‧‧‧P+佈植區
501‧‧‧閘極電極特徵
702‧‧‧第一金屬徑跡
703‧‧‧閘極電極空隙
本發明將可藉由上述詳細說明及隨附之相對應圖式而容易理解。為便於描述,相似的參照數字代表相似的結構單元。
圖1依據本發明之一實施例顯示用以定義動態陣列架構的通用層疊。
圖2A依據本發明之一實施例顯示欲投射至動態陣列上以便於定義限制拓樸的示範性基底座標格。
圖2B依據本發明之示範性實施例顯示橫越晶粒之分隔區所投影的分隔基底座標格。
圖3依據本發明之一實施例顯示示範性動態陣列的擴散層佈局。
圖4依據本發明之一實施例顯示圖3的閘極電極層與擴散層。
圖5A依據本發明之一實施例說明使用PMOS與NMOS之邏輯反相器的電路表示法。
圖5B依據本發明之一實施例說明示範性邏輯反相器的平面圖,以展示自對準局部互連線的使用。
圖6A依據本發明之一實施例說明示範性邏輯反相器的平面圖,顯示電晶體源極/汲極、閘極電極,與圍繞閘極電極的側壁間隔部。
圖6B依據本發明之一實施例說明圖6A的示範性邏輯反相器之切線A-A’的橫剖面,顯示電晶體阱、電晶體源極/汲極、閘極電極、側壁間隔部,與STI區。
圖7A依據本發明之一實施例顯示示範性邏輯反相器之斷面,此反相器帶有覆蓋下層圖6A中所示之元件的局部互連層。
圖7B依據本發明之一實施例顯示示範性邏輯反相器之斷面的橫剖面視圖,此反相器帶有覆蓋下層圖6B中所示之元件的局部互連層。
圖8A依據本發明之一實施例說明經由局部互連層的退火而形成矽化物。
圖8B依據本發明之一實施例說明於基板上之局部互連層的頂端沉積硬式遮罩。
圖9A依據本發明之一實施例說明覆蓋圖8B之元件的聚合物層。
圖9B依據本發明之一實施例說明經由電漿蝕刻部分移除聚合物層之基板的橫剖面視圖。
圖9C依據本發明之一實施例說明聚合物層回蝕至閘極電極之頂端附近的基板之平面圖。
圖10A依據本發明之一實施例說明在濕式蝕刻自介電間隔部移除聚合物之後示範性邏輯反相器的平面圖。
圖10B依據本發明之一實施例說明在移除覆蓋介電間隔部的聚合物之後示範性邏輯反相器的橫剖面視圖。
圖11A依據本發明之一實施例說明在自閘極電極與介電間隔部蝕刻局部互連層與硬式遮罩之後示範性邏輯反相器的橫剖面視圖。
圖11B依據本發明之一實施例說明在留存之聚合物層與硬式遮罩的選擇性蝕刻之後示範性邏輯反相器的橫剖面視圖。
圖12依據本發明之一實施例說明在留存之聚合物層與硬式遮罩的選擇性蝕刻之後示範性邏輯反相器的平面圖。
圖13依據本發明之一實施例說明在遮蔽部分局部互連層以於所需處保護局部互連層之後示範性邏輯反相器的平面圖。
圖14依據本發明之一實施例說明示範性邏輯反相器的平面圖,顯示矽化與無矽化局部互連層的留存區。
圖15依據本發明之一實施例說明如圖14之示範性邏輯反相器的平面圖,其帶有增加的接觸點與金屬線以顯示機能互連。
圖16依據本發明之一實施例說明示範性邏輯反相器的平面圖,顯示閘極線之空隙中的自對準局部互連線。
圖17A-17D依據本發明之一實施例說明示範性邏輯反相器的橫剖面視圖,其使用局部互連金屬以製作與閘極的相連。
圖18依據本發明之一實施例說明示範性邏輯反相器的平面圖,顯示閘極線之空隙中的自對準局部互連線與藉著『攀上』間隔部而製作與閘極的相連。
Claims (27)
- 一種積體電路,包含: 一第一閘極電極層次導電結構,建構成包含一實質線性成型部分在一第一方向上延伸且具有定向在該第一方向上的一縱向中心線,該第一閘極電極層次導電結構的該實質線性成型部分形成一第一電晶體類型的一第一電晶體的一閘極電極及一第二電晶體類型的一第一電晶體的一閘極電極,該第一電晶體類型的該第一電晶體包含一第一擴散類型的一第一擴散區域及該第一擴散類型的一第二擴散區域,該第二電晶體類型的該第一電晶體包含一第二擴散類型的一第一擴散區域及該第二擴散類型的一第二擴散區域; 一第二閘極電極層次導電結構,建構成包含一實質線性成型部分在該第一方向上延伸且具有定向在該第一方向上的一縱向中心線,該第二閘極電極層次導電結構係配置成相鄰該第一閘極電極層次導電結構,使得該第一擴散類型的該第一擴散區域係介於該第一閘極電極層次導電結構與該第二閘極電極層次導電結構之間,且該第二擴散類型的該第一擴散區域係介於該第一閘極電極層次導電結構與該第二閘極電極層次導電結構之間;及 一局部互連導電結構,建構成物理性接觸該第一擴散類型的該第一擴散區域及該第二擴散類型的該第一擴散區域,該局部互連導電結構係配置在該第一閘極電極層次導電結構與第二閘極電極層次導電結構之間。
- 如申請專利範圍第1項之積體電路,其中該第二閘極電極層次導電結構係不使用該第一擴散類型的該第一擴散區域形成一電晶體。
- 如申請專利範圍第2項之積體電路,其中該第二閘極電極層次導電結構係不使用該第二擴散類型的該第一擴散區域形成一電晶體。
- 如申請專利範圍第1項之積體電路,其中該局部互連導電結構係在垂直於該第一方向的一第二方向上位在該第一閘極電極層次導電結構與該第二閘極電極層次導電結構之間的實質中心。
- 如申請專利範圍第4項之積體電路,其中該局部互連導電結構的一部分係配置成,與該第一擴散類型的該第一擴散區域相比,更靠近該第二閘極電極層次導電結構。
- 如申請專利範圍第5項之積體電路,其中該局部互連導電結構的該部分係配置成,與該第二擴散類型的該第一擴散區域相比,更靠近該第二閘極電極層次導電結構。
- 如申請專利範圍第1項之積體電路,其中該局部互連導電結構不物理性接觸該第一閘極電極層次導電結構,且其中該局部互連導電結構不物理性接觸該第二閘極電極層次導電結構。
- 如申請專利範圍第1項之積體電路,其中在垂直於該第一方向的一第二方向上測得的該第一閘極電極層次導電結構的寬度係實質相等於在該第二方向上測得的該第二閘極電極層次導電結構的寬度。
- 如申請專利範圍第1項之積體電路,更包含: 一第一側壁間隔部,沿著與該第二閘極電極層次導電結構最接近的該第一閘極電極層次導電結構的側壁加以配置;及 一第二側壁間隔部,沿著與該第一閘極電極層次導電結構最接近的該第二閘極電極層次導電結構的側壁加以配置。
- 如申請專利範圍第9項之積體電路,其中該局部互連導電結構係與該第一側壁間隔部加以分隔開,且其中該局部互連導電結構係與該第二側壁間隔部加以分隔開。
- 如申請專利範圍第1項之積體電路,更包含: 一第三閘極電極層次導電結構,建構成包含一實質線性成型部分在該第一方向上延伸且具有定向在該第一方向上的一縱向中心線,該第三閘極電極層次導電結構係配置成相鄰該第一閘極電極層次導電結構,使得該第一擴散類型的該第二擴散區域係介於該第一閘極電極層次導電結構與該第三閘極電極層次導電結構之間,且該第二擴散類型的該第二擴散區域係介於該第一閘極電極層次導電結構與該第三閘極電極層次導電結構之間。
- 如申請專利範圍第11項之積體電路,其中在垂直於該第一方向的一第二方向上在該第一閘極電極層次導電結構的該實質線性成型部分的該縱向中心線與該第二閘極電極層次導電結構的該實質線性成型部分的該縱向中心線之間測得的距離係實質等於一閘極電極間距,且 其中在該第二方向上在該第一閘極電極層次導電結構的該實質線性成型部分的該縱向中心線與該第三閘極電極層次導電結構的該實質線性成型部分的該縱向中心線之間測得的距離係實質等於該閘極電極間距。
- 如申請專利範圍第11項之積體電路,其中該局部互連導電結構係一第一局部互連導電結構,該積體電路更包含一第二局部互連導電結構,該第二局部互連導電結構建構成物理性接觸該第一擴散類型的該第二擴散區域。
- 如申請專利範圍第13項之積體電路,其中該第一擴散類型的該第二擴散區域係藉由一內部非有效區而與該第二擴散類型的該第二擴散區域加以分隔開,其中該第二局部互連導電結構在背向該內部非有效區的該第一方向上自該第一擴散類型的該第二擴散區域延伸。
- 如申請專利範圍第14項之積體電路,更包含: 一第三局部互連導電結構,建構成物理性接觸該第二擴散類型的該第二擴散區域。
- 如申請專利範圍第15項之積體電路,其中該第三局部互連導電結構在背向該內部非有效區的該第一方向上自該第二擴散類型的該第二擴散區域延伸。
- 如申請專利範圍第16項之積體電路,其中該第三閘極電極層次導電結構係不使用該第一擴散類型的該第二擴散區域形成一電晶體。
- 如申請專利範圍第17項之積體電路,其中該第三閘極電極層次導電結構係不使用該第二擴散類型的該第二擴散區域形成一電晶體。
- 如申請專利範圍第18項之積體電路,其中該第二局部互連導電結構係在垂直於該第一方向的一第二方向上位在該第一閘極電極層次導電結構與該第三閘極電極層次導電結構之間的實質中心。
- 如申請專利範圍第19項之積體電路,其中該第二局部互連導電結構的一部分係配置成,與該第一擴散類型的該第二擴散區域相比,更靠近該第三閘極電極層次導電結構。
- 如申請專利範圍第20項之積體電路,其中該第三局部互連導電結構的一部分係配置成,與該第二擴散類型的該第二擴散區域相比,更靠近該第三閘極電極層次導電結構。
- 如申請專利範圍第16項之積體電路,其中該第二局部互連導電結構不物理性接觸該第一閘極電極層次導電結構,且其中該第二局部互連導電結構不物理性接觸該第三閘極電極層次導電結構。
- 如申請專利範圍第22項之積體電路,其中該第三局部互連導電結構不物理性接觸該第一閘極電極層次導電結構,且其中該第三局部互連導電結構不物理性接觸該第三閘極電極層次導電結構。
- 如申請專利範圍第16項之積體電路,其中在垂直於該第一方向的一第二方向上測得的該第一閘極電極層次導電結構的寬度係實質相等於在該第二方向上測得的該第二閘極電極層次導電結構的寬度,且其中在該第二方向上測得的該第三閘極電極層次導電結構的寬度係實質相等於在該第二方向上測得的該第一閘極電極層次導電結構的寬度。
- 如申請專利範圍第16項之積體電路,更包含: 一第一側壁間隔部,沿著與該第三閘極電極層次導電結構最接近的該第一閘極電極層次導電結構的側壁加以配置;及 一第二側壁間隔部,沿著與該第一閘極電極層次導電結構最接近的該第三閘極電極層次導電結構的側壁加以配置。
- 如申請專利範圍第25項之積體電路,其中該第二局部互連導電結構係與該第一側壁間隔部加以分隔開,且其中該第二局部互連導電結構係與該第二側壁間隔部加以分隔開,且其中該第三局部互連導電結構係與該第一側壁間隔部加以分隔開,且其中該第三局部互連導電結構係與該第二側壁間隔部加以分隔開。
- 一種製造積體電路的方法,包含: 形成一第一閘極電極層次導電結構,該第一閘極電極層次導電結構建構成包含一實質線性成型部分在一第一方向上延伸且具有定向在該第一方向上的一縱向中心線,該第一閘極電極層次導電結構的該實質線性成型部分形成一第一電晶體類型的一第一電晶體的一閘極電極及一第二電晶體類型的一第一電晶體的一閘極電極,該第一電晶體類型的該第一電晶體包含一第一擴散類型的一第一擴散區域及該第一擴散類型的一第二擴散區域,該第二電晶體類型的該第一電晶體包含一第二擴散類型的一第一擴散區域及該第二擴散類型的一第二擴散區域; 形成一第二閘極電極層次導電結構,該第二閘極電極層次導電結構建構成包含一實質線性成型部分在該第一方向上延伸且具有定向在該第一方向上的一縱向中心線,該第二閘極電極層次導電結構係配置成相鄰該第一閘極電極層次導電結構,使得該第一擴散類型的該第一擴散區域係介於該第一閘極電極層次導電結構與該第二閘極電極層次導電結構之間,且該第二擴散類型的該第一擴散區域係介於該第一閘極電極層次導電結構與該第二閘極電極層次導電結構之間;及 形成一局部互連導電結構,該局部互連導電結構係物理性接觸該第一擴散類型的該第一擴散區域及該第二擴散類型的該第一擴散區域,該局部互連導電結構係配置在該第一閘極電極層次導電結構與第二閘極電極層次導電結構之間。
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US11/969,854 | 2008-01-04 | ||
US11/969,854 US7763534B2 (en) | 2007-10-26 | 2008-01-04 | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
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TW097141040A TWI402940B (zh) | 2007-10-26 | 2008-10-24 | 積體電路中採用之自對準局部互連線用之方法、結構與設計 |
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