TWI598998B - 積體電路中採用之自對準局部互連線用之方法、結構與設計 - Google Patents

積體電路中採用之自對準局部互連線用之方法、結構與設計 Download PDF

Info

Publication number
TWI598998B
TWI598998B TW105134374A TW105134374A TWI598998B TW I598998 B TWI598998 B TW I598998B TW 105134374 A TW105134374 A TW 105134374A TW 105134374 A TW105134374 A TW 105134374A TW I598998 B TWI598998 B TW I598998B
Authority
TW
Taiwan
Prior art keywords
shaped conductive
conductive structures
gate electrode
integrated circuit
linearly
Prior art date
Application number
TW105134374A
Other languages
English (en)
Other versions
TW201701408A (zh
Inventor
C 史麥林麥克
T 貝克史考特
Original Assignee
泰拉創新股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 泰拉創新股份有限公司 filed Critical 泰拉創新股份有限公司
Publication of TW201701408A publication Critical patent/TW201701408A/zh
Application granted granted Critical
Publication of TWI598998B publication Critical patent/TWI598998B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/62—Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

積體電路中採用之自對準局部互連線用之方法、結構與設計
本發明係關於積體電路，尤有關於用於積體電路中互連半導體裝置的自對準局部互連線的設計與製造，但非限之。
隨著半導體技術持續進步，持續的趨勢係朝向帶有越來越小積體電路之製造的超大規模積集度，其於單一半導體晶片上包含越來越多的裝置。
裝置的尺寸縮小長久來係用以增加邏輯與記憶功能的密度。因光刻與其它處理步驟的改進，此尺寸縮小已是可行的。然而，隨著光學微影達到成本效益改善曲線之末端，需要其它方法以改善密度。
在半導體晶片中，互連線提供NMOS及PMOS電晶體與其它如電阻及電容的單元之間的連接。通常藉由於半導體裝置與被動單元上首先沉積介電層與使其平坦化而製造互連線。接著，在介電層中形成連通線(feed-thrus)。最後，在介電層上形成與定義導線路徑以連接連通線。層疊係由多層介電質、連通線，與導線所形成，以完成電路節點互連。製造互連線的此過程通常稱『金 屬噴敷』(metallization)。隨著半導體晶片上裝置之密度的增加，金屬噴敷的複雜性也隨之增加。
局部互連線為互連線之一特殊形式。局部互連線通常用以短距離，如功能單元(functional cell)內。對於局部與總體連接兩者，習知的電路使用相同的互連層。
傳統上，擴散區至Vdd與Vss的接觸需要製造自PMOS與NMOS擴散區個別地朝Vdd與Vss線延伸的L形或T形彎曲擴散區。因為此彎曲區需要更昂貴的光刻設備而製造，故不是最佳的。另外，可在矩形擴散區上延伸Vdd與Vss軌條，而可形成至擴散區的接觸。然而，因為電力軌條佔據了可用於訊號的徑跡，且電力軌條不再坐落於單元邊界，無法於垂直毗連單元之間共享之，故於擴散區上具有電力軌條係無效益的。
於此背景下產生了本發明的實施例。
廣義而言，本發明的實施例定義製造方法、結構、佈局、設計方法，與傳導結構，以定義電路的局部互連線。依據本發明之實施例，當此局部互連線於閘極電極之間或旁邊的通道或區域中對準(做為製造過程的回應)時，本文則稱其為『自對準』局部互連線。此局部互連線係以自對準傾向(self-aligned orientation)所定義之物，可使其圖形化以移除若干材料，僅留下需要完成所選局部互連線的那些部分。
許多有益特徵中的一個係於矩形或實質矩形的擴散區附近著手電路佈局。以優於帶有彎曲或延伸部分之擴散區的精確度製造這些矩形擴散 區。此外，此自對準局部互連線係用以製作與電晶體之源極與汲極的電力連接(即Vdd與Vss)，而不需擴散區延伸部分。自對準局部互連線也可消除電晶體擴散區之特定接觸的需求。如下文將更詳細描述，此局部互連線製作與擴散區的直接且整合接觸。因此，此局部互連線於基板平面上提供以前不可得之金屬路線訂定，此舉用於消除特定第一金屬徑跡、特定介層孔，與在若干例中的第二金屬徑跡(如用以連接NMOS電晶體源極/汲極與PMOS電晶體源極/汲極)之需求。
進一步，藉由消除有效電晶體通道中的傳統擴散區接觸，不用變更此擴散區中的應變層。此舉改善加強應變層之移動率的效益。此外，允許擴散區接觸點與許多供選擇的第一金屬徑跡連接在電路設計中給予更多彈性，從而加強佈局且有利於更有效的放置與路線訂定。
在一實施例中，揭露用以定義局部互連結構的方法。此方法包括於基板上設計不同擴散區。複數個閘極中的若干個係設計為有效閘極，而複數個閘極中的若干個係設計為於隔絕區上形成。此方法包括沿著相同方向以規則且重複對準地設計複數個閘極，且複數個閘極中的每一個係設計為具有介電間隔部。此方法也包括於複數個閘極之間或毗鄰複數個閘極而設計一局部互連層。此局部互連層有導電性且設置於基板上以允許與有效閘極之若干擴散區的電性接觸或互連。藉由此複數個閘極的介電間隔部而使此局部互連層自我對準。
本發明的優點有許多個。最明顯的是，此自對準局部互連線容許帶有較少的彎曲、延伸部分等。此自對準局部互連線也降低所需接觸點的數量、第一金屬徑跡使用、製作擴散區之接觸所需的介層孔數量，與metal-2徑跡使用。因此，呈現更多的徑跡用以訂立路線。此外，自對準局部互連線的使用降低擴 散區接觸之金屬的使用，此舉於基板上降低對應變材料的干預。因此，藉著消除擴散區的大部分金屬，在相當大的程度上提高裝置效益。此自對準局部互連線也於用以在一單元或單元內相連的第一金屬徑跡分配中提供更多彈性，改善密度與簡化後續放置與路線訂定。
於光學對位處理上用以製造局部互連線的自對準過程之另一優點係此自對準局部互連線的製造不需依靠用以使此局部互連線與閘極之側壁間隔部對準的微影技術。眾所週知，由於微影技術具有誤差幅度，因此即使於積體電路中局部互連層朝向閘極之側壁間隔部的微小偏移也可能引起裝置短路或導致不欲之結果。
本發明之其他實施態樣及優點由隨後之舉例說明本發明原理的詳細說明及隨附之相對應圖式當可更加明白。
50‧‧‧第一金屬線/Vdd
54‧‧‧第一金屬線/Vss
58‧‧‧自對準局部互連線
60‧‧‧自對準局部互連線
62‧‧‧自對準局部互連線
64‧‧‧P擴散區
68‧‧‧N擴散區
64(184)‧‧‧(P)擴散區
68(184)‧‧‧(N)擴散區
70‧‧‧第一金屬線
72‧‧‧第一金屬線
74‧‧‧閘極電極(線)
74a‧‧‧閘極電極(線)
74b‧‧‧閘極電極(線)
110‧‧‧PMOS電晶體
112‧‧‧NMOS電晶體
114‧‧‧輸出
116‧‧‧輸入
118‧‧‧Vdd
120‧‧‧接地/Vss
180‧‧‧淺層溝渠隔離區
182‧‧‧阱
184‧‧‧擴散區
196‧‧‧局部互連層
196'‧‧‧矽化物
199‧‧‧硬式遮罩
201‧‧‧基底基板
203‧‧‧擴散區
205‧‧‧擴散接觸點
207‧‧‧閘極電極特徵
209‧‧‧閘極電極接觸點
210‧‧‧聚合物層
211‧‧‧第一金屬層
213‧‧‧第一介層孔層
215‧‧‧第二金屬層
217‧‧‧第二介層孔層
219‧‧‧第三金屬層
221‧‧‧第三介層孔層
223‧‧‧第四金屬層
225‧‧‧額外的互連層
230‧‧‧(閘極電極)介電間隔部
231‧‧‧距離
238‧‧‧側部
300‧‧‧遮罩
300'‧‧‧遮罩
400‧‧‧橫剖面
401‧‧‧p擴散區
402‧‧‧區域
403‧‧‧n擴散區
404‧‧‧遮罩
412‧‧‧N+佈植區
414‧‧‧P+佈植區
501‧‧‧閘極電極特徵
702‧‧‧第一金屬徑跡
703‧‧‧閘極電極空隙
本發明將可藉由上述詳細說明及隨附之相對應圖式而容易理解。為便於描述，相似的參照數字代表相似的結構單元。
圖1依據本發明之一實施例顯示用以定義動態陣列架構的通用層疊。
圖2A依據本發明之一實施例顯示欲投射至動態陣列上以便於定義限制拓樸的示範性基底座標格。
圖2B依據本發明之示範性實施例顯示橫越晶粒之分隔區所投影的分隔基底座標格。
圖3依據本發明之一實施例顯示示範性動態陣列的擴散層佈局。
圖4依據本發明之一實施例顯示圖3的閘極電極層與擴散層。
圖5A依據本發明之一實施例說明使用PMOS與NMOS之邏輯反相器的電路表示法。
圖5B依據本發明之一實施例說明示範性邏輯反相器的平面圖，以展示自對準局部互連線的使用。
圖6A依據本發明之一實施例說明示範性邏輯反相器的平面圖，顯示電晶體源極/汲極、閘極電極，與圍繞閘極電極的側壁間隔部。
圖6B依據本發明之一實施例說明圖6A的示範性邏輯反相器之切線A-A’的橫剖面，顯示電晶體阱、電晶體源極/汲極、閘極電極、側壁間隔部，與STI區。
圖7A依據本發明之一實施例顯示示範性邏輯反相器之斷面，此反相器帶有覆蓋下層圖6A中所示之元件的局部互連層。
圖7B依據本發明之一實施例顯示示範性邏輯反相器之斷面的橫剖面視圖，此反相器帶有覆蓋下層圖6B中所示之元件的局部互連層。
圖8A依據本發明之一實施例說明經由局部互連層的退火而形成矽化物。
圖8B依據本發明之一實施例說明於基板上之局部互連層的頂端沉積硬式遮罩。
圖9A依據本發明之一實施例說明覆蓋圖8B之元件的聚合物層。
圖9B依據本發明之一實施例說明經由電漿蝕刻部分移除聚合物層之基板的橫剖面視圖。
圖9C依據本發明之一實施例說明聚合物層回蝕至閘極電極之頂端附近的基板之平面圖。
圖10A依據本發明之一實施例說明在濕式蝕刻自介電間隔部移除聚合物之後示範性邏輯反相器的平面圖。
圖10B依據本發明之一實施例說明在移除覆蓋介電間隔部的聚合物之後示範性邏輯反相器的橫剖面視圖。
圖11A依據本發明之一實施例說明在自閘極電極與介電間隔部蝕刻局部互連層與硬式遮罩之後示範性邏輯反相器的橫剖面視圖。
圖11B依據本發明之一實施例說明在留存之聚合物層與硬式遮罩的選擇性蝕刻之後示範性邏輯反相器的橫剖面視圖。
圖12依據本發明之一實施例說明在留存之聚合物層與硬式遮罩的選擇性蝕刻之後示範性邏輯反相器的平面圖。
圖13依據本發明之一實施例說明在遮蔽部分局部互連層以於所需處保護局部互連層之後示範性邏輯反相器的平面圖。
圖14依據本發明之一實施例說明示範性邏輯反相器的平面圖，顯示矽化與無矽化局部互連層的留存區。
圖15依據本發明之一實施例說明如圖14之示範性邏輯反相器的平面圖，其帶有增加的接觸點與金屬線以顯示機能互連。
圖16依據本發明之一實施例說明示範性邏輯反相器的平面圖，顯示閘極線之空隙中的自對準局部互連線。
圖17A-17D依據本發明之一實施例說明示範性邏輯反相器的橫剖面視圖，其使用局部互連金屬以製作與閘極的相連。
圖18依據本發明之一實施例說明示範性邏輯反相器的平面圖，顯示閘極線之空隙中的自對準局部互連線與藉著『攀上』間隔部而製作與閘極的相連。
揭露用以於積體電路中設計、佈局、製作、製造與執行『自對準局部互連線』的方法與製程之發明的實施例。在下文描述中，為提供本發明之徹底了解而闡明眾多的具體描述。在一實施例中，提供製造自對準局部互連線的過程。在其它實施例中，揭露方法與佈局技術，其說明使用此自對準局部互連線的方式。下文也特別參照一特殊邏輯單元而概述使用這些自對準局部互連線的益處與優點。然而，應了解到，在自對準局部互連線的使用上，此示範邏輯單元非限制性。可使自對準局部互連線的使用延伸至任何電路佈局、邏輯裝置、邏輯單元、邏輯基元(logic primitive)、內連結構、設計光罩等。因此，在下文描述中，為提供本發明之徹底了解而闡明眾多的具體描述。然而，對於熟悉本技藝者，明顯的是，不用這些特定細節的部分或全部即可實行本發明。在其他例子中，為了避免非必要地搞混本發明而沒有詳盡地描述眾所皆知的處理操作。
此自對準局部互連線於積體電路的製造中具有許多應用。既使是積體電路上局部互連線的微小錯位可能導致電性短路與/或致使裝置不能運作，積體電路中局部互連線的自我對準也消除了微影誤差幅度(lithography error margins)與由此產生的裝置損耗。
此外，自對準局部互連線可用於各式其它用途。一種這樣的用途係使用此自對準局部互連線而自電晶體的擴散區中移開金屬接觸點。
此外，於積體電路中製造『自對準』局部互連線的過程較需要經由微影處理而精確對位的其它技術係有利的。眾所週知，隨著特徵尺寸持續縮小，精確對準光罩的能力難以齊頭並進。此外，來自鄰近形狀的干涉圖案產生建設性或破壞性干涉。以建設性干涉而言，可能不注意地產生不必要的形狀。以破壞性干涉而言，可能不注意地移除所需的形狀。在任一例中，以異於計畫的方式印刷出特殊形狀可能引起裝置故障。如光學鄰近修正術(optical proximity correction，OPC)的修正方法企圖預測來自鄰近形狀的影響，而修正光罩使印刷形狀如所需地被製造。然而，如前所述，隨著製程幾何拓撲結構(process geometries)縮小與隨著光交互作用變得更複雜，光交互作用預測的品質也隨之每況愈下。
隨著此概要銘記於心，下文圖表將說明範例結構、製程步驟、佈局幾何拓撲、遮罩，與互連線佈局。上述種種可以佈局、光罩、具有光罩定義的電腦檔案，與半導體基板上由此產生的層別而表達。因此，應了解到，下文所述的製造過程僅為示範性，且只要維持『自對準』局部互連線的精神與定義，就可省略若干步驟或藉其它步驟而代之。
在一實施例中，本發明的方法與結構利用一致的特徵方向，此舉定義實質一致的特徵方向的畫布(canvas)。在畫布中，於基板內定義若干擴散區以定義電晶體裝置的有效區。此畫布也包括於基板上以共同方向所定向的若干線性閘極電極段。此線性閘極電極段中的一些係設置於擴散區上。擴散區上所設置的每一線性閘極電極段包括於擴散區上所定義之必須的有效區，與定義 為於基板上超過擴散區的均勻延伸部分。此外，此線性閘極電極段係定義為具有可變長度而使邏輯閘運作。此畫布更包括於閘極電極段上的平面內所設置的若干線性導線段，其以實質垂直的方向跨越閘極電極段的共同方向。線性導線段的數目係定義為使基板上一共同線內毗鄰線性導線段之間的端間間隔減至最小。
在描述圖式與解釋實施例中，省略本技藝中眾所皆知的製造過程之各式細節，用以提供易懂且聚焦於待述的實施例。此外，因為與製造過程相關的許多項目於本技藝中係眾所皆知的，故不再細說之。
I.執行一致相對特徵定向之畫布設計的概要
圖1係一說明，依據本發明之一實施例顯示用以定義動態陣列架構的通用層疊。應理解到，如有關圖1所描述的，用以定義動態陣列架構的通用層疊並不旨在窮舉CMOS製造過程的描述。然而此動態陣列係依據標準CMOS製造過程而建立。一般而言，此動態陣列架構包括此動態陣列之下層結構的定義，與用以針對區域利用與可製造性之最優化而組合此動態陣列的技術兩者。因此，此動態陣列係設計為使半導體製造能力最優化。
關於動態陣列之下層結構的定義，於基底基板(如半導體晶圓)201上，例如於矽質基板或絕緣層上覆矽(silicon-on-insulator，SOI)的基板上，以成層方式逐漸建立此動態陣列。擴散區203界定於基底基板201中。通常藉由隔絕區或淺層溝渠隔離(Shallow Trench Isolation，STI)區隔開擴散區203。此擴散區203表示基底基板201的所選區域，其係為改良基底基板201之電性特性的目的而於區內引進雜質。於擴散區203之上，擴散接觸點205係定義為連接擴散區203與導線。例如，此擴散接觸點205係定義為連接源極及汲極擴散區203與其 個別的導線網。此外，於擴散區203之上定義閘極電極特徵207以形成電晶體閘極。閘極電極接觸點209係定義為連接閘極電極特徵207與導線。例如，此閘極電極接觸點209係定義為連接電晶體閘極與其個別導線網。
於擴散接觸點205層與閘極電極接觸點209層上定義互連層。此互連層包括第一金屬(metal 1)層211，、第一介層孔(via 1)層213、第二金屬(metal 2)層215、第二介層孔(via 2)層217、第三金屬(metal 3)層219、第三介層孔(via 3)層221，與第四金屬(metal 4)層223。此金屬與介層孔層定義所需的電路連接性。例如，此金屬與介層孔層電性上連接各式擴散接觸點205與閘極電極接觸點209，而實現電路的邏輯功能。應理解到，此動態陣列架構不限制互連層(即金屬與介層孔層)的特定數目。在一實施例中，此動態陣列除了第四金屬(metal 4)層223以外可包括額外的互連層225。另外，在另一實施例中，此動態陣列可包括少於四層金屬層。
定義此定義動態陣列而使層別(除了擴散區層203以外)受限於關於層中所定義的佈局特徵形狀。具體地說，在非擴散區層203的每一層別中，允許實質線性成型(linear-shaped)佈局特徵。在一既定層中線性成型佈局特徵的特點係具有一致的垂直截面形狀，且於基板上以單一方向延伸。然而，假設對若干線路需要做接觸點，則允許若干微小的垂直擠壓，但這些微小的垂直擠壓不應在方向上構成實質改變。因此，此線性成型佈局特徵定義一維變化的結構。儘管若必要時允許擴散區203係一維變化，但其係不需如此。具體地說，關於與基板之頂端表面一致的一平面，基板內的擴散區203係定義為具有任何二維變化形狀。在一實施例中，限制擴散彎曲拓撲的數目而使擴散區的彎曲與形成電晶體之閘極電極的導電材料(如多晶矽)之間的交互作用係可預期且可精確 地建模。既定層中的線性成型佈局特徵係定位為彼此平行。因此，既定層中的線性成型佈局特徵於基板上以一共同方向延伸且平行於此基板。
在一實施例中，於微影處理中動態陣列的下層佈局方法可(但非必須)使用光波之建設性光干涉，以於既定層中加強鄰近形狀的曝光。因此，在駐光波的建設性光干涉周圍定義既定層中的平行線性成型佈局特徵之間隔，而使光學修正(例如OPC/RET)減至最小量或消除之。因此，對照習知以OPC/RET為基底的微影處理，本文所定義的動態陣列利用鄰近特徵之間的光交互作用，而非企圖針對鄰近特徵之間的光交互作用進行補償。
因為可精確地建立既定線性成型佈局特徵之駐光波的模型，有可能預測與既定層中平行所設置的鄰近線性成型佈局特徵有關的駐光波將如何交互作用。因此，有可能預測用以照射一線性成型特徵的駐光波將如何促成其鄰近線性成型特徵的曝光。鄰近線性成型特徵之間的光交互作用之預測可確認最佳特徵間間隔(feature-to-feature spacing)，而使用以顯現既定形狀的光將加強其鄰近形狀。既定層中的特徵間間隔係定義為特徵間距，其中此間距係既定層中毗鄰線性成型特徵之間的中心間(center-to-center)相隔距離。
在一實施例中，為提供鄰近特徵之間所需的曝光增強，將既定層中的線性成型佈局特徵均勻分開而使自鄰近特徵的光之建設性與破壞性干涉最佳化，以產生鄰近區中所有特徵的最佳成像(rendering)。既定層中的特徵間間隔係正比於用以照射此特徵的光波長。用以照射離既定特徵約五倍波長距離內的每一特徵的光將用於使既定特徵的曝光增強至若干程度。充分利用用以照射鄰近特徵的光波之建設性干涉可使製造設備能力於微影處理期間能夠最大化且不被關於光交互作用之考量而限制。
如上述，動態陣列加入限制拓樸，其中需要每一層(非擴散層)內的特徵在形狀上為實質線性，且以平行方式定向而以一共同方向橫越基板。帶著此動態陣列的拓樸，可使光刻處理中的光交互作用最佳化而完成佈局之精確移轉至光阻上。
圖2A係一說明，依據本發明之一實施例顯示欲投射至動態陣列上的示範性基底座標格(base grid)，以便於定義此限制拓樸。此基底座標格可用以便於以適當最佳間距而於每一動態陣列層中平行排列線性成型特徵。儘管基底座標格非實體上定義為動態陣列之一部分，此基底座標格可認為是每一動態陣列層上的投影。此外，應了解到，以關於每一動態陣列層上之位置的實質一致方式投影此基底座標格，從而使精確的特徵便於堆疊與對準。
在圖2A的示範性實施例中，此基底座標格係依據第一參考方向(x)與第二參考方向(y)定義為矩形座標格，即笛卡耳座標格(Cartesian grid)。第一與第二參考方向中的座標格點間間隔(gridpoint-to-gridpoint spacing)必要時係定義為以最佳特徵間間隔定義線性成型特徵。此外，第一參考方向(x)中的座標格點間隔可異於第二參考方向(y)中的座標格點間隔。在一實施例中，橫越整個晶粒(die)投影單一基底座標格以於橫越整個晶粒的每一層中設立各式線性成型特徵。然而，在其它實施例中，橫越晶粒的不同區投影不同的基底座標格，以於晶粒的不同區內支持不同特徵間間隔需求。圖2B係一說明，依據本發明之示範實施例顯示橫越晶粒之不同區所投影的不同基底座標格。
此動態陣列的佈局架構跟隨此基底座標格圖案。因此，有可能使用座標格點表示於閘極電極與金屬線性成型特徵所設置的擴散區中哪裡發生方向上的改變、那裡設置接觸點、於線性成型閘極電極與金屬特徵中開孔在哪裡 等。對於既定特徵線寬應設定座標格點的間距，即座標格點間間隔，而使既定特徵線寬之鄰近線性成型特徵的曝光將彼此加強，其中此線性成型特徵係集中於座標格點上。參照圖1的動態陣列層疊與圖2A的示範基底座標格，在一實施例中，藉由所要求的閘極電極間距而設定第一參考方向(x)中的座標格點間隔。在此相同的實施例中，藉由第一金屬間距而設定第二參考方向(y)中的座標格點間距。例如，在90nm邏輯製程技術中，第二參考方向(y)中的座標格點間距約為0.24微米。在一實施例中，第一金屬與第二金屬層具有共同的間隔與間距。可於此第二金屬層上使用不同間隔與間距。
定義此動態陣列的各式層別而使毗鄰層中的線性成型特徵彼此以相互交叉的方式延伸。例如，毗鄰層的線性成型特徵可正交地延伸，即彼此相互垂直。此外，一層的線性成型特徵可以如約45度的角度延伸橫越毗鄰層的線性成型特徵。例如，在一實施例中，一層的線性成型特徵在第一參考方向(x)上延伸，而毗鄰層的線性成型特徵在相對於第一(x)與第二(y)參考方向上對角地延伸。應理解到，為在具有於毗鄰層中以相互交叉方式設置的線性成型特徵之動態陣列中訂定路線設計，在線性成型特徵中定義開口，且如必要時定義接觸點與介層孔。
此動態陣列使佈局形狀中的彎曲(或方向上實質改變)使用減至最小，以消除不可預期的微影交互作用。具體地說，在OPC或其它RET處理之前，動態陣列允許擴散層中的彎曲以控制裝置大小，但不允許擴散層上之層別中的實質彎曲(或方向上實質改變)。
關於圖3與4係描述自擴散層至第二金屬層之動態陣列的示範性增長。應理解到，僅經由範例方式提供關於圖3與4所描述的動態陣列，並不旨 在傳達此動態陣列架構的限制性。可依據本文所呈現的原理使用此動態陣列，以根本上定義任何積體電路設計、任何邏輯單元、基本單元、架構，或設計佈局。設計可在實體晶片、晶圓、基板上或畫在紙、薄膜上，或存在檔案中。假設存在檔案中，此檔案可存於任何電腦可讀裝置。此電腦可讀裝置可存於區域電腦上、網路電腦上，且可經由網際或區域網路傳輸、分享或使用此檔案。
圖3依據本發明之一實施例顯示示範性動態陣列的擴散層佈局。圖3的擴散層顯示p擴散區401與n擴散區403。當依據下層的基底座標格定義此擴散區時，此擴散區係不受與擴散層上方層別有關的線性成型特徵限制之影響。然而，應注意到，佈植區佈局係較先前技藝設計更為簡單，其先前技藝設計另外需要更多形狀延伸與彎曲。如所示，n+佈植區(412)與p+佈植區(414)係定義為(x)與(y)座標格上不帶有外來的差階(jogs)與凹口之矩形。此樣式容許使用更大的佈植區，降低OPC/RET的需求，且能使用較低解析度與較低成本的微影系統，如365nm的i-line曝光系統。
圖4係一說明，依據本發明之一實施例顯示於圖3的擴散層之上且與其毗鄰的閘極電極層。如熟悉CMOS技藝者的理解，閘極電極特徵501定義電晶體閘極。此閘極電極特徵501係定義為於第二參考方向(y)上以平行關係延伸橫越於動態陣列的線性成型特徵。在一實施例中，此閘極電極特徵501係定義為具有共同的寬度。然而，在其它實施例，閘極電極特徵中一或多個係定義為具有不同的寬度。當確保鄰近閘極電極特徵501所提供的微影增強，即共振成像，最優化時，此閘極電極特徵501的間距(中心間間隔)減至最小量。為討論目的，在既定線條上延伸橫越於動態陣列的閘極電極特徵501稱為閘極電極徑跡。
當閘極電極特徵501橫越擴散區403與401時，個別地形成n-通道與p-通道電晶體。僅管在若干座標格位置上無呈現擴散區，但藉由在每一座標格位置上繪製閘極電極特徵501而完成最佳的閘極電極特徵501印刷。此外，於動態陣列的內部之內，長形連續閘極電極特徵501於其端點上有助於改善線端縮短效應。另外，當自此閘極電極特徵501中實質移除所有的彎曲時，在相當大的程度上改善閘極電極印刷。
在線性橫越動態陣列中，可數次打斷(即斷開)每一閘極電極徑跡以提供欲執行之特定邏輯功能的所要求電性連通性。當要求打斷既定閘極電極徑跡時，使此閘極電極徑跡線段之末端於斷開點處之間的分隔減小至考慮到製造能力與電性效應的可能寬度。在一實施例中，當於特定層內特徵之間使用共同端間間隔時，達成最佳化的可製造性。
II.在畫布上使用自對準局部互連線的邏輯單元設計
圖5A說明示範性邏輯反相器的電路表示法。然而，如上所述，僅顯示及討論此邏輯反相器以傳達製作自對準局部互連線的過程，此過程可執行任何其它基元、單元、邏輯裝置，或處理方法。如所示，連結PMOS電晶體110與NMOS電晶體112以製作一邏輯反相器。PMOS電晶體110的源極係連接於Vdd 118，而PMOS電晶體110的汲極係連接於NMOS電晶體112的汲極。NMOS電晶體112的源極係接地(Vss)120。為電晶體設置共同的輸入116，且在PMOS電晶體110的汲極與NMOS電晶體112的汲極之連接處設置輸出114。再者，使用此邏輯反相器為例子以提供本發明之實施例的了解。然而，熟悉本技藝者將理解此實施例也可用於任何其它形式之邏輯單元、裝置，與積體電路的製造。
圖5B說明示範性邏輯反相器的平面圖，其具有將P 64及N 68擴散區分別連接至Vdd 50及Vss 54的自對準局部互連線58/60。也使用自對準局部互連線62連接PMOS電晶體的汲極與NMOS電晶體的汲極。在一實施例中，於基板上積體電路中的所有自對準局部互連線係平行於閘極電極通道。使局部互連線舖設為一方向的許多優點之一係此局部互連層可取代另外需要使用自對準局部互連線製作連接點的一金屬層。第一金屬線50、72、70，與54係對準垂直於閘極電極線74的一方向。在其它實施例中，金屬線的對位可為不同。
仍參照圖5B，使用自對準局部互連線有許多優點。在一實施例中，連接P擴散區64與Vdd線50的自對準局部互連線58消除製造朝向Vdd線50延伸之L形擴散區的需要。在若干設計中，此自對準局部互連線58消除連接擴散區64與Vdd線50之金屬帶的需要。此金屬帶與相關接觸點之消除提高裝置效能與縮小裝置尺寸。因為連接擴散區的金屬帶需要一或多個連接點，其干預矽的有益應變，而降低了效能。因此，除非若干設計組態的需要，減少擴散區的金屬接觸點將促進裝置效能。
圖6A說明部分已製成積體電路之平面圖，顯示於P擴散區64與N擴散區68上的P擴散區64、N擴散區68與閘極電極線74。在此部分視圖例子中，其它的閘極電極線74a與74b係舖設於淺層溝渠隔離(STI)區上。閘極電極線74、74a與74b包括兩邊的間隔部(或閘極側壁間隔部)。
儘管為討論之便易而未顯示，閘極電極的端點也具有介電間隔部。既然於基板上藉由設計而均勻放置閘極電極線，若干閘極電極線係形成於STI區上。因此，於STI區上所形成的閘極係無效閘極(inactive gates)。當於擴 散區上放置閘極電極時，形成有效閘極，且定義了電晶體。在一實施例中，使用標準CMOS製造過程製造此部分已製成積體電路。
圖6B說明圖6A的部分已製成積體電路之橫剖面。應了解到，此圖不意味提供精確的維度呈現或精確的相對維度。另一方面，此圖應被理解為通常傳達特徵與層別的安排，與處理的範例順序。此外，應了解到，當若干順序步驟為熟悉本技藝者所知悉，且對本文所說明的處理及順序流程係不重要時，不用圖畫地說明之。
將此銘記於心，此部分已製成積體電路係於矽晶圓上形成，且包括阱182與淺層溝渠隔離(STI)區180，以於積體電路中提供毗鄰有效裝置之間的隔絕。阱182包括擴散區184與閘極電極74。此閘極電極包括沿著閘極電極線之側所形成的介電間隔部(也稱為側壁間隔部)230。如上文討論，為使設計最佳化，以平行方向彼此相對地製造此閘極電極(或線)。因此，如本文所述，『通道』係定義於個別閘極電極之間。藉由閘極電極線的規則間隔而因此指定介於兩毗鄰閘極電極通道之間的間隔。如下文更詳細地討論，由此產生的自對準局部互連線將存在於毗鄰閘極電極(或若無鄰近閘極電極時，於閘極電極旁邊)之間的通道。因為自對準局部互連線主要留存在通道中，其將可自我對準。
在圖7A與7B中，於擴散區184、閘極電極74、74a與74b，與間隔部上形成局部互連層196。舉例來說，可經由金屬沉積處理形成局部互連層196。為透視之便易，圖7A中以半透明層顯示此局部互連層196。圖7B的橫剖面顯示圖6B之特徵上所沉積的局部互連層196。
在一實施例中，此局部互連層196通常為金屬。在更具體的實施例中，此金屬主要為鎳(Ni)。在其它實施例中，此金屬為鈦、鉑，或鈷。在 另一實施例中，使用鎳與鉑的合金。最好，局部互連層中所用的金屬之純度遵守工業標準金屬。在一實施例中，使用物理氣相沉積(PVD)技術沉積此局部互連層。在其它實施例中，經由化學氣相沉積(CVD)或原子層沉積(ALD)而沉積此局部互連層。
在沉積局部互連層196之後，互連層的金屬與下層的矽反應，且若互連層出現在閘極電極中，則與多晶矽反應。在一實施例中，經由熱處理步驟而促進此反應。在若干處理條件下可實現此反應，以鎳層做為一例子，溫度的範圍係於約攝氏200至400度之間、運作的時間範圍約5至約60秒；更高溫可用於其它金屬。在另一實施例中，溫度係設定為約攝氏300度，運作約30秒。通常在使用氮氣或其它惰性氣體的腔室中執行此反應步驟。
如圖8A所示，做為反應過程的結果，於裸露矽質區上形成矽化物196’。因此，此矽化作用(即矽化物196’的形成)發生於裸露矽基板部分與裸露多晶矽閘極(若存在時)上。如眾所週知，儘管矽化物196’係薄的，其提供良好導電。當然，在反應過程之後，未觸及矽質的部份局部互連層196依然係金屬。在圖示中，圖8A以陰影顯示矽化物196’，對照於未反應之局部互連層196的金屬。
圖8B說明於局部互連層196上沉積硬式遮罩199後的結果。在一實施例中，此硬式遮罩199為氧化物(如SiO2等)。在其它實施例中，此硬式遮罩199為氮化物(如氮化矽等)。在另一實施例中，此硬式遮罩199為非晶碳(APC)。可以若干方法形成硬式遮罩199，且一種如此的示範方法係藉由使用CVD、ALD，與PECVD處理中的一種。在此實施例中，此硬式遮罩199係用以於後續移除步驟期間保護局部互連層196，此移除步驟移除不需導電連接的部分局部互連層196。
圖9A依據本發明之一實施例顯示於70199上形成聚合物層210之後圖8B的橫剖面。以本技藝中所知悉的若干方法塗佈聚合物層210。在一實施例中，於硬式遮罩199的表面上最好是旋塗聚合物層210。在另一實施例中，聚合物層210為光阻材料，正型或負型，取決於所需顯影處理。例如，其他形式的光阻包括未敏化光阻(unsensitized photoresists)、聚甲基丙烯酸甲酯(PMMA)抗蝕劑等。如圖9B所示，一經塗佈，部分且均勻地移除聚合物層210直至裸露硬式遮罩199。最好使用電漿蝕刻處理執行此移除。一個範例蝕刻處理發生在氧氣電漿中。在此步驟中，此蝕刻處理實質上最好係非等向性而完成實質均勻移除輪廓深至首先裸露的硬式遮罩199。可使用標準端點偵測(end-point detection)技術判定何時停止圖9B中所說明的蝕刻操作。圖9C係一平面圖，顯示裸露的硬式遮罩199與留存的聚合物層210。在此階段，閘極側壁間隔部(即介電間隔部)230仍被聚合物層210所覆蓋。
應注意到，以一致的規則間隔放置閘極電極的另一優點為聚合物層210係一致地定義為具有實質相等厚度。若無如此一致間隔，聚合物層210將在厚度上顯出變化，其係所不欲之事。例如，假設此聚合物層210之厚度無法實質均勻覆蓋基板，帶有相對少量聚合物材料的若干閘極電極將首先裸露，於特定閘極上引起硬式遮罩之可能的過蝕刻。
一旦裸露閘極電極74、74a與74b之頂部上的硬式遮罩199，便執行等向蝕刻。此等向蝕刻係設計為移除聚合物層210之側部238，如閘極電極介電間隔部230上的聚合物層210。如圖10A與10B所示，在完成此等向蝕刻後，聚合物層210應以帶狀形式留存在閘極電極74、74a與74b之間，水平錯斷(offset) 且自我對準於閘極介電間隔部230。因此，除閘極電極線74、74a與74b與閘極電極介電間隔部230上之外，聚合物層210將留存在基板上各處。
圖11A說明移除未被除聚合物層210所覆蓋的硬式遮罩199之後基板的橫剖面。取決於所選硬式遮罩的材料，使用若干已知的濕式或乾式蝕刻處理執行此移除。在一實施例中，一旦移除裸露的硬式遮罩199，繼續蝕刻以自介電間隔部230上移除部分局部互連層196。此部分局部互連層196之移除將為局部互連層196/矽化物196’與介電間隔部230之間的輕微分開做準備。在這一點上，留存的局部互連層196材料、矽化物196’材料與仍被聚合物層210所覆蓋的硬式遮罩199將存於介電間隔部230之間且為其所對準的通道中。
圖11B說明執行另外選擇性蝕刻操作以自局部互連層196(包括矽化物部分196’)上移除聚合物層210與硬式遮罩199之後基板的橫剖面。可以看出，此局部互連層196材料與矽化物部分196’將於介電間隔部230之間自我對準。圖12顯示圖11B中基板的平面圖。如所示，此局部互連層196存於閘極介電間隔部230之間的通道中。如上所述，做為蝕刻的結果，此自對準局部互連線196也與介電間隔部230間隔一距離231。圖12也說明P 64與N 68擴散區(在橫剖面中此兩區係說明為擴散區184)。
圖13依據本發明之一實施例說明使蝕刻便利的圖形化操作。在一實施例中，旋塗一光阻，接著使用標準光刻曝光以定義遮罩300。如所示，此遮罩300係定義為覆蓋執行蝕刻操作後所留存的部分局部互連層196。既使於裸露矽質或多晶矽(若存在的話)上形成矽化物196’的反應材料不被遮罩300所覆蓋，其也將在蝕刻後留存下來。在一實施例中，因為此遮罩300係定義為寬鬆地舖設於閘極電極74、74a與74b上，故無需嚴格佈局限制即可輕易定義之。
應理解到，當局部互連層196材料僅舖設於通道中，且於介電間隔部230之間已自對準時，不需要嚴格的佈局限制。再者，在執行蝕刻以移除局部互連層196的未受保護部份之後，矽化物196’材料仍留存著。電性上，此局部互連層196與矽化物196’材料將定義導電連結或連接或導線，相似於常例的互連金屬線。
圖14說明蝕刻與後續移除遮罩300之後基板的平面圖。如所示，局部互連層196將留存在遮罩300保護材料的通道中，從而形成實際的自對準局部互連特徵。因此，留存的局部互連層196將於介電間隔部230之間所定義的通道內機能上完成任何所需的互連。在移除遮罩300之後，執行退火操作。例如，此退火可為快速熱退火(RTA)法，其針對鎳係於約攝氏450度下操作約30秒。
回頭參照圖5B，如圖15所示垂直於閘極電極線74、74a與74b而製造第一金屬線。此外，於所需處形成接觸點以提供各式層別之間的電性連接，此舉對形成示範性邏輯電路係必要的。
在一實施例中，彼此緊靠地製造第一金屬徑跡702，此舉可更輕易地訂定路線與所需連接。當然，線間的間距將取決於製造能力、特殊電路、佈局，與設計與/或電路之形式的佈局限制。隨著垂直於第一金屬徑跡702而對準自對準局部互連線196，將提供更大的空間自由度用以定義/選擇自對準局部互連線196與所選第一金屬徑跡之間的接觸點。因此，除了先前所討論的自對準局部互連線之優點之外，自對準局部互連線也可在上述層面訂定金屬徑跡中幫助提供更多自由度，轉而提供設計與製造的彈性。
圖16說明示範性反相器邏輯單元，其係使用本發明之自對準局部互連線所製造。除了閘極電極線74a係分成兩段以提供閘極電極空隙703之外， 此電路相似於圖5A中所說明者。應注意到，僅為說明之便易而僅顯示一個空隙。在其它實施例中，一或多條閘極電極線具有一或多個閘極電極空隙。在一實施例中，此閘極電極空隙703係用以製造自對準局部互連線，其係垂直於閘極電極線74a而對準。在這些閘極電極空隙703中的自對準局部互連線係用以連接二或多個裝置，或連接平行於閘極電極線74a的兩條自對準局部互連線。在這些閘極電極空隙703中的自對準局部互連線也可使金屬徑跡路線排定容易且消除若干第一金屬徑跡的需求。
圖17A-17D依據本發明之另一實施例說明用以使用局部互連層196製造連接的處理操作，以製作與閘極電極74的接觸。為了解之便易，請參考橫剖面400，其也於顯示於圖18中。圖17A呈現相似於演變成圖10B所述的處理中的一階段。然而，於區402上也形成遮罩404，其實質位於閘極電極74之間隔部230的側壁上。只要於沿著間隔部230的材料上提供保護，精確的尺寸就非格外重要。遮罩404於此區保護局部互連線材料196免於隨後的蝕刻。取決於所選的製造過程，可自硬式遮罩或光阻遮罩定義此遮罩404。
圖17B顯示在使用蝕刻操作移除裸露的硬式遮罩199之後的處理。如所示，移除裸露的硬式遮罩199與局部互連層196，其相似於圖11A的處理。現在，移除遮罩404、聚合物層210，與硬式遮罩199，如圖17C所示，留下局部互連層196。圖17C也顯示遮罩300’，其用以於欲留存局部互連層196之處保護局部互連層196。顯示遮罩300’於區域402中覆蓋局部互連層196且保護之。因此，因為使用遮罩404，局部互連層196將留存在間隔部230之側壁上，從而允許局部互連層196與閘極電極74之矽化物196’材料產生連接。因此，無需上層金屬層與接觸點，於基板之層面上製作連接用以與閘極電極74連接。
圖18顯示使用局部互連層196的例子，其攀上介電間隔部230以於區域402中製作與閘極電極74的連接。在此例中，此局部互連層196(其跨上介電間隔部230)與閘極電極電性上相連。然而，應了解到，用以形成攀上間隔部230之連接的結構與方法可用於許多不同的設計、電路、單元，與邏輯互連。
已揭露方法、設計、佈局，與結構，其定義使用自對準局部互連線的方式。應銘記於心，使用這些自對準局部互連線的益處與優點並不限於任一特定電路、單元或邏輯。相反地，這些自對準局部互連方法與結構的揭露可延伸至任一電路佈局、邏輯裝置、邏輯單元、邏輯基元、互連結構、設計光罩等。而且，由此產生用以定義此自對準局部互連線(於晶片、較大之完整系統或實施之任一部分或區域中)的佈局、設計、組態或資料可電子式地存於檔案中。此檔案可存於電腦可讀媒體，且此電腦可讀媒體可於如網際網路的網路上分享、傳送或交流。
因此，隨著上述實施例銘記於心，應了解到，本發明在製造過程、製造步驟、製造步驟之順序、製造中所用的化學劑、製造中所用的處理、組態與各式單元的相對位置中可採用其它的變化。雖然已按照數個較佳實施例而敘述本發明，應理解熟悉本技藝者研讀具體說明及研究圖式時可在其中做各式替換、增加、交換及等價動作。因此，意味著本發明包含落入本發明的真實精神及範圍內之所有如替代、增加、交換及等價動作。
50‧‧‧第一金屬線/VDD
54‧‧‧第一金屬線/VSS
58‧‧‧自對準局部互連線
60‧‧‧自對準局部互連線
62‧‧‧自對準局部互連線
64‧‧‧P擴散區
68‧‧‧N擴散區
70‧‧‧第一金屬線
72‧‧‧第一金屬線
74‧‧‧閘極電極(線)
74A‧‧‧閘極電極(線)
74B‧‧‧閘極電極(線)

Claims (22)

  1. 一種積體電路，包含： 　　至少四個線性成型導電結構，形成為以彼此平行的方式在一第一方向上縱向延伸，且各自分別包括一閘極電極部分及自該閘極電極部分延伸出去的一延伸部分，該至少四個線性成型導電結構的該等閘極電極部分分別形成不同電晶體的閘極電極，該至少四個線性成型導電結構的該等延伸部分包括至少二個不同的延伸部分長度，其中，該至少四個線性成型導電結構其中二者分別形成具有第一擴散類型的一共享擴散區域的二個第一電晶體類型的電晶體，其中，該至少四個線性成型導電結構其中二者分別形成具有第二擴散類型的一共享擴散區域的二個第二電晶體類型的電晶體，其中該第一擴散類型的該共享擴散區域係電連接至該第二擴散類型的該共享擴散區域；及 　　一局部互連導電結構，形成在該至少四個線性成型導電結構其中至少二者之間，以沿著該至少四個線性成型導電結構的該至少二者在該第一方向上延伸。
  2. 如申請專利範圍第1項之積體電路，其中當在垂直於該第一方向的一第二方向上量測時，介於該至少四個線性成型導電結構任何者的縱向定向中心線之間的距離係一相等間距的整數倍。
  3. 如申請專利範圍第2項之積體電路，更包含： 　　至少一非閘極的線性成型導電結構，其不形成一電晶體的一閘極電極，且係形成在與該至少四個線性成型導電結構相同的一層面內。
  4. 如申請專利範圍第3項之積體電路，其中當在垂直於該第一方向的該第二方向上量測時，介於該至少四個線性成型導電結構的毗鄰配置者的縱向定向中心線之間的距離係該相等間距。
  5. 如申請專利範圍第3項之積體電路，其中該等不同電晶體包括集合配置的多個第一電晶體類型的電晶體及集合配置的多個第二電晶體類型的電晶體，該至少四個線性成型導電結構的該等延伸部分係形成在介於該等第一電晶體類型的電晶體的一集合位置與該等第二電晶體類型的電晶體的一集合位置之間的一區域之內。
  6. 如申請專利範圍第1項之積體電路，更包含： 　　一非閘極的線性成型導電結構，其不形成一電晶體的一閘極電極，且係形成在與該至少四個線性成型導電結構相同的一層面內，且當在垂直於該第一方向的一第二方向上量測時係在一最鄰近之線性成型導電結構的至少360奈米之內；及 　　一擴散區域，在一區域的一部分之內加以形成，該區域係在該非閘極的線性成型導電結構與該最鄰近之線性成型導電結構之間延伸且位於該非閘極的線性成型導電結構與該最鄰近之線性成型導電結構下方之一層面處。
  7. 如申請專利範圍第6項之積體電路，其中當在垂直於該第一方向的該第二方向上量測時，該非閘極的線性成型導電結構與該最鄰近之線性成型導電結構具有實質相同大小。
  8. 如申請專利範圍第1項之積體電路，其中該第一擴散類型的該共享擴散區域係經由該局部互連導電結構加以電連接至該第二擴散類型的該共享擴散區域。
  9. 如申請專利範圍第1項之積體電路，更包含： 　　一第一線性成型導電互連結構，形成為在垂直於該第一方向的一第二方向上縱向延伸。
  10. 如申請專利範圍第9項之積體電路，更包含： 　　一第二線性成型導電互連結構，形成為在垂直於該第一方向的該第二方向上縱向延伸，且形成為與該第一線性成型導電互連結構相鄰且分隔開。
  11. 如申請專利範圍第1項之積體電路，更包含： 　　一第一線性成型導電互連結構，形成為在該第一方向上縱向延伸。
  12. 如申請專利範圍第11項之積體電路，更包含： 　　一第二線性成型導電互連結構，形成為在該第一方向上縱向延伸，且形成為與該第一線性成型導電互連結構相鄰且分隔開。
  13. 如申請專利範圍第12項之積體電路，其中當在垂直於該第一方向的一第二方向上量測時，介於該至少四個線性成型導電結構任何者的縱向定向中心線之間的距離係一相等間距的整數倍數，且 　　其中當在垂直於該第一方向的該第二方向上量測時，該第一和第二線性成型導電互連結構的縱向定向中心線之間的距離係該相等間距的有理數倍數。
  14. 如申請專利範圍第13項之積體電路，其中該有理數倍數係小於或等於一。
  15. 如申請專利範圍第14項之積體電路，其中該有理數倍數係一。
  16. 如申請專利範圍第1項之積體電路，更包含： 　　一互連層面，包括以在該第一方向上測得之一第一中心線到中心線距離分隔開的毗鄰配置的導電互連結構，該至少四個線性成型導電結構的該等延伸部分其中至少一者具有大於該第一中心線到中心線距離之在該第一方向上測得的一延伸部分長度。
  17. 如申請專利範圍第16項之積體電路，其中該至少四個線性成型導電結構的該等延伸部分其中至少一者具有大於二倍的該第一中心線到中心線距離之在該第一方向上測得的一延伸部分長度。
  18. 如申請專利範圍第1項之積體電路，其中該至少四個線性成型導電結構其中至少一者具有大於其閘極電極部分長度的一延伸部分長度。
  19. 如申請專利範圍第1項之積體電路，其中該至少四個線性成型導電結構的該等延伸部分包括至少三個不同的延伸部分長度。
  20. 如申請專利範圍第1項之積體電路，其中該等不同電晶體包括集合配置的多個第一電晶體類型的電晶體及集合配置的多個第二電晶體類型的電晶體，該至少四個線性成型導電結構的該等延伸部分係形成在介於該等第一電晶體類型的電晶體的一集合位置與該等第二電晶體類型的電晶體的一集合位置之間的一區域之內。
  21. 一種資料儲存裝置，具有儲存於其上的程式指令用於半導體元件佈局，包含： 　　至少四個線性成型導電結構的佈局，該至少四個線性成型導電結構以彼此平行的方式在一第一方向上縱向延伸，且各自分別包括一閘極電極部分及自該閘極電極部分延伸出去的一延伸部分，該至少四個線性成型導電結構的該等閘極電極部分分別形成不同電晶體的閘極電極，該至少四個線性成型導電結構的該等延伸部分包括至少二個不同的延伸部分長度，其中，該至少四個線性成型導電結構其中二者分別形成具有第一擴散類型的一共享擴散區域的二個第一電晶體類型的電晶體，其中，該至少四個線性成型導電結構其中二者分別形成具有第二擴散類型的一共享擴散區域的二個第二電晶體類型的電晶體，其中該第一擴散類型的該共享擴散區域係電連接至該第二擴散類型的該共享擴散區域；及 　　一局部互連導電結構的佈局，該局部互連導電結構係形成在該至少四個線性成型導電結構其中至少二者之間，以沿著該至少四個線性成型導電結構的該至少二者在該第一方向上延伸。
  22. 一種製作積體電路的方法，包含： 　　在該積體電路的一閘極電極層面之內形成至少四個線性成型導電結構，該至少四個線性成型導電結構以彼此平行的方式在一第一方向上縱向延伸且各自分別包括一閘極電極部分及自該閘極電極部分延伸出去的一延伸部分，該至少四個線性成型導電結構的該等閘極電極部分分別形成不同電晶體的閘極電極，該至少四個線性成型導電結構的該等延伸部分包括至少二個不同的延伸部分長度，其中，該至少四個線性成型導電結構其中二者分別形成具有第一擴散類型的一共享擴散區域的二個第一電晶體類型的電晶體，其中，該至少四個線性成型導電結構其中二者分別形成具有第二擴散類型的一共享擴散區域的二個第二電晶體類型的電晶體，其中該第一擴散類型的該共享擴散區域係電連接至該第二擴散類型的該共享擴散區域；及 　　形成一局部互連導電結構於該至少四個線性成型導電結構其中至少二者之間，以沿著該至少四個線性成型導電結構的該至少二者在該第一方向上延伸。
TW105134374A 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計 TWI598998B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98309107P 2007-10-26 2007-10-26
US11/969,854 US7763534B2 (en) 2007-10-26 2008-01-04 Methods, structures and designs for self-aligning local interconnects used in integrated circuits

Publications (2)

Publication Number Publication Date
TW201701408A TW201701408A (zh) 2017-01-01
TWI598998B true TWI598998B (zh) 2017-09-11

Family

ID=40580283

Family Applications (6)

Application Number Title Priority Date Filing Date
TW106120372A TWI619204B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW097141040A TWI402940B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW105134374A TWI598998B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW102123005A TWI552267B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW105111571A TWI569369B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW106145373A TW201814835A (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW106120372A TWI619204B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW097141040A TWI402940B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計

Family Applications After (3)

Application Number Title Priority Date Filing Date
TW102123005A TWI552267B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW105111571A TWI569369B (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計
TW106145373A TW201814835A (zh) 2007-10-26 2008-10-24 積體電路中採用之自對準局部互連線用之方法、結構與設計

Country Status (5)

Country Link
US (8) US7763534B2 (zh)
EP (4) EP2592648A1 (zh)
KR (7) KR101588626B1 (zh)
TW (6) TWI619204B (zh)
WO (1) WO2009054936A2 (zh)

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8653857B2 (en) * 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9349738B1 (en) * 2008-02-04 2016-05-24 Broadcom Corporation Content addressable memory (CAM) device having substrate array line structure
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US7709301B2 (en) * 2008-04-23 2010-05-04 Texas Instruments Incorporated Integrated circuit having efficiently packed decoupling capacitors
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
GB2466313A (en) 2008-12-22 2010-06-23 Cambridge Silicon Radio Ltd Radio Frequency CMOS Transistor
KR101536562B1 (ko) * 2009-02-09 2015-07-14 삼성전자 주식회사 반도체 집적 회로 장치
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US7969199B1 (en) 2010-05-10 2011-06-28 Pdf Solutions, Inc. Pattern controlled IC layout
US9312260B2 (en) 2010-05-26 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and manufacturing methods thereof
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
DE102011004922B4 (de) * 2011-03-01 2016-12-15 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zur Herstellung von Transistoren mit Metallgatestapeln mit erhöhter Integrität
US8742464B2 (en) 2011-03-03 2014-06-03 Synopsys, Inc. Power routing in standard cells
US8612914B2 (en) 2011-03-23 2013-12-17 Synopsys, Inc. Pin routing in standard cells
US8513978B2 (en) * 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US8631374B2 (en) 2011-03-30 2014-01-14 Synopsys, Inc. Cell architecture for increasing transistor size
KR101294449B1 (ko) * 2011-04-13 2013-08-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 집적 회로 및 집적 회로의 제조 방법
US8446176B1 (en) * 2011-12-15 2013-05-21 Freescale Semiconductor, Inc. Reconfigurable engineering change order base cell
US8598633B2 (en) * 2012-01-16 2013-12-03 GlobalFoundries, Inc. Semiconductor device having contact layer providing electrical connections
US8921136B2 (en) * 2013-01-17 2014-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Self aligned contact formation
US20140241055A1 (en) * 2013-02-25 2014-08-28 Infineon Technologies Ag Method and System for Reducing the Complexity of Electronically Programmable Nonvolatile Memory
US9024418B2 (en) * 2013-03-14 2015-05-05 Qualcomm Incorporated Local interconnect structures for high density
TWI588596B (zh) * 2013-08-15 2017-06-21 聯華電子股份有限公司 產生佈局圖案的方法
US9761489B2 (en) * 2013-08-20 2017-09-12 Applied Materials, Inc. Self-aligned interconnects formed using substractive techniques
KR102233211B1 (ko) * 2013-10-11 2021-03-29 삼성전자주식회사 반도체 소자
KR102224525B1 (ko) * 2014-02-03 2021-03-08 삼성전자주식회사 레이아웃 디자인 시스템, 이를 이용하여 제조한 반도체 장치 및 그 반도체 장치의 제조 방법
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features
US9466604B2 (en) * 2014-11-13 2016-10-11 Globalfoundries Inc. Metal segments as landing pads and local interconnects in an IC device
KR102318410B1 (ko) * 2015-04-01 2021-10-28 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9887210B2 (en) 2015-08-28 2018-02-06 Samsung Electronics Co., Ltd. Semiconductor device
US10146900B2 (en) * 2015-09-17 2018-12-04 Qualcomm Incorporated Hybrid diffusion standard library cells, and related systems and methods
US9553088B1 (en) * 2015-09-24 2017-01-24 International Business Machines Corporation Forming semiconductor device with close ground rules
US9633999B1 (en) 2015-11-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for semiconductor mid-end-of-line (MEOL) process
US10541243B2 (en) 2015-11-19 2020-01-21 Samsung Electronics Co., Ltd. Semiconductor device including a gate electrode and a conductive structure
US9589847B1 (en) * 2016-02-18 2017-03-07 International Business Machines Corporation Metal layer tip to tip short
US10056265B2 (en) * 2016-03-18 2018-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Directed self-assembly process with size-restricted guiding patterns
KR20170109874A (ko) * 2016-03-22 2017-10-10 삼성전자주식회사 반도체 장치 및 그의 제조 방법
US10236302B2 (en) * 2016-06-22 2019-03-19 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count
EP3480211A4 (en) 2016-07-01 2019-12-25 Daiichi Sankyo Company, Limited HANP FC CONTAINING MOLECULAR CONJUGATE
KR20180069465A (ko) 2016-12-15 2018-06-25 삼성전자주식회사 수직형 트랜지스터를 구비하는 집적 회로 및 이를 포함하는 반도체 장치
US10347546B2 (en) * 2016-12-23 2019-07-09 Globalfoundries Inc. Integrated circuit structure including power rail and tapping wire with method of forming same
US11347925B2 (en) 2017-05-01 2022-05-31 Advanced Micro Devices, Inc. Power grid architecture and optimization with EUV lithography
US11211330B2 (en) * 2017-05-01 2021-12-28 Advanced Micro Devices, Inc. Standard cell layout architectures and drawing styles for 5nm and beyond
US10747931B2 (en) * 2017-07-28 2020-08-18 Advanced Micro Devices, Inc. Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic
US10692808B2 (en) 2017-09-18 2020-06-23 Qualcomm Incorporated High performance cell design in a technology with high density metal routing
US11018157B2 (en) 2017-09-28 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Local interconnect structure
DE102018102685A1 (de) 2017-11-30 2019-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Kontaktbildungsverfahren und zugehörige Struktur
KR102446164B1 (ko) 2017-12-26 2022-09-22 삼성전자주식회사 부하 스탠다드 셀을 포함하는 집적 회로 및 그 설계 방법
US10534888B2 (en) * 2018-01-03 2020-01-14 International Business Machines Corporation Hybrid back end of line metallization to balance performance and reliability
US10748889B2 (en) 2018-06-15 2020-08-18 Samsung Electronics Co., Ltd. Power grid and standard cell co-design structure and methods thereof
US10957601B2 (en) * 2018-10-11 2021-03-23 International Business Machines Corporation Self-aligned fin recesses in nanosheet field effect transistors
AU2019379418A1 (en) 2018-11-14 2021-06-03 Daiichi Sankyo Company, Limited Anti-CDH6 antibody-pyrrolobenzodiazepine derivative conjugate
JPWO2020196474A1 (zh) 2019-03-25 2020-10-01
JPWO2020196712A1 (zh) 2019-03-27 2020-10-01
US11126775B2 (en) * 2019-04-12 2021-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. IC layout, method, device, and system
US11488947B2 (en) * 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
US10796061B1 (en) 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11257827B2 (en) * 2019-12-30 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Layout structure including anti-fuse cell

Family Cites Families (733)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3521242A (en) 1967-05-02 1970-07-21 Rca Corp Complementary transistor write and ndro for memory cell
US4069493A (en) 1970-10-02 1978-01-17 Thomson-Csf Novel integrated circuit and method of manufacturing same
US4197555A (en) 1975-12-29 1980-04-08 Fujitsu Limited Semiconductor device
JPS5746536A (en) 1980-09-04 1982-03-17 Matsushita Electric Ind Co Ltd Gate circuit
US4424460A (en) 1981-07-14 1984-01-03 Rockwell International Corporation Apparatus and method for providing a logical exclusive OR/exclusive NOR function
JPS5943824B2 (ja) 1982-03-03 1984-10-24 三菱電機株式会社 半導体集積回路装置
JPS58182242A (ja) 1982-04-19 1983-10-25 Nec Corp 半導体集積回路装置
JPS58182242U (ja) 1982-05-28 1983-12-05 パイオニア株式会社 スライドロツク付プツシユボタン
JPS58215827A (ja) 1982-06-09 1983-12-15 Toshiba Corp 論理回路
JPS5943548A (ja) 1982-09-06 1984-03-10 Hitachi Ltd 半導体集積回路装置
US4613940A (en) 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
JPS6035532A (ja) 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
US4575648A (en) 1983-12-23 1986-03-11 At&T Bell Laboratories Complementary field effect transistor EXCLUSIVE OR logic gates
US5121186A (en) * 1984-06-15 1992-06-09 Hewlett-Packard Company Integrated circuit device having improved junction connections
KR940002772B1 (ko) 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치 및 그 제조방법
US5545904A (en) 1986-01-17 1996-08-13 Quick Technologies Ltd. Personalizable gate array devices
JPH0695570B2 (ja) 1985-02-07 1994-11-24 三菱電機株式会社 半導体集積回路装置
JPS61202451A (ja) 1985-03-05 1986-09-08 Nec Corp 半導体集積回路の配線構体
US4804636A (en) * 1985-05-01 1989-02-14 Texas Instruments Incorporated Process for making integrated circuits having titanium nitride triple interconnect
US4975756A (en) 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
US4657628A (en) 1985-05-01 1987-04-14 Texas Instruments Incorporated Process for patterning local interconnects
JPH0216605Y2 (zh) 1985-05-02 1990-05-08
US4602270A (en) 1985-05-17 1986-07-22 United Technologies Corporation Gate array with reduced isolation
JPS6247148A (ja) 1985-08-27 1987-02-28 Toshiba Corp 半導体集積回路装置
JPS62169472A (ja) 1986-01-22 1987-07-25 Hitachi Ltd 半導体集積回路装置
US5097422A (en) 1986-10-10 1992-03-17 Cascade Design Automation Corporation Method and apparatus for designing integrated circuits
US4745084A (en) 1986-11-12 1988-05-17 Vlsi Technology, Inc. Method of making a customized semiconductor integrated device
US4884115A (en) 1987-02-27 1989-11-28 Siemens Aktiengesellschaft Basic cell for a gate array arrangement in CMOS Technology
US4801986A (en) 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
JP2742052B2 (ja) 1987-06-12 1998-04-22 日本電信電話株式会社 相補型ｍｉｓマスタスライス論理集積回路
JPH067345B2 (ja) 1987-06-24 1994-01-26 株式会社 エイ・ティ・ア−ル自動翻訳電話研究所 ベクトル量子化を用いた音声認識方式
US5119313A (en) 1987-08-04 1992-06-02 Texas Instruments Incorporated Comprehensive logic circuit layout system
KR100212098B1 (ko) 1987-09-19 1999-08-02 가나이 쓰도무 반도체 집적회로 장치 및 그 제조 방법과 반도체 집적 회로 장치의 배선기판 및 그 제조 방법
US5068603A (en) 1987-10-07 1991-11-26 Xilinx, Inc. Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays
US4812688A (en) 1987-12-30 1989-03-14 International Business Machines Corporation Transistor delay circuits
JPH01284115A (ja) 1988-05-11 1989-11-15 Sharp Corp 論理回路
US5268319A (en) 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
US4928160A (en) 1989-01-17 1990-05-22 Ncr Corporation Gate isolated base cell structure with off-grid gate polysilicon pattern
JPH02198154A (ja) 1989-01-27 1990-08-06 Hitachi Ltd 配線の形成方法及びこれを利用した半導体装置
US5224057A (en) 1989-02-28 1993-06-29 Kabushiki Kaisha Toshiba Arrangement method for logic cells in semiconductor IC device
US5351197A (en) 1989-04-13 1994-09-27 Cascade Design Automation Corporation Method and apparatus for designing the layout of a subcircuit in an integrated circuit
JPH03165061A (ja) 1989-11-22 1991-07-17 Hitachi Ltd 半導体集積回路装置
US5298774A (en) 1990-01-11 1994-03-29 Mitsubishi Denki Kabushiki Kaisha Gate array system semiconductor integrated circuit device
US5483104A (en) 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
KR100199258B1 (ko) 1990-02-09 1999-06-15 가나이 쓰도무 반도체집적회로장치
US6100025A (en) 1990-04-20 2000-08-08 Cold Spring Harbor Laboratory Cloning by complementation and related processes
US5977305A (en) 1990-04-20 1999-11-02 Cold Spring Harbor Laboratories Cloning by complementation and related processes
US5047979A (en) 1990-06-15 1991-09-10 Integrated Device Technology, Inc. High density SRAM circuit with ratio independent memory cells
US5208765A (en) 1990-07-20 1993-05-04 Advanced Micro Devices, Inc. Computer-based method and system for product development
US5057895A (en) 1990-08-06 1991-10-15 Harris Corporation Trench conductor and crossunder architecture
US5079614A (en) 1990-09-26 1992-01-07 S-Mos Systems, Inc. Gate array architecture with basic cell interleaved gate electrodes
JP3017789B2 (ja) 1990-10-18 2000-03-13 三菱電機株式会社 半導体集積回路装置のレイアウト設計方法
JP2851447B2 (ja) 1991-03-08 1999-01-27 三菱電機株式会社 形状シミュレーション方法
US5183769A (en) * 1991-05-06 1993-02-02 Motorola, Inc. Vertical current flow semiconductor device utilizing wafer bonding
JPH05152937A (ja) 1991-11-26 1993-06-18 Hitachi Ltd 論理ゲート回路
JP3129336B2 (ja) 1991-12-09 2001-01-29 沖電気工業株式会社 半導体記憶装置
US7071060B1 (en) 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US5242770A (en) 1992-01-16 1993-09-07 Microunity Systems Engineering, Inc. Mask for photolithography
JP2760195B2 (ja) 1992-01-20 1998-05-28 日本電気株式会社 論理回路
US5526307A (en) 1992-01-22 1996-06-11 Macronix International Co., Ltd. Flash EPROM integrated circuit architecture
JPH05218362A (ja) 1992-02-04 1993-08-27 Sharp Corp ゲートアレイのベーシックセル
JP3248749B2 (ja) * 1992-03-19 2002-01-21 ジヤトコ・トランステクノロジー株式会社 クラッチピストンのスプリングリテーナ
IT1257184B (it) 1992-12-22 1996-01-10 Applied Research Systems Preparato ad attivita' antinfiammatoria, anticoagulante e antitumorale
US5367187A (en) 1992-12-22 1994-11-22 Quality Semiconductor, Inc. Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions
US5420447A (en) 1993-01-29 1995-05-30 Sgs-Thomson Microelectronics, Inc. Double buffer base gate array cell
US5359226A (en) 1993-02-02 1994-10-25 Paradigm Technology, Inc. Static memory with self aligned contacts and split word lines
US5497334A (en) 1993-02-19 1996-03-05 International Business Machines Corporation Application generator for use in verifying a hierarchical circuit design
US5410107A (en) 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
US5723908A (en) 1993-03-11 1998-03-03 Kabushiki Kaisha Toshiba Multilayer wiring structure
US5536955A (en) 1993-03-29 1996-07-16 Toppan Electronics (Usa) Inc. Electronic devices for use in generating integrated circuit structures and method therefor
US5338963A (en) 1993-04-05 1994-08-16 International Business Machines Corporation Soft error immune CMOS static RAM cell
US5691218A (en) 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5396128A (en) 1993-09-13 1995-03-07 Motorola, Inc. Output circuit for interfacing integrated circuits having different power supply potentials
JP3285438B2 (ja) 1993-10-29 2002-05-27 三菱電機株式会社 半導体記憶装置
JP3144967B2 (ja) 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
JP2746087B2 (ja) 1993-12-01 1998-04-28 日本電気株式会社 半導体集積回路
US5625568A (en) 1993-12-22 1997-04-29 Vlsi Technology, Inc. Method and apparatus for compacting integrated circuits with standard cell architectures
JP2684980B2 (ja) 1993-12-24 1997-12-03 日本電気株式会社 半導体記憶装置及びその製造方法
US6675361B1 (en) 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
US5756385A (en) 1994-03-30 1998-05-26 Sandisk Corporation Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
US5378649A (en) 1994-04-08 1995-01-03 United Microelectronics Corporation Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas
US5636002A (en) 1994-04-29 1997-06-03 Lucent Technologies Inc. Auxiliary mask features for enhancing the resolution of photolithography
JP3463180B2 (ja) 1994-05-02 2003-11-05 Ｎｅｃトーキン株式会社 磁性ガーネット酸化物粉末の製造方法及び磁性ガーネット酸化物膜の製造方法
US5591995A (en) 1994-05-10 1997-01-07 Texas Instruments, Incorporated Base cell for BiCMOS and CMOS gate arrays
TW297158B (zh) 1994-05-27 1997-02-01 Hitachi Ltd
JP3202490B2 (ja) 1994-07-22 2001-08-27 株式会社東芝 集積回路のレイアウト方法及び集積回路のレイアウト装置
JP3469362B2 (ja) 1994-08-31 2003-11-25 株式会社東芝 半導体記憶装置
US5528177A (en) 1994-09-16 1996-06-18 Research Foundation Of State University Of New York Complementary field-effect transistor logic circuits for wave pipelining
US5497337A (en) 1994-10-21 1996-03-05 International Business Machines Corporation Method for designing high-Q inductors in silicon technology without expensive metalization
US5852562A (en) 1994-12-13 1998-12-22 Matsushita Electric Industrial Co., Ltd. Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones
JPH08292938A (ja) 1995-02-24 1996-11-05 Fujitsu Ltd 有限要素メッシュ発生方法及び装置、並びに解析方法及び装置
JP2647045B2 (ja) 1995-02-28 1997-08-27 日本電気株式会社 半導体記憶装置及びその製造方法
US5682323A (en) 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
US5581098A (en) 1995-05-05 1996-12-03 Circuit Integration Technology, Inc. Circuit routing structure using fewer variable masks
JP3708168B2 (ja) 1995-06-13 2005-10-19 富士通株式会社 遅延装置
JP3535615B2 (ja) 1995-07-18 2004-06-07 株式会社ルネサステクノロジ 半導体集積回路装置
US5774367A (en) 1995-07-24 1998-06-30 Motorola, Inc. Method of selecting device threshold voltages for high speed and low power
US5764533A (en) 1995-08-01 1998-06-09 Sun Microsystems, Inc. Apparatus and methods for generating cell layouts
US5754826A (en) 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US5841663A (en) 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
JPH0993118A (ja) 1995-09-22 1997-04-04 Kawasaki Steel Corp パストランジスタ論理回路
US5789776A (en) 1995-09-22 1998-08-04 Nvx Corporation Single poly memory cell and array
JPH0997885A (ja) 1995-09-28 1997-04-08 Denso Corp ゲートアレイ
US5973369A (en) * 1997-03-11 1999-10-26 Nec Corporation SRAM having P-channel TFT as load element with less series-connected high resistance
US5723883A (en) 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US5640342A (en) 1995-11-20 1997-06-17 Micron Technology, Inc. Structure for cross coupled thin film transistors and static random access memory cell
JP3400215B2 (ja) 1995-11-21 2003-04-28 沖電気工業株式会社 半導体装置
JP3486725B2 (ja) 1995-11-28 2004-01-13 株式会社ルネサステクノロジ 可変論理集積回路
JP3934719B2 (ja) 1995-12-22 2007-06-20 株式会社東芝 光近接効果補正方法
US6043562A (en) 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
KR100229577B1 (ko) 1996-01-31 1999-11-15 포만 제프리 엘 게이트 어레이 셀 및 이것을 포함한 집적 회로 칩
US5798298A (en) 1996-02-09 1998-08-25 United Microelectronics Corporation Method of automatically generating dummy metals for multilevel interconnection
US5705301A (en) 1996-02-27 1998-01-06 Lsi Logic Corporation Performing optical proximity correction with the aid of design rule checkers
US6269472B1 (en) 1996-02-27 2001-07-31 Lsi Logic Corporation Optical proximity correction method and apparatus
US5698873A (en) 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
JPH09282349A (ja) 1996-04-17 1997-10-31 Shinko Electric Ind Co Ltd データ変換処理装置
JPH09289251A (ja) 1996-04-23 1997-11-04 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造およびその検証方法
JP2914292B2 (ja) 1996-04-25 1999-06-28 日本電気株式会社 半導体装置
US5740068A (en) 1996-05-30 1998-04-14 International Business Machines Corporation Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction
JP2809200B2 (ja) 1996-06-03 1998-10-08 日本電気株式会社 半導体装置の製造方法
US5935763A (en) 1996-06-11 1999-08-10 International Business Machines Corporation Self-aligned pattern over a reflective layer
US6026223A (en) 1996-06-28 2000-02-15 Scepanovic; Ranko Advanced modular cell placement system with overlap remover with minimal noise
JP3311244B2 (ja) 1996-07-15 2002-08-05 株式会社東芝 基本セルライブラリ及びその形成方法
US5796128A (en) 1996-07-25 1998-08-18 Translogic Technology, Inc. Gate array with fully wired multiplexer circuits
JP2918101B2 (ja) 1996-07-25 1999-07-12 日本電気株式会社 半導体集積回路のレイアウト方法
US5920486A (en) 1996-08-16 1999-07-06 International Business Machines Corporation Parameterized cells for generating dense layouts of VLSI circuits
US5717635A (en) 1996-08-27 1998-02-10 International Business Machines Corporation High density EEPROM for solid state file
JP3152635B2 (ja) 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
US5858580A (en) 1997-09-17 1999-01-12 Numerical Technologies, Inc. Phase shifting circuit manufacture method and apparatus
US5790417A (en) 1996-09-25 1998-08-04 Taiwan Semiconductor Manufacturing Company Ltd. Method of automatic dummy layout generation
US5923060A (en) 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells
US5684733A (en) 1996-09-30 1997-11-04 Holtek Microelectronics, Inc. Fixed resistance high density parallel ROM device
JP3529563B2 (ja) 1996-10-09 2004-05-24 株式会社東芝 半導体集積回路の再レイアウト方法及び半導体集積回路の再レイアウトプログラムを記録した媒体
US6209123B1 (en) 1996-11-01 2001-03-27 Motorola, Inc. Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
US5984510A (en) 1996-11-01 1999-11-16 Motorola Inc. Automatic synthesis of standard cell layouts
US6099584A (en) 1996-12-06 2000-08-08 Vsli Technology, Inc. System to fix post-layout timing and design rules violations
JP3523762B2 (ja) 1996-12-19 2004-04-26 株式会社東芝 半導体記憶装置
JP3352895B2 (ja) 1996-12-25 2002-12-03 株式会社東芝 半導体集積回路、半導体集積回路の設計方法および製造方法
JP3420694B2 (ja) 1996-12-27 2003-06-30 株式会社東芝 スタンダードセル方式の集積回路
JPH10189746A (ja) 1996-12-27 1998-07-21 Oki Electric Ind Co Ltd Ｌｓｉ論理回路の配線レイアウト方法
JP3180700B2 (ja) 1997-02-03 2001-06-25 日本電気株式会社 半導体集積回路装置
JP3036588B2 (ja) 1997-02-03 2000-04-24 日本電気株式会社 半導体記憶装置
JP3352349B2 (ja) 1997-02-24 2002-12-03 シャープ株式会社 双方向サイリスタ素子
US5900340A (en) 1997-03-03 1999-05-04 Motorola, Inc. One dimensional lithographic proximity correction using DRC shape functions
US5977574A (en) 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US5880991A (en) 1997-04-14 1999-03-09 International Business Machines Corporation Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure
US6393601B1 (en) 1997-04-14 2002-05-21 Matsushita Electric Industrial Co., Ltd. Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method
JP3178799B2 (ja) 1997-04-18 2001-06-25 シャープ株式会社 Ｍｏｓ論理回路及びこのｍｏｓ論理回路を備えた半導体装置
KR100227621B1 (ko) 1997-05-22 1999-11-01 김영환 반도체 소자의 트랜지스터 제조방법
US6005296A (en) 1997-05-30 1999-12-21 Stmicroelectronics, Inc. Layout for SRAM structure
US6445049B1 (en) 1997-06-30 2002-09-03 Artisan Components, Inc. Cell based array comprising logic, transfer and drive cells
US6282696B1 (en) 1997-08-15 2001-08-28 Lsi Logic Corporation Performing optical proximity correction with the aid of design rule checkers
US6470489B1 (en) 1997-09-17 2002-10-22 Numerical Technologies, Inc. Design rule checking system and method
US6370679B1 (en) 1997-09-17 2002-04-09 Numerical Technologies, Inc. Data hierarchy layout correction and verification method and apparatus
US6009251A (en) 1997-09-30 1999-12-28 Synopsys, Inc. Method and system for layout verification of an integrated circuit design with reusable subdesigns
US6114071A (en) 1997-11-24 2000-09-05 Asml Masktools Netherlands B.V. Method of fine feature edge tuning with optically-halftoned mask
JP3701781B2 (ja) 1997-11-28 2005-10-05 株式会社ルネサステクノロジ 論理回路とその作成方法
DE69727581D1 (de) 1997-11-28 2004-03-18 St Microelectronics Srl RAM-Speicherzelle mit niedriger Leistungsaufnahme
US6034433A (en) 1997-12-23 2000-03-07 Intel Corporation Interconnect structure for protecting a transistor gate from charge damage
JP3926011B2 (ja) 1997-12-24 2007-06-06 株式会社ルネサステクノロジ 半導体装置の設計方法
JP3777768B2 (ja) 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
KR100278273B1 (ko) 1997-12-30 2001-02-01 김영환 반도체장치의콘택홀형성방법
US6249902B1 (en) 1998-01-09 2001-06-19 Silicon Perspective Corporation Design hierarchy-based placement
US6571140B1 (en) 1998-01-15 2003-05-27 Eutech Cybernetics Pte Ltd. Service-oriented community agent
JPH11214662A (ja) 1998-01-29 1999-08-06 Mitsubishi Electric Corp 半導体装置
US6091845A (en) 1998-02-24 2000-07-18 Micron Technology, Inc. Inspection technique of photomask
US6230299B1 (en) 1998-03-31 2001-05-08 Mentor Graphics Corporation Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design
US6378110B1 (en) 1998-03-31 2002-04-23 Synopsys, Inc. Layer-based rule checking for an integrated circuit layout
JPH11297856A (ja) 1998-04-16 1999-10-29 Mitsubishi Electric Corp スタティック半導体記憶装置
TWI240372B (en) * 1998-04-17 2005-09-21 Taiwan Semiconductor Mfg Fabrication method for self-aligned passivation of damascene interconnect structure
US5915199A (en) 1998-06-04 1999-06-22 Sharp Microelectronics Technology, Inc. Method for manufacturing a CMOS self-aligned strapped interconnection
US6262487B1 (en) 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6063132A (en) 1998-06-26 2000-05-16 International Business Machines Corporation Method for verifying design rule checking software
US6480989B2 (en) 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6714903B1 (en) 1998-07-10 2004-03-30 Lsi Logic Corporation Placement and routing of circuits using a combined processing/buffer cell
US6240542B1 (en) 1998-07-14 2001-05-29 Lsi Logic Corporation Poly routing for chip interconnects with minimal impact on chip performance
US6182272B1 (en) 1998-07-16 2001-01-30 Lsi Logic Corporation Metal layer assignment
JP3562975B2 (ja) 1998-09-29 2004-09-08 株式会社東芝 集積回路設計方法及び集積回路設計装置
US20020008257A1 (en) 1998-09-30 2002-01-24 John P. Barnak Mosfet gate electrodes having performance tuned work functions and methods of making same
JP2000114262A (ja) 1998-10-05 2000-04-21 Toshiba Corp 半導体装置及びその製造方法
JP3852729B2 (ja) 1998-10-27 2006-12-06 富士通株式会社 半導体記憶装置
US6174742B1 (en) 1998-10-30 2001-01-16 Lsi Logic Corporation Off-grid metal layer utilization
US6275973B1 (en) 1998-10-30 2001-08-14 Lsi Logic Corporation Integrated circuit design with delayed cell selection
US6166415A (en) 1998-11-02 2000-12-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with improved noise resistivity
US6430805B1 (en) * 1998-11-06 2002-08-13 Raytheon Company Method of fabricating a true-time-delay continuous transverse stub array antenna
JP3680594B2 (ja) 1998-11-10 2005-08-10 株式会社日立製作所 半導体集積回路
TW476069B (en) 1998-11-20 2002-02-11 Via Tech Inc Placement and routing for array device
AU1913500A (en) 1998-11-25 2000-06-13 Nanopower, Inc. Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits
JP4437565B2 (ja) 1998-11-26 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置、半導体集積回路装置の設計方法、及び、記録媒体
US6477695B1 (en) 1998-12-09 2002-11-05 Artisan Components, Inc. Methods for designing standard cell transistor structures
US6588005B1 (en) 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
KR100291384B1 (ko) 1998-12-31 2001-07-12 윤종용 반도체장치의레이아웃방법
TW444335B (en) * 1999-02-05 2001-07-01 Vanguard Int Semiconduct Corp Process for forming self-aligned multi-level interconnect structure
US6159839A (en) 1999-02-11 2000-12-12 Vanguard International Semiconductor Corporation Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections
US6691297B1 (en) 1999-03-04 2004-02-10 Matsushita Electric Industrial Co., Ltd. Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI
US6480032B1 (en) 1999-03-04 2002-11-12 Intel Corporation Gate array architecture
US6974978B1 (en) 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
US6331733B1 (en) 1999-08-10 2001-12-18 Easic Corporation Semiconductor device
US6194912B1 (en) 1999-03-11 2001-02-27 Easic Corporation Integrated circuit device
US6044007A (en) 1999-03-24 2000-03-28 Advanced Micro Devices, Inc. Modification of mask layout data to improve writeability of OPC
JP3986036B2 (ja) 1999-04-16 2007-10-03 株式会社日立製作所 半導体集積回路装置
US6505328B1 (en) 1999-04-27 2003-01-07 Magma Design Automation, Inc. Method for storing multiple levels of design data in a common database
US6507941B1 (en) 1999-04-28 2003-01-14 Magma Design Automation, Inc. Subgrid detailed routing
JP4565700B2 (ja) 1999-05-12 2010-10-20 ルネサスエレクトロニクス株式会社 半導体装置
US6492066B1 (en) 1999-05-28 2002-12-10 Advanced Micro Devices, Inc. Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion
US6207479B1 (en) 1999-06-14 2001-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Place and route method for integrated circuit design
US6425112B1 (en) 1999-06-17 2002-07-23 International Business Machines Corporation Auto correction of error checked simulated printed images
US6381730B1 (en) 1999-07-09 2002-04-30 Sequence Design, Inc. Method and system for extraction of parasitic interconnect impedance including inductance
US6525350B1 (en) 1999-07-16 2003-02-25 Kawasaki Steel Corporation Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same
JP2001056463A (ja) 1999-08-20 2001-02-27 Casio Comput Co Ltd 液晶表示装置
JP2001068558A (ja) 1999-08-30 2001-03-16 Hitachi Ltd 半導体集積回路装置
US6436805B1 (en) * 1999-09-01 2002-08-20 Micron Technology, Inc. Local interconnect structures and methods for making the same
US6496965B1 (en) 1999-09-20 2002-12-17 Magma Design Automation, Inc. Automated design of parallel drive standard cells
TW423218B (en) 1999-10-06 2001-02-21 Ind Tech Res Inst Charge-redistribution low-swing differential logic circuit
US6194104B1 (en) 1999-10-12 2001-02-27 Taiwan Semiconductor Manufacturing Company Optical proximity correction (OPC) method for improving lithography process window
US6737347B1 (en) 1999-10-20 2004-05-18 Texas Instruments Incorporated Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
US6426269B1 (en) 1999-10-21 2002-07-30 International Business Machines Corporation Dummy feature reduction using optical proximity effect correction
US6255845B1 (en) 1999-11-16 2001-07-03 Advanced Micro Devices, Inc. Efficient use of spare gates for post-silicon debug and enhancements
EP1234336A1 (en) 1999-11-17 2002-08-28 Aeroflex UTMC Microelectronic Systems Inc. Radiation resistant integrated circuit design
JP2001144603A (ja) 1999-11-18 2001-05-25 Oki Micro Design Co Ltd レベルシフタ回路およびそれを含むデータ出力回路
AU1770301A (en) 1999-11-18 2001-05-30 Pdf Solutions, Inc. System and method for product yield prediction using device and process neighborhood characterization vehicle
JP2001168707A (ja) 1999-12-03 2001-06-22 Sony Corp 論理回路およびそれを用いた全加算器
US6421820B1 (en) 1999-12-13 2002-07-16 Infineon Technologies Ag Semiconductor device fabrication using a photomask with assist features
US6303252B1 (en) 1999-12-27 2001-10-16 United Microelectronics Corp. Reticle having assist feature between semi-dense lines
TW436992B (en) * 1999-12-30 2001-05-28 Taiwan Semiconductor Mfg Manufacturing method of self-aligned source connection lines used in memory array
US6295224B1 (en) 1999-12-30 2001-09-25 Stmicroelectronics, Inc. Circuit and method of fabricating a memory cell for a static random access memory
KR100346832B1 (ko) 2000-01-12 2002-08-03 삼성전자 주식회사 스태틱 랜덤 억세스 메모리 소자 및 그 제조 방법
US6737199B1 (en) 2000-01-31 2004-05-18 Taiwan Semiconductor Manufacturing Company Using new pattern fracturing rules for optical proximity correction mask-making to improve critical dimension uniformity
US6408427B1 (en) 2000-02-22 2002-06-18 The Regents Of The University Of California Wire width planning and performance optimization for VLSI interconnects
US6331790B1 (en) 2000-03-10 2001-12-18 Easic Corporation Customizable and programmable cell array
US6756811B2 (en) 2000-03-10 2004-06-29 Easic Corporation Customizable and programmable cell array
US6399972B1 (en) 2000-03-13 2002-06-04 Oki Electric Industry Co., Ltd. Cell based integrated circuit and unit cell architecture therefor
US6536028B1 (en) 2000-03-14 2003-03-18 Ammocore Technologies, Inc. Standard block architecture for integrated circuit design
JP2001272228A (ja) 2000-03-24 2001-10-05 Railway Technical Res Inst 相対変位量計測システム及び相対変位量計測方法
US6356112B1 (en) 2000-03-28 2002-03-12 Translogic Technology, Inc. Exclusive or/nor circuit
US6553544B2 (en) 2000-04-04 2003-04-22 Matsushita Electric Industrial Co., Ltd. Method for design of partial circuit
US6416907B1 (en) 2000-04-27 2002-07-09 Micron Technology, Inc. Method for designing photolithographic reticle layout, reticle, and photolithographic process
JP2001306641A (ja) 2000-04-27 2001-11-02 Victor Co Of Japan Ltd 半導体集積回路の自動配置配線方法
US6583041B1 (en) 2000-05-01 2003-06-24 Advanced Micro Devices, Inc. Microdevice fabrication method using regular arrays of lines and spaces
TW512424B (en) 2000-05-01 2002-12-01 Asml Masktools Bv Hybrid phase-shift mask
JP4885365B2 (ja) 2000-05-16 2012-02-29 ルネサスエレクトロニクス株式会社 半導体装置
US6509952B1 (en) 2000-05-23 2003-01-21 Silicon Valley Group, Inc. Method and system for selective linewidth optimization during a lithographic process
US6610607B1 (en) 2000-05-25 2003-08-26 International Business Machines Corporation Method to define and tailor process limited lithographic features using a modified hard mask process
US6445065B1 (en) 2000-06-06 2002-09-03 In-Chip Systems, Inc. Routing driven, metal programmable integrated circuit architecture with multiple types of core cells
US6617621B1 (en) 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
US6425113B1 (en) 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US6889370B1 (en) 2000-06-20 2005-05-03 Unisys Corporation Method and apparatus for selecting and aligning cells using a placement tool
JP2002026296A (ja) 2000-06-22 2002-01-25 Internatl Business Mach Corp <Ibm> 半導体集積回路装置
JP2002009160A (ja) 2000-06-26 2002-01-11 Nec Microsystems Ltd 半導体集積回路の自動レイアウト方法、この方法で製造した半導体集積回路及びこの方法を記録した記録媒体
US7225423B2 (en) 2000-06-30 2007-05-29 Zenasis Technologies, Inc. Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
US6978436B2 (en) 2000-07-05 2005-12-20 Synopsys, Inc. Design data format and hierarchy management for phase processing
US6787271B2 (en) 2000-07-05 2004-09-07 Numerical Technologies, Inc. Design and layout of phase shifting photolithographic masks
US7028285B2 (en) 2000-07-05 2006-04-11 Synopsys, Inc. Standard cell design incorporating phase information
US6733929B2 (en) 2000-07-05 2004-05-11 Numerical Technologies, Inc. Phase shift masking for complex patterns with proximity adjustments
US6516459B1 (en) 2000-07-10 2003-02-04 Mentor Graphics Corporation Integrated circuit design correction using fragment correspondence
JP4794030B2 (ja) 2000-07-10 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置
US6632741B1 (en) 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US6574786B1 (en) 2000-07-21 2003-06-03 Aeroflex UTMC Microelectronics Systems, Inc. Gate array cell generator using cadence relative object design
US20050136340A1 (en) 2000-07-21 2005-06-23 Asml Netherlands B.V. Lithographic apparatus and methods, patterning structure and method for making a patterning structure, device manufacturing method, and device manufactured thereby
US6523162B1 (en) 2000-08-02 2003-02-18 Numerical Technologies, Inc. General purpose shape-based layout processing scheme for IC layout modifications
DE10040458B4 (de) * 2000-08-18 2015-08-27 Infineon Technologies Ag Vertikaler Feldeffekt-Transistor und Verfahren zu dessen Herstellung
JP4357101B2 (ja) 2000-08-23 2009-11-04 株式会社ルネサステクノロジ 半導体記憶装置
JP4764987B2 (ja) 2000-09-05 2011-09-07 富士電機株式会社 超接合半導体素子
WO2002025373A2 (en) 2000-09-13 2002-03-28 Massachusetts Institute Of Technology Method of design and fabrication of integrated circuits using regular arrays and gratings
US6800883B2 (en) 2000-09-21 2004-10-05 Matsushita Electric Industrial Co., Ltd. CMOS basic cell and method for fabricating semiconductor integrated circuit using the same
US6453457B1 (en) 2000-09-29 2002-09-17 Numerical Technologies, Inc. Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout
US6557162B1 (en) 2000-09-29 2003-04-29 Numerical Technologies, Inc. Method for high yield reticle formation
US6625801B1 (en) 2000-09-29 2003-09-23 Numerical Technologies, Inc. Dissection of printed edges from a fabrication layout for correcting proximity effects
US6794677B2 (en) 2000-10-02 2004-09-21 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method for fabricating the same
US6555450B2 (en) 2000-10-04 2003-04-29 Samsung Electronics Co., Ltd. Contact forming method for semiconductor device
US6566720B2 (en) 2000-10-05 2003-05-20 United Memories, Inc. Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits
US6978437B1 (en) 2000-10-10 2005-12-20 Toppan Photomasks, Inc. Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same
KR20020034313A (ko) 2000-10-31 2002-05-09 박종섭 에스램셀의 제조 방법
US6498088B1 (en) * 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same
US6703170B1 (en) 2000-12-13 2004-03-09 Dupont Photomasks, Inc. Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process
JP2002184870A (ja) 2000-12-18 2002-06-28 Mitsubishi Electric Corp スタティック型半導体記憶装置
KR100355036B1 (ko) 2000-12-22 2002-10-05 삼성전자 주식회사 크로스 커플드 트랜지스터 쌍의 레이아웃 방법
US6992394B2 (en) 2000-12-28 2006-01-31 Infineon Technologies Ag Multi-level conductive lines with reduced pitch
US6553559B2 (en) 2001-01-05 2003-04-22 International Business Machines Corporation Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions
US6578190B2 (en) 2001-01-11 2003-06-10 International Business Machines Corporation Process window based optical proximity correction of lithographic images
JP2002289703A (ja) 2001-01-22 2002-10-04 Nec Corp 半導体記憶装置およびその製造方法
JP2002252161A (ja) 2001-02-23 2002-09-06 Hitachi Ltd 半導体製造システム
US6792591B2 (en) 2001-02-28 2004-09-14 Asml Masktools B.V. Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs
JP4928675B2 (ja) 2001-03-01 2012-05-09 エルピーダメモリ株式会社 半導体装置
JP4736206B2 (ja) 2001-03-05 2011-07-27 大日本印刷株式会社 フォトマスクパタン欠陥検査方法および微細図形パタンの検出方法
TW571571B (en) 2001-03-14 2004-01-11 Asml Masktools Bv An optical proximity correction method utilizing ruled ladder bars as sub-resolution assist features
US6514849B1 (en) 2001-04-02 2003-02-04 Advanced Micro Devices, Inc. Method of forming smaller contact size using a spacer hard mask
US6732334B2 (en) 2001-04-02 2004-05-04 Matsushita Electric Industrial Co., Ltd. Analog MOS semiconductor device, manufacturing method therefor, manufacturing program therefor, and program device therefor
US6534805B1 (en) 2001-04-09 2003-03-18 Cypress Semiconductor Corp. SRAM cell design
US6574779B2 (en) 2001-04-12 2003-06-03 International Business Machines Corporation Hierarchical layout method for integrated circuits
US6505327B2 (en) 2001-04-13 2003-01-07 Numerical Technologies, Inc. Generating an instance-based representation of a design hierarchy
US6524870B2 (en) 2001-04-24 2003-02-25 Pell, Iii Edwin A. Method and apparatus for improving resolution of objects in a semiconductor wafer
JP4187947B2 (ja) 2001-04-26 2008-11-26 株式会社東芝 パターン補正方法、パターン補正装置、およびパターン補正プログラムを記録した記録媒体
US6936908B2 (en) 2001-05-03 2005-08-30 Ixys Corporation Forward and reverse blocking devices
US6553562B2 (en) 2001-05-04 2003-04-22 Asml Masktools B.V. Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques
US6590289B2 (en) 2001-05-17 2003-07-08 Lsi Logic Corporation Hexadecagonal routing
US6523156B2 (en) 2001-06-08 2003-02-18 Library Technologies, Inc. Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries
US6759282B2 (en) 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
JP2002368135A (ja) 2001-06-12 2002-12-20 Hitachi Ltd 半導体記憶装置
JP4746770B2 (ja) 2001-06-19 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置
US6609235B2 (en) 2001-06-22 2003-08-19 Bae Systems Information And Electronic Systems Integration, Inc. Method for providing a fill pattern for an integrated circuit design
US7079989B2 (en) 2001-06-29 2006-07-18 Shmuel Wimer Arrangements for automatic re-legging of transistors
US6835591B2 (en) 2001-07-25 2004-12-28 Nantero, Inc. Methods of nanotube films and articles
DE10137830A1 (de) 2001-08-02 2003-02-27 Infineon Technologies Ag Verfahren zum Herstellen einer selbstjustierten Struktur auf einem Halbleiter-Wafer
DE10143723B4 (de) 2001-08-31 2006-09-28 Infineon Technologies Ag Verfahren zur Optimierung eines Layouts für eine Maske zur Verwendung bei der Halbleiterherstellung
US6684382B2 (en) 2001-08-31 2004-01-27 Numerical Technologies, Inc. Microloading effect correction
US6633182B2 (en) 2001-09-05 2003-10-14 Carnegie Mellon University Programmable gate array based on configurable metal interconnect vias
JP4786836B2 (ja) 2001-09-07 2011-10-05 富士通セミコンダクター株式会社 配線接続部設計方法及び半導体装置
JP2003092250A (ja) 2001-09-18 2003-03-28 Hitachi Ltd 半導体装置及びその製造方法
JP3989213B2 (ja) 2001-09-25 2007-10-10 シャープ株式会社 パストランジスタ論理回路
JP3637299B2 (ja) 2001-10-05 2005-04-13 松下電器産業株式会社 半導体記憶装置
JP3706364B2 (ja) 2001-10-09 2005-10-12 アスムル マスクツールズ ビー．ブイ． ２次元フィーチャ・モデルの較正および最適化方法
JP2003124339A (ja) 2001-10-11 2003-04-25 Toshiba Corp 半導体装置およびその製造方法
JP3526450B2 (ja) 2001-10-29 2004-05-17 株式会社東芝 半導体集積回路およびスタンダードセル配置設計方法
JP2003142584A (ja) 2001-11-05 2003-05-16 Matsushita Electric Ind Co Ltd 半導体集積回路装置の設計方法
US6833593B2 (en) 2001-11-09 2004-12-21 Thin Film Electronics Asa Electrode means, a method for its manufacture, an apparatus comprising the electrode means as well as use of the latter
US6673638B1 (en) 2001-11-14 2004-01-06 Kla-Tencor Corporation Method and apparatus for the production of process sensitive lithographic features
JP2003218238A (ja) 2001-11-14 2003-07-31 Mitsubishi Electric Corp 半導体記憶装置
JP3789351B2 (ja) 2001-11-30 2006-06-21 株式会社日立製作所 反射型液晶表示装置及びその製造方法
JP2003168640A (ja) 2001-12-03 2003-06-13 Hitachi Ltd 半導体装置の製造方法
JP2003188361A (ja) 2001-12-20 2003-07-04 Mitsubishi Electric Corp ゲートアレイ構造の半導体集積回路
JP3828419B2 (ja) * 2001-12-25 2006-10-04 株式会社東芝 半導体装置及びその製造方法
US6787469B2 (en) 2001-12-28 2004-09-07 Texas Instruments Incorporated Double pattern and etch of poly with hard mask
US7159197B2 (en) 2001-12-31 2007-01-02 Synopsys, Inc. Shape-based geometry engine to perform smoothing and other layout beautification operations
US6817000B2 (en) 2002-01-02 2004-11-09 International Business Machines Corporation Delay correlation analysis and representation for vital complaint VHDL models
US7085701B2 (en) 2002-01-02 2006-08-01 International Business Machines Corporation Size reduction techniques for vital compliant VHDL simulation models
JP2003203993A (ja) 2002-01-10 2003-07-18 Mitsubishi Electric Corp 半導体記憶装置及びその製造方法
US6749972B2 (en) 2002-01-15 2004-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Optical proximity correction common process window maximization over varying feature pitch
US6721926B2 (en) 2002-01-25 2004-04-13 Intel Corporation Method and apparatus for improving digital circuit design
US6662350B2 (en) 2002-01-28 2003-12-09 International Business Machines Corporation FinFET layout generation
US6820248B1 (en) 2002-02-14 2004-11-16 Xilinx, Inc. Method and apparatus for routing interconnects to devices with dissimilar pitches
US6904582B1 (en) 2002-02-28 2005-06-07 Dupont Photomasks, Inc. Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same
JP2003264231A (ja) 2002-03-11 2003-09-19 Mitsubishi Electric Corp レイアウト設計方法および半導体装置
TWI252516B (en) 2002-03-12 2006-04-01 Toshiba Corp Determination method of process parameter and method for determining at least one of process parameter and design rule
US7386433B2 (en) 2002-03-15 2008-06-10 Synopsys, Inc. Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout
US6732338B2 (en) 2002-03-20 2004-05-04 International Business Machines Corporation Method for comprehensively verifying design rule checking runsets
US6765245B2 (en) 2002-03-25 2004-07-20 Bae Systems Information And Electronic Systems Integration Inc. Gate array core cell for VLSI ASIC devices
US6754121B2 (en) 2002-03-29 2004-06-22 Stmicroelectronics, Inc. Sense amplifying circuit and method
US6745372B2 (en) 2002-04-05 2004-06-01 Numerical Technologies, Inc. Method and apparatus for facilitating process-compliant layout optimization
US6789246B1 (en) 2002-04-07 2004-09-07 Barcelona Design, Inc. Method and apparatus for automatic layout of circuit structures
US7252909B2 (en) 2002-04-18 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce CD non-uniformity in IC manufacturing
TW543147B (en) * 2002-04-23 2003-07-21 Chartered Semiconductor Mfg Integrated circuit with self-aligned line and via and manufacturing method therefor
JP4190796B2 (ja) 2002-04-24 2008-12-03 Ｎｅｃエレクトロニクス株式会社 露光原版の作成方法
US6992925B2 (en) 2002-04-26 2006-01-31 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US6826738B2 (en) 2002-05-10 2004-11-30 Pdf Solutions, Inc. Optimization of die placement on wafers
US6794914B2 (en) 2002-05-24 2004-09-21 Qualcomm Incorporated Non-volatile multi-threshold CMOS latch with leakage control
JP2004013920A (ja) 2002-06-03 2004-01-15 Mitsubishi Electric Corp 半導体記憶装置
US6980211B2 (en) 2002-06-04 2005-12-27 Springsoft, Inc. Automatic schematic diagram generation using topology information
US7363099B2 (en) 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US7712056B2 (en) 2002-06-07 2010-05-04 Cadence Design Systems, Inc. Characterization and verification for integrated circuit designs
US20030229875A1 (en) 2002-06-07 2003-12-11 Smith Taber H. Use of models in integrated circuit fabrication
US7774726B2 (en) 2002-06-07 2010-08-10 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7152215B2 (en) 2002-06-07 2006-12-19 Praesagus, Inc. Dummy fill for integrated circuits
EP1532670A4 (en) 2002-06-07 2007-09-12 Praesagus Inc CHARACTERIZATION AND REDUCTION OF VARIATION FOR INTEGRATED CIRCUITS
US7124386B2 (en) 2002-06-07 2006-10-17 Praesagus, Inc. Dummy fill for integrated circuits
JP3879063B2 (ja) 2002-06-11 2007-02-07 富士通株式会社 半導体装置およびその製造方法
US6795953B2 (en) 2002-06-11 2004-09-21 Hpl Technologies, Inc. Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design
JP2004022070A (ja) 2002-06-17 2004-01-22 Renesas Technology Corp 半導体記憶装置
US7039882B2 (en) 2002-06-17 2006-05-02 Amar Pal Singh Rana Technology dependent transformations for Silicon-On-Insulator in digital design synthesis
JP4036688B2 (ja) 2002-06-18 2008-01-23 松下電器産業株式会社 自動配置配線用スタンダードセルライブラリ及び半導体集積装置
JP4462528B2 (ja) 2002-06-24 2010-05-12 株式会社日立製作所 半導体集積回路装置
EP1376676A3 (en) 2002-06-24 2008-08-20 Interuniversitair Microelektronica Centrum Vzw Multibit non-volatile memory device and method
US6687895B2 (en) 2002-07-03 2004-02-03 Numerical Technologies Inc. Method and apparatus for reducing optical proximity correction output file size
JP2004040042A (ja) * 2002-07-08 2004-02-05 Fujitsu Ltd 半導体記憶装置
US6998722B2 (en) 2002-07-08 2006-02-14 Viciciv Technology Semiconductor latches and SRAM devices
US20040009409A1 (en) 2002-07-11 2004-01-15 Jiunn-Ren Hwang Optical proximity correction method
US7063923B2 (en) 2002-07-11 2006-06-20 United Electronics Corp. Optical proximity correction method
JP2006502422A (ja) 2002-07-12 2006-01-19 ケイデンス デザイン システムズ インコーポレイテッド コンテクスト特定型のマスク検査のための方法及びシステム
JP4416384B2 (ja) 2002-07-19 2010-02-17 株式会社ルネサステクノロジ 半導体集積回路
KR100445638B1 (ko) 2002-07-26 2004-08-25 삼성전자주식회사 전기적으로 분리된 영역들을 연결하는 상호 연결 구조 및그 제조방법
US7739624B2 (en) 2002-07-29 2010-06-15 Synopsys, Inc. Methods and apparatuses to generate a shielding mesh for integrated circuit devices
US7171645B2 (en) 2002-08-06 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device
KR100493025B1 (ko) 2002-08-07 2005-06-07 삼성전자주식회사 반도체 메모리 장치의 제조 방법
US7143380B1 (en) 2002-08-08 2006-11-28 Xilinx, Inc. Method for application of network flow techniques under constraints
FR2843481B1 (fr) 2002-08-08 2005-09-16 Soisic Memoire sur substrat du type silicium sur isolant
US6789244B1 (en) 2002-08-08 2004-09-07 Xilinx, Inc. Placement of clock objects under constraints
US6785875B2 (en) 2002-08-15 2004-08-31 Fulcrum Microsystems, Inc. Methods and apparatus for facilitating physical synthesis of an integrated circuit design
US6854100B1 (en) 2002-08-27 2005-02-08 Taiwan Semiconductor Manufacturing Company Methodology to characterize metal sheet resistance of copper damascene process
JP3795846B2 (ja) * 2002-08-29 2006-07-12 富士通株式会社 半導体装置
US7345511B2 (en) 2002-08-29 2008-03-18 Technion Research & Development Foundation Ltd. Logic circuit and method of logic circuit design
US6734521B2 (en) 2002-08-30 2004-05-11 Texas Instruments Incorporated Integrated circuit cells
DE10241170A1 (de) 2002-09-05 2004-03-18 Infineon Technologies Ag Hochdichter NROM-FINFET
US20040049754A1 (en) 2002-09-06 2004-03-11 Sun Microsystems, Inc. Method and apparatus for filling and connecting filler material in a layout
TWI274969B (en) 2002-09-11 2007-03-01 Asml Masktools Bv Method and computer program product of generating masks and mask generated thereby, device manufacturing method and device manufactured thereby, and method of printing pattern
US6807663B2 (en) 2002-09-23 2004-10-19 Numerical Technologies, Inc. Accelerated layout processing using OPC pre-processing
US6928635B2 (en) 2002-09-25 2005-08-09 Numerical Technologies, Inc. Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits
US7327597B1 (en) 2002-10-02 2008-02-05 Cisco Technology, Inc. Static random access memory architecture
WO2004034463A1 (ja) 2002-10-10 2004-04-22 Fujitsu Limited レイアウト方法及び装置並びにそのプログラム及び記録媒体
US7214579B2 (en) 2002-10-24 2007-05-08 Nxp Bv. Self-aligned 2-bit “double poly CMP” flash memory cell
US6994939B1 (en) 2002-10-29 2006-02-07 Advanced Micro Devices, Inc. Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types
US7053424B2 (en) 2002-10-31 2006-05-30 Yamaha Corporation Semiconductor integrated circuit device and its manufacture using automatic layout
US7219326B2 (en) 2002-12-16 2007-05-15 Intrinsity, Inc. Physical realization of dynamic logic using parameterized tile partitioning
JP3848248B2 (ja) 2002-12-17 2006-11-22 株式会社東芝 Ｓｒａｍセルおよびそれを用いたメモリ集積回路
US6953956B2 (en) 2002-12-18 2005-10-11 Easic Corporation Semiconductor device having borderless logic array and flexible I/O
US7378710B2 (en) 2002-12-19 2008-05-27 International Business Machines Corporation FinFET SRAM cell using inverted FinFET thin film transistors
US7093228B2 (en) 2002-12-20 2006-08-15 Lsi Logic Corporation Method and system for classifying an integrated circuit for optical proximity correction
EP1434264A3 (en) 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique
JP4202120B2 (ja) 2002-12-27 2008-12-24 セイコーインスツル株式会社 集積回路の最適化設計装置
US6898770B2 (en) 2003-01-09 2005-05-24 Lsi Logic Corporation Split and merge design flow concept for fast turnaround time of circuit layout design
JP4136684B2 (ja) 2003-01-29 2008-08-20 Ｎｅｃエレクトロニクス株式会社 半導体装置及びそのダミーパターンの配置方法
US6996790B2 (en) 2003-01-30 2006-02-07 Synopsys, Inc. System and method for generating a two-dimensional yield map for a full layout
JP2004241529A (ja) 2003-02-05 2004-08-26 Matsushita Electric Ind Co Ltd 半導体回路装置及びその回路シミュレーション方法
US6884712B2 (en) 2003-02-07 2005-04-26 Chartered Semiconductor Manufacturing, Ltd. Method of manufacturing semiconductor local interconnect and contact
JP2004253730A (ja) * 2003-02-21 2004-09-09 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6777146B1 (en) 2003-02-21 2004-08-17 International Business Machines Corporation Method of optical proximity correction with sub-resolution assists
US7149999B2 (en) 2003-02-25 2006-12-12 The Regents Of The University Of California Method for correcting a mask design layout
JP4531340B2 (ja) 2003-02-27 2010-08-25 ルネサスエレクトロニクス株式会社 マルチプレクサセルのレイアウト構造
EP1597631B1 (en) 2003-02-27 2009-07-22 The University of Hong Kong Multiple exposure method for circuit performance improvement and maskset
JP4290457B2 (ja) 2003-03-31 2009-07-08 株式会社ルネサステクノロジ 半導体記憶装置
JP3920804B2 (ja) 2003-04-04 2007-05-30 松下電器産業株式会社 半導体記憶装置
US6931617B2 (en) 2003-04-21 2005-08-16 Synopsys, Inc. Mask cost driven logic optimization and synthesis
TW594991B (en) 2003-04-29 2004-06-21 Faraday Tech Corp Integrated circuit with one metal layer for programming functionality of a logic operation module
US7065731B2 (en) 2003-05-07 2006-06-20 Cadence Design Systems, Inc. Removal of acute angles in a design layout
TWI371674B (en) 2003-05-07 2012-09-01 Mosaid Technologies Inc Managing power on integrated circuits using power islands
US7093208B2 (en) 2003-05-12 2006-08-15 International Business Machines Corporation Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
JP2004342757A (ja) 2003-05-14 2004-12-02 Toshiba Corp 半導体集積回路及びその設計方法
US7063920B2 (en) 2003-05-16 2006-06-20 Asml Holding, N.V. Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems
JP4233381B2 (ja) 2003-05-21 2009-03-04 株式会社ルネサステクノロジ 半導体装置とその製造方法
US7062740B2 (en) 2003-05-22 2006-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for reducing design cycle time for designing input/output cells
US7770144B2 (en) 2003-05-28 2010-08-03 Eric Dellinger Modular array defined by standard cell logic
US7107551B1 (en) 2003-05-30 2006-09-12 Prolific, Inc. Optimization of circuit designs using a continuous spectrum of library cells
US7291878B2 (en) 2003-06-03 2007-11-06 Hitachi Global Storage Technologies Netherlands B.V. Ultra low-cost solid-state memory
US7183611B2 (en) 2003-06-03 2007-02-27 Micron Technology, Inc. SRAM constructions, and electronic systems comprising SRAM constructions
US7400627B2 (en) 2003-06-05 2008-07-15 Brooktree Broadband Holding, Inc. ATM header compression using hash tables
US6992916B2 (en) 2003-06-13 2006-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM cell design with high resistor CMOS gate structure for soft error rate improvement
JP4245418B2 (ja) 2003-06-25 2009-03-25 富士通マイクロエレクトロニクス株式会社 斜め方向配線を有する半導体集積回路装置及びそのレイアウト方法
US20050009312A1 (en) 2003-06-26 2005-01-13 International Business Machines Corporation Gate length proximity corrected device
US6900999B1 (en) 2003-06-30 2005-05-31 Integrated Device Technology, Inc. Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio
US6993741B2 (en) 2003-07-15 2006-01-31 International Business Machines Corporation Generating mask patterns for alternating phase-shift mask lithography
KR100577610B1 (ko) 2003-07-15 2006-05-10 삼성전자주식회사 반도체 장치, 반도체 장치의 제조 방법 및 에스램 장치,에스램 장치 제조 방법.
EP1519421A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum Vzw Multiple gate semiconductor device and method for forming same
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
EP1503411A1 (fr) 2003-07-30 2005-02-02 St Microelectronics S.A. Lignes conductrices enterrées dans des zones d'isolement
US6924560B2 (en) 2003-08-08 2005-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Compact SRAM cell with FinFET
JP4398195B2 (ja) 2003-08-08 2010-01-13 パナソニック株式会社 半導体記憶装置
JP2005059375A (ja) 2003-08-12 2005-03-10 Fuji Xerox Co Ltd インクジェット記録ヘッド、インクジェットヘッドカートリッジ及びインクジェット記録装置
JP4620942B2 (ja) 2003-08-21 2011-01-26 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク
TWI220268B (en) 2003-09-17 2004-08-11 Faraday Tech Corp Method for programming a routing layout design through one via layer
US6957402B2 (en) 2003-09-24 2005-10-18 Artisan Components, Inc. Yield maximization in the manufacture of integrated circuits
US7345909B2 (en) 2003-09-24 2008-03-18 Yen-Jen Chang Low-power SRAM memory cell
KR100516226B1 (ko) 2003-09-25 2005-09-23 동부아남반도체 주식회사 에스램 테스트용 셀 및 에스램 셀 테스트 방법
JP4599048B2 (ja) 2003-10-02 2010-12-15 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク
JP2005114752A (ja) 2003-10-02 2005-04-28 Yamaha Corp 演奏装置
JP4632287B2 (ja) 2003-10-06 2011-02-16 株式会社日立製作所 半導体集積回路装置
US7155689B2 (en) 2003-10-07 2006-12-26 Magma Design Automation, Inc. Design-manufacturing interface via a unified model
FR2860920A1 (fr) * 2003-10-14 2005-04-15 St Microelectronics Sa Procede de realisation de connexions conductrices de circuits integres, et circuit integre mettant en oeuvre des telles connexions
JP2005123524A (ja) 2003-10-20 2005-05-12 Toshiba Corp 半導体装置及びその製造方法
JP2005123537A (ja) 2003-10-20 2005-05-12 Sony Corp 半導体装置及び製造方法
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
JP4346410B2 (ja) 2003-10-28 2009-10-21 東芝メモリシステムズ株式会社 半導体集積回路の配線設計方法及び半導体集積回路
US7329953B2 (en) 2003-10-29 2008-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same
JP2005149265A (ja) 2003-11-18 2005-06-09 Olympus Corp 演算処理システム及び演算処理装置
US7269803B2 (en) 2003-12-18 2007-09-11 Lsi Corporation System and method for mapping logical components to physical locations in an integrated circuit design environment
US7052972B2 (en) 2003-12-19 2006-05-30 Micron Technology, Inc. Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus
JP4585197B2 (ja) 2003-12-22 2010-11-24 ルネサスエレクトロニクス株式会社 レイアウト設計方法およびフォトマスク
KR100702552B1 (ko) * 2003-12-22 2007-04-04 인터내셔널 비지네스 머신즈 코포레이션 이중 게이트 ＦｉｎＦＥＴ 디자인을 위한 자동화 레이어생성 방법 및 장치
ATE501907T1 (de) 2003-12-26 2011-04-15 Tan-Cheng Huang Hydraulische scheibenbremse
JP2005197345A (ja) 2004-01-05 2005-07-21 Hitachi Ltd 半導体装置
JP2005203447A (ja) 2004-01-13 2005-07-28 Toshiba Corp 半導体集積回路、半導体集積回路設計システム及び半導体集積回路設計方法
US7064068B2 (en) 2004-01-23 2006-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method to improve planarity of electroplated copper
KR100564612B1 (ko) 2004-02-19 2006-03-28 삼성전자주식회사 하드 디스크 드라이브
US7523429B2 (en) 2004-02-20 2009-04-21 Takumi Technology Corporation System for designing integrated circuits with enhanced manufacturability
TW200532768A (en) 2004-02-24 2005-10-01 Univ Hong Kong Rectangular contact lithography for circuit performance improvement
US7353492B2 (en) 2004-02-26 2008-04-01 International Business Machines Corporation Method of IC fabrication, IC mask fabrication and program product therefor
US7335966B2 (en) 2004-02-26 2008-02-26 Triad Semiconductor, Inc. Configurable integrated circuit capacitor array using via mask layers
JP2005243928A (ja) 2004-02-26 2005-09-08 Fujitsu Ltd トレンチアイソレーションで分離されたトランジスタ対を有する半導体装置
US7084476B2 (en) 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US7115343B2 (en) 2004-03-10 2006-10-03 International Business Machines Corporation Pliant SRAF for improved performance and manufacturability
JP4317777B2 (ja) 2004-03-10 2009-08-19 パナソニック株式会社 半導体集積回路
US7423298B2 (en) 2004-03-17 2008-09-09 Sharp Kabushiki Kaisha Bidirectional photothyristor chip, optical lighting coupler, and solid state relay
JP2005268610A (ja) 2004-03-19 2005-09-29 Matsushita Electric Ind Co Ltd スタンダードセルの設計方法及び半導体集積回路
DE102004014472B4 (de) 2004-03-24 2012-05-03 Infineon Technologies Ag Anwendungsspezifischer integrierter Halbleiter-Schaltkreis
US7126837B1 (en) 2004-03-26 2006-10-24 Netlogic Microsystems, Inc. Interlocking memory/logic cell layout and method of manufacture
WO2005096381A1 (en) 2004-04-01 2005-10-13 Soisic Improved layout of a sram memory cell
TWI297446B (en) 2004-04-02 2008-06-01 Clear Shape Technologies Inc Delta information design closure in integrated circuit fabrication
JP2007536564A (ja) 2004-04-02 2007-12-13 クリア・シェイプ・テクノロジーズ・インコーポレーテッド 集積回路の製造における超解像プロセスのモデル化
WO2005098954A1 (en) 2004-04-02 2005-10-20 Triad Semiconductor, Inc. Via configurable architecture for customization of analog circuitry in a semiconductor device
US7404173B2 (en) 2004-04-07 2008-07-22 Aprio Technologies, Inc. Intermediate layout for resolution enhancement in semiconductor fabrication
US20050229130A1 (en) 2004-04-07 2005-10-13 Aprio Technologies, Inc. Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
US7115920B2 (en) 2004-04-12 2006-10-03 International Business Machines Corporation FinFET transistor and circuit
US7724087B2 (en) 2004-04-20 2010-05-25 Nxp B.V. High speed differential receiver with rail to rail common mode operation having a symmetrical differential output signal with low skew
JP2007536581A (ja) 2004-05-07 2007-12-13 メンター・グラフィクス・コーポレーション プロセス変動バンドを用いた集積回路レイアウト設計法
US7194712B2 (en) 2004-05-12 2007-03-20 Synopsys, Inc. Method and apparatus for identifying line-end features for lithography verification
US7053668B2 (en) 2004-05-25 2006-05-30 Kabushiki Kaisha Toshiba SOI sense amplifier with cross-coupled body terminal
US7426710B2 (en) 2004-05-27 2008-09-16 Verisilicon Holdings, Co. Ltd. Standard cell library having cell drive strengths selected according to delay
US6975133B1 (en) 2004-05-27 2005-12-13 International Business Machines Corporation Logic circuits having linear and cellular gate transistors
US7257017B2 (en) 2004-05-28 2007-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cell for soft-error rate reduction and cell stability improvement
KR100591158B1 (ko) 2004-06-01 2006-06-19 동부일렉트로닉스 주식회사 반도체 소자의 게이트 전극의 제조 방법
US20070257277A1 (en) 2004-06-04 2007-11-08 Nec Corporation Semiconductor Device and Method for Manufacturing the Same
JP4834853B2 (ja) 2004-06-10 2011-12-14 シャープ株式会社 薄膜トランジスタ回路、薄膜トランジスタ回路の設計方法、薄膜トランジスタ回路の設計プログラム、設計プログラム記録媒体、及び表示装置
JP4248451B2 (ja) 2004-06-11 2009-04-02 パナソニック株式会社 半導体装置およびそのレイアウト設計方法
JP4778689B2 (ja) 2004-06-16 2011-09-21 パナソニック株式会社 標準セル、標準セルライブラリおよび半導体集積回路
US7327591B2 (en) 2004-06-17 2008-02-05 Texas Instruments Incorporated Staggered memory cell array
US7003068B2 (en) 2004-06-21 2006-02-21 Kenet, Inc. Device for subtracting or adding a constant amount of charge in a charge-coupled device at high operating frequencies
JP4405865B2 (ja) 2004-06-24 2010-01-27 富士通マイクロエレクトロニクス株式会社 多層配線構造の製造方法及びｆｉｂ装置
JP4175649B2 (ja) 2004-07-22 2008-11-05 松下電器産業株式会社 半導体装置
BRPI0513689A (pt) 2004-07-27 2008-05-13 Easic Corp dispositivos semicondutores, conjuntos lógicos e wafers semicondutores
US7176508B2 (en) 2004-07-27 2007-02-13 International Business Machines Corporation Temperature sensor for high power very large scale integration circuits
JP2006049780A (ja) 2004-08-09 2006-02-16 Elpida Memory Inc 半導体集積回路装置
US7093213B2 (en) 2004-08-13 2006-08-15 International Business Machines Corporation Method for designing an integrated circuit defect monitor
US7365432B2 (en) 2004-08-23 2008-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell structure
JP2006073696A (ja) * 2004-09-01 2006-03-16 Matsushita Electric Ind Co Ltd スタンダードセルを用いた半導体集積回路とその設計方法
US7632610B2 (en) 2004-09-02 2009-12-15 Intel Corporation Sub-resolution assist features
US20060063334A1 (en) 2004-09-17 2006-03-23 International Business Machines Corporation Fin FET diode structures and methods for building
US7227183B2 (en) 2004-09-17 2007-06-05 International Business Machines Corporation Polysilicon conductor width measurement for 3-dimensional FETs
US7185294B2 (en) 2004-09-23 2007-02-27 Verisilicon Holdings, Co Ltd Standard cell library having globally scalable transistor channel length
DE102004047263B4 (de) 2004-09-24 2010-04-22 Qimonda Ag Verfahren zum Erzeugen eines Abbildungsfehler vermeidenden Maskenlayouts für eine Maske
KR100594295B1 (ko) 2004-09-24 2006-06-30 삼성전자주식회사 층 성장을 이용한 게이트 형성 방법 및 이에 따른 게이트구조
US7337421B2 (en) 2004-09-30 2008-02-26 Cadence Design Systems, Inc. Method and system for managing design corrections for optical and process effects based on feature tolerances
US7466607B2 (en) 2004-09-30 2008-12-16 Analog Devices, Inc. Memory access system and method using de-coupled read and write circuits
US7335583B2 (en) 2004-09-30 2008-02-26 Intel Corporation Isolating semiconductor device structures
JP2006100718A (ja) 2004-09-30 2006-04-13 Matsushita Electric Ind Co Ltd 半導体集積回路装置の動作解析方法、これに用いられる解析装置およびこれを用いた最適化設計方法
JP2006114668A (ja) 2004-10-14 2006-04-27 Sony Corp 半導体集積回路およびその製造方法
US7487475B1 (en) 2004-10-15 2009-02-03 Cadence Design Systems, Inc. Systems, methods, and apparatus to perform statistical static timing analysis
JP2006119195A (ja) 2004-10-19 2006-05-11 Nec Electronics Corp 配線のレイアウト方法
US7302651B2 (en) 2004-10-29 2007-11-27 International Business Machines Corporation Technology migration for integrated circuits with radical design restrictions
US7458045B2 (en) 2004-10-29 2008-11-25 Synopsys, Inc. Silicon tolerance specification using shapes as design intent markers
JP4768251B2 (ja) 2004-11-01 2011-09-07 株式会社東芝 半導体集積回路の設計方法、半導体集積回路の設計システム及び半導体集積回路の製造方法
US7278118B2 (en) 2004-11-04 2007-10-02 Pdf Solutions, Inc. Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
KR100587692B1 (ko) 2004-11-05 2006-06-08 삼성전자주식회사 반도체 메모리 장치에서의 회로 배선 배치구조와 그에따른 배치방법
US7350183B2 (en) 2004-11-05 2008-03-25 International Business Machines Corporation Method for improving optical proximity correction
JP2006156778A (ja) 2004-11-30 2006-06-15 Matsushita Electric Ind Co Ltd 半導体装置及びそのレイアウト設計方法
US7424696B2 (en) 2004-12-03 2008-09-09 Lsi Corporation Power mesh for multiple frequency operation of semiconductor products
US7465973B2 (en) 2004-12-03 2008-12-16 International Business Machines Corporation Integrated circuit having gates and active regions forming a regular grating
JP2006165365A (ja) 2004-12-09 2006-06-22 Renesas Technology Corp 半導体装置および半導体装置の製造方法
US7345330B2 (en) * 2004-12-09 2008-03-18 Omnivision Technologies, Inc. Local interconnect structure and method for a CMOS image sensor
US7396732B2 (en) 2004-12-17 2008-07-08 Interuniversitair Microelektronica Centrum Vzw (Imec) Formation of deep trench airgaps and related applications
JP4357409B2 (ja) 2004-12-17 2009-11-04 株式会社東芝 半導体集積回路装置及びその設計方法
JP2007043049A (ja) 2004-12-20 2007-02-15 Matsushita Electric Ind Co Ltd セル、スタンダードセル、スタンダードセル配置方法、スタンダードセルライブラリ、ならびに半導体集積回路
FR2879816B1 (fr) 2004-12-20 2007-06-08 Atmel Nantes Sa Sa Circuit electronique comprenant au moins une premiere et une seconde paires differentielles dont les transistors partagent un meme caisson
WO2006069340A2 (en) 2004-12-21 2006-06-29 Carnegie Mellon University Lithography and associated methods, devices, and systems
EP1833091A4 (en) 2004-12-28 2008-08-13 Spansion Llc SEMICONDUCTOR DEVICE AND METHOD OF OPERATING CONTROL
US7106620B2 (en) 2004-12-30 2006-09-12 International Business Machines Corporation Memory cell having improved read stability
US7743349B2 (en) 2004-12-31 2010-06-22 Tela Innovations, Inc. Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit
US7509621B2 (en) 2005-01-03 2009-03-24 Synopsys, Inc. Method and apparatus for placing assist features by identifying locations of constructive and destructive interference
US7366997B1 (en) 2005-01-11 2008-04-29 Synplicity, Inc. Methods and apparatuses for thermal analysis based circuit design
JP2006196627A (ja) 2005-01-12 2006-07-27 Nec Electronics Corp 半導体装置、及び半導体装置の設計プログラム
DE102005002533B4 (de) 2005-01-14 2007-09-13 Infineon Technologies Ag Verfahren zum Erzeugen eines Abbildungsfehler vermeidenden Maskenlayouts für eine Maske
JP4455356B2 (ja) 2005-01-28 2010-04-21 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4602112B2 (ja) 2005-02-17 2010-12-22 株式会社東芝 半導体集積回路の製造方法及び半導体集積回路
KR20060092408A (ko) 2005-02-17 2006-08-23 삼성전자주식회사 고성능 배타적 오아 및 배타적 노아 회로 및 방법
WO2006090445A1 (ja) 2005-02-23 2006-08-31 Fujitsu Limited 半導体回路装置及びその半導体回路装置の製造方法
US7287237B2 (en) 2005-02-24 2007-10-23 Icera Inc. Aligned logic cell grid and interconnect routing architecture
US7721246B2 (en) 2005-02-24 2010-05-18 Synopsys, Inc. Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout
US7421678B2 (en) 2005-02-24 2008-09-02 Synopsys, Inc. Assist feature placement using a process-sensitivity model
US7266787B2 (en) 2005-02-24 2007-09-04 Icera, Inc. Method for optimising transistor performance in integrated circuits
US7200835B2 (en) 2005-02-24 2007-04-03 Texas Instruments Incorporated Method of locating sub-resolution assist feature(s)
US7188322B2 (en) 2005-02-25 2007-03-06 International Business Machines Corporation Circuit layout methodology using a shape processing application
TWI281317B (en) 2005-03-07 2007-05-11 Sunplus Technology Co Ltd Self DC-bias high frequency logic gate, NAND gate, and NOR gate using the same
US7304874B2 (en) 2005-03-08 2007-12-04 Lsi Corporation Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas
US7992122B1 (en) 2005-03-25 2011-08-02 Gg Technology, Inc. Method of placing and routing for power optimization and timing closure
US7563701B2 (en) 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
US7882456B2 (en) 2005-04-09 2011-02-01 Cadence Design Systems, Inc. Optical lithography correction process
JP4617272B2 (ja) 2005-04-12 2011-01-19 エーエスエムエル マスクツールズ ビー．ブイ． 二重露光リソグラフィを実行するための方法、プログラム製品及びデバイス製造方法
JP4634849B2 (ja) 2005-04-12 2011-02-16 株式会社東芝 集積回路のパターンレイアウト、フォトマスク、半導体装置の製造方法、及びデータ作成方法
JP4921723B2 (ja) 2005-04-18 2012-04-25 株式会社東芝 半導体装置の製造方法
TWI297101B (en) 2005-04-20 2008-05-21 Nanya Technology Corp Phase shifting mask for equal line/space dense line patterns
US7480891B2 (en) 2005-04-29 2009-01-20 Cadence Design Systems, Inc. Method and apparatus of model-based photomask synthesis
US7506300B2 (en) 2005-04-29 2009-03-17 Cadence Design Systems, Inc. Apparatus and method for breaking up and merging polygons
US7441211B1 (en) 2005-05-06 2008-10-21 Blaze Dfm, Inc. Gate-length biasing for digital circuit optimization
US8044437B1 (en) 2005-05-16 2011-10-25 Lsi Logic Corporation Integrated circuit cell architecture configurable for memory or logic elements
JP4936418B2 (ja) 2005-05-17 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法、及び半導体装置の設計プログラム
US7308669B2 (en) 2005-05-18 2007-12-11 International Business Machines Corporation Use of redundant routes to increase the yield and reliability of a VLSI layout
JP4912016B2 (ja) 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR20080018905A (ko) 2005-05-26 2008-02-28 엔엑스피 비 브이 전자 장치 및 그 설계 방법
US7411252B2 (en) 2005-06-21 2008-08-12 International Business Machines Corporation Substrate backgate for trigate FET
US7960791B2 (en) 2005-06-24 2011-06-14 International Business Machines Corporation Dense pitch bulk FinFET process by selective EPI and etch
US7492013B2 (en) 2005-06-27 2009-02-17 International Business Machines Corporation Systems and arrangements to interconnect components of a semiconductor device
EP1907957A4 (en) 2005-06-29 2013-03-20 Otrsotech Ltd Liability Company INVESTMENT METHODS AND SYSTEMS
US8405216B2 (en) 2005-06-29 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for integrated circuits
US7236396B2 (en) 2005-06-30 2007-06-26 Texas Instruments Incorporated Area efficient implementation of small blocks in an SRAM array
JP2007012855A (ja) * 2005-06-30 2007-01-18 Matsushita Electric Ind Co Ltd 半導体集積回路、標準セル、標準セルライブラリ、半導体集積回路の設計方法および半導体集積回路の設計装置
JP2007013060A (ja) 2005-07-04 2007-01-18 Matsushita Electric Ind Co Ltd 半導体装置
JP2007018588A (ja) * 2005-07-06 2007-01-25 Toshiba Corp 半導体記憶装置および半導体記憶装置の駆動方法
US7235424B2 (en) 2005-07-14 2007-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for enhanced CMP planarization using surrounded dummy design
WO2007010621A1 (ja) 2005-07-22 2007-01-25 Fujitsu Limited フォトマスクパターンデータの作成方法、そのフォトマスクパターンデータを用いて作成されたフォトマスク、及び、そのフォトマスクを用いた半導体装置の製造方法
EP1917715A2 (en) 2005-07-22 2008-05-07 Nanopower Technologies, Inc. High sensitivity rfid tag integrated circuits
US7404154B1 (en) 2005-07-25 2008-07-22 Lsi Corporation Basic cell architecture for structured application-specific integrated circuits
US7934172B2 (en) 2005-08-08 2011-04-26 Micronic Laser Systems Ab SLM lithography: printing to below K1=.30 without previous OPC processing
US7568174B2 (en) 2005-08-19 2009-07-28 Cadence Design Systems, Inc. Method for checking printability of a lithography target
JP2007093861A (ja) 2005-09-28 2007-04-12 Renesas Technology Corp マスクパターン設計方法および半導体装置の製造方法
US7749662B2 (en) 2005-10-07 2010-07-06 Globalfoundries Inc. Process margin using discrete assist features
US7485934B2 (en) 2005-10-25 2009-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated semiconductor structure for SRAM cells
JP4796817B2 (ja) 2005-10-31 2011-10-19 エルピーダメモリ株式会社 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム
US20070106971A1 (en) 2005-11-04 2007-05-10 Lizotech, Inc. Apparatus for a routing system
US7397260B2 (en) 2005-11-04 2008-07-08 International Business Machines Corporation Structure and method for monitoring stress-induced degradation of conductive interconnects
US7569309B2 (en) 2005-11-09 2009-08-04 Texas Instruments Incorporated Gate critical dimension variation by use of ghost features
US7527900B2 (en) 2005-11-10 2009-05-05 United Microelectronics Corp. Reticle and optical proximity correction method
US7934184B2 (en) 2005-11-14 2011-04-26 Takumi Technology Corporation Integrated circuit design using modified cells
JP2007141971A (ja) 2005-11-15 2007-06-07 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法
DE102006027178A1 (de) 2005-11-21 2007-07-05 Infineon Technologies Ag Multi-Fin-Bauelement-Anordnung und Verfahren zum Herstellen einer Multi-Fin-Bauelement-Anordnung
WO2007063990A1 (ja) 2005-12-02 2007-06-07 Nec Corporation 半導体装置およびその製造方法
US7543262B2 (en) 2005-12-06 2009-06-02 Cadence Design Systems, Inc. Analog layout module generator and method
US7569310B2 (en) 2005-12-07 2009-08-04 Intel Corporation Sub-resolution assist features for photolithography with trim ends
US7512017B2 (en) 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
JP4774294B2 (ja) 2005-12-26 2011-09-14 富士通株式会社 集積回路レイアウト装置、その方法及びプログラム
EP1804282A1 (en) 2005-12-29 2007-07-04 Interuniversitair Microelektronica Centrum vzw ( IMEC) Methods for manufacturing dense integrated circuits
US7640522B2 (en) 2006-01-14 2009-12-29 Tela Innovations, Inc. Method and system for placing layout objects in a standard-cell layout
US7614030B2 (en) 2006-01-17 2009-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Scattering bar OPC application method for mask ESD prevention
JP5091462B2 (ja) 2006-01-19 2012-12-05 パナソニック株式会社 セルおよび半導体装置
JP4675249B2 (ja) 2006-02-07 2011-04-20 パナソニック株式会社 位置依存変動量計算方法並びに回路解析方法
US7480880B2 (en) 2006-02-21 2009-01-20 International Business Machines Corporation Method, system, and program product for computing a yield gradient from statistical timing
US7469401B2 (en) 2006-02-22 2008-12-23 International Business Machines Corporation Method for using partitioned masks to build a chip
JP4644614B2 (ja) 2006-02-27 2011-03-02 富士通セミコンダクター株式会社 レイアウトエディタ装置、配線表示方法、及び配線表示プログラム
JP4791855B2 (ja) 2006-02-28 2011-10-12 株式会社東芝 半導体記憶装置
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US20070218685A1 (en) 2006-03-17 2007-09-20 Swaminathan Sivakumar Method of forming trench contacts for MOS transistors
JP2007265179A (ja) 2006-03-29 2007-10-11 Fujitsu Ltd レイアウト検証方法、レイアウト検証装置
JP4882455B2 (ja) 2006-03-31 2012-02-22 富士通セミコンダクター株式会社 半導体集積回路のユニットセルおよびユニットセルを使用した配線方法および配線プログラム
US7382054B2 (en) * 2006-04-07 2008-06-03 Macronix International Co., Ltd. Method for forming self-aligned contacts and local interconnects simultaneously
US7437691B2 (en) 2006-04-11 2008-10-14 International Business Machines Corporation VLSI artwork legalization for hierarchical designs with multiple grid constraints
US7484197B2 (en) 2006-04-14 2009-01-27 International Business Machines Corporation Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs
US7509622B2 (en) 2006-04-17 2009-03-24 Synopsys, Inc. Dummy filling technique for improved planarization of chip surface topography
JP5579959B2 (ja) 2006-04-18 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
US7407890B2 (en) 2006-04-21 2008-08-05 International Business Machines Corporation Patterning sub-lithographic features with variable widths
US7355906B2 (en) 2006-05-24 2008-04-08 International Business Machines Corporation SRAM cell design to improve stability
US7941776B2 (en) 2006-05-26 2011-05-10 Open-Silicon Inc. Method of IC design optimization via creation of design-specific cells from post-layout patterns
WO2007149004A1 (en) 2006-06-13 2007-12-27 Freescale Semiconductor, Inc. Methods and apparatus for simulating distributed effects
US7317339B1 (en) 2006-06-16 2008-01-08 Via Technologies, Inc. N-domino register with accelerated non-discharge path
US7459792B2 (en) 2006-06-19 2008-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Via layout with via groups placed in interlocked arrangement
US7992117B2 (en) 2006-06-20 2011-08-02 Adtran, Inc. System and method for designing a common centroid layout for an integrated circuit
JP2008004796A (ja) 2006-06-23 2008-01-10 Matsushita Electric Ind Co Ltd 半導体装置および回路素子レイアウト方法
US7763932B2 (en) 2006-06-29 2010-07-27 International Business Machines Corporation Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices
US7444609B2 (en) 2006-06-29 2008-10-28 International Business Machines Corporation Method of optimizing customizable filler cells in an integrated circuit physical design process
US7739627B2 (en) 2006-07-05 2010-06-15 Chew Marko P System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells
JP2008027940A (ja) 2006-07-18 2008-02-07 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法および回路シミュレーション方法
DE102006037162B4 (de) 2006-08-01 2008-08-21 Qimonda Ag Verfahren und Vorrichtung und deren Verwendung zur Prüfung des Layouts einer elektronischen Schaltung
JP5080578B2 (ja) 2006-08-04 2012-11-21 サガンテック イスラエル リミテッド 回路レイアウトを所定のグリッドに適応させるための方法及びシステム
US7966579B2 (en) 2006-08-04 2011-06-21 Infineon Technologies Ag Methods of optical proximity correction
US7873929B2 (en) 2006-08-14 2011-01-18 The Regents Of The University Of California Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction
US7886262B2 (en) 2006-08-15 2011-02-08 Chew Marko P System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization
TW200811704A (en) 2006-08-31 2008-03-01 Univ Nat Yunlin Sci & Tech Full adder of complementary type carry logic voltage compensator
KR100773353B1 (ko) * 2006-09-26 2007-11-05 삼성전자주식회사 기판 플러그를 가지는 반도체 장치들 및 그의 형성방법들
US7434185B2 (en) 2006-09-27 2008-10-07 International Business Machines Corporation Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data
JP4362785B2 (ja) 2006-09-28 2009-11-11 エルピーダメモリ株式会社 半導体装置の製造方法
US20080082952A1 (en) 2006-09-29 2008-04-03 Texas Instruments Incorporated Method of inclusion of sub-resolution assist feature(s)
US7592247B2 (en) 2006-10-04 2009-09-22 International Business Machines Corporation Sub-lithographic local interconnects, and methods for forming same
JP4814044B2 (ja) 2006-10-05 2011-11-09 ルネサスエレクトロニクス株式会社 パターン設計方法
US8230379B2 (en) 2006-10-20 2012-07-24 Kabushiki Kaisha Toshiba Layout generating method for semiconductor integrated circuits
JP2008103610A (ja) 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体集積回路の配線構造およびその設計方法と設計装置
US7624369B2 (en) 2006-10-31 2009-11-24 International Business Machines Corporation Closed-loop design for manufacturability process
US7774739B2 (en) 2006-11-30 2010-08-10 Texas Instruments Incorporated Methods for adjusting shifter width of an alternating phase shifter having variable width
US7802219B2 (en) 2006-11-30 2010-09-21 Cadence Design Systems, Inc. Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout
US8378407B2 (en) 2006-12-07 2013-02-19 Tower Semiconductor, Ltd. Floating gate inverter type memory cell and array
US8156450B2 (en) 2006-12-18 2012-04-10 Cadence Design Systems, Inc. Method and system for mask optimization
US7814447B2 (en) 2006-12-29 2010-10-12 Cadence Design Systems, Inc. Supplant design rules in electronic designs
US8178905B2 (en) 2007-01-12 2012-05-15 Panasonic Corporation Layout structure of semiconductor device
US7535751B2 (en) 2007-02-12 2009-05-19 Taiwan Semioconductor Manufacturing Co., Ltd. Dual-port SRAM device
JP5217180B2 (ja) 2007-02-20 2013-06-19 富士通セミコンダクター株式会社 静電放電保護装置の製造方法
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US20080216207A1 (en) 2007-03-09 2008-09-11 Shen-Hai Tsai Finger pressing massage glove
KR100911187B1 (ko) 2007-03-13 2009-08-06 주식회사 하이닉스반도체 래치 구조 및 그것을 포함하는 비트라인 센스앰프 구조
US7575973B2 (en) 2007-03-27 2009-08-18 Sandisk 3D Llc Method of making three dimensional NAND memory
US7543252B2 (en) 2007-03-28 2009-06-02 International Business Machines Corporation Migration of integrated circuit layout for alternating phase shift masks
US7791109B2 (en) 2007-03-29 2010-09-07 International Business Machines Corporation Metal silicide alloy local interconnect
US7757196B2 (en) 2007-04-04 2010-07-13 Cisco Technology, Inc. Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards
US7723786B2 (en) 2007-04-11 2010-05-25 Ronald Kakoschke Apparatus of memory array using FinFETs
US7964267B1 (en) 2007-04-13 2011-06-21 Bae Systems Tensylon H.P.M., Inc. Ballistic-resistant panel including high modulus ultra high molecular weight polyethylene tape
US7453125B1 (en) 2007-04-24 2008-11-18 Infineon Technologies Ag Double mesh finfet
JP4461154B2 (ja) 2007-05-15 2010-05-12 株式会社東芝 半導体装置
US20080283910A1 (en) 2007-05-15 2008-11-20 Qimonda Ag Integrated circuit and method of forming an integrated circuit
US7911830B2 (en) 2007-05-17 2011-03-22 Integrated Magnetoelectronics Scalable nonvolatile memory
JP4445521B2 (ja) 2007-06-15 2010-04-07 株式会社東芝 半導体装置
US7898040B2 (en) 2007-06-18 2011-03-01 Infineon Technologies Ag Dual gate FinFET
US7923337B2 (en) 2007-06-20 2011-04-12 International Business Machines Corporation Fin field effect transistor devices with self-aligned source and drain regions
US7759194B2 (en) 2008-07-25 2010-07-20 Semiconductor Manufacturing International (Shanghai) Corporation Electrically programmable device with embedded EEPROM and method for making thereof
JP2009025914A (ja) 2007-07-17 2009-02-05 Nec Electronics Corp 半導体集積回路の設計方法及び設計プログラム
US7625790B2 (en) 2007-07-26 2009-12-01 International Business Machines Corporation FinFET with sublithographic fin width
US7700466B2 (en) 2007-07-26 2010-04-20 International Business Machines Corporation Tunneling effect transistor with self-aligned gate
US20090057780A1 (en) 2007-08-27 2009-03-05 International Business Machines Corporation Finfet structure including multiple semiconductor fin channel heights
US8156451B2 (en) 2007-09-14 2012-04-10 Renesas Electronics Corporation Method of manufacturing photomask
KR100905157B1 (ko) 2007-09-18 2009-06-29 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
JP2009088085A (ja) 2007-09-28 2009-04-23 Tokyo Electron Ltd 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びプログラム記憶媒体
US20090101940A1 (en) 2007-10-19 2009-04-23 Barrows Corey K Dual gate fet structures for flexible gate array design methodologies
US8042070B2 (en) 2007-10-23 2011-10-18 International Business Machines Corporation Methods and system for analysis and management of parametric yield
JP2009130238A (ja) 2007-11-27 2009-06-11 Fujitsu Microelectronics Ltd 半導体装置
JP5193582B2 (ja) 2007-12-12 2013-05-08 株式会社東芝 半導体装置の製造方法
WO2009078069A1 (ja) 2007-12-14 2009-06-25 Fujitsu Limited 半導体装置
JP2009152368A (ja) 2007-12-20 2009-07-09 Hitachi Ltd 半導体装置およびその製造方法
US7825437B2 (en) 2007-12-28 2010-11-02 Intel Corporation Unity beta ratio tri-gate transistor static random access memory (SRAM)
PL2235453T3 (pl) 2007-12-31 2017-02-28 Arçelik Anonim Sirketi Urządzenie chłodzące
US7983071B2 (en) 2008-01-04 2011-07-19 Texas Instruments Incorporated Dual node access storage cell having buffer circuits
US7934173B2 (en) 2008-01-14 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse dummy insertion algorithm
US7926001B2 (en) 2008-01-16 2011-04-12 Cadence Design Systems, Inc. Uniformity for semiconductor patterning operations
US7984395B2 (en) 2008-01-17 2011-07-19 Synopsys, Inc. Hierarchical compression for metal one logic layer
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US7962878B2 (en) 2008-02-26 2011-06-14 Infineon Technologies Ag Method of making an integrated circuit using pre-defined interconnect wiring
US8423947B2 (en) 2008-03-13 2013-04-16 International Business Machines Corporation Gridded glyph geometric objects (L3GO) design method
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8173544B2 (en) 2008-05-02 2012-05-08 Texas Instruments Incorporated Integrated circuit having interleaved gridded features, mask set and method for printing
US7958465B2 (en) 2008-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy pattern design for reducing device performance drift
US7917877B2 (en) 2008-05-09 2011-03-29 Cadence Design Systems, Inc. System and method for circuit schematic generation
EP2117045A1 (en) 2008-05-09 2009-11-11 Imec Design Methodology for MuGFET ESD Protection Devices
US7830025B2 (en) 2008-05-19 2010-11-09 United Microelectronics Corp. Contact layout structure
US7853915B2 (en) 2008-06-24 2010-12-14 Synopsys, Inc. Interconnect-driven physical synthesis using persistent virtual routing
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8136072B2 (en) 2008-11-03 2012-03-13 Arm Limited Standard cell placement
US8363455B2 (en) 2008-12-04 2013-01-29 David Rennie Eight transistor soft error robust storage cell
JP2010141047A (ja) 2008-12-10 2010-06-24 Renesas Technology Corp 半導体集積回路装置および半導体集積回路装置の製造方法
US20100187609A1 (en) 2009-01-27 2010-07-29 Synopsys, Inc. Boosting transistor performance with non-rectangular channels
US8116121B2 (en) 2009-03-06 2012-02-14 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing methods with using non-planar type of transistors
EP2248161B1 (en) 2009-03-06 2019-05-01 Kaixin Inc. Leadless integrated circuit package having high density contacts
US8184472B2 (en) 2009-03-13 2012-05-22 International Business Machines Corporation Split-gate DRAM with lateral control-gate MuGFET
US8004042B2 (en) 2009-03-20 2011-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Static random access memory (SRAM) cell and method for forming same
US8053299B2 (en) 2009-04-17 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabrication of a FinFET element
US8076236B2 (en) 2009-06-01 2011-12-13 Globalfoundries Inc. SRAM bit cell with self-aligned bidirectional local interconnects
US8782586B2 (en) 2009-07-16 2014-07-15 Cadence Design Systems, Inc. Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning
US8294212B2 (en) 2009-09-18 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed
US8675397B2 (en) 2010-06-25 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure for dual-port SRAM
US8860107B2 (en) 2010-06-03 2014-10-14 International Business Machines Corporation FinFET-compatible metal-insulator-metal capacitor
US8839162B2 (en) 2010-07-14 2014-09-16 International Business Machines Corporation Specifying circuit level connectivity during circuit design synthesis
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8418111B2 (en) 2010-11-24 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for achieving multiple patterning technology compliant design layout
US8402397B2 (en) 2011-07-26 2013-03-19 Mentor Graphics Corporation Hotspot detection based on machine learning
US8689164B2 (en) 2011-10-18 2014-04-01 National Taiwan University Method of analytical placement with weighted-average wirelength model
US9006841B2 (en) 2011-12-30 2015-04-14 Stmicroelectronics International N.V. Dual port SRAM having reduced cell size and rectangular shape
FR2996950B1 (fr) 2012-10-11 2016-01-01 Dolphin Integration Sa Réseau de mémoire base sur des bascules

Also Published As

Publication number Publication date
KR20160118388A (ko) 2016-10-11
US20160133626A1 (en) 2016-05-12
TW200943480A (en) 2009-10-16
TW201342531A (zh) 2013-10-16
TWI619204B (zh) 2018-03-21
US8680626B2 (en) 2014-03-25
KR101749881B1 (ko) 2017-06-21
KR20170032487A (ko) 2017-03-22
KR101669383B1 (ko) 2016-10-25
KR101718676B1 (ko) 2017-03-21
US9240413B2 (en) 2016-01-19
US7763534B2 (en) 2010-07-27
US20090108360A1 (en) 2009-04-30
KR20150016564A (ko) 2015-02-12
US10734383B2 (en) 2020-08-04
TW201814835A (zh) 2018-04-16
TW201628128A (zh) 2016-08-01
US20160133625A1 (en) 2016-05-12
EP2592649B1 (en) 2015-04-29
EP2592648A1 (en) 2013-05-15
KR20160081990A (ko) 2016-07-08
US20180145075A1 (en) 2018-05-24
KR101530736B1 (ko) 2015-06-22
KR20150066611A (ko) 2015-06-16
TWI569369B (zh) 2017-02-01
KR101588626B1 (ko) 2016-02-12
US20140167185A1 (en) 2014-06-19
TWI402940B (zh) 2013-07-21
US20100252896A1 (en) 2010-10-07
TW201701408A (zh) 2017-01-01
TWI552267B (zh) 2016-10-01
EP3188217A3 (en) 2017-08-02
EP2592649A1 (en) 2013-05-15
US7994545B2 (en) 2011-08-09
WO2009054936A2 (en) 2009-04-30
EP2206146A2 (en) 2010-07-14
KR20160014105A (ko) 2016-02-05
KR20100103469A (ko) 2010-09-27
US9741719B2 (en) 2017-08-22
EP2206146B1 (en) 2017-01-18
US20110278681A1 (en) 2011-11-17
TW201733011A (zh) 2017-09-16
EP3188217A2 (en) 2017-07-05
US9859277B2 (en) 2018-01-02
US20200381429A1 (en) 2020-12-03
WO2009054936A3 (en) 2009-07-02
EP2206146A4 (en) 2011-01-05
KR101669395B1 (ko) 2016-11-09

Similar Documents

Publication Publication Date Title
TWI598998B (zh) 積體電路中採用之自對準局部互連線用之方法、結構與設計
TWI521678B (zh) 動態陣列結構
KR20090077195A (ko) 반도체 소자 및 그 제조방법
US20150243735A1 (en) Semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees