BRPI0513689A - dispositivos semicondutores, conjuntos lógicos e wafers semicondutores - Google Patents

dispositivos semicondutores, conjuntos lógicos e wafers semicondutores

Info

Publication number
BRPI0513689A
BRPI0513689A BRPI0513689-0A BRPI0513689A BRPI0513689A BR PI0513689 A BRPI0513689 A BR PI0513689A BR PI0513689 A BRPI0513689 A BR PI0513689A BR PI0513689 A BRPI0513689 A BR PI0513689A
Authority
BR
Brazil
Prior art keywords
customizable
multiplicity
semiconductor
semiconductor devices
cells
Prior art date
Application number
BRPI0513689-0A
Other languages
English (en)
Inventor
Zvi Or-Bach
Petrica Avram
Romeo Iacobut
Adrian Apostol
Ze Ev Wurman
Adam Leventhal
Richard Zeman
Alon Kapel
George Catalin Grigore
Original Assignee
Easic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/899,020 external-priority patent/US7098691B2/en
Application filed by Easic Corp filed Critical Easic Corp
Publication of BRPI0513689A publication Critical patent/BRPI0513689A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Dispositivos Semicondutores, Conjuntos Lógicos o Wafers Semicondutores Um conjunto lógico configurável pode incluir: uma multiplicidade de células lógicas, contendo tabelas de consulta; camadas de metal customizáveis e de conexão de vias que revestem a multiplicidade de células lógicas; uma multiplicidade de células I/O customizáveis do dispositivo; urna multiplicidade de blocos RAM customizáveis do dispositivo; um bloco ROM de conteúdos customizáveis; e um microprocessador com I/O customizável para configurar e testar o conjunto em que as customizações são todas feitas sobre uma única camada de vias.
BRPI0513689-0A 2004-07-27 2005-07-25 dispositivos semicondutores, conjuntos lógicos e wafers semicondutores BRPI0513689A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/899,020 US7098691B2 (en) 2004-07-27 2004-07-27 Structured integrated circuit device
US11/186,923 US7157937B2 (en) 2004-07-27 2005-07-22 Structured integrated circuit device
PCT/US2005/026227 WO2006014849A2 (en) 2004-07-27 2005-07-25 Structured integrated circuit device

Publications (1)

Publication Number Publication Date
BRPI0513689A true BRPI0513689A (pt) 2008-05-13

Family

ID=35787738

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0513689-0A BRPI0513689A (pt) 2004-07-27 2005-07-25 dispositivos semicondutores, conjuntos lógicos e wafers semicondutores

Country Status (8)

Country Link
US (1) US7514959B2 (pt)
EP (1) EP1776762B1 (pt)
JP (1) JP2008512850A (pt)
KR (1) KR101234746B1 (pt)
AU (1) AU2005269568A1 (pt)
BR (1) BRPI0513689A (pt)
CA (1) CA2585870C (pt)
WO (1) WO2006014849A2 (pt)

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US6873185B2 (en) * 2002-06-19 2005-03-29 Viasic, Inc. Logic array devices having complex macro-cell architecture and methods facilitating use of same
US7337425B2 (en) 2004-06-04 2008-02-26 Ami Semiconductor, Inc. Structured ASIC device with configurable die size and selectable embedded functions
US7257797B1 (en) * 2004-06-07 2007-08-14 Pulsic Limited Method of automatic shape-based routing of interconnects in spines for integrated circuit design
US7343581B2 (en) 2005-06-27 2008-03-11 Tela Innovations, Inc. Methods for creating primitive constructed standard cells
US7295035B1 (en) * 2005-08-09 2007-11-13 Lattice Semiconductor Corporation Programmable logic device with enhanced logic block architecture
US7590968B1 (en) 2006-03-01 2009-09-15 Tela Innovations, Inc. Methods for risk-informed chip layout generation
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7943967B2 (en) * 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7577049B1 (en) 2006-08-08 2009-08-18 Tela Innovations, Inc. Speculative sense enable tuning apparatus and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7692309B2 (en) * 2007-09-06 2010-04-06 Viasic, Inc. Configuring structured ASIC fabric using two non-adjacent via layers
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG192532A1 (en) 2008-07-16 2013-08-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
JP5453850B2 (ja) * 2009-03-06 2014-03-26 富士通セミコンダクター株式会社 半導体集積回路
KR101113031B1 (ko) * 2009-09-25 2012-02-27 주식회사 실리콘웍스 드라이버 집적회로 칩의 패드 배치 구조
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8937491B2 (en) * 2012-11-15 2015-01-20 Xilinx, Inc. Clock network architecture
US10523209B1 (en) * 2017-11-14 2019-12-31 Flex Logix Technologies, Inc. Test circuitry and techniques for logic tiles of FPGA
US11694015B2 (en) * 2021-06-23 2023-07-04 Nxp B.V. Signal routing between memory and memory controller

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JPH07263628A (ja) * 1994-03-18 1995-10-13 Fujitsu Ltd 半導体装置
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US6427222B1 (en) * 1997-09-30 2002-07-30 Jeng-Jye Shau Inter-dice wafer level signal transfer methods for integrated circuits
US6242767B1 (en) * 1997-11-10 2001-06-05 Lightspeed Semiconductor Corp. Asic routing architecture
US6236229B1 (en) 1999-05-13 2001-05-22 Easic Corporation Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities
US6331733B1 (en) 1999-08-10 2001-12-18 Easic Corporation Semiconductor device
US6194912B1 (en) 1999-03-11 2001-02-27 Easic Corporation Integrated circuit device
US6245634B1 (en) 1999-10-28 2001-06-12 Easic Corporation Method for design and manufacture of semiconductors
US6580289B2 (en) * 2001-06-08 2003-06-17 Viasic, Inc. Cell architecture to reduce customization in a semiconductor device
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6742172B2 (en) * 2002-03-29 2004-05-25 Altera Corporation Mask-programmable logic devices with programmable gate array sites
US6693454B2 (en) * 2002-05-17 2004-02-17 Viasic, Inc. Distributed RAM in a logic array
US6873185B2 (en) * 2002-06-19 2005-03-29 Viasic, Inc. Logic array devices having complex macro-cell architecture and methods facilitating use of same

Also Published As

Publication number Publication date
KR20070087545A (ko) 2007-08-28
US7514959B2 (en) 2009-04-07
WO2006014849A3 (en) 2006-06-15
AU2005269568A1 (en) 2006-02-09
US20060139057A1 (en) 2006-06-29
WO2006014849A2 (en) 2006-02-09
KR101234746B1 (ko) 2013-02-19
EP1776762A4 (en) 2008-01-23
CA2585870A1 (en) 2006-02-09
JP2008512850A (ja) 2008-04-24
EP1776762B1 (en) 2012-02-01
EP1776762A2 (en) 2007-04-25
CA2585870C (en) 2014-09-09

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired