TW543147B - Integrated circuit with self-aligned line and via and manufacturing method therefor - Google Patents
Integrated circuit with self-aligned line and via and manufacturing method therefor Download PDFInfo
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543147 五、發明說明(1) [發明領域] 本發明主要係關於積體電路,尤其係關於用於半導體 元件之導線及通孔内連線。 [背景技藝] 半導體技術已經快速發展至使積體電路的合併超過百 萬個電晶體成為可能的事。然而,需要此類積體電路之技 術的快速發展,才剛開始迅速地增加。諸如即時圖像、高 晝質電視、虛擬實境及其它科學與工業應用正需要較高 速、較大功能性及甚至是在超大型積體電路技術上有更快 速的進步。 在更多功能性方面的需求則需要使電晶體整合在單一 積體電路晶片上之數目的大量增加。這需要縮減該電晶體 之尺寸及/或擁有較大的晶片尺寸。 當電晶體的尺寸減小時,因此而增加的密度必須在該 積體電路晶片内增加内連線數目。當該内連線數目增加 時,在該半導體晶片上由該内連線所佔據的面積數量變得 相對地大並且可能抵消由縮減該電晶體之尺寸所省下的面 積。 對於超大型積體電路在半導體工業上之長遠尋求的目 標是在於對内連線能達到最小面積的佈局,因為最小面積 佈局通常提供最佳的效能及經濟性。 此外,當電晶體之數目增量時,在内連接導線與連接 不同階層之通孔(v i a)之間之多重階層的内連線是必須 的0543147 V. Description of the invention (1) [Field of the invention] The present invention is mainly related to integrated circuits, and more particularly, it relates to wires used in semiconductor elements and interconnections in through holes. [Background Art] Semiconductor technology has been rapidly developed to enable the integration of integrated circuits with more than one million transistors. However, the rapid development of technologies that require such integrated circuits has only just begun to increase rapidly. Technologies such as instant image, high-quality TV, virtual reality, and other scientific and industrial applications are demanding higher speeds, greater functionality, and even faster advancements in ultra-large integrated circuit technology. The need for more functionality requires a significant increase in the number of transistors integrated on a single integrated circuit chip. This requires reducing the size of the transistor and / or having a larger wafer size. As the size of the transistor decreases, the increased density must therefore increase the number of interconnects within the integrated circuit chip. As the number of interconnects increases, the amount of area occupied by the interconnects on the semiconductor wafer becomes relatively large and may offset the area saved by reducing the size of the transistor. The long-term goal of the ultra-large integrated circuit in the semiconductor industry is to achieve the smallest area layout of the interconnects, because the smallest area layout usually provides the best efficiency and economy. In addition, as the number of transistors increases, multiple levels of interconnects between the interconnecting wires and vias (v i a) connecting different levels are necessary.
92086.ptd 第6頁 54314792086.ptd Page 6 543147
餘刻清洗溶液所腐钱之通孔意外將會放大 成的問題。 via chain)生成 -via)重疊及受至,j l因對準失調所造 直是長遠追求的,但是同 對於這些問題的解決方式一 樣地也長期困惑著熟習此項技藝之人士。 一 [發明揭露] 本發明係提供一種積體電路及其製造方法,該積體 路具有-第-介電層形成於一基底坊。—第二介電層 於該第一介電層之上。一第三介電層以間距分隔長條 (spaced-apart strips)方式形成於該第二介電層之上。 一第一溝槽開孔穿越位在該第三介電層之間距分隔長條 間的該第一及第二介電層而形成。一第二溝槽開孔穿越伋 在該第三介電層之間距分隔長條之間的該第一介電層而與 該第一溝槽開孔相鄰地形成。導體金屬,諸如鋁或^經^ 積於該溝槽開孔内以形成自我對準的溝槽内連線。此自^ 對準的圖案化(p a 11 e r n i n g)技術達到避免對準失調與加強 該内連線之實行能力之自我對準的内連接。The problem of accidentally magnifying the through-holes of the spoiled money in the cleaning solution at a later time will be magnified. via chain) generation -via) overlap and suffering, j l caused by misalignment is a long-term pursuit, but the same as the way to solve these problems has long puzzled those who are familiar with this technique. [Disclosure of Invention] The present invention provides an integrated circuit and a method for manufacturing the integrated circuit. The integrated circuit has a first dielectric layer formed on a substrate. A second dielectric layer on top of the first dielectric layer. A third dielectric layer is formed on the second dielectric layer in spaced-apart strips. A first trench opening is formed through the first and second dielectric layers located between the third dielectric layer and the separating strip. A second trench opening is formed adjacent to the first trench opening through the first dielectric layer between the third dielectric layer and the spaced apart strip. A conductive metal, such as aluminum or aluminum, is accumulated in the trench opening to form a self-aligned trench interconnect. This self-aligned patterning (p a 11 e r n i n g) technique achieves a self-aligned interconnect that avoids misalignment and enhances the ability of the interconnect to perform.
從下列詳細描述之閱讀並結合隨附之圖式,對於熟習 變得顯 543147 五、發明說明(3) 而易見。 [實施本發明之最佳模式] 參考第1圖’該圖顯示依據本發明之部分積體電路在 製造的中間階段之視圖。積體電路内連線丨0建立在基底i 2 上’該基底可以疋半導體基板、用於絕緣體碎 一 (silicon-on-insulator,SOI)構造之矽、介電層、擋止 層或其它導線、通孔或接觸器。該其它導線 '通孔或接觸 器將連接至位於半導體基板、絕緣體矽、介電層或擋止層 之上、之内或之下方的半導體裝置。在本發明中^ 一 ^ 電層14已經沉積在位於該基底12上方之初始擋止層15上。 該介電層於此可以是諸如氧化矽、氮化矽或具有介電常數 約3 · 9以下之低介電常數的材料。 第一擋止層16也已經沉積在該第一介電層η之上並且 第二介電層18也已經沉積在該第一擋止層16上方。該專有 名詞π擔止層”於此使用是作為方便之考量,因為此声通當 用於終止各種蚀刻製程,雖然並非必須執行此項功^。該 擋止層可以是諸如氧化矽或氮化矽之材料。 於此使用之術語Η水平的(h 〇 r i ζ ο n t a 1)π是定義平行於 晶圓之習知的平面或表面,諸如該基底丨2,而不管該晶圓 之方向。術語”垂直的(vert i cai)”意指垂直於剛定義之水 平面之方向。術語,諸如”在…之上(〇n)”、”在…上 (above)”、”在…下面(below)”、”側面(side)(如同侧壁 (sidewall))”、”較高的(hi gher)”、”較低的(1〇wer)”、,, 在表面上(over)及在…之下(un(jer)”,是依據該水平平From the following detailed description, combined with the accompanying drawings, it will become apparent to familiarity. 543147 Description of the invention (3) is easy to see. [Best Mode for Carrying Out the Invention] Referring to FIG. 1 ', this figure shows a view of a part of the integrated circuit according to the present invention at an intermediate stage of manufacturing. Integrated circuit interconnects are established on the substrate i 2 'The substrate can be a semiconductor substrate, silicon, dielectric layer, barrier layer or other wires used for silicon-on-insulator (SOI) construction , Through-hole or contactor. The other wire 'through-hole or contactor will be connected to a semiconductor device on, in, or below a semiconductor substrate, insulator silicon, dielectric or barrier layer. In the present invention, the electrical layer 14 has been deposited on the initial blocking layer 15 above the substrate 12. The dielectric layer may be a material having a low dielectric constant such as silicon oxide, silicon nitride, or a dielectric constant of about 3.9 or less. A first blocking layer 16 has also been deposited on the first dielectric layer n and a second dielectric layer 18 has also been deposited on the first blocking layer 16. The proper term "π stop layer" is used here as a convenient consideration, because this sound is used to terminate various etching processes, although it is not necessary to perform this function ^. The stop layer can be, for example, silicon oxide or nitrogen Silicon material. The term Η horizontal (h 〇 ri ζ ο nta 1) π is used to define a conventional plane or surface parallel to the wafer, such as the substrate 2, regardless of the orientation of the wafer. The term "vert i cai" means a direction perpendicular to the horizontal plane just defined. Terms such as "above (0n)", "above", "below ( below "", "side (like sidewall)", "higher (her gher)", "lower (1〇wer)", on, and on the surface (over) "Under (un (jer)" "is based on the horizontal level
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面來定義。 參 二擋止 主要使 後續的 參 槽光罩 部分該 參 由通孔 層2 4及 之大體 解,可 可以任 圓形的 考第2圖,該圖顯示第1圖 層22之沉積構造。該保護 用具低介電常數之介電材 光阻之沉積所污染。 考第3圖,該圖顯示第2圖 之圖案化及進行移除部分 保護介電層2〇後之構造。 考第4圖,該圖顯示第3圖 光f圖案化之均勻光阻層 該第二擋止層22經聯合以 上矩开》的區域。對於熟習 以是該保護的介電層20或 何需要的形狀曝露出來, 、方形的或其它形狀。 具有保護的介電層20及第 介電層2〇為選擇性的並且 料以避免該介電材料受到 在該第二擋止層22使用溝 該第二擋止層22並曝露出 在沉積、圖案化及處理藉 2 4後之構造。該均勻光阻 曝露出該保護的介電層2〇 此項技藝之人士將會瞭 該第二介電層18之介電層 以便該最後的通孔可以是 、參考第5圖,該圖顯示第4圖經過非等向性蝕刻以形成 通孔26及28之構造。該通孔26及28經蝕刻而穿越該保護的 介電層20:該第二介電層18而到達該第一擋止層16。 參考第6圖’該圖顯示第5圖在該均勻光阻層24之移除 後之構邊以預備該内連接導線之形成。 1 6及選擇性蝕刻該第二擋止層2 2後之構造。 參考第7圖’該圖顯示第6圖在藉由該保護的介電層2〇 之非等命性餘刻後之構造以曝露出該第二介電層1 8。 參考第8圖’該圖顯示第7圖在蝕刻穿越該第一擋止層To define. The second stop is mainly used to make the subsequent part of the mask groove partially understandable by the through-hole layers 24 and 4, but it can be any circular shape. Consider the second figure, which shows the layer 22's deposition structure. The protective device was contaminated by the deposition of the photoresist of a low-k dielectric material. Consider Fig. 3, which shows the patterning and removal of the protective dielectric layer 20 after the patterning of Fig. 2. Consider FIG. 4, which shows the uniform photoresist layer patterned by the light f in FIG. 3. The second blocking layer 22 is opened by combining the above moments. The dielectric layer 20, which is familiar with the protection, or any desired shape is exposed, square, or other shapes. The protected dielectric layer 20 and the second dielectric layer 20 are selective and are required to prevent the dielectric material from being exposed to the second barrier layer 22 using the trench and the second barrier layer 22 and exposed to the deposition, Patterning and processing the structure after borrowing 24. The uniform photoresist exposes the protected dielectric layer 20. Those skilled in the art will have the dielectric layer of the second dielectric layer 18 so that the final via can be, refer to Figure 5, which shows that FIG. 4 illustrates a structure in which through holes 26 and 28 are formed by anisotropic etching. The through holes 26 and 28 are etched to pass through the protected dielectric layer 20: the second dielectric layer 18 and reach the first blocking layer 16. Referring to Fig. 6 ', this figure shows the edge formation of Fig. 5 after the uniform photoresist layer 24 is removed in preparation for the formation of the interconnecting wires. 16 and the structure after the second blocking layer 22 is selectively etched. Referring to Fig. 7 ', this figure shows the structure of Fig. 6 after the non-equivalence of the protected dielectric layer 20 is left to expose the second dielectric layer 18. Referring to FIG. 8 ’, the figure shows that FIG. 7 etched through the first blocking layer during etching.
92086.ptd 第9頁 543147 五、發明說明(5) 參考第9圖,該圖顯示第8圖在藉由非等向性蝕刻之移 除該曝露出的第二介電層18而到達該第一擋止層16及該第 一介電層14而到達該初始擋止層15之構造。此步驟形成該 内連接導線開孔3 0及3 2,該開孔3 0及3 2分別精確地與通孔 開孔26及28相交使得在第一介電層14及該第二介電層18之 間之該相鄰的開孔之寬度是完全地相同並自我對準。 參考第10圖,該圖顯示第9圖在蝕刻該第一擋止層16 及該初始擔止層15之構造。該初始播止層之餘刻是為了連 接至該積體電路之其它構造,諸如半導體電晶體或其它組 件(未顯示)。 參考第11圖,該圖顯示依據本發明之該完成的内連線 1 0。藉由該通孔開孔2 6及2 8以及該内連接導線開孔3 〇及 32(參閱第10圖)分別由導體金屬34及36所填覆,通孔38及 40分別與内連接導線42及44形成無滾邊的内連線。需瞭解 的是各種導體金屬包含鋁及銅皆可使用。但使用銅則必須 先沉積擴散阻障層。 ' 因為該通孔階層及該内連線層是在同時間形成,此形 成的方式將描述為雙鑲嵌(Dual iniaid)或雙層嵌入(Dual damascene)技術的無滾邊内連線。 參考第1 2圖,該圖顯示内連線5 〇在製造之中間階段中 之另一種實施例。在第12圖中,如第1至3圖所顯示之相同 步驟已經完成。基底52具有初始擋止層53及第一介電層54 沉積在其上面。第一擋止層56沉積在該第一介電層54上面 並且第二介電層58沉積在該第一擋止層56上。當保護介電92086.ptd Page 9 543147 V. Description of the invention (5) Reference is made to Figure 9, which shows that Figure 8 reaches the first dielectric layer 18 by removing the exposed second dielectric layer 18 by anisotropic etching. A blocking layer 16 and the first dielectric layer 14 reach the initial blocking layer 15. This step forms the inner connecting wire openings 30 and 32. The openings 30 and 32 accurately intersect the through-hole openings 26 and 28 respectively so that the first dielectric layer 14 and the second dielectric layer are intersected. The widths of the adjacent openings between 18 are exactly the same and self-aligned. Referring to FIG. 10, which shows the structure of FIG. 9 in which the first stop layer 16 and the initial stop layer 15 are etched. The initial stop layer is left to connect to other structures of the integrated circuit, such as a semiconductor transistor or other components (not shown). Reference is made to Fig. 11, which shows the completed internal connection line 10 according to the present invention. The through-hole openings 26 and 28 and the interconnecting conductor openings 3 0 and 32 (see FIG. 10) are filled with conductor metals 34 and 36, respectively, and the through-holes 38 and 40 are connected to the interconnecting wires, respectively. 42 and 44 form an inner line without piping. It should be understood that various conductor metals including aluminum and copper can be used. However, the use of copper requires the deposition of a diffusion barrier. '' Because the via hole layer and the interconnect layer are formed at the same time, the formation method will be described as a dual inlay (Dual iniaid) or a dual damascene (Dual damascene) technology without piping. Reference is made to Figure 12, which shows another embodiment of the interconnect 50 in the intermediate stage of manufacture. In Figure 12, the same steps as shown in Figures 1 to 3 have been completed. The substrate 52 has an initial blocking layer 53 and a first dielectric layer 54 deposited thereon. A first barrier layer 56 is deposited on the first dielectric layer 54 and a second dielectric layer 58 is deposited on the first barrier layer 56. When protecting the dielectric
92086.ptd 第10頁 543147 五、發明說明(6) 層60為低介電常數之介電 二介電層58上面。 第二擋止層62已經沉 積在該第二擋止層62上面 6 2及該光阻層6 4經聯合以 護介電層6 0上面。在此形 連接5 0之中心。 參考第13圖,該圖顯 向性餘後之構造。該深溝 介電層60、該第二介電層 電層54,而到達該初始擋 參考第14圖,該圖顯 介電層60之移除後之構造 介電層5 4之非等向性蝕刻 達該第一播止層56及初始 56及該初始擋止層53也已 確地形成分別與該深溝槽 導線開孔70及72,使得在 5 8之間之該相鄰的開孔之 參考第15圖,該圖顯 積後之構造,該導體金屬 及84所連接之深溝槽几至 是雙鑲嵌或雙層嵌入技術 參考第16圖,該圖顯 材料時,係選擇性地沉積在該第 積及圖案化並 及進行處理, 曝露出通孔或 狀中,該光阻 且光阻層6 4已經沉 以便該第二播止層 深溝槽區域在該保 層64重疊覆蓋該内 示第1 2圖在深 槽6 6到6 9經餘 溝槽6 6到6 9之非等 刻而穿越該保護的 58、該第一擋止層56及該第一介 止層53。 不第1 3圖在該 。藉由該第二 之移除製程已 擔止層53。接 經藉由非等向 66至67及68至 該第一介電層 寬度完全相同 示第14圖在導 74及76將形成 81。該内連線 的無滾邊内連 示又一種實施 光阻層 介電層 經執行 著,該 性蝕刻 69相交 54及該 並且自 體金屬 分別藉 50之完 線。例,其 6 4及該保護 58及該第一 而分別地到 第一擋止層 移除以便精 之該内連接 第二介電層 我對準。 74及76之沉 由淺溝槽82 整的構造將 中第13圖之92086.ptd Page 10 543147 V. Description of the invention (6) The layer 60 is on top of the second dielectric layer 58 with a low dielectric constant. The second blocking layer 62 has been deposited on the second blocking layer 62 and the photoresist layer 64 is combined to protect the dielectric layer 60. Connect the center of 50 in this shape. Refer to Figure 13 for the remainder of the structure. The deep trench dielectric layer 60 and the second dielectric layer electrical layer 54 reach the initial barrier with reference to FIG. 14, which shows the anisotropy of the structured dielectric layer 54 after the dielectric layer 60 is removed. The first stop layer 56 and the initial 56 and the initial stop layer 53 have been etched to form the deep trench wire openings 70 and 72, respectively, so that the adjacent openings between 5 and 8 Refer to Figure 15, which shows the structure after the accumulation. The conductive metal and the deep grooves connected to 84 are double-inlaid or double-embedded. Refer to Figure 16, which shows that the material is selectively deposited on the material. The first product is patterned and processed, exposing the through hole or state, the photoresist and photoresist layer 64 have been sunk so that the deep groove region of the second stop layer overlaps the cover layer 64 to cover the inner display Figure 1 2 passes through the protection 58, the first blocking layer 56 and the first blocking layer 53 at the deep grooves 66 to 69 through the unequal cuts of the remaining grooves 66 to 69. No. 1 3 in the picture. The layer 53 has been stopped by the second removal process. Then through the anisotropy 66 to 67 and 68 to the first dielectric layer, the width is exactly the same, as shown in FIG. 14 where 81 and 74 will be formed. The inner edge of the non-rolled inner interconnection shows another implementation of a photoresist layer and a dielectric layer. The etching 69 intersects 54 and the self metal is borrowed from 50 to complete the wiring. For example, its 64 and the protection 58 and the first are respectively removed to the first barrier layer so as to precisely align the second dielectric layer. The structure of 74 and 76 is formed by the shallow trench 82.
92086.ptd92086.ptd
第11頁 543147 五、發明說明(7) 構造具有附加的介電層在其上面,該附加的介電層以習知 的方式圖案化及進行處理以形成介電間隔物2 3、2 5、2 7及 2 9 °對於熟習此項技藝之人士將顯而易見的是,此間隔物 將相容於在此先前描述的構造製造以形成滾邊結構,其中 導電金屬之較上方層較大於導電金屬之較下方層,以便當 該自我對準特性欲維持時,藉由該間隔物之寬度該内連接 導線將比該通孔之寬度還要寬。 參考第17圖’該圖顯示沿著第n圖截線17_17之雙鑲 後或雙層嵌入技術的無滾邊内連線1 〇 〇之橫面圖,用以明 確表示通道34之無滾邊通孔38及通道36之無滾邊通孔4〇。 參考第18圖,該圖顯示沿第16圖完成體之截線18_18 之雙鑲嵌或雙層嵌入技術的滾邊内連接11〇之橫面圖,用 以明確表示較小於通道34之通孔38,及較小於通道36之通 孔40 。該介電間隔物23、25、27及29經使用於蝕刻該通 孔38及40’並且接著將該間隔物移除。接著在未使用該介 電間隔物23、25、27及29下蝕刻該通道34及36,因此該通 道將寬於該通孔之寬度。 ^ 當本發明結合特定最佳的模式而描述後,需要瞭解的 是很多的替代、修改及變換對於熟習此項技藝之人士而言 在依據前文之描述後將會變得顯而易見。因此,含括此類 的替代、修改及變換均包含在申請專利範圍之精神與範疇 ^二在此之前於本文所提出或在隨附的圖式所顯示^内容 應虽視為說明及非限定之意涵。Page 11 543147 V. Description of the invention (7) Structure with additional dielectric layer on it, the additional dielectric layer is patterned and processed in a conventional manner to form a dielectric spacer 2 3, 2 5, 2 7 and 2 9 ° It will be apparent to those skilled in the art that this spacer will be compatible with the construction described previously to form a piping structure, where the conductive metal is larger than the upper layer than the conductive metal. The lower layer, so that when the self-alignment characteristic is to be maintained, the interconnecting wire will be wider than the width of the through hole by the width of the spacer. Refer to Figure 17 'This figure shows a cross-section view of the 100-degree non-piping through-line of the double-posted or double-embedded technology along the n-th section of the line 17_17. 38 and channel 36 without piping through holes 40. Referring to Figure 18, this figure shows a cross-section view of the internal connection 11 of the double-inlay or double-embedding technology along the section line 18_18 of the completed body in Figure 16 to clearly indicate the through hole 38 smaller than the channel 34 And smaller than the through hole 40 of the channel 36. The dielectric spacers 23, 25, 27, and 29 are used to etch the through holes 38 and 40 'and then remove the spacers. The channels 34 and 36 are then etched without using the dielectric spacers 23, 25, 27, and 29, so the channel will be wider than the width of the via. ^ When the present invention is described in conjunction with a specific best mode, it should be understood that many substitutions, modifications, and alterations will become apparent to those skilled in the art after following the description above. Therefore, the inclusion of such substitutions, modifications and transformations are included in the spirit and scope of the scope of patent application ^ 2 previously proposed in this article or shown in the accompanying drawings ^ contents should be regarded as illustrative and non-limiting Meaning.
543147 圖式簡單說明 [圖式之簡單說明] 第1圖為依據本發明之部分積體電路在製造的中間階 段之視圖; 第2圖為第1圖在沉積保護的介電層及第二擋止層 (stop layer)後之構造; 第3圖為第2圖在使用溝槽光罩來圖案化該第二擋止層 及移除部分該第二擋止層以曝露出部分該第二介電層後之 構造; 第4圖為第3圖在使用通孔光罩來沉積、圖案化及處理 光阻層後之構造; 第5圖為第4圖在蝕刻以形成通孔初期後之構造; 第6圖為第5圖在移除該光阻層後之構造; 第7圖為第6圖在移除該保護的介電層以曝露出該第二 介電層之構造; 第8圖為第7圖在蝕刻穿越該第一擋止層及選擇性蝕刻 該第二擋止層後之構造; 第9圖為第8圖在移除該第二介電層到達該第一擋止層 及移除該第一介電層到達初始擔止層而形成該内連接導線 開孔和該通孔開孔相交之構造; 第10圖為第9圖在蝕刻該第一擋止層及初始擋止層後 之構造; 第11圖為依據本發明之完整的内連線; 第1 2圖為内連線在製造的中間階段之另一項實施例之 視圖,543147 Brief description of the drawings [Simplified description of the drawings] FIG. 1 is a view of a part of the integrated circuit according to the present invention in the middle stage of manufacturing; The structure behind the stop layer; Figure 3 is Figure 2. Figure 2 uses a trench mask to pattern the second stop layer and remove a portion of the second stop layer to expose a portion of the second interface. Structure after electrical layer; Figure 4 is the structure of Figure 3 after the photoresist layer is deposited, patterned, and processed using a via mask; Figure 5 is the structure of Figure 4 after the initial stage of etching to form a via Figure 6 is the structure of Figure 5 after removing the photoresist layer; Figure 7 is the structure of Figure 6 after removing the protected dielectric layer to expose the second dielectric layer; Figure 8 FIG. 7 is a structure after etching through the first blocking layer and selectively etching the second blocking layer; FIG. 9 is FIG. 8 illustrating removing the second dielectric layer and reaching the first blocking layer in FIG. 8 And removing the first dielectric layer to reach the initial supporting layer to form a structure where the opening of the interconnecting wire intersects with the opening of the through hole; FIG. 10 is the etching of FIG. 9 The structure after the first barrier layer and the initial barrier layer; FIG. 11 is a complete interconnection line according to the present invention; and FIG. 12 is a view of another embodiment of the interconnection line in the middle stage of manufacturing ,
92086.ptd 第13頁 543147 圖式簡單說明 第1 3圖為第1 2圖在做深溝槽蝕刻後之構造; 第1 4圖為第1 3圖在形成該内連接導線開孔和深溝槽相 父後之構造, 第15圖為第14圖在沉積導體金屬以形成該内連接導線 和通孔相交之構造; 第1 6圖為第3圖在本發明之又一項實施例中以額外的 介電層沉積於該構造上之附加修改以形成間隔物 (spacer),· 第" ,圖 為 第 11 圖 沿 著截 線1 7 -17之橫 面圖;以 第1S )S3 >圃 為 第 16 圖 沿 著截 線1 8 -18 之橫 面圖。 [元件符號說明] 10 積體 電 路 内 連 線 12 > 52 基 底 14、 54 第 _ I 介 電 層 15 ^ 53 初 始播止層 16 ^ 56 第 _一 擋 止 層 17- 17 ^ 1 8 ~ 18截線 18 ^ 58 第 介 電 層 20 介 電保 護層 11、 62 第 二 擋 止 層 23 > 25 > 27 、29 介· 24、 64 光 阻 層 26 > 28 > 38 38 •40 ’ 、40, 通 孔 30 > 32 開 孔 34、 36 導 體金屬 42 ^ 44 内 連 接 導 線 50 内 連線 60 保護 介 電 層 66 > 67 > 68 69 78 79 ^ 80 > 81 深溝 槽 70 ^ 72 開 孔 82、 84 淺 溝槽 100 雙鑲 散 或 雙 層 嵌 入 技術 的無 滚邊内連線92086.ptd Page 13 543147 Brief description of the drawings Figure 13 shows the structure of Figure 12 after deep trench etching; Figure 14 shows the structure of the internal connection wire opening and deep groove phase in Figure 13 The structure of the father, FIG. 15 is the structure of FIG. 14 where the conductive metal is deposited to form the interconnection wire and the through hole; FIG. 16 is the illustration of FIG. 3 in another embodiment of the present invention. An additional modification of the dielectric layer deposited on the structure to form a spacer is shown in Figure 11 as a cross-sectional view of Figure 11 along the section line 1 7 -17; Figure 1S) S3 > It is a cross-sectional view of Fig. 16 along the section line 1 8 -18. [Explanation of component symbols] 10 Integrated circuit interconnect 12 > 52 Substrate 14, 54 First _ I dielectric layer 15 ^ 53 Initial stop layer 16 ^ 56 First stop layer 17- 17 ^ 1 8 ~ 18 Section 18 ^ 58 Dielectric layer 20 Dielectric protection layer 11, 62 Second barrier layer 23 > 25 > 27, 29 Di 24, 64 Photoresist layer 26 > 28 > 38 38 40 , 40, through hole 30 > 32 opening 34, 36 conductor metal 42 ^ 44 inner connecting wire 50 inner wiring 60 protective dielectric layer 66 > 67 > 68 69 78 79 ^ 80 > 81 deep trench 70 ^ 72 Openings 82, 84 Shallow grooves 100 Double-bump or double-embedded technology without piping
92086.ptd 第14頁 54314792086.ptd Page 14 543147
92086.ptd 第15頁92086.ptd Page 15
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