JP5792918B2 - 高集積メモリデバイス - Google Patents
高集積メモリデバイス Download PDFInfo
- Publication number
- JP5792918B2 JP5792918B2 JP2002520307A JP2002520307A JP5792918B2 JP 5792918 B2 JP5792918 B2 JP 5792918B2 JP 2002520307 A JP2002520307 A JP 2002520307A JP 2002520307 A JP2002520307 A JP 2002520307A JP 5792918 B2 JP5792918 B2 JP 5792918B2
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- charge storage
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- vertical semiconductor
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Classifications
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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Description
本出願は、2001年3月6日付けで出願された米国特許出願第09/801,233号の一部継続出願であり、この出願は、2000年12月21日付けで出願された米国特許出願第09/745,125号の一部継続出願であり、これら両方の特許出願は一体のものとしてここに統合される。本出願は、同様に、2000年8月14日付けで出願された米国特許出願第09/639,579号の一部継続出願であり、この特許出願は一体のものとしてここに統合される。本出願は、同様に、2000年8月14日付けで出願された米国特許出願第09/639,702号の一部継続出願であり、この特許出願は一体のものとしてここに統合される。本出願は、同様に、2000年8月17日付けで出願された米国特許出願第09/639,749号の一部継続出願であり、この特許出願は一体のものとしてここに統合される。さらに本出願は、2001年3月28日付けで出願された仮米国特許出願60/279,855号の優先権を主張し、この仮特許出願は一体のものとしてここに統合される。
1.発明の分野
本発明は、一般に、半導体デバイスに関し、とりわけ3次元TFTアレイに関する。
集積回路およびコンピュータの機能が向上するにつれ、大容量のデータを記憶する機能を必要とする新しいアプリケーションが開発されている。データを書きこみ、消去できる機能、およびデータを揮発させないように記憶する機能を有するメモリを必要とするアプリケーションもある。1メガバイト当たりの半導体メモリの価格を1(US)ドルよりも安価にすることにより、利用可能なアプリケーションが数多くある。例えば、(1)写真画像を記録するための化学的フィルム、(2)配布用の音楽データおよびテキストデータを記録するためのコンパクトディスク(CD)、(3)配布用のビデオデータおよびマルチメディアデータを記録するためのデジタル多用途ディスク(DVD)、および(4)視聴者がオーディオおよびビデオデータを記録するためのデジタルオーディオテープおよびビデオテープなどが挙げられる。こうしたメモリは、不揮発性であって、アーカイブに収容され、その中に記録された情報を実質的に全く破壊されないように維持しながら、約10年以上の期間、本体装置およびすべての電源から取り外しておくことができる。こうした要請は、CD、DVD、磁気テープ、およびほとんどの形態の写真用フィルムが長期間に亙ってデータ保持することに対応している。
本発明の好適な実施形態によれば、複数のデバイス階層を含む電荷記憶デバイスのモノリシック3次元アレイを有する半導体デバイスであって、2つの連続するデバイス階層間の少なくとも1つの面が、化学機械的な研磨により平坦化される半導体デバイスを提供することができる。
本発明者は、メモリデバイスおよび論理デバイスの集積度が向上すれば、これらのデバイスの価格が低減するという認識を有していた。そして本発明者により、高い集積度を有し、安価である電荷記憶半導体デバイスの超高密度マトリックスアレイが提供された。
この実施形態は、柱状構造物として(すなわち、基板に対して垂直方向に)構成される(このとき、デバイスの長さは基板に対して垂直方向にある。)薄膜トランジスタ(TFT)および薄膜トランジスタ、およびその製造方法に関する。好適には、この柱状デバイスは、垂直方向の読み出し電流を有する電荷捕獲メモリを構成する。このメモリは、基板平面の直ぐ上または上方に形成された第1の入力/出力導電体と、第1の入力/出力導電体から離間し、その上方に配置された第2の入力/出力導電体とを有する。第1および第2の入力/出力導電体は、重なり合うか、互いに交差し、好適には、互いに垂直に交差するように配置される。ドープされたシリコン領域などの半導体領域は、第1および第2の入力/出力導電体が交差するところで、第1および第2の入力/出力導電体の間に形成される。これに限定しないが、電荷捕獲誘電体などの電荷記憶媒体は、この半導体領域付近において形成され、第1および第2の入力/出力導電体の間に印加された所定の電圧に関連して、第1および第2の入力/出力導電体の間にある半導体領域を流れる電流量に影響を与える。1つの電圧に対して、この半導体領域を流れる電流量(読み出し電流量)を用いて、電荷が電荷記憶媒体に蓄積されたかどうか、すなわちメモリが書き込まれたか、消去されたかを判断することができる。第1および第2の入力/出力導電体の間にある半導体領域を流れる読み出し電流は、基板平面とは垂直な方向に流れる。メモリは、この基板の内部またはその上に形成される。この実施形態の電荷捕獲メモリの構造物、およびその製造方法は、3次元アレイのメモリデバイスに集積化する上で理想的に適したものである。
本発明の実施形態は、3端子不揮発性積層可能柱状メモリデバイスである。本発明のこの実施形態による柱状メモリデバイス100は、図1Aを用いて大まかに図示されている。柱状メモリデバイス100は、第1の入力/出力導電体(I/O)103の上に形成された第1のコンタクト領域102を有する。第1の入力/出力導電体(I/O)103は、単結晶基板101のx−y平面の直ぐ上またはその上方に形成されている。半導体本体部104が第1のコンタクト領域102上に直接的に形成され、第2のコンタクト領域106が半導体本体部104上に直接的に形成される。第2の入力/出力導電体(I/O)116が第2のコンタクト領域106上に形成される。第1のコンタクト領域102、半導体本体部104、および第2のコンタクト(ソース/ドレイン)領域106は、柱状物108を形成するように垂直方向において互いに位置合わせされる。半導体本体部104に隣接し、接触しているのが、電荷記憶媒体110である。制御ゲート112は、電荷記憶媒体110に隣接し、これと直接的に接触するように形成されている。制御ゲート112および電荷記憶媒体110は、柱状物108と電気的に通信できるように、柱状物108に対して水平方向に隣接するように構成されている。電荷記憶媒体110は、制御ゲート112とこれに接続されるチャンネル領域を電気的に遮断する領域である。
図29Aにおいて、このセルは、ダイオードと、領域2921、2922、および2923を含む積層物とを有する。これらの領域の間には、電荷を捕獲するために用いられる記憶領域が配置されている。電荷を保持することで、セルの「メモリ」機能を果たすめは、主にこの領域である。以下に説明するように、電荷を、この領域2922の中に電気的に配置し、電気的に検出し、この領域2922から排除することができる。
図30を参照すると、本発明の第1の実施形態によるメモリセルは、p型基板2930内に配置されるように図示されている。ダイオード(セルの支配因子)は、基板内に形成され、例えば5×1016ないし1×1018原子数/cm3の不純物濃度でドープされたn−領域2932と、n−領域2932内に形成され、1×1019原子数/cm3未満の不純物濃度でドープされたP+領域2931とを有する。これらの領域は、拡散法またはイオン注入法などの広く知られた方法を用いて形成することができる。
図31において、このセルは、ソース領域、ドレイン領域、およびゲート2946を有する電界効果型トランジスタを採用している。領域2941および2942は、基板2940内において、ゲート2946に対して位置合わせされている。酸化領域2943、トラップ領域2944、および酸化領域2945を含む積層物が領域2941上に形成されている。領域2943、2944、および2945は、図30に示す領域2943、2944、および2945と同じものであってもよい。
本出願の譲受人に譲渡された、「3次元メモリアレイの製造方法」と題する2000年4月28日付けで出願された米国特許出願第09/560,626号、および2001年3月21日付けで出願された同時係属中の一部継続出願第09/814,727号において、レール積層物を有し、基板上に形成された3次元メモリアレイが開示されている。この特許出願に開示された技術を用いて、本発明のこの実施形態による3次元の電荷捕獲または電荷記憶メモリを製造することができる。
米国特許第6,034,882号において、平行で、離間した導電層を有する複数の階層を有する3次元メモリアレイが開示されている。交互階層における導電層は、互いに直交する。柱状構造物は、隣接する階層内にある導電層の交差点に形成される。この特許で開示されている構造物は、導電層に対して位置合わせされるように形成されている。この特許で開示される製造方法を用いて、この実施形態の電荷記憶領域または電荷捕獲領域を有するセルを採用したメモリセルアレイを形成することができる。
柱状構造物とは異なる別のセル構造物が自己整合TFTである。本発明者は、メモリセルまたは論理セルが、異なる層上の特徴形状が完全に重なり合うように設定される不良位置合わせ公差により拡大することを認識していた。つまり、本発明者は、不良位置合わせ公差を必要としない完全に位置合わせされたメモリセルまたは論理セルを開発した。したがって、こうしたセル構造体において、1ビット当たり(すなわち、1セル当たり)の面積がより小さく、より少ないマスクステップにより形成される。完全に位置合わせされたセル構造体により、アレイ集積度を向上させ、ダイサイズを小さくし、コストを下げる。さらに、随意であるが、セルを垂直方向、つまりz方向に積層することにより、アレイ集積度をさらに向上させて、ダイサイズをさらに小さくし、さらにコストを下げる。
以下の好適な実施形態によれば、レール積層構造内に形成されたEEPROMのTFTなどの電荷記憶領域を有するTFTアレイが提供される。ここに開示される実施形態は、不揮発性の再プログラム可能な半導体メモリと、製造方法および使用方法に関連している。当業者ならば理解されるように、本発明の以下に詳述する実施形態は、単に例示的なものであって、いかようにも限定しない。この開示内容を見た当業者に対し、本発明の他の実施形態を容易に示唆することであろう。添付図面に示された本発明の手段に関して、ここで詳細に説明する。図面全体および以下の詳細な説明を通じて、同様または類似の構成部品に関して、同様の参照符号を用いる。
先の実施形態においては、TFTは仮想グランドアレイ(VGA)として構成された。先の実施形態に図示されたVGAにおいて、各EEPROMのプログラムは、ホットキャリアを注入することにより行われる。ホットキャリアの注入時、ダイオードの両端(TFT EEPROMのソースおよびドレイン間)に電圧が印加される。TFT EEPROMのソースからチャンネルを通ってドレインへ移動するホットキャリア(つまり、ホットエレクトロンおよびホットホール)は、チャンネルに隣接して形成される電荷記憶領域内に注入される。この処理は、比較的に高い電力を要する。
NMOSデバイスまたはPMOSデバイスのアレイに関し、先の実施形態で説明された。しかし、本発明の別の好適な実施形態において、CMOS(相補型金属酸化膜半導体)トランジスタのアレイが提供される。好適には、隣接するNMOSトランジスタおよびPMOSトランジスタは、共通ゲートを有する。しかし、必要ならば、隣接するNMOSトランジスタおよびPMOSトランジスタは、個別のゲートを有してもよい。CMOSデバイスのアレイは、先の実施形態で開示したように、垂直方向の柱状CMOSデバイスのアレイ、自己整合されたCMOS TFTのアレイ、またはレール積層物のTFTアレイであってもよい。CMOSデバイスは、好適には、基板の上方にある3次元のモノリシックアレイとして構成される。しかし、CMOSデバイスは、必要ならば、基板の中または上方に2次元アレイとして構成することができる。
本発明の好適な実施形態は、基板上に構成された不揮発性の薄膜トランジスタ(TFT)のメモリデバイスまたは論理デバイスに関する。このデバイスは、ソース領域、ドレイン領域、および遷移金属誘導による水平方向の結晶化(MILC)プロセスを用いて結晶化された、積層または成膜アモルファスシリコンまたはポリシリコンからなるチャンネル領域を有する。2次元、または好適には、それ以上3次元の多数回プログラム可能な(MTP)不揮発性メモリまたはロジックは、こうした薄膜トランジスタメモリデバイスから構成される。
これまで説明したさまざまな実施形態において、金属シリサイド層は、ポリシリコンのワードラインまたはビットラインなどのシリコン層と接触するように形成された。シリコン層と接触するチタンシリサイドを形成する1つの好適な方法において、シリコンキャップとTiN層を用いた。チタンシリサイド層は、ドープされないアモルファスシリコンのキャップ層上に形成される。このキャップ層は、1019cm−3を超える濃度、例えば、1019cm−3ないし1021cm−3の濃度でドープされたポリシリコンまたはアモルファスシリコンなどの高濃度で不純物ドープされたシリコン層で構成される。このキャップ層は、好適には、p+ポリシリコン層またはn+ポリシリコン層の上に積層される。n+アモルファスシリコンは、後のアニールステップの間に、n+ポリシリコン層に再結晶化スることができる。
101.単結晶基板
102.第1のコンタクト領域
103.第1の入力/出力導電体(ソース/ドレイン導電体)
104.半導体本体部
106.第2のコンタクト領域
108.柱状物
110.電荷記憶媒体
112.制御ゲート
116.第2の入力/出力導電体(ソース/ドレイン導電体)
Claims (13)
- メモリデバイスであって、
基板と、
前記基板の上面に形成された第1の入力/出力導電層と、
前記第1の入力/出力導電層の上に配置された第1の垂直な半導体チャンネルと、
前記第1の垂直な半導体チャンネルの下面及び上面で、前記第1の垂直な半導体チャンネルとそれぞれ接触する第1および第2のソース/ドレインコンタクト領域と、
前記第2のソース/ドレインコンタクト領域の上面に形成された第2の入力/出力導電層と、
前記第2の入力/出力導電層の上に配置された第2の垂直な半導体チャンネルと、
前記第2の垂直な半導体チャンネルの下面及び上面で、前記第2の垂直な半導体チャンネルとそれぞれ接触する第3および第4のソース/ドレインコンタクト領域と、
前記第4のソース/ドレインコンタクト領域の上面に形成された第3の入力/出力導電層と、を有し、
前記第1の垂直な半導体チャンネルと、第1および第2のソース/ドレインコンタクト領域は、第1のデバイス階層にある第1の柱状物であり、前記第2の垂直な半導体チャンネルと、第3および第4のソース/ドレインコンタクト領域は、第2のデバイス階層にある第2の柱状物であり、さらに、
前記第1のデバイス階層にあり、前記第1の柱状物の第1面の第1部分に隣接して配置された第1の電荷記憶媒体と、
前記第1のデバイス階層に配置され、前記第1の電荷記憶媒体に隣接して配置された第1の制御ゲートと、
前記第1のデバイス階層および第2のデバイス階層にあり、前記第1の柱状物の前記第1面と直交する方向の第2面の第2部分に隣接して配置され、かつ前記第1の柱状物の前記第2面の前記第2部分の上方にある前記第2の柱状物の第2面の第2部分に隣接して配置された第2の電荷記憶媒体と、
前記第1のデバイス階層および前記第2のデバイス階層に配置され、前記第2の電荷記憶媒体に隣接して配置された第2の制御ゲートと、
前記第2のデバイス階層に配置された部分を少なくとも有し、前記第1の柱状物の前記第1面の前記第1部分の上方にある前記第2の柱状物の前記第2面と直交する方向の第1面の第1部分に隣接して配置された第3の電荷記憶媒体と、
前記第2のデバイス階層に配置された部分を少なくとも有し、前記第3の電荷記憶媒体に隣接して配置された第3の制御ゲートと、を有し、
前記第1の電荷記憶媒体は、前記第1の制御ゲートよりも前記第1の垂直な半導体チャンネルの近くに配置された第1のトンネル誘電膜を有し、
前記第2の電荷記憶媒体は、前記第2の制御ゲートよりも前記第1の垂直な半導体チャンネルおよび第2の垂直な半導体チャンネルの近くに配置され、第1のデバイス階層と第2のデバイス階層において連続した第2のトンネル誘電膜を有し、
前記第3の電荷記憶媒体は、前記第3の制御ゲートよりも前記第2の垂直な半導体チャンネルの近くに配置された第3のトンネル誘電膜を有し、
前記第1および第3の制御ゲートの双方は、互いに分離されるとともに独立して制御可能であるメモリデバイス。 - 請求項1記載のメモリデバイスであって、
前記第1および第2の垂直な半導体チャンネルは、シリコンチャンネルを有するメモリデバイス。 - 請求項1記載のメモリデバイスであって、
前記第1のソース/ドレインコンタクト領域は前記第1の垂直な半導体チャンネルの下面と接触し、前記第2のソース/ドレインコンタクト領域は前記第1の垂直な半導体チャンネルの上面と接触するメモリデバイス。 - 請求項1記載のメモリデバイスであって、
前記第1の電荷記憶媒体は、前記垂直な半導体チャンネルと前記第1の制御ゲートとの間に配置された第1の誘電体分離フローティングゲートを有し、
前記第2の電荷記憶媒体は、前記垂直な半導体チャンネルと前記第2の制御ゲートとの間に配置された第2の誘電体分離フローティングゲートを有するメモリデバイス。 - 請求項1記載のメモリデバイスであって、
前記第1および第2の電荷記憶媒体は、ONO誘電膜または導電性ナノ結晶を含む絶縁層を有するメモリデバイス。 - 請求項1記載のメモリデバイスであって、
前記デバイスは、複数のデバイス階層からなる電荷記憶デバイスのモノリシックな3次元アレイを有するメモリデバイス。 - メモリデバイスであって、
基板と、
前記基板の上面に形成された第1の入力/出力導電層と、
前記第1の入力/出力導電層の上に配置された第1の垂直な半導体チャンネルと、
前記第1の垂直な半導体チャンネルの下面及び上面で、前記第1の垂直な半導体チャンネルとそれぞれ接触する第1および第2のソース/ドレインコンタクト領域と、
前記第2のソース/ドレインコンタクト領域の上面に形成された第2の入力/出力導電層と、
前記第2の入力/出力導電層の上に配置された第2の垂直な半導体チャンネルと、
前記第2の垂直な半導体チャンネルの下面及び上面で、前記第2の垂直な半導体チャンネルとそれぞれ接触する第3および第4のソース/ドレインコンタクト領域と、
前記第4のソース/ドレインコンタクト領域の上面に形成された第3の入力/出力導電層と、を有し、
前記第1の垂直な半導体チャンネルと、第1および第2のソース/ドレインコンタクト領域は、第1のデバイス階層にある第1の柱状物であり、前記第2の垂直な半導体チャンネルと、第3および第4のソース/ドレインコンタクト領域は、第2のデバイス階層にある第2の柱状物であり、さらに、
前記第1のデバイス階層にあり、前記第1の柱状物の第1面の第1部分に隣接して配置された第1の電荷記憶媒体と、
前記第1のデバイス階層に配置され、前記第1の電荷記憶媒体に隣接して配置された第1の制御ゲートと、
前記第1のデバイス階層および第2のデバイス階層にあり、前記第1の柱状物の前記第1面と直交する方向の第2面の第2部分に隣接して配置され、かつ前記第1の柱状物の前記第2面の前記第2部分の上方にある前記第2の柱状物の第2面の第2部分に隣接して配置された第2の電荷記憶媒体と、
前記第1のデバイス階層および前記第2のデバイス階層に配置され、前記第2の電荷記憶媒体に隣接して配置された第2の制御ゲートと、
前記第2のデバイス階層に配置された部分を少なくとも有し、前記第1の柱状物の前記第1面の前記第1部分の上方にある前記第2の柱状物の前記第2面と直交する方向の第1面の第1部分に隣接して配置された第3の電荷記憶媒体と、
前記第2のデバイス階層に配置された部分を少なくとも有し、前記第3の電荷記憶媒体に隣接して配置された第3の制御ゲートと、を有し、
前記第1の電荷記憶媒体は、前記第1の制御ゲートよりも前記第1の垂直な半導体チャンネルの近くに配置された第1の層または膜を有し、
前記第2の電荷記憶媒体は、前記第2の制御ゲートよりも前記第1の垂直な半導体チャンネルおよび第2の垂直な半導体チャンネルの近くに配置され、第1のデバイス階層と第2のデバイス階層において連続した第2の層または膜を有し、
前記第3の電荷記憶媒体は、前記第3の制御ゲートよりも前記第2の垂直な半導体チャンネルの近くに配置された第3の層または膜を有し、
前記第1および第3の制御ゲートの双方は、互いに分離されるとともに独立して制御可能であるメモリデバイス。 - 請求項7記載のメモリデバイスであって、
前記デバイスは、複数のデバイス階層からなる電荷記憶デバイスのモノリシックな3次元アレイを有するメモリデバイス。 - 請求項7記載のメモリデバイスであって、
前記第1および第2の垂直な半導体チャンネルは、シリコンチャンネルを有するメモリデバイス。 - 請求項7記載のメモリデバイスであって、
前記第1のソース/ドレインコンタクト領域は前記第1の垂直な半導体チャンネルの下面と接触し、前記第2のソース/ドレインコンタクト領域は前記第1の垂直な半導体チャンネルの上面と接触するメモリデバイス。 - 請求項7記載のメモリデバイスであって、
前記第1、第2および第3の層または膜は、絶縁層または絶縁膜であるメモリデバイス。 - 請求項7記載のメモリデバイスであって、
前記第1および第2の電荷記憶媒体は、ONO誘電膜または導電性ナノ結晶を含む絶縁層を有するメモリデバイス。 - 請求項7記載のメモリデバイスであって、
前記第1および第2の垂直な半導体チャンネルの上面および下面に対し略直角方向の側面と前記第1および第2の電荷記憶媒体の双方との間に配置された連続したトンネル誘電膜をさらに有するメモリデバイス。
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US09/639,749 | 2000-08-17 | ||
US74512500A | 2000-12-21 | 2000-12-21 | |
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