TW540086B - Dense arrays and charge storage devices, and methods for making same - Google Patents

Dense arrays and charge storage devices, and methods for making same Download PDF

Info

Publication number
TW540086B
TW540086B TW90119945A TW90119945A TW540086B TW 540086 B TW540086 B TW 540086B TW 90119945 A TW90119945 A TW 90119945A TW 90119945 A TW90119945 A TW 90119945A TW 540086 B TW540086 B TW 540086B
Authority
TW
Taiwan
Prior art keywords
input
charge storage
output conductor
storage devices
methods
Prior art date
Application number
TW90119945A
Inventor
Thomas H Lee
Vivek Subramanian
James M Cleeves
Andrew J Walker
Christopher Petti
Original Assignee
Matrix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US63970200A priority Critical
Priority to US63957900A priority
Priority to US63974900A priority
Priority to US74512500A priority
Priority to US27985501P priority
Application filed by Matrix Semiconductor Inc filed Critical Matrix Semiconductor Inc
Application granted granted Critical
Publication of TW540086B publication Critical patent/TW540086B/en

Links

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. A memory device comprising: a first input/output conductor formed above or on a first plane of a substrate; a second input/output conductor; a semiconductor region located between said first input/output conductor and said second input/output conductor an intersection of their projections; a charge storage medium; and wherein charge stored in said charge storage medium affects the amount of current that flows between said first input/output conductor and second input/output conductor.
TW90119945A 2000-08-14 2001-08-13 Dense arrays and charge storage devices, and methods for making same TW540086B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US63970200A true 2000-08-14 2000-08-14
US63957900A true 2000-08-14 2000-08-14
US63974900A true 2000-08-17 2000-08-17
US74512500A true 2000-12-21 2000-12-21
US27985501P true 2001-03-28 2001-03-28

Publications (1)

Publication Number Publication Date
TW540086B true TW540086B (en) 2003-07-01

Family

ID=29587907

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90119945A TW540086B (en) 2000-08-14 2001-08-13 Dense arrays and charge storage devices, and methods for making same

Country Status (1)

Country Link
TW (1) TW540086B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI493659B (en) * 2010-04-13 2015-07-21 Ibm Nanowire circuits in matched devices
TWI582907B (en) * 2008-06-13 2017-05-11 桑迪士克科技有限責任公司 Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars
US9716153B2 (en) 2007-05-25 2017-07-25 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
TWI629788B (en) * 2012-07-01 2018-07-11 賽普拉斯半導體公司 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
TWI631692B (en) * 2017-01-20 2018-08-01 旺宏電子股份有限公司 Memory device and manufacturing method thereof
US10079314B2 (en) 2007-05-25 2018-09-18 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10079314B2 (en) 2007-05-25 2018-09-18 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US10263087B2 (en) 2007-05-25 2019-04-16 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US9716153B2 (en) 2007-05-25 2017-07-25 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US9741803B2 (en) 2007-05-25 2017-08-22 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
TWI582907B (en) * 2008-06-13 2017-05-11 桑迪士克科技有限責任公司 Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars
TWI493659B (en) * 2010-04-13 2015-07-21 Ibm Nanowire circuits in matched devices
TWI629788B (en) * 2012-07-01 2018-07-11 賽普拉斯半導體公司 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
TWI631692B (en) * 2017-01-20 2018-08-01 旺宏電子股份有限公司 Memory device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
CN1199192C (en) A read-only memory and read-only memory devices
US7528440B2 (en) Vertical gain cell
US6951789B2 (en) Method of fabricating a random access memory device utilizing a vertically oriented select transistor
CN1199280C (en) Semiconductor memory
US6794699B2 (en) Annular gate and technique for fabricating an annular gate
DE602004010859T2 (en) Method for fabricating a nanoscale resistance crosspoint memory device and device
JP3423128B2 (en) Sidewall capacitance element dram cell
US7732221B2 (en) Hybrid MRAM array structure and operation
US5571743A (en) Method of making buried-sidewall-strap two transistor one capacitor trench cell
DE10291412B4 (en) Self-Adjusting Graben-Free Magneto-Random Access Memory (MRAM) - Sidewall Enclosed Device for MRAM Structure
US6242770B1 (en) Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same
US7180160B2 (en) MRAM storage device
US20040165421A1 (en) Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation
US6037212A (en) Method of fabricating a semiconductor memory cell having a tree-type capacitor
US20030062516A1 (en) Method of fabricating a three-dimensional array of active media
US4287571A (en) High density transistor arrays
EP1107258A1 (en) Multibit MTJ stacked cell memory sensing method and apparatus
US20080247219A1 (en) Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods
US20050112846A1 (en) Storage structure with cleaved layer
JP5735107B2 (en) Three-dimensional memory and method for forming the same
DE102007022095B4 (en) Integrated circuit with a memory cell arrangement, integrated circuit with a NAND memory cell arrangement and method for producing an integrated circuit with a memory cell arrangement
US20050133852A1 (en) High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
TW439063B (en) High density semiconductor memory having diagonal bit lines and dual word lines
TW512334B (en) Write circuit for large MRAM arrays
KR100643425B1 (en) Semiconductor device with vertical transistor and buried word line

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees