TW540086B - Dense arrays and charge storage devices, and methods for making same - Google Patents

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. A memory device comprising: a first input/output conductor formed above or on a first plane of a substrate; a second input/output conductor; a semiconductor region located between said first input/output conductor and said second input/output conductor an intersection of their projections; a charge storage medium; and wherein charge stored in said charge storage medium affects the amount of current that flows between said first input/output conductor and second input/output conductor.

Description

540086 A7 _ B7 V. Description of the Invention (1) This application is a continuation of the US application serial number 09 / 801,233 (filed on March 6, 2001), and the latter is US application serial number 09 / 745,125 (2000 Partial applications were filed on December 22, 2014, both of which are incorporated herein by reference in their entirety. This application is also a continuation of the US application serial number 09 / 639,579 (filed on August 14, 2000), which is incorporated herein by reference in its entirety. This application is also part of a continuation of US Application Serial No. 09 / 639,702 (filed on August 14, 2000), which is incorporated herein by reference in its entirety. This application is also part of a continuation of US Application Serial No. 09 / 639,749 (filed on August 14, 2000), which is incorporated herein by reference in its entirety. This application also claims priority over provisional application 60 / 279,855 (filed on March 28, 2001), which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices; and more particularly, to a three-dimensional TFT (thin film transistor) array. 2. Related technical discussions As integrated circuits and computers become more powerful, new applications are emerging that require the ability to store large amounts of data. Some applications require the memory to have the ability to write and erase data and the ability to store data in a non-volatile manner. There are many possible applications that are competitive with the price of semiconductor memory, which is less than one dollar per million bytes: ⑴ chemical film to store photographic images: ⑵ CDs [Compact Disks] ) To store the distributed music and text data; (3) Digital Volatile Discs (DVDs [Digital Versatile -4-This paper size applies to China National Standard (CNS) A4 specifications (210 x 297 mm) 540086 A7 ^ _B7 ___ V. Description of Invention (2)

Disks]), used to store distributed video and multimedia materials, and (4) Video Tape and Digital Audio and Video Tape, used to store consumer audio and video recordings. Such memory can be removed from the device and all power sources for about 10 years without any significant corruption of the stored information. Therefore, it should be built-in and non-volatile. This requirement is approximately the typical life of CDs, DVDs, magnetic tapes, and photographic films in most forms. Today, these memory systems are formed of electrically erasable non-volatile memory such as flash memory and EEPROMs (electrically erasable programmable read-only memory). Unfortunately, these devices are generally manufactured on single-crystal silicon substrates and are therefore limited to two-dimensional storage device arrays; the amount of data that can be stored is limited to the number of devices that can be manufactured on a single silicon flat. It is known that other non-volatile memories can be manufactured which use the electric charges trapped in the dielectric layer. Typically, electrons are trapped in the nitride layer by, for example, current tunneling through a layer of silicon nitride. A silicon nitride system is formed between a gate to insulate the gate from the field effect transistor channel. The trapped charge shifts the threshold voltage of the transistor, so that the threshold voltage is sensed to determine whether the charge is trapped in the nitride layer. For an example of such memory, see U.S. Patent No. 5,768,192. US Patent No. 5,768,192 (issued to BJEitan), and entitled "NROM: Novel Localized Trap 2-Bit Nonvolatile Memory Cell" (NROM: A Novel Localized Trapping, 2- Bit Nonvolatile Memory Cell) (B · Aitan et al., IEEE Electron Device Letters, Vol. 21, No. 11 [2000], pp. 543-545), teaches a non-volatile semiconductor memory Body unit, which is -5- stacked on the oxide-nitride-oxide (NO) stack. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of the invention (3 ) In the nitride charge storage layer, asymmetric charge trapping is used, and two bits are stored in one cell. The writing to the cell is performed by injecting a hot electron into the charge storage layer above the junction of the drain. The reading of the cell is opposite to the writing direction, that is, the voltage is applied to the source and gate, and The drain is grounded. The memory unit is constructed in a P-type silicon substrate. However, the silicon-oxide-nitride-oxide-silicon (SONOS) 1TC memory system is arranged in a NOR (reverse OR) virtual ground array (Virtual Ground Array), and the cell area per bit is 2.5F2 , Where F is the minimum feature size, "The area of this element is larger than necessary, and the element density is smaller than the optimum. Negative resistance devices of the prior art are also known. These devices were discovered around 1972 and described in "Thin-MIS-Structure Si Negative-Resistance Diode" (Applied Physics Letters, Vol. 20, No. 8) [April 15, 1972], p. 269). The device described in this article is a junction diode (such as the diode 5510 in FIG. 96) and a thin oxide region (such as the oxide region 5511 in FIG. 96) disposed on the P-type region of the diode. ). The device provides a switching phenomenon, and exhibits a negative resistance region as shown in FIG. Note that since the potential on the diode increases in the forward direction of the diode, little conduction occurs until the voltage reaches the voltage shown at point 5512 (at which point the device exhibits negative resistance). From this point, the device. Exhibits a certain degree of diode characteristics, as shown in paragraph 5513 in FIG. 97. This swapping feature is used to make static memory cells (flip-flops), such as shown in U.S. Patent Nos. 5,533,156 and 6,015,738. In addition, the basic operation of this device is described in Sze, The Physics of Semiconductor Devices ^ 2nd Edition, Chapter 9.5, 549-553, but its explanation-6- this paper Standards apply to China National Standard (CNS) A4 (210 X 297 mm)

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540086 A7 B7 5. Description of the Invention (4) When discussing polarity, it may be wrong or wrong. The device of FIG. 96 includes a PN junction diode and a thin oxide region. When the diode is forward-biased, a portion of the applied voltage is the diode junction voltage and the rest is the voltage drop across the η-region and the oxide region, so very little current flows initially. The number of holes injected into the η-region from the ρ region is very small, so the η- region is maintained as an η-type region under the tunneling current through the oxide (regardless of its barrier to the hole flow). Similarly, any holes generated in the depletion region can pass through the thin oxide, and any generated electrons are swept across the P region and out of the anode contact. As the applied forward voltage increases, the interface between the η-region and the oxide begins to deplete, as it approaches the threshold voltage in a normal MOSFET (metal oxide semiconductor field effect transistor). At a sufficiently high voltage, this depletion region extends all the way to the junction and causes punch-through, causing a large number of holes to be injected into the n-layer from the p-region. It is difficult for these holes to flow through the oxides, so they accumulate near the surface. Therefore, the η-region is strongly reversed near the oxide interface, and the voltage drop across the oxide is increased (Mo forget V = Q / C). If the forward bias across the diode is increased and the current is increased, the electron tunneling current through the oxide increases with a super-exponential factor. At the same time, the hole is cleared in the η-region, which increases the conductivity of the η-region and reduces its voltage drop. The voltage across the diode is relatively small (and rarely changes, even if there is a large change in current), the drastic reduction in the η-voltage drop makes the voltage across the structure drop sharply (assuming there is a suitable series resistance in the circuit to Avoid breakdown of the device [rupture]) ^ In this way, the aforementioned regenerating effect causes the current to rapidly rise and the voltage to fall rapidly. It is this negative resistance area, which is used to manufacture the SRAM (Static Random Access Memory -7) described in the cited patent. This paper size applies the Chinese National Standard (CMS) A4 specification (210 X 297 mm).

540086 A7 ___B7 V. Description (5) Body) unit. At higher current levels, the device basically operates as a normal forward biased diode, as most voltages eventually fall across the PN junction. In summary, the V-I characteristics of this structure are shown in Figure 97, and the slope of its line segment 5513 is largely determined by the series resistance coupled to the structure of Figure 96. When reverse biased, the diode is in its blocking state, and the only current flowing through the oxide is the electron leakage current. The applied voltage decreases because part of it crosses the oxide region, and part of it is the reverse junction voltage. It should be noted that under reverse bias and strong forward voltage, electrons carry current through the oxide region. Another type of prior art memory device is disclosed in the title "New Cell Structure, Using Polycrystalline Silicon Thin Film Transistors for Gigabit Erasable Programmable Read-Only Memory and Flash Memory" ( A Novel Cell Structure for Giga-bit EPROMs and Flash Memories Using Poiysilicon Thin Film Transistors) Papers], pp. 44-45). As shown in FIG. 98, each memory cell is a "self-aligned" floating gate unit, and a polycrystalline silicon thin film transistor on top of an insulating layer is electrically erasable. Dividable programmable read-only memory (TFT EEPROM). In this device, the bit line extends parallel to the source-channel-drain direction (that is, the bit line extends parallel to the direction of charge carrier flow). The word line extends perpendicular to the source-channel-drain direction (that is, the word line extends orthogonal to the direction of charge carrier flow). These TFT EEPROMs do not include separate control gates; these TFT EEPROMs cover floating gates -8-degrees applicable to China National Standards (CNS) A4 specifications (210X 297 mm) A7 B7 __ _ 5. Description of the invention (6) The word line is used as the control gate in the area. The layout of the hill requires the formation of two polycrystalline silicon silicide contact pads to contact the source and gate of each TFT. The bit lines are formed on the word lines and contact the contact pads via a contact via in an interlayer insulator separating the bit lines and the word lines. Therefore, because the contact pads and contact vias are patterned by non-self-aligned lithography steps, the cells in this layout are not completely self-aligned. Therefore, the area of each memory cell is larger than necessary and the cell density is smaller than optimal. Oyama's memory cell is complicated because it requires the formation of contact pads and bit line contact vias. In addition, the manufacturability of the Oyama device is less than optimal because its bit lines and word lines have non-planar top surfaces caused by non-planar base topologies. This may lead to open circuits in bit lines and word lines. The use of virtual ground arrays to obtain crystalline silicon non-volatile memory has also been known for a long time, and it is an excellent way to actively reduce the size of memory cells. Now see Figure 99. The basic approach is to use the buried n + diffusion 5612 bit line cross point array 5610 (in the single crystal silicon p-type substrate 5614), and the polycrystalline silicon rails 5616 The formed word line (arranged on the substrate 5614). The transistor system is formed by an adjacent bit line 5612 and a p-type channel region 5618 disposed between the adjacent bit lines 5612. A layer of gate oxide 5620 insulates the floating gate 5622; the floating gate 5622 is located above the channel 5618 and is formed of polycrystalline debris (for example, ㊁). An upper dielectric layer 5624 insulates the floating gate 5622 from polysilicon word lines (WLs) 5616. "Virtual ground" means that there is no dedicated ground wire in the array. Whenever a unit is selected for predicate or program, there is a pair of buried leaf bit lines as ___ -9 -___ This paper size applies to China National Standard (CMS) A4 (210 X 297 mm) binding

540086 A7 B7 V. Description of the invention (7) Source and drain, and the source is grounded. For example, if unit 5624 outlined in Figure 100 is selected, BL (k) and BL (k + 1) will be selected as the source and drain (or vice versa), and WL (j) will be selected as the control of the device Gate. In one approach, all bit lines to the left of BL (k) (as shown in Figure 100) remain at the same potential as BL (k), while all bit lines to the right of BL (k + 1) remain at Same potential as BL (k + 1), in order to make the source-drain current flow only in the selected cell (all other WLs are grounded) (for readout and programming). In all of these approaches, the charge storage medium is a conductive floating gate made of doped polycrystalline silicon. Stylized by hot electron injection (specifically the method selected for all top-level EPROMs and single transistor flash memory cells), the floating gates are electronically injected to change the inherent MOS (metal oxide semiconductor) transistor Threshold voltage. For the non-volatile MTP (multi-programmable) memory arranged in the virtual ground array structure 5626 (as shown in FIG. 101), it may be considered to use SONOS (polycrystalline silicon-blocking oxide-nitrogen) discussed above. Ions-tunneling oxide-silicon) charge trapping pathway. The array includes n + buried bit lines 5612 arranged in a single crystal silicon substrate 5614. An ONO (oxide-nitride-oxide) dielectric stack 5628 insulates the bit line 5612 from the polysilicon word line 5630. Hot electrons are implanted into the NOx dielectric stack 5628 near the edge of the drain during programming, where the charge is trapped in the nitride layer. Using this approach, since the thermoelectron is implanted with a NOx dielectric stack at the edge of the drain used for programming, each memory cell can store Z bits. Since the nitride charge storage medium does not conduct electricity laterally, the charge stays where it is injected. The trapped electricity near the source of the transistor has a huge effect on the threshold voltage of the transistor, while the trapped charge near the drain has a value of -10-. (Centi) 340086 A7 B7 5. Description of the invention (8) The threshold voltage has a slight effect. According to this, the connection between the drain and the source is reversed, and the individual charge regions on either side of the ONO layer can be written and read. When the cell is programmed, the charge is most recently injected into the drain region. If the source and drain of the same cell are reversed, another charge can be injected into the same cell but at the "other" drain. Since both sides can be read, each unit can store and retrieve two bits. The density of the above-mentioned prior art installations is not optimal and relatively expensive. SUMMARY OF THE INVENTION According to a preferred embodiment of the present invention, a semiconductor device includes a monolithic three-dimensional charge storage device array, which includes a plurality of device stages, and at least one surface between two consecutive device stages is obtained by chemical mechanical polishing. Planar In another preferred embodiment of the present invention, a monolithic three-dimensional charge storage device array is formed in an amorphous or polycrystalline semiconductor layer on a single crystalline semiconductor substrate, and there is a driver circuit at least in part. It is formed in the substrate, below the array, within the array, or above the array. Another preferred embodiment of the present invention provides a memory device including a first input / output conductor formed on or above a first plane of a substrate. The memory device also includes a second input / output conductor. A semiconductor region is located between the first input / output conductor and the second input / output conductor at their projection phase X. The memory device includes a charge storage medium, wherein the charge stored in the charge storage medium affects the amount of current flowing between the first input / output conductor and the second input / output conductor. -11-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of the invention (9) Another preferred embodiment of the present invention provides a non-volatile read-write A memory unit includes an N-doped region, a P-doped region, and a storage element disposed between the two regions. Another preferred embodiment of the present invention provides a method for operating a memory unit. The method includes the steps of: trapping a charge in a region to program the cell; and when reading data from the cell, a current is passed through the region. Another preferred embodiment of the present invention provides a memory cell array. The array includes a plurality of memory cells, each of which includes at least one semiconductor region and a storage member for trapping electric charges. The array also includes a control member. , Used to control the current flowing through the semiconductor region of the cell and the storage member. Another preferred embodiment of the present invention provides a non-volatile stackable pillar type memory device and a manufacturing method thereof. The memory device includes a substrate including a first plane. A first contact is formed on or above the substrate plane. A body is formed on the first contact. A second contact is formed on the main body, wherein the second contact is at least partially aligned above the first contact. A control gate is formed adjacent the charge storage medium. A read current flows between the first contact and the second contact, and the direction is orthogonal to the plane of the substrate. Another preferred embodiment of the present invention provides a field-effect transistor, which includes a source, an electrode, a channel, a gate, and at least one insulating layer between the gate and the channel; and includes a The gate line extends substantially parallel to the source-channel-drain direction, contacts the gate, and is self-aligned to the gate. Another preferred embodiment of the present invention is for a three-dimensional non-volatile memory array, which includes a plurality of vertically separated device stages, each stage contains a TFT EEPROMs array, and each TFT EEPR0M contains One channel, source and -12- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 540086 A7 B7 5. Description of the invention (10 non-polar area and a charge storage area adjacent to the channel; in A plurality of bit line rows in each device level, each bit line contacting a source or drain region of the TFT EEPROMs; a plurality of word line columns in each device level; and at least one between the device levels Interlayer insulation layer. Another preferred embodiment of the present invention provides an EEPROM, which includes a channel, a source, an electrode, and a through dielectric on the channel, and on the through dielectric. Floating gate above the ground, a side wall spacer located adjacent to the side wall of the floating gate, a word line above the floating gate, and a control gate dielectric between the control gate and the floating gate The control gate dielectric is located at On the side wall spacer. Another preferred embodiment of the present invention provides a non-volatile memory cell array, wherein each memory cell includes a semiconductor device, and the cell size of each bit of the memory is (2F2) / N, here the smallest feature size, and N is the number of device layers in the third dimension, and N > 1. Another preferred embodiment of the present invention provides a method for manufacturing EEPROM, It includes: providing a semiconductor active area surface; forming a charge storage area on the active area surface; forming a conductive gate layer on the charge storage area; and patterning the gate layer to form a covered charge The control gate of the storage area. The method also includes using the control gate mask to dope the active area surface to form the source and drain regions in the active area surface; forming on and adjacent to the control gate A first insulating layer; the exposed grandson without the shadow mask on the top of the control gate: and forming a word line 'that contacts the top of the g-gate exposed, so that the word line is self-aligned to the control gate. Falun Yue Provided a method of manufacture thereof embodiment

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540086 A7 B7 invention description, which includes: providing a semiconductor active area surface; forming a tunneling dielectric layer on the active area surface; forming a conductive gate layer on the tunneling dielectric layer, pattern The gate layer is changed to form a floating gate covering the tunneling dielectric layer; and the active gate surface is doped with the floating gate mask to form source and drain regions in the active region surface. The method also includes: forming sidewall spacers adjacent to the sidewalls of the floating gate; forming a first insulating layer on and adjacent to the sidewall spacers and above the source and drain regions; and floating the A control gate dielectric layer is formed on the gate; and a word line is formed on the control gate dielectric layer and on the first insulating layer. Another preferred embodiment of the present invention provides a method for forming a non-volatile memory implant array, which includes: forming a semiconductor active layer; forming a first insulating layer on the active layer; on the first insulating layer Forming a plurality of gate electrodes; and using the gate electrodes as a mask to dope the active layer, and forming a plurality of source and drain regions in the active layer, and forming a plurality of approximately perpendicular to the source drain A bit line extending in the polar direction. The method also includes forming a second insulating layer on and adjacent to the gate electrode and on the source region, the drain region, and the bit line; planarizing the second insulating layer; and, A plurality of zigzag lines extending substantially parallel to the source-drain direction are formed on the second insulating layer. Another preferred embodiment of the present invention provides a method for manufacturing an EEPROM array, which includes: providing a semiconductor active area surface; and forming a plurality of du_y blocks on the active area surface for factory use. The dummy block is a mask to mix the 4 active area planes, and the source and drain regions are formed in the active area planes; A whole insulation layer is formed on and between the blocks; the complete insulation is planarized

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-14- 540086 A7 B7 V. Description of the invention (12) layer to expose the top of the dummy block; selectively remove the dummy block from the parts of the planarized complete insulation layer, and between the parts of the complete insulation layer Forming a plurality of through-holes; forming a charge storage region on the active area surface of the plurality of through-holes; forming a conductive gate layer on the charge storage regions; and patterning the conductive gate layer to form a A control gate covering a charge storage area. Another preferred embodiment of the present invention provides a method for forming a TFT EEPROM, which includes forming a TFT EEPROM including an amorphous silicon or polycrystalline silicon active layer, a charge storage region, and a control gate; providing a A crystallization catalyst is brought into contact with the active layer; and after the step of providing the catalyst and recrystallizing the active layer using the catalyst, the active layer is heated. Another preferred embodiment of the present invention provides a two-dimensional or three-dimensional memory array constructed by a thin film transistor disposed on a substrate. The spaced-apart conductors arranged in a first direction contact a memory unit formed in a rail stack arranged in a second direction different from the first direction. A localized charge trap is received by the media and stores the thermoelectrons injected by the thin film transistors formed at the intersections of the spaced-apart conductors and rail stacks. The local charge trapping medium can be used to store the charge near the drain of the transistor; if necessary, the drain and source lines are inverted to store two bits in each memory cell. The programmatic approach guarantees that stored memory is not inadvertently disturbed. Another preferred embodiment of the present invention provides a non-volatile thin film transistor (TFT) memory device constructed on a substrate. It uses source, drain, and channel formed from transition metal junction silicon. A localized charge storage film is disposed vertically adjacent to the channel and stores the injected charge. Such a device, the second one is -15- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of the invention (13) A three-dimensional or three-dimensional array can be constructed on the substrate. The spaced-apart conductors arranged in a first direction contact the memory cells formed in a rail stack arranged in a second direction different from the first direction. TFTs are formed at the intersection of the spaced-apart conductors and the rail stacks; the charge injected by TFTs is received and stored by the local charge storage film. The local charge storage film can be used to store the charge adjacent to the drain of a transistor; if necessary, the drain and source lines are inverted to stagger two bits in each memory cell. The programmatic approach guarantees that stored memory is not inadvertently disturbed. Another preferred embodiment of the present invention provides a flash memory array disposed on a substrate. The array includes a first plurality of spaced apart conductive bit lines arranged in a first direction to the At a first height above the substrate; and a second plurality of spaced apart rail stacks, which are arranged in a second direction different from the first direction to a second height, each rail stack includes a plurality of Semiconductor islands, and a first surface of the semiconductor islands contacts the first plurality of spaced apart conductive bit lines, a conductive word line, and is disposed between the second surface of the semiconductor island and the word line Storage area for electricity. Another preferred embodiment of the present invention provides a TFT CMOS (Complementary Metal Oxide Semiconductor) device, which includes a gate electrode, a first insulating layer adjacent to the first side of the gate electrode, and includes a ... The first semiconductor layer has a first conductivity type, and is disposed on the first insulating layer opposite to the other side of the gate electrode JE :; the first and drain regions of the second conductivity type are arranged on In the first semiconductor layer; and, the first source and drain electrodes contact the first source and drain regions, and are arranged on the first semiconductor layer opposite to the first insulating layer. Standard (CNS) A4 size (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (14) on the other side. The TFT CMOS device further includes a second insulating layer adjacent to the second side of the gate electrode; and includes a second semiconductor layer having a second conductivity type and disposed on the second insulating layer opposite to the gate electrode On the other side; the second source and drain regions of the first conductivity type are disposed in the second semiconductor layer; and the second source and drain electrodes contact the second source and drain regions, And disposed on the other side of the second semiconductor layer opposite to the second insulating layer. Another preferred embodiment of the present invention provides a circuit including a plurality of charge storage devices and a plurality of non-fuse devices. Another preferred embodiment of the present invention provides a semiconductor device including a semiconductor active region, a charge storage region adjacent to the semiconductor active region, a first electrode, and a second electrode. When a first stylized voltage is applied between the first and second electrodes, charges are stored in the charge storage region; and when a second stylized voltage higher than the first voltage is applied to the first and second electrodes Between them, a conductive chain is formed to pass through the charge storage region, and a conductive path is formed between the first and second electrodes. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A illustrates a pillar-type memory according to an embodiment of the present invention. FIG. 1B is a perspective view of a pillar-type memory according to a specific embodiment of the present invention, in which there is a single charge storage medium and a single control gate surrounding the pillar. Fig. 1C is a perspective view of a guide post type memory according to a specific embodiment of the present invention. The factory has a plurality of charge storage media and a plurality of control gates surrounding the guide post. FIG. 2 illustrates a pillar-type memory according to an embodiment of the present invention. Figures 3A-3D illustrate a superfine channel guide post type according to a specific embodiment of the present invention-17- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 540086 A7 B7 V. Description of the invention (15 Memory device and manufacturing method thereof. Fig. 4 illustrates a pillar-type memory according to a specific embodiment of the present invention, including Schottky contacts. Fig. 5 illustrates a memory according to a specific embodiment of the present invention. Gate-controlled diode-guided pillar memory. FIG. 6 illustrates a pillar-type memory according to a specific embodiment of the present invention, in which a nanocrystal floating gate is installed. FIG. 7 illustrates a structure according to the present invention. The pillar-type memory of a specific embodiment has a charge trapping dielectric therein. FIGS. 8A and 8B illustrate a method for forming a pillar using an explicit pillar-forming process. FIGS. 9A and 9B illustrate a A method for forming a guide post by using an intersecting etching technique. FIGS. 10A-10E illustrate a method for forming a guide post memory device according to a specific embodiment of the present invention by using a “spacer etch” technique. 11A-11C shows the distance between adjacent guide posts Gate insulation system, shown also explain a control method of a common gate between adjacent guide column memory formation.

Lines 12A and 12B illustrate a method for forming a common continuous film control gate between two or more stages of pillar memory. 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A 21B, FIG. 22A, FIG. 22B, FIG. 2 3A, FIG. 2 3B, FIG. 23C, FIG. 24, FIG. 25A, FIG. 25B, FIG. 26, FIG. 27A, FIG. 27B, and FIG. A specific embodiment is a method for manufacturing a multi-level guide pillar type memory. FIG. 29A shows a memory unit according to a specific embodiment of the present invention. Fig. 29B illustrates the unit of Fig. 29A. Fig. 30 is a sectional front view of a two terminal unit constructed according to a specific embodiment of the present invention. __18- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). 5. Description of the invention (1δ) Figure 31 is a sectional front view according to the present invention. FIG. 32 is a front view of a rail stack constructed using a three-terminal memory array according to a specific embodiment of the present invention. Figure 33 is a perspective view of a unit of a column according to the present invention. A specific embodiment is formed as a guide pattern on a substrate. 4 is another specific embodiment of a unit formed as a guide post. 35 and 36 are schematic diagrams of a three-dimensional device array. The figure is a cross-sectional side view of a circle after the ZO dielectric f, the first interrogation electrode, and the protective oxide-plugged nitride layer are deposited according to the method of the present invention. μ Figure. 8 is a cross-sectional side view of the-! Memory array after bit line patterning and source / drain implantation. The cross section is orthogonal to the bit line. The picture shows a cross-sectional side view of the array after the self-aligned fragmentation process. The section is orthogonal to the bit line. FIG. 40 is a cross-sectional side view of the array after oxide filling and planarization. The cross section is orthogonal to the bit line. FIG. 41 is a cross-sectional side view of the array after the blocking layer is removed. The cross section is orthogonal to the bit line. FIG. 42 is a cross-sectional side view of an array during word line formation. The cross section is orthogonal to the bit line. 43 is a cross-sectional side view of the array during the formation of a word line along the line of FIG. 42. The cross section is orthogonal to the word line and passes through a bit line. Figure 44 is a cross-sectional side view of the array during the formation of the word line along the line BB in Figure 42. ____- 19- This spider scale applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love :) 540086 A7 B7 V. Invention description (17). The cross section is orthogonal to the word line and passes through a transistor channel. Figure 45 is a cross-sectional side view of a second preferred embodiment of the array after oxide filling and planarization. The cross section is orthogonal to the bit line. Fig. 46 is a cross-sectional side view of a second preferred embodiment of the array after word line formation. The cross section is orthogonal to the bit line. Fig. 47 is a cross-sectional side view of a preferred embodiment of the array after word line formation. The cross section is orthogonal to the bit line. Figures 48A-C and 49A-C illustrate an alternative method of fabricating the T-FT of a preferred embodiment array. Figures 50 and 51 are cross-sectional side views of two preferred arrays of a preferred embodiment after word line formation. The cross section is orthogonal to the bit line. FIG. 52 is a three-dimensional view of a three-dimensional array of a preferred embodiment. Fig. 53 is a sectional side view of a word line contact conductor and a one-bit line contact conductor in the same stage. The opening is made for the next level of contact. Fig. 54 is a cross-sectional side view of a zigzag line contact conductor on the N + 1th level and a zigzag line and bit line contact conductor on the Nth level. In N + 1 level conductors, landing pads are manufactured for the next level of contacts. 55-61 are cross-sectional side views of a method of manufacturing an array of a preferred embodiment. The cross section is orthogonal to the bit line. FIG. 62 is a top view of an array after a crystallization window is formed in a preferred embodiment of the present invention. 63 and 764 are cross-sectional side views of lines A-Al B-B in FIG. 62, respectively. The cross section is orthogonal to the bit line in FIG. 63 and parallel to the bit line in FIG. 64. Figure 65 is a top view of a preferred embodiment of the array after crystallization of the active layer. -20-

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LINE This paper size applies to China National Standard (CNS) A4 (2l0x 297 mm) 540086 A7 B7 5. Description of the invention (18) Fig. 66 shows a front perspective view of a two-dimensional memory array according to a specific embodiment of the present invention. Fig. 67 shows a cross-sectional front view of a two-dimensional memory array according to a specific embodiment of the present invention. FIG. 68 shows a top plan view of a memory array according to a specific embodiment of the present invention. FIG. 69 shows a cross-sectional front view of a three-dimensional memory array according to a specific embodiment of the present invention. FIG. 70 shows a cross-sectional front view of a two-dimensional memory array according to a specific embodiment of the present invention. FIG. 71 shows a cross-sectional front view of a three-dimensional memory array according to a specific embodiment of the present invention. FIG. 72 shows a cross-sectional front view of a memory array according to a specific embodiment of the present invention. FIG. 73 shows a cross-sectional front view of a three-dimensional memory array according to a specific embodiment of the present invention. Figures 74 and 75 illustrate a method for programming a memory cell according to a particular embodiment of the invention. FIG. 76 illustrates a method of manufacturing a memory cell according to a specific embodiment of the present invention. The figure illustrates a cross-sectional view of one of the SONOS on a dielectric stack. Fig. 78 is a cross-sectional view illustrating a nanocrystalline charge storage medium. -21-This paper size applies to China National Standard (CNS) A4 (21 × 297 mm)

Line 540086 A7 B7 V. Description of the invention (19) Figure 79 is a cross-sectional view of a doped polycrystalline silicon bit line, in which a pair of refractory metal petrified compounds are formed to improve lateral conductivity rate. FIG. 80 is a cross-sectional view of a substrate according to a specific embodiment of the present invention. 81A-81H illustrate manufacturing steps of a memory array according to a specific embodiment of the present invention. Figures 82A-82I illustrate manufacturing steps for a memory array according to a particular embodiment of the present invention. 83A, 83B, 84 and 85 illustrate a flash memory array according to a preferred embodiment of the present invention. Figures 86A-86J illustrate a method of manufacturing the array of Figures 83-85. FIG. 87 illustrates a CMOS array according to a preferred embodiment of the present invention. 88A-88D illustrate a method of manufacturing the CMOS array of FIG. 87. 89-92 illustrate logic and memory circuits using the CMOS array of FIG. 87.

Line diagram 93 is a flowchart illustrating a process for manufacturing a crystallized amorphous silicon layer, and the crystallized amorphous silicon layer is used for a nonvolatile TFT according to a specific embodiment of the present invention. Memory device. 94A-94H are vertical sectional views illustrating steps in the process of FIG. 93. Fig. 95 is a partial plan top view of a silicon wafer after being processed according to the process of Fig. 93. Fig. 96-101 illustrates a prior art device. Detailed description of preferred embodiments The present invention truly understands that: increasing the density of the device can reduce the cost of memory and logic devices. Therefore, the present invention provides an ultra-compact charge storage semiconductor device matrix array, which has improved density and lower cost. ___ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of the invention (20) One of the methods to improve the density of the device is to arrange the device in a device level with multiple device levels. Monolithic three-dimensional charge storage device array. The word "monolithic" means that the layers of each level of the array are deposited directly on the layers of each bottom level. Two-dimensional arrays are very different. They can be formed separately and assembled together to form a non-monolithic memory device. To form such a three-dimensional array, especially an array having four or more layers, at least one surface between two consecutive device levels is planarized by chemical mechanical polishing (CMP). Unlike other planarization methods (such as etch back), chemical mechanical polishing allows a sufficient degree of planarization ^ to allow multiple commercially available device levels to be stacked on top of one another. The inventors have found that in three-dimensional memory arrays, chemical mechanical polishing typically achieves flatness in the field of flatness of the order of 4000 Angstroms (Angstroms) or less, that is, in the order of 10 to 50 mm The area will have a peak to peak roughness value of 4000 Angstroms or less, even after the array has 4 to 8 layers formed. Preferably, after CMP polishing, the Peak-to-peak roughness is 3000 angstroms or less, such as 500 to 1000 angstroms (in the area of flatness). In contrast, etchback alone does not generally provide sufficient flatness to achieve a three-dimensional commercial fit. Memory or logic monolithic array. For example, the phrase "at least one surface between two consecutive device levels is planarized by CMP" does not only include the interlayer insulation layer disposed between the device layers The surface also includes the surface formed in the bottom and intermediate device layers. 0 Here, the surface of the conductive and / or insulating layer in each intermediate and bottom device level of the array is planarized by chemical mechanical polishing. Therefore, If the array Including at least four device levels, at least three device levels should be between -23- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

540086 A7 B7 5. Description of the invention (ζι) One surface is flattened by chemical mechanical polishing. The surface of the conductive and / or insulating layer in the top device level can also be planarized by chemical mechanical polishing. Another way to improve device density is to vertically integrate drives or peripheral circuits with memory or logic arrays. In the prior art, the peripheral circuits were formed in the periphery of the single crystal silicon substrate, and the memory or logic array was formed in other parts of the substrate (adjacent to the peripheral circuits). Therefore, the peripheral circuits occupy valuable in the prior art devices. Substrate space. A preferred embodiment of the present invention is quite different. It provides a monolithic three-dimensional charge storage device array formed in an amorphous or polycrystalline semiconductor layer on a single crystalline semiconductor substrate, and the driver (Ie, peripheral) circuits are at least partially, preferably all formed in a substrate, under the array, within the array, or above the array. Preferably, the driver circuit includes a sense amp and a charge At least one of the pumps is formed entirely or partially in the substrate and below the array. Figure 35 shows a charge storage logic or memory device array 3101, which is formed on an interlayer insulating layer 3102, and the interlayer insulating layer 3102 is It is arranged on a single crystalline substrate 3105. The charge storage logic or memory device array 3101 is arranged in this way, and is a three-layer structure in an amorphous or polycrystalline silicon layer. Monolithic array thin-film transistors or diodes. Array 3101 has multiple device levels 3104, but should be separated by interlayer insulation. Driver circuits 3103, such as sense amplifiers and charge pumps, are arranged in a single crystal substrate 3105 As a CMOS or other transistor. Figure 36 shows a charge storage logic or memory device array 3101, which is formed on a single crystalline substrate 3105, and is a thin film transistor or amorphous silicon or polycrystalline silicon layer. Diodes. Driver circuits 3103, such as sense amplifiers and charge pumps, are formed within array 3101 and / or above array 3101. -24- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 A7 B7 V. Explanation of the invention (22) Another method to improve the density of the device is to do self-adjustment and use the same lithography steps to pattern different layers. The area of the device unit is misalignment The tolerance is expanded to ensure that features on different layers overlap completely. In this way, the inventor has developed a fully or partially aligned memory cell structure that does not require misalignment tolerances. Only a reduced misalignment tolerance is required. In such a unit structure, some device features can be self-aligned to other device features without the need for lithography steps for patterning. Alternatively, the same photoresistance can be used Mask to etch multiple layers; alternatively, a patterned upper device layer can be used as a mask to etch the lower device layer. The following will discuss the special case of aligned memory cells in more detail. Charge storage of the array The device may be any type of semiconductor device that stores charge, such as EPROMs or EEPROMs. In the preferred embodiment of the present invention described in detail below, the charge storage device is formed in various configurations, such as a pillar-type TFT EEPROM, pillar-type diode with a charge storage area, self-aligned TFT EEPROM, rail-stacked TFT EEPROM, and various other configurations. These configurations provide the device with a high degree of planarity and alignment or self-alignment to increase array density. For example, in a pillar-type TFT EEPROM or a pillar-type diode having a charge storage region, at least one side of a semiconductor active region is aligned with an electrode that contacts the semiconductor active region. Thus, in the configuration of the pillar-type TFT EEPROM, the semiconductor active region is aligned with the source and drain electrodes. This alignment occurs because at least two sides of the semiconductor active area and one of the electrodes are patterned in the same lithography step (ie, using the same photoresist mask, or using one layer as the other layer Mask). -25- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (23) In a self-aligned TFT, the two sides of the semiconductor active region are only in the channel portion of the semiconductor active region, not the source and drain regions, and the gate electrode is aligned. One side. This alignment occurs because at least two sides of the channel region and the gate electrode are patterned in the same lithography step (ie, using the same photoresist mask, or using one layer as a mask for the other ). Obviously, the source and electrode regions are not etched. In the following description, many specific details are stated, such as specific thicknesses, materials, etc., and the present invention is thoroughly understood. For those skilled in the art, it is obvious that the present invention can be implemented without specific details. In other examples, well-known concepts, circuits, and manufacturing techniques have not been elaborated so as not to unnecessarily obscure the present invention. The features of any of the specific embodiments described below can be used in other specific embodiments. The first group of specific embodiments describes various different pillar type devices, the second group of specific embodiments describes self-aligned TF devices, and the third group of specific embodiments describes rail-stacked TFT devices. The fourth and fifth sets of embodiments illustrate how these devices can be used in logic or memory circuits. The last set of specific examples illustrates the use of metal to induce crystallization to improve device-level crystallinity. I. Guide post device This specific embodiment refers to thin film transistors (TFTs) and diodes arranged in a guide post configuration (that is, a direction perpendicular to the substrate, in which the device length is orthogonal to the substrate, and a method of manufacturing the same). It is preferable that the pillar-type devices form a charge trapping memory with a vertical readout of 1 stream. The memory includes a first input / output conductor formed on or above a substrate plane, and a One above the first input / output conductor and separated from the first input / output conductor by a distance of -26- The paper wattage applies to China National Standard (CNS) A4 (210X 297 mm) binding

Line 540086 A7 B7 V. Description of Invention (24) Second input / output conductor. The first input / output conductor and the second input / output conductor are positioned to overlap or intersect each other, and it is preferable that they intersect at right angles to each other. A half-conductor region, such as a doped silicon region, is formed between the first input / output conductor and the second input / output conductor at the intersection of the first input / output conductor and the second input / output conductor. A charge storage medium, such as (but not limited to) a charge trapping dielectric, is formed near the semiconductor region and affects a given voltage across a first input / output conductor and a second input / output conductor. The amount of current flowing through the semiconductor region between the first input / output conductor and the second input / output conductor. The amount of current (reading current) flowing through the semiconductor region under a single voltage can be used to determine whether the charge is stored in the charge storage medium, thereby determining whether the memory is programmed or erased. It should flow through the first input / output The current in the semiconductor region between the conductor and the second input / output conductor flows in a vertical direction of the substrate (in which a memory is formed). The structure of the charge trapping memory and the manufacturing method thereof in this embodiment are ideally integrated into a three-dimensional memory device array. As will be discussed below, the charge trapping memory device of this embodiment can be manufactured from one of two general substrates. In a specific embodiment, the charge storage medium is formed adjacent to the semiconductor region; in a second embodiment, the charge storage medium is formed above or below the semiconductor region. 1. Three-terminal pillar-type memory with adjacent charge storage media One embodiment of the present invention is a three-terminal non-volatile stackable pillar-type memory device. In Fig. 1A, a pillar-type memory device 100 according to one embodiment of the present invention is schematically illustrated. The guide post type memory device 100 includes a first contact area 102, and the first contact area 102 is formed on a first input / output-27. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 540086 A7 B7 5. Description of the Invention (25) (I / O) 103 conductor, the first I / O 103 conductor is formed on or above the plane (xy) of a single crystal substrate 101. A semiconductor body 104 is formed directly on the first contact area 102; a second contact area 106 is formed directly on the body 104. A second I / O conductor 116 is formed on the second contact area 106. The first contact area 102, the main body 104, and the second contact (source / drain) area 106 are aligned with each other vertically to form a guide pillar 108. Adjacent and in contact with the main body 104 is a charge storage medium 110. A control gate 112 is formed adjacent to and in direct contact with the charge storage medium 110. The control gate 112 and the charge storage medium 110 are constructed adjacent to the lateral side of the guide post 108 for electrical communication with the guide post 108. The charge storage medium is an area that electrically shields the control gate and the channel area defined by the control gate. The programmed or unprogrammed state of the pillar-type memory device depends on whether the charge is stored in the charge storage medium 110 or not. The charge stored in the charge storage medium 110 increases or decreases the voltage applied to the control gate, thereby replacing the voltage required to form a conductive channel in the main body 104, and the conductive channel enables a current (such as the readout current IR) at Flow between the first and second contact (source / drain) regions. This voltage is defined as VT. The amount of voltage required to form a conductive channel in the body 104, or the amount of current flowing in the body under a given control gate voltage, can be used to determine whether the device is programmed or non-programmed. In addition, a single charge storage medium 110 can store multiple data bits, whereby a different VT is established for each different stored charge amount, and each charge represents a different state of the charge storage medium. Because a charge storage medium can have multiple states, multiple bits can be stored in a single charge storage medium. During the reading operation of the device 100, when a conductive channel is formed in the main body 104, the current 114 is to the plane (xy) of the substrate 101 (a guide post type is formed thereon. -28- This paper size applies to Chinese national standards ( CNS) A4 size (210 X 297 mm) 540086 A7 B7 5. Description of the invention (26) Memory device) flows vertically or orthogonally. By establishing a memory device with a "vertical" readout current path, the pillar-type memory cells of the present invention can be easily stacked in a three-dimensional array, so that the source / drain conductors 103 and 116 extend parallel or orthogonal to each other And parallel to the plane of the substrate 101, there is no need to use a vertical interconnection strategy to connect the source and the drain. The conductor 112 to the control gate may extend vertically (as shown in FIG. 1A) or horizontally. Although the memory device 100 shown in FIG. 1A only forms a charge storage medium 110 and a control gate 112 on one side or a surface of the guide pillar 108, it should be understood that the guide pillar memory of the present invention. The device can be manufactured as shown in FIG. 1B so that the entire body 104 of the guide post 108 is surrounded by a single charge storage member 110 and a single control gate 112. In addition, each surface of the guide post 108 may have an independently controlled charge storage member and a control gate as shown in FIG. 1C, so that multiple data bits can be stored in a single guide post memory device of the present invention. . By using multiple charge storage members and control gates, multiple values can be stored on a single guide post device by determining how many channels are exposed to charge. In addition, each side of the main body 104 of the guide pillar 108 may have a different doping density, and different threshold voltages are established for each side, so that the guide pillar memory can increase the storage state (ie, more bits). FIG. 2 shows a specific embodiment of the present invention, wherein the guide post 207 includes a first source / drain contact region 202, and the first source / non-contact contact region 202 is formed on a first input / output 204. (Eg, bit line) on the conductor, the first input / output 204 is formed on or on a substrate 201. A source / drain contact region 202 has a thickly doped N + silicon film, and the doping density of the silicon film is in the range of 1 X 1019 to 1 X 102G atoms / cm3, and is 1 X 1〇19 to 1 X 1021 are preferred. 1 -29- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

540086 A7 B7 Description of the invention The body of the lightly doped P-type silicon film 206 is formed by direct contact on the first N + source / drain contact region 202, and the doping density of the silicon film is 1 x 1 to i χ 1018 atoms / cm3. A second source / non-electrode region 208 is formed by direct contact on the p-type broken film 206 (as shown in FIG. 2), which contains a thickly doped N4 film and the doping density of the silicon film. Then it is 1 X 1019 to 1 X 俨 atoms / cubic centimeter, and preferably 1X10 丨 9 to 1 × 1021. A second conductive input / output (e.g., word line / bit line) 210 is formed on the second N + source / inverted region 208. The N + source / non-electrode films 202 and 208 may have a thickness of 500-1000 Angstroms (A). The first and second input / output 204 and 210 can be made of highly conductive materials such as (but not limited to) metals (eg, cranes), silicides (eg, titanium silicide or tungsten silicide), or thickly doped Of silicon. In the memory device 200, the N + source / inverted region 202, the P-type silicon body 206, and the N + source / inverted region 208 are aligned substantially perpendicular to each other to form a guide post 207 β a guide post memory 200 (shown in FIG. 2) has a charge storage medium 211, which includes a tunneling dielectric 212, a floating gate 214, and a control gate dielectric 216. The tunneling dielectric is formed adjacent to and directly in contact with the P-type silicon body 206. The floating gate 214 is formed adjacent to and in direct contact with the tunneling dielectric 212. The floating gate 214 contains a conductor such as, but not limited to, doped silicon (e.g., n-type silicon), or a metal (e.g., 'tungsten'). The control gate dielectric 216 is formed adjacent to and directly in contact with the floating gate 214. Finally, a control gate 218 is formed adjacent to and in direct contact with the control gate dielectric 216. The control gate 218 is made of a highly conductive material, such as (but not limited to) miscellaneous debris, or a metal (eg, plutonium). The degree of the P-type chip-film 206 and the tunneling dielectric 212 depends on the necessary voltage for programming and erasing. If low voltage stylized operation of 4 to 5 volts is required, the P-type silicon film 206 may have a thickness of 1000-2500 angstroms, and the tunneling dielectric may have a thickness of -30. Standard (CNS) A4 size (210X 297 male)

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Line 540086 A7 B7 V. Description of the invention (28) The degree is 20-150 angstroms (such as 20-50 angstroms, and 80-130 angstroms is preferred). If a nitride tunneling dielectric 212 is required, its thickness will be slightly enlarged. It should be understood that the thickness of the P-type silicon film 206 defines the channel length of the device. If high voltage (6 to 10 volts) stylization is required, the P-type silicon film 206 may have a thickness of 6000-7000 angstroms, and the tunneling dielectric may have a thickness of 60-100 angstroms. The typical thickness of the control gate dielectric 216 is on the order of thickness of the tunneling dielectric 212, but is slightly thicker (10-30 angstroms), and preferably 130-180 angstroms. The identification of the pillar-type memory 200 as programmed or unprogrammed depends on whether the charge is stored on the floating gate 214 or not. The programming of the guide post type memory device 200 can be done on the drain side, and the electrons are placed on the floating gate 214 here. This system grounds the source region 202, applies a relatively high voltage to the drain region 208, and applies approximately 4-5 volts (for low-voltage operation) or 6-10 volts (for high-voltage operation) to the control gate 218. ), Inverting a portion of the P-type silicon region 206 into N-type silicon to form a channel region, so that electrons flow between the source region and the drain region. The high control gate voltage pulls electrons out of the inverse channel region, passes through the tunneling dielectric 212, and onto the floating gate 214. Because the electrons consume some energy as they tunnel through the tunneling oxide, there is no longer enough energy to escape the floating gate surrounded by the insulator. Other techniques, such as (but not limited to) source-side implantation, can also be used to program the memory device 200. By removing the stored electrons from the floating gate 214, the memory device 200 can be erased. Put a relatively high positive voltage (3 volts) on the source region, and apply a voltage of about 4-5 volts (in low voltage operation) or 6-10 volts (in high voltage operation) to the control gate 218 The negative voltage can erase the memory device 200. The positive voltage on the source region attracts the electrons of the floating gate 214 and pulls the electrons away from the floating gate -31-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 540086 A7 B7 V. Invention Explanation (29) 214 passes through the tunneling dielectric 212 and enters the source region. To read the state of the memory device 200, a voltage (such as 3.3 volts) may be applied to the drain, and a given control gate voltage may be applied to the control gate. The current (readout current) flows from the drain region through the channel region to the source region under a given control gate voltage, and its amount can be used to determine the state of the memory device. Alternatively, the state of the memory 200 can be read by sensing the amount of gate current required to cause the read current to flow through the body 206. The read current is in the first and second source / drain regions 202 and 208. When the main body 206 flows between them, it flows in the orthogonal direction ⑵ of the plane (Xy) of the substrate 201 on which the device is built. Fig. 3 shows another embodiment of the non-volatile guide type memory device of the present invention. FIG. 3 shows a three-terminal non-volatile pillar-type memory device 300, which includes an ultra-thin silicon channel or body 302. Similar to the memory device 200, the ultra-thin memory device 300 has a first N + source / drain contact area 202 formed on a first input / output 204. An insulator 304, such as a SiO2 film or a silicon nitride film, is formed on the first N + source / drain contact region 202. A second source / drain region 208 is formed on the insulator layer 304. The insulator 304 separates the source / drain regions 202 and 208 from each other, thereby defining the channel length of the device. A thin P-type silicon film 302 has a concentration in the range of 1X1016 to 1X1018 atoms / cubic centimeter and is formed along the side wall of the N + / insulator / N + stack. This is to not only adjoin and directly contact the separation insulator 304, but also Adjacent and directly contact the first and second source / drain regions. The P-type silicon film is used as a channel or a body of the device, and bridges the thin gap between the source / ¾ region 202 and 208. By forming a thin P-type silicon film adjacent to the N + / insulator / N + stack, an extremely thin channel region (50-100 angstroms) can be obtained. The thickness of the P-type silicon film indicates the thickness of the channel, and the length of the channel is less than 1/2 of the channel length. -32- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 30) It is better (that is, the distance between the source / drain regions 202 and 208), and is ideally less than 1/3 channel length. Similar to the memory device 200, the memory device 300 also includes a charge storage medium 211 and a control gate 218. When transistor 300 is turned on, a portion of the P-type silicon region is reversed and a conductive path is formed therein, so that current can flow from one source / drain region 202 to another source / drain region 208. The current path 306 flows from one source / drain region through the ultra-thin body 302 or channel to another source / drain region, most of which is on the substrate plane (xy) (the device is above it) Construction) flow in the orthogonal direction ^ For example, "spacer etching" technology can be used to form ultra-thin channels or bulk transistors. For example, as shown in FIG. 3B, a blanket deposit—N + silicon / insulator / N + silicon stack can be deposited on a substrate containing patterned metal I / O 204. The well-known lithography and etching techniques are then used to pattern the stacked pattern into the guide pillars 306 shown in FIG. 3B. Then a P-type silicon film is blanket deposited on the guide post, as shown in FIG. 3C. The P-type silicon film is deposited to a thickness which is necessary for the device channel thickness. The P-type polycrystalline silicon film is then anisotropically etched, so that the P-type silicon film 302 is removed from the horizontal surface and remains on a vertical surface such as a sidewall of the guide pillar 306. In this way, a P-type silicon film is formed adjacent to the pillar and bridges the source / drain region across the insulator 304. As with other pillar type devices, a charge storage medium 211 and a control gate 218 can be formed next. FIG. 4 shows another embodiment of the three-terminal stackable non-volatile pillar-type memory device of the present invention. Fig. 4 is a three-terminal stackable non-volatile conductive post memory device, in which Schottky contacts are used to form the source and drain regions of the device. The Schottky contact M0SFET 400 of the present invention includes a first input _-33- _ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of the invention (31) / The first metal contact 402 formed on the output 204. A doped silicon body or channel 404 (such as N-type silicon) is formed on the metal contact 402, which is doped to a concentration level of 1 X 1016 to IX 1018 atoms per cubic centimeter, and has a function of the channel length. Say it is the necessary thickness. A second metal contact 406 is formed in direct contact with the silicon body 404. A second I / O is then formed on the second metal contact 406. The first metal contact 402 and the second metal contact 406 are made of materials such as platinum silicide, tungsten silicide, and titanium silicide; the thickness achieved is a Schottky contact in contact with the silicon body 404. The first metal contact 402, the silicon body 404, and the second metal contact 406 are all vertically aligned with each other to form a guide post 408 as shown in FIG. The memory device 400 also includes a charge storage medium 211 in close proximity to the silicon body 404, as shown in FIG. 4. In addition, the memory device 400 includes a control gate adjacent to and in direct contact with the charge storage medium 211. When a channel is formed in the silicon body 404, a current (eg, a readout current IR) flows in a direction orthogonal to the substrate surface (xy) (on which the memory device 400 is formed) and flows from the metal contact 402 to the metal contact 406. Fig. 5 shows another embodiment of the three-terminal non-volatile memory device of the present invention. FIG. 5 illustrates a gated diode memory device 500. The memory device 500 includes a P + -type silicon film contact region 502 having a dopant density of 1 X 1019 to 1 X 102G atoms / cm3 (preferably 1 X 1019 to 1 X 1021) and a thickness of 500-1000 Angstroms. A P-silicon film 504 has a doping density of 1 X 1016 to 1 X 1018 atoms / cm3, and is formed by directly contacting the P + silicon film 502. An N + -type silicon film contact region 506 has a doping density of 1 X 1019 to 1 X 102G atoms / cm3 (preferably 1 X 1019 to 1 > Γΐ〇21), and has a thickness of 50-1000. Angstroms are formed directly on the P-silicon film 504. In a specific embodiment of the present invention, the P + silicon film 502, the P-silicon film 504, and the N + silicon film 506 are vertically aligned with each other to form a guide post 508 as shown in FIG. Note -34- This paper size applies to China National Standard (CNS) Α4 size (210X 297mm) binding

Line 540086 A7 B7 V. Description of the Invention (32) The memory device 500 also includes a memory storage medium 211, which is formed adjacent to and directly contacting the P-silicon film 504 and the N + silicon film 506, as shown in FIG. Adjacent and in contact with the charge storage medium 211 is a control gate 218. In addition, similar to the transistors 100, 200, 300, and 400, when the gated diode 500 is connected to "on", the current (I) is orthogonal to the surface (xy) of the substrate 501 (the memory device 500 is formed thereon). In the direction ⑵, it flows from the P + silicon film 502 to the N-type silicon film 506. Although devices 200-500 have been shown to have a charge storage medium including a continuous film floating gate 214 isolated by a tunneling dielectric 212 and a control gate dielectric 216, the floating gate may not necessarily be formed by a continuous Is formed by a conductive silicon film or a metal film, and a plurality of electrically isolated nanocrystals 602 (as shown in FIG. 6) may be used instead. Nanocrystals are dusters or crystals of electrically conductive material that are electrically isolated from each other. The use of nanometer crystals for floating gates has an advantage: because they do not form a continuous film, nanometer crystal floating gates are extremely self-isolating. The nanocrystal 602 enables multiple self-isolated floating gates to be formed around a single silicon body 206. For example, for a square or rectangular guide post, a floating gate can be formed on each side of the silicon body or channel. A single square guide post can form four or more isolated floating gates. In this way, multiple bits can be stored in each guide pillar memory. Similarly, because nanocrystals form a discontinuous film, floating gates can be formed after two or more stages of pillars are formed, without having to worry about a cell-level floating gate and its immediate vicinity above or below it. (Ie, vertically adjacent) the floating gates of the cells are shorted. There is another good thing about using nanometer crystals for floating gates: the charge leakage they suffer is the same as that of continuous film floating gates. The nanocrystal 602 may be formed of a conductive material such as silicon, tungsten, or aluminum. It is -35- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of invention (33) The nano crystal must have a material group size smaller than the cell spacing Half to isolate floating gates of vertically or horizontally adjacent cells. That is, the nanocrystal or material cluster 602 must be small enough that a single nanocrystal 602 cannot bridge vertically or horizontally adjacent cells. Using chemical vapor deposition to decompose silicon source gases (such as silane) at very low pressures, silicon nanocrystals can be formed from silicon. Similarly, by chemical vapor deposition, the tungsten source gas (such as WF6) is decomposed under extremely low pressure to form a tungsten nanocrystal floating gate. Also, sputter deposition below or near the melting temperature of aluminum can form aluminum nanocrystal floating gates. In addition, a trap layer (as shown in FIG. 7) formed in the dielectric stack 702 can be used instead of the floating gate isolated by the dielectric to store the charge in the memory device of the present invention. For example, the charge storage medium may be a dielectric stack 702 including a first oxide layer 704 adjacent to a silicon body or channel, a nitride layer 706 adjacent to the first oxide layer, and a adjacent to the first oxide layer 706. The nitride layer is adjacent to the second oxide layer 708 of the control gate 218. Such a dielectric stack 702 is often referred to as an ONO stack (ie, an oxide-nitride-oxide stack) when referenced. If necessary, other suitable charge-trapping dielectric films may also be used, such as osmium + -containing oxide films. It should be understood that by simply inverting the conductivity type of each silicon region in the guide post and maintaining its concentration range, the memory devices 200-500 shown in Figures 2-5 can be made with opposite polarities. With this, not only the NMOS (N-type metal oxide semiconductor) device shown in FIG. 2-5 can be manufactured, but also the PMOS (P-type metal oxide semiconductor) device can be manufactured when necessary. In addition, the silicon film used to form the pillars of the device may be single crystalline silicon or polycrystalline silicon. In addition, the silicon film can be a silicon alloy film, such as doped _-36-_ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇x 297 mm) 540086 A7 B7 V. Description of the invention (34) N-type or P-type conductivity Si-Ge film with the necessary concentration. Furthermore, as shown in Figures 1-3 and 5, the guide posts 108, 208, 308, and 508 are manufactured so that the contacts and the main body are aligned with each other (viewed from the top). To this end, an I / O 204 may be formed first, and then a blanket deposition pillar film stack (eg, N + / PVN +) is formed, as shown in FIG. 8A. The film stack 802 is then masked, and all three films are etched non-isotropically in a single step (as shown in FIG. 8B) to form a guide post 804. The explicit guide post forming step can form guide posts having any shape. For example, the guide post 804 may be a square (viewed from above) as shown in FIG. 8B, or may be a rectangle or a circle. Alternatively, as shown in FIGS. 9A and 9B, the first and second I / O's may be patterned to intersect, thereby forming a guide post. For example, a first I / O conductor 900 may be blanket deposited first, and then a desired pillar film stack 902 (eg, N + / P- / N +) may be sequentially deposited. The first I / O film 900 and the pillar film stack 902 are then etched to form a plurality of pillar strips 904, as shown in FIG. 9A. During the subsequent processing to pattern the second I / O, the second I / O 906 is etched in the orthogonal or orthogonal direction of the plurality of guide bars 904. The etching step of patterning the second I / O 906 is continued to etch away the portion of the pillar film stack 902 in the pillar 904 that is not covered or masked by the second I / O 906. Accordingly, the guide pillar 908 is formed at the intersection of the first and second I / O's. The guide post 908 is formed by directly aligning the intersection or overlap of the first and second I / O's. The intersection technique for forming the guide post is advantageous because it eliminates the addition of a lithography step. The charge storage medium of the memory device of the present invention can be formed using a "spacer etching" technique. For example, as shown in FIGS. 10A-10E, a guide post 1000 or a guide post bar is first formed. Then, a first tunneling dielectric 1002 is blanket deposited on the guide pillar 1000. _-37-_ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 540086 A7 B7 V. Description of the invention (35). Next, a floating gate material 1004 is blanket deposited on the first tunneling dielectric 1002. The floating gate material is deposited to a thickness that is necessary for the floating gate. The floating gate material may be a nanocrystal or may be a continuous conductive film. Then, the floating gate material 1004 and the tunneling dielectric 1002 are returned isotropically, and the floating gate material on a horizontal surface (such as the top of the guide post 1000 and between adjacent guide posts) is removed to A floating gate 1008 is left, which is isolated by the pillar 1000 or the tunnel dielectric on the sidewall of the pillar. If the floating gate is made of a conductive film instead of nanometer crystals, care must be taken to ensure that the floating gate material 1004 is completely removed from adjacent cells in order to isolate the floating gate 1008 of adjacent cells. It should be understood that when the floating gate is made of nanocrystals, or when the charge storage medium is a trapped dielectric, the film need not be etched from the horizontal surface between adjacent cells, because these films are not electrically coupled to adjacent unit. However, if necessary, the charge can be trapped non-isotropically with dielectric and nanocrystalline floating gates. Secondly, as shown in FIG. 10C, a control gate dielectric 1006 is blanket-deposited on top of the floating gate 1008 and the top of the guide pillar 1000. The control gate can also be formed using a "spacer etch" technique. In this case, a control gate material 1010 (such as doped polycrystalline silicon) is blanket deposited on the control gate dielectric 1006 to a necessary thickness for a pair of control gates, as shown in FIG. 10D. Show. The gate material 1010 is then etched back non-isotropically (as shown in FIG. 10E), and the horizontal surface (such as the top of the control gate dielectric 1006 and the adjacent pillars or pillars) is controlled. The 1-gate material 1010 is removed to form a control gate 1012 adjacent to the control gate dielectric 1006. The control gate dielectric 1006 protects the silicon pillar 1000 under the protection, so that it is free from the control gate material -38- This paper size is applicable to the national standard (CNS) A4 specification (210X297 mm) 540086 A7 B7 Five inventions Explanation (36 Isotropic etching during the isotropic etching. The floating gate must be isolated from adjacent cells, but the control gate can be shared by horizontal or vertical adjacent cells. Use lithography to form a connected level The conductor bars of adjacent transistors can be used to obtain a horizontally shared control gate. Or, as shown in Figures 11A-11C, the horizontal coupling of the Zheng unit can be achieved. This is to correctly control the interval between adjacent units 1100. Therefore, there is a minimum interval 1102 between the control gates to couple the saponins, and there is a large gap 1104 between the units to be isolated by the control gates, as shown in Figure 11a. When the gate material 1106 is deposited, it will fill the smallest or small gap between adjacent cells, while the large gap 1104 between the cells to be isolated will leave only a thin film, as shown in the figure. Thin control gate material in large gap during isotropic etching The king is removed to isolate adjacent cells, while the thicker control gate material 1106 in the small gap is left with a portion of 1108. In order to bridge adjacent cells and couple horizontally adjacent cells, as shown in Figure 11C In addition, after two or more stages of guide pillars have been formed, a control gate plug can be formed between adjacent units to achieve vertical sharing of control gates, as shown in Figures 12A and 12B. A pole plug can be formed by blanketly depositing a conductive film, such as a doped polycrystalline silicon film or tungsten film 1200, on top of two or more stages of pillars and between them, and then planarizing or patterning the tungsten film in the conductive layer. The part above the pillars forms a plug between the guide pillars. In this way, the control gate will be shared by the device on two or more vertical planes and between horizontally adjacent cells. A method for integrating the pillar-type memory device of the present invention into a multi-level memory cell array. As shown in FIG. 13, the manufacturing process begins by providing a substrate 1300 ′ on which a multi-level memory device array is to be formed. L · _-39- The standard of this paper CNS) Μ specifications (21G x 297 public love)

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540086 A7 B7 V. Description of the invention (37) A thinly doped single crystal silicon substrate 1302, in which a transistor such as a metal oxide semiconductor (MOS) is formed. These transistors can be used, for example, to access transistors, or they can be coupled together into a circuit to form (for example) a charge pump or a sense amplifier for the manufactured memory device. The substrate 1300 also typically contains multilevel interconnections and interlayer dielectrics 1304, which are used to couple the transistors in the substrate 1302 together into a functional circuit. The top surface 1306 of the substrate 1300 typically contains an insulating layer or a passivation layer to protect the underlying transistors and interconnects from contamination. The top surface 1306 typically includes electrical contact pads, and the multi-level memory device array of the present invention can be electrically coupled thereto for electrical contact with transistors in the silicon substrate 1302. In a specific embodiment of the present invention, the memory device is physically isolated and separated from the single crystal substrate by a multi-level interconnection and a dielectric 1304. The top surface of the passivation or insulation layer 1306 is typically planarized, enabling the multi-stage charge storage device of the present invention to be manufactured uniformly and reliably. Fig. 13A shows a cross-sectional view through the substrate, and Fig. 13B illustrates a perspective view of the substrate, which is viewed from above the plane spanned by the substrate 1300 when the device of the present invention is manufactured. According to a specific embodiment of the present invention, the memory device is physically separated from the single crystal silicon substrate 1302. In an alternative embodiment of the invention, the memory device can be fabricated on a glass substrate 1300, such as those used in flat panel displays. According to a specific embodiment of the present invention, the process of forming a multi-level memory device array begins by blanketly depositing a first conductor layer 1308 on the surface 1306 of the substrate 1300. The conductor 1308 may be any suitable conductor, such as (but not limited to) titanium silicide, doped polycrystalline silicon, or a metal such as aluminum or tungsten and its alloy (formed by a suitable technique). The conductor layer 1308 is used, for example, as a bit line or a word line, and together as a column or a row of the memory device. Secondly, the paper size applicable to China Paper Standard (CNS) A4 (210 X 297 mm) 540086 A7 B7 is applicable to this paper size. 5. Description of the invention (38) The blanket deposited film stack 1310 on the body 1308 (such as FIG. 13A), and the first-stage guide post is to be manufactured therefrom. For example, in a specific embodiment, the pillar system includes an N + source / drain region, a P-silicon body, and an N + silicon source / drain region. A suitable film stack 1310 can be formed by first depositing an amorphous silicon film blanket by chemical vapor deposition (CVD), and the film is doped with N-type impurities to 1 X 1019 to 1 X in situ. Doping density of 102G atoms / cm3 (preferably 1 X 1019 to 1 X 1021). Secondly, a P-silicon film is deposited on the N + silicon film 1312. For example, this is a chemical vapor deposition method to deposit an amorphous silicon film, and the film is in-situ with P-type impurities (such as boron ) Doping to a dopant density of 1 X 1016 to 1 X 1018 atoms / cm3. An N + silicon film 1316 is then blanket deposited on the P-silicon body 1314, which is an amorphous silicon film deposited by chemical vapor deposition, and the film is doped in situ to 1 X 1019 to 1 X 102G. Atomic / cm3 (preferably 1 X 1019 to 1 X 1021). These amorphous silicon films are then converted into polycrystalline silicon by subsequent annealing. In addition to in-situ doping, another option is to deposit the film stack with un-doped silicon, and then implant or diffuse with ice doping. It should be understood that other film memory devices of the present invention can be manufactured by depositing appropriate film stacks to obtain the guide pin configuration of the device, which has configurations such as N + / Si〇2 / N + stacks (to form the structure shown in FIG. 3A). Device 300), such as metal / silicon / metal strips (to form the device 400 shown in FIG. 4) and P + / P- / N + stacks (to form the device 500 shown in FIG. 5). Next, as shown in FIGS. 14A and 14B, the blanket deposited film stack 1310 and the metal conductor 1308 are patterned using well-known lithography and etching techniques to form a plurality of conductor strips 1318. The film of the deposited film stack 1310 and the metal conductor 1308 are aligned and etched to each other to form a guide bar with vertical sidewalls. _ -41 -__ This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 540086 A7 B7 V. Description of the invention (39) Secondly, as shown in Figures 15A and 15B, if necessary, the substrate Accept the threshold adjusting ion implantation step to replace the doping density of the surface or surface of the P-type silicon region on each strip. That is, at this time, a first ion implantation step 1315 may be performed, and a surface of the guide pillar 1318 may be implanted with a P-type dopant to increase its P-type doping density, or an N-type dopant may be used. To reverse doping to reduce its P-type doping density. Similarly, after the first implantation 1315, the substrate may be rotated and subjected to a second ion implantation step 1317 to replace the opposite side or opposite doping density on the guide bar 1318. The threshold adjustment implant should have a sufficient dose to replace the threshold voltage of each side in order to fully distinguish or sense the individual readout currents associated with each side. The angle of the ion implantation step is selected so that the implantation generally enters the surface of the P-type body 1314. The angle of placement depends not only on the spacing of the guide bar strips 1318, but also on the strip height. Next, as shown in FIGS. 16A and 16B, on the portion of the substrate 1300 between the guide post bars 1318, a tunnel dielectric 1320 is also formed on the side walls and the top of the guide post bars 1318. The tunneling dielectric may be an oxide, a nitride, an oxynitride, or other suitable dielectric. The tunneling dielectric 1320 should be deposited by a plasma deposition method or a growth process. The temperature is preferably less than 750 ° C and preferably less than 600 ° C. The thickness and quality of the tunneling dielectric 1320 prevent breakdown & leakage under operating conditions. Secondly, FIGS. 16A and 16B also show that a floating gate material 1322 is blanket deposited on the tunneling dielectric 1320. In a preferred embodiment of the present invention, the floating gate material is made of nanocrystals. The smash is deposited so that the smash has a very high surface diffusivity relative to its sticking coefficient, thereby forming silicon nanocrystals. For example, ___- 42-_ This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 540086 A7 B7 V. Description of the invention (4〇) Silicon nanocrystals can be obtained by chemical vapor deposition (CVD), which decomposes silane (SiH4) under very low pressure (1 millitorr to 200 millitorr) and the temperature is 250-650 ° C. In such processes, very thin deposits (50-250 angstroms) will form small silicon islands 1322. If H2 is incorporated with silane during sedimentation, higher pressures can be used while still obtaining nanocrystals. In an alternative embodiment of the present invention, metal nanocrystals (such as aluminum nanocrystals) can be formed, which are formed by sputtering a metal target, and the temperature is about the melting temperature of the metal; to sinter the metal Nano-crystals are formed. Tungsten nanocrystals can be formed by using a chemical vapor deposition method using a reaction gas mixture containing a tungsten source gas such as WF6 and germane [GeH4]. In another embodiment of the present invention, a continuous floating and moving gate material film can be deposited and then precipitated (by heating) to form silicon islands in the film. It should be understood that nanometer crystals are better for floating gates because of the self-isolating quality of nanocrystals. Nevertheless, continuous films can still be used to form floating gates, such as (but not limited to) metals (such as Tungsten), or a silicon film (such as polycrystalline or amorphous silicon doped to the necessary conductivity type, N + silicon is typical for N + / P- / N + pillar systems). If a continuous film is used as the floating gate material 1322, the film 1322 will be etched non-isotropically at this time, and the portion of the floating gate material 1322 between the guide post bars 1318 will be removed, and the guide post bars will be electrically isolated. . Next, as shown in FIGS. 16A and 16B, a control gate dielectric 1324 is blanket deposited on the floating gate material or nanocrystal 1322. The control gate dielectric 1324 is a deposited oxide or oxynitride (for example) dielectric film, which is formed by a plasma enhanced deposition process to reduce the deposition temperature. The control gate dielectric 1324 is similar in thickness to the tunneling dielectric 1320, but slightly thicker (eg, 20-30 angstroms). Control gate dielectric 1324 is used to make the floating gate and a subsequent control _ ^ _- 43-_ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Line 540086 A7 B7 V. Description of the invention (41) The gate is isolated. The thickness and quality of the control gate dielectric depends on the programmed threshold voltage used for programming and non-programming the memory cells. As discussed above, not only the thickness of the P-type silicon body or channel, but also the thickness of the tunneling dielectric, depends on the necessary stylized voltage. Next, as shown in FIGS. 17A and 17B, a control gate material 1328 is blanket deposited on and above the guide bar 1318. The gate material is controlled to a thickness of at least enough to fill the gap between adjacent strips. Typically, if a conformal film is deposited at least half the width of the gap 1330, the J, J guarantees that it will fill the gap 1330. In a specific embodiment of the present invention, the control gate material 1328 is a doped polycrystalline silicon film, and is formed by a chemical vapor deposition method. Alternatively, the control gate can be formed by other conductors, such as a blanket deposited tungsten film formed by WF6 by chemical vapor deposition. Second, as shown in FIGS. 18A and 18B, the control gate film 1328 is planarized by, for example, chemical mechanical polishing, until the top surface of the control gate is substantially flat and the top of the guide bar 1318 is controlled. Gate dielectric. A plasma etching process is then used to make the top surface of the control gate material recess 1331 below the top surface of the guide bar 1318, and it is better to etch it slightly above the top source / body junction (for example, The interface between the N + silicon film 1316 and the P- silicon film 1314), as shown in FIG. 18A. Control gate dielectric 1324 on top of guide post 1318 protects guide post 1318 from recessed etch

Eroded during this period. After the recess etching, the control gates 1332A and B are formed. Secondly, an interlayer dielectric (ILD) 1334 (such as an oxide) is not only blanket-deposited into the recess 1331 above the control gate 1332, The blanket is also deposited on top of the guide bar 1318. Then control the gate dielectric, nanocrystalline __- 44 -__ This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (42) The tunneling dielectric on the top of the body and the pillar 1318 will similarly grind or etch back the deposited oxide layer 1334 (as shown in Figures 19A and 19B) To expose and open the surface of the top source / drain region (eg, N + film 1316) of each guide bar 1318. Secondly, as shown in FIGS. 20A and 20B, a second conductive layer 1336 is not only blanket-deposited on the ILD 1334, but also blanket-deposited to contact the top source / drain region (eg, N + source / Drain region 1316). The second conductor layer 1336 is used to form a second input / output (eg, a bit line or a word line) for the first-level memory device; and will be used to form a first input / output (eg, Bit line or word line) for second-level memory devices. The second conductive layer 1336 can be formed of a material similar to the first conductive layer 1308 to a similar thickness. Second, a film stack 1338 (such as an N + / P- / N + stack) is blanket deposited on the second conductive layer 1336. ) To form a second-level guide post, as shown in FIGS. 20A and 20B. The film stack 1338 can be formed from the same material as that used for the film stack 1310 and has a similar thickness. Alternatively, if it is necessary to have a different memory device type, a film stack corresponding to this device type will be formed. Secondly, as shown in FIGS. 21A and 21B, the second guide pillar stack 1338 and the second conductor layer 1336 are patterned by well-known lithography and etching techniques to form orthogonal or orthogonal to the first plurality of guide pillar bars 1318 of a plurality of second guide bars 1340. It should be understood that the second guide pillar stack 1338 film and the second conductor layer 1336 film are aligned with each other and etched to form guide pillar strips with vertical sidewalls. Figure 22λ ^ 22B shows the substrates of Figures 21A and 21B rotated by 90 °. Once the second pillar film stack 1338 and the second conductor 1336 have been etched and patterned into the pillar bars 1340, the etching is continued to remove the first pillar bar 1318. The paper standard is applicable to Chinese national standards CNS) Α4 size (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (43) The part 1341 covered or covered by the second guide post 1340 (shown in Figures 22A and 22B). Etching continues until the first conductive layer 308 is reached. Thus, as shown in FIGS. 23A and 23B, at the intersection or overlap of the first and second I / O 1308 and 1336 (Ml and M2 shown in FIG. 23A), the first-level square or rectangular guide post 1342 is Formed by the first guide bar 1318. In a specific embodiment of the present invention, a square guide pillar with a width of less than 0.18 micrometers (• um) is formed. It should be understood that the etching step used should be capable of selectively engraving the guide bar to pass ILD 1334 and pass through and control the gate dielectric. For example, if the pillar contains doped silicon, and the ILD and the tunneling and control gate dielectrics are oxides, the plasma etching method uses CL and HBr to etch silicon, but does not significantly etch the oxide ILD. Or tunnel and control the gate dielectric. It should be understood that the ILD 1334 protects the underlying silicon control gate 1332 from etching, as shown in FIG. 23C. In addition, the purpose of ILD 1334 is to electrically isolate the control gate 1332 from the control gates that are subsequently formed for the second-level guide post. At this time, if necessary, the substrate can be subjected to a continuous ion implantation step to replace the doping density of each newly exposed surface of the P-type body 1314 of the guide pillar 1342 (see FIG. 23A) in order to replace the doping on each side. The density changes the threshold voltage of each side. Next, as shown in FIG. 24, on the substrate 1300, a tunnel dielectric 1344, a nanocrystalline floating gate material 1346, and a gate dielectric 1348 are successively deposited, not only along the The side wall of the second guide post 1340 is also formed on the side wall of the guide post device 1342, forming a tunneling dielectric / nano crystal floating gate / control gate (see FIG. 23A). Moreover, this film stack is not only formed on the first conductor 1308 between the first-stage guide posts 1342 and on the ILD 1334, but is also formed along the top surface of the second guide post 1340. -46-This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 1-

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Line 540086 A7 B7 V. Description of the invention (44) From the gap 1343 between adjacent guide posts 1342, to remove the floating gate material to isolate the guide posts, it is not necessary to etch the floating gate non-isotropically. This is because the floating gate material is electrically conductive, but the discontinuous nature of the nanocrystals isolates the pillars. In this way, the tunneling dielectric, the floating gate 1346, and the control gate dielectric can be used to isolate the control gate and the first metal conductor formed later. In addition, since the floating gate 1346 is formed of a nanocrystal, it is self-isolated from the floating gate directly above the second stage, even if they are formed at the same time. Next, as shown in FIG. 25A, not only in the gap 1343 between the guide posts 1342, but also between the second guide post bars 1340, a control gate 1350 is formed. The control gate can be formed as discussed in FIGS. 17-20 above, and it is blanket-deposited with a control gate film (such as doped polycrystalline silicon) instead of filling the gap between the second guide pillars 1340. The ground also fills the gap 1343 between adjacent guide posts 1342. Then, if necessary, the control gate film can be ground and recessed under the top surface of the N + source / drain region, and a second ILD 1352 is formed at the recess (as shown in FIG. 25A). More layers. The ILD 1352 and the tunneling dielectric / floating gate / control gate dielectric on top of the second guide post 1340 are then reground to reveal the top N + source / drain regions of the guide post 1340. At this time, the first-level memory device is completed. Each guide post 1342 on the first stage contains a separate floating gate and a control gate on each of them, and there are a total of four independently controllable charge storage regions, as shown in FIG. That is, as illustrated in FIG. 26, the guide post 1342 includes a first control gate pair 1332A and B, which are formed by the lateral tiles along the opposite side walls of the guide post 1342. Control gates 1332A and B are also shared by horizontally adjacent guide posts. The guide post 1342 also contains a second control gate pair 1350A and B, which is transversely aligned along the opposite third on the guide post 1342. Mm)

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540086 A7 B7 Description of the invention (formed on the 45th and fourth sides. Each control gate 1350 will be shared not only by horizontally adjacent guide posts 1342 in the same stage, but also in the second stage formed later in the vertical The above guide post memory device is shared. Because guide post 1342 includes four independently controllable control gates and four associated and isolated floating gates, each guide post memory device 1342 can store more The process illustrated in Figure 20-25 can be repeated to make a memory device on the second stage and start manufacturing a memory device on the third stage. That is, as shown in Figures 27A and 27B (Figure 26 is rotated 90 ° ), The steps of FIGS. 20-25 can be repeated to form a third guide post 1360 orthogonal to the second guide post 1340. These steps are used for the second guide post 1340 on the second stage. The figure is transformed into a plurality of second guide posts 1362, and a second control gate pair 1364 is formed adjacent to the second guide posts. Thus, a second-level memory guide post 1362 is manufactured, which includes four independent Controlled control gate and four floating gates that are isolated together. A first control gate pair 13 50A and B are formed laterally along the opposite two side walls on the second-stage guide column 1362, and are not only shared by the horizontally adjacent units, but also shared by the memory guide column 1342 on the first stage. The second control gate pair 1364A and B are formed laterally along opposite third and fourth faces on the second-stage guide post 1362, and are shared by the subsequent-formed guide posts in the third stage of the memory array. The process described above can be repeated as many times as necessary to add more stages of column-type memory to the array. The last-level memory unit can be patterned as the last I / O W by a column of stacked columns. Although the second embodiment of the present invention is integrated into a three-dimensional memory array as shown in a specific preferred embodiment, it should be understood that Paper size applies Chinese National Standard (CMS) A4 specification (210 X 297 mm)

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Line 540086 A7 B7 V. Description of the invention (46) Deviating from the spirit of the present invention, other methods can also be used to manufacture the three-dimensional memory array. 2. A memory cell utilizing a charge storage body located above or below a conductor region. In FIG. 29A, the cell includes a diode and a stack containing regions 2921, 2922, and 2923. Region 2921 contains a first dielectric-region; region 2923 contains a second dielectric-region. Arranged between these areas is a storage area 2922, which is used to trap charges. It is mainly this area that retains the charge and thus provides the "memory" of the cell. As will be discussed below, the charge may be electrically placed in the region 2922 to undergo an inductive measurement, and electrically removed from the region 2922. The region 2921 contains an oxide, typically having a thickness of 1-5 nm, and more preferably 2-3 nm. In a specific embodiment, the region 2921 referred to in this application refers to a tunneling dielectric. Region 2922 is a region that stores trapped charges, such as nitride regions, and is known in the art (discussed in more detail below). In a specific embodiment, the region 2922 referred to in this application refers to storage dielectric. Region 2923 may contain an oxide and act as a barrier to retain the trapped charge. In a specific embodiment, the region 2923 referred to in this application refers to a blocking dielectric. The region 2923 may have a thickness similar to that of the region 2921. Once a breakdown occurs, the electrons carry a forward current in the diode. Therefore, the types of carriers trapped in the tunneling dielectric-storage dielectric interface 2925 and the region 2922 are electrons. Note that the polarity of these electrons will stimulate the premature inversion of the N region in the interface region 2921. In this way, the voltage when the negative resistance part of the cell characteristic first appears will decrease due to the stored electrons, as shown in the curve 2926 versus the curve 2927 in FIG. 29B. -49- The paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the Invention (47) In a specific embodiment, the stylization is composed of: applying a sufficient forward bias to the diode to make the device conductive; and allowing the forward current to continue Long enough for sufficient charge to be trapped, thereby shifting the voltage threshold from the peak forward voltage shown in curve 2927 to the peak forward voltage shown in curve 2926 ^ Although binary programming is discussed next, However, multiple threshold shift values may be used to store multiple bits in each cell. By analogy, some flash memory stores 2-4 bits or more in each unit. A forward voltage falling between the peaks 2928 and 2929 can be applied for reading (sensing). If the current flow exceeds a predetermined threshold, the cell is programmed; if the conduction does not occur, it is unprogrammed; the conductive charge flowing through the programmed cell during the read operation increases the trapped charge. The erasure is achieved by using a reverse bias voltage sufficiently applied to the memory cell to cause the electrons to tunnel out of the trap and pass through the blocking oxide 2923; or through the hole current to neutralize the trapped electrons. This effect must require the diode to operate under breakdown, so the erase voltage must be at least the lowest point of the breakdown voltage. A. Two terminal units in a substrate As shown in FIG. 30, the memory unit of the first embodiment of the present invention is arranged in a P-type substrate 2930. In the substrate, a diode (a steering element of the unit) is formed, which includes: an n-region 2932 doped to 5 × 1016-1018 / cm 3 (for example); and, A ρ + region 2931 is doped to > 1019 / cm3, and is formed in the η- region 2932. These areas can be formed by cooked stone methods such as diffusion or ion implantation. A storage stack is formed on region 2932, which includes a dielectric (eg, oxide) region 2933, a trapping layer 2934, and a second dielectric (eg, oxide) region -50-This paper size applies China National Standard (CNS) A4 Specification (210 X 297 mm) 540086 A7 B7 V. Description of Invention (48) Domain 2935. The dielectric region 2933 can be a grown oxide layer or a deposited silicon dioxide region. If oxides are included, this area can be 1-5 nm thick. These areas can be formed by ordinary processing. The trapped area 2934 and other trapped areas discussed in this application may be formed from other materials than nitrogen compounds. In the prior art, silicon nitride (nitride) is the most common in this application. Other available nitrogen compound layers are oxynitride (ON) and oxide-nitride-oxide (ONO). Other materials (alone or in combination) that exhibit charge trapping properties can also be used. By way of example, alumina (ΑΙΑ;) and silicon dioxide with insulated polycrystalline silicon regions exhibit these characteristics. The capture area is generally 2-20 nm thick, and preferably 3-10 nm thick. The thickness of the regions 2933 and 2934 is determined by well-known factors in SONOS memory technology. For example, the tunneling dielectric region must be thin enough so that there is no excessive voltage drop under the tunnel for longevity; the trapped dielectric region must be thick enough to not allow considerable charge to spontaneously detrap. . As mentioned above, for oxide region 2933, the typical thickness is in the range of 1-5 nanometers, and preferably 2-3 nanometers; for nitride-captured layers, it is 3 -10 nm. The layer 2935 is an oxide or other dielectric region and may have the same thickness as the region 2933. Other dielectrics that can be used include perovskites, ceramics, diamonds (and diamond-like films), silicon carbide, and undoped silicon (including polycrystalline silicon). "This region can be formed by well-known deposition techniques. As previously mentioned, all The referenced region 2933 refers to a tunneling dielectric layer that results in (at least in part) the negative resistance characteristics previously discussed. On the other hand, the layer 2935 prevents the charge from the region 2934 from leaking (to be true_-51 -_ This paper size uses Chinese National Standard (CNS) A4 (210X 297mm) binding

Line 540086 A7 B7 V. Description of the invention (49) For example) to contact 2938. Therefore, the layer 2935 is sometimes referred to as a blocking dielectric. Storage stacks with regions 2933, 2934, and 2935 can be manufactured in a single continuous process, replacing gas mixtures in the deposition chamber: by way of example, oxides are provided first, then nitrides, and finally oxides. Due to the relative thickness of these areas, the entire stack can be placed in about a few seconds. In order to operate the cell of FIG. 30, it is first assumed that the trap layer is neutral when manufactured, that is, there is no trapped charge in the trap region 2934. In order to place the electric charge in the region 2934, the anode contact 2937 is made to a positive potential with respect to the contact 2938, and the diodes defined by the regions 2931 and 2932 are forward biased until the potential reaches the potential shown in FIG. Voltage up to 2929. Tunneling now occurs not only through oxide 2935, but also through oxide 2933; the charge is trapped within region 2934. The amount of charge trapped depends on the total charge flow and the trapping efficiency of region 2934. In order to sense the existence of this charge, a second electric charge is applied between lines 2937 and 2938 to forward-bias the diodes defined by regions 2931 and 2932. However, the potential at this time is within a range larger than the voltage 2928 shown in FIG. 29B and smaller than the voltage 2929. If the current flows beyond a predetermined threshold, it is known that the charge is trapped in the area 2934. On the other hand, if such a current does not flow, it is known that there is little or no charge storage in this layer. Thus, for the case of binary data, it can be determined whether the unit is programmed or unprogrammed. As mentioned earlier, different levels of charge can be placed in the trapping layer 2934, and the voltage at which this current flow occurs (for example, between voltages 2928 and 2929) can be measured. This corresponds to the electricity that can be used when providing more than one bit of data from individual units in layer 2934. f 0 -52- This paper size applies to China National Standard (CNS) A4 (210X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (50) It should be noted that during the readout operation, the readout current passes through a stylized unit and then passes through the area 2933, the trapped area 2934, and the oxide area 2935. This is not like a typical readout; a typical readout uses charge to shift, for example, the threshold voltage in a field effect transistor, and when the cell state is read, the current does not pass through the trapped charge region itself. As mentioned earlier, when the current passes through the area 2934 for reading, the current actually supplements the cell again; that is, if the cell was originally programmed, it will remain programmed when the data is read. When reading data from the unit, care must be taken not to exceed the current represented by line 2924. If a current exceeds this limit, such as 500 (M0,000 Amperes per square centimeter (amps / cm2), one or both of the Bay 1J oxide regions 2933 or 2935 will be permanently damaged and may have a short circuit or an open circuit. In order to erase The information in the unit is the reverse bias of the diode: that is, the anode is made negative with respect to the cathode. If a sufficient potential is applied, the diode will collapse (eg, avalanches, Zeners ] Collapse or break through) and deprive charge from area 2934. The substrate 2930 may have to be floated during erasure to prevent the junction between the layer 2932 and the substrate 2930 from being forward biased. Other isolation methods, such as shallow Trench isolation (STI) or "Silicon on Insulator (SOI)" can also be used. B. Three-terminal unit in the substrate In Figure 31, the unit does not have a field effect transistor, which contains source and drain regions and gates. The poles 2946 and regions 2941 and 2942 are formed by aligning the gates 2946 in the substrate 2940, as is well known in the art. A stack is formed on the region 2941, which contains a hafnium oxide region 2943, a trapped region 294, and oxidation. Object area 2945. Areas 2943, 2944, and 2945 can be the same as those in Figure 30. 2933,2934 and 2935. Example domain, rather than a forward bias of a diode in this particular embodiment, the lines to the gate -53-

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The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 540086 A7 B7 V. Description of the invention (51) The pole 2946 applies a positive potential and maintains the contact 2948 relative to the contact 2947 as positive. This is done for the programming and reading of the unit. To erase the cell, the contact 2948 is negative with respect to the contact 2947, and the trapped charge is removed from the region 2944. For the specific embodiments of Figs. 30 and 31, in some memory arrays, it may be more necessary to erase one array at a time through the substrate by reverse biasing, for example, reverse biasing the region 2941 and the substrate 2940. When necessary, the cells of FIGS. 30 and 31 may be formed on the substrate without being in the substrate, and / or stacked in three dimensions. C. Three-dimensional specific sound examples of the use of stacked rails _ US Application Serial No. 0 / 560,626 (filed on April 28, 2000), and some of its co-pending applications-US Application Serial No. 09 / 814,727 (proposed on March 21, 2001), both cases assigned the assignee of the present invention, and the title is "Three-Dimensional Memory Array Method of Fabrication"; it discloses a method manufactured in A three-dimensional memory array on a substrate and stacked using a guide " can use the technology described in this patent application to build a three-dimensional charge trapping or storage memory according to the present embodiment of the present invention, as discussed below. Shown in FIG. 32 are three full stages of a memory array, specifically stages 2950, 2951, and 2952. Each stage contains a plurality of parallel and spaced apart rail stacks. The rail stacks 3 and 5 of FIG. 32 extend in a first direction; the rail stacks 4 and 6 extend in a second direction, which is typically perpendicular to the first direction. Each of the guide rails of FIG. 32 includes a conductor or an input / output portion at the center thereof, and semiconductor regions are arranged on both sides of the conductor. For the specific embodiment of FIG. 32, the first alternate rail stack (for example, rail stacks 3 and 5) is fabricated from n-type polycrystalline silicon disposed on these conductors. The second alternate guide ___-54-This paper size is in accordance with Chinese national practice ~ ^ (CNS) Α4 size (210X297 mm)

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Line 540086 A7 B7 5. Description of the Invention (52) The rail stacks 4 and 6 have p-type polycrystalline silicon on their conductors. More specifically, see rail stack 5, which includes: a center conductor or input / output 2953, for example an aluminum or silicide conductor; n + regions 2954 and 2956, arranged on both sides of the conductor; and, η-region 2955 and 2957 are located in areas 2954 and 2956, respectively. The n + region can be doped to a level of> 1019 / cm3; the N- region can be doped to 5 × 1016-1018 / cm3. Furthermore, the guide stacks 4 and 6 include a conductor or input / output, such as conductor 2960, with ρ + regions on both sides of the conductor (shown as ρ + regions 2961 and 2962 on one of the rail stacks). The manufacture of these areas and the entire stack is described in the application cited above; this application is incorporated herein by reference. The application cited above uses a blanket of antifuse material in the stack of guide rails. For the purposes of the present invention, three blankets are used between each stage of the rail stack. Specifically, a layer 2963 is arranged between the rail stacks 5 and 6; a layer 2964 is arranged between the rail stacks 4 and 5. Layers 2963 and 2964 correspond to, for example, layers 2933, 2934, and 2935 of FIG. Thus, the layer 2964 includes a dielectric (eg, oxide) layer 2966, which may be 1-5 nanometers thick, and preferably 2-3 nanometers; a trapping layer 2967, such as a silicon nitride layer, The thickness may be 2-20 nm, and preferably 3-10 nm; and, a dielectric (eg, oxide) layer 2968 may be similar in thickness to layer 2966. The materials used to form the regions 2933, 2934, and 2935 of FIG. 30 can be applied to the layers 2966, 2967, and 2968 of FIG. 32. The cells in the array of Figure 32 are generated at the intersection of the rail stacks. For the specific embodiment of FIG. 32, the storage stack is disposed between the p region and the n region of the diode. That is, the storage stack is embedded in the guide element. For example, the conductor 2960 makes a cell accessible via the p-region 2961. The layer 2963 is arranged in the ρ area _; _-55 -__ This paper size is applicable to the China National Standard (CNS) A4 specification (210 X 297 mm) binding

Line 540086 A7 B7 V. Invention Description (53) 2961 and η-zone 2955. The other contact of the two terminal unit passes through area 2954 to conductor 2953. The cell of Figure 32 is programmed, read, and erased in the same way as the cell of Figure 30 above. With the configuration of Fig. 32, the diodes between two adjacent pairs of memory arrays "point" to a common conductor. More specifically, as illustrated in FIG. 32, at the level of the memory array 2950, the cathode is connected to the conductor 2953. The cell illustrated in memory level 2951 has a cathode connected to a conductor 2953 as well. Since the conductor 2953 is used for two sets of units, manufacturing, stylization, reading and erasing are simplified because of this. In the application cited above, there are several specific embodiments with different configuration of the guide pillars. The three-dimensional array is used The preferred storage stacker of the present invention can be manufactured using these specific embodiments. D. Three-Dimensional Specific Embodiment Using a Guided-Pole Diode Structure U.S. Patent No. 6,034,882 discloses a three-dimensional memory array using a plurality of stages, each stage having parallel spaced apart conductors. The guide systems on these alternating levels are perpendicular to each other. The pillar structure is formed at the intersection of adjacent-level conductors. As described in the patent, the structure is formed by alignment of conductors. If the cells used in the memory array contain the charge storage or trapping area of this embodiment, the array can be manufactured using the manufacturing technology described in this patent. Referring to FIG. 33, illustrated is a single stage of three-dimensional memory. At one level of the array, there is a conductor or input / output 2981, and at the next level, there is a conductor 2980. A guide post structure is formed by aligning 2980 and 2981. According to the present invention, the guide post structure forms a unit. In particular, referring to Figure 33, this unit contains a guide element -56-

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The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 540086 A7 B7 5. The invention description (54) pieces, and the guide element contains a junction diode, and the junction diode Contains p + region 2982, n-region 2983, and storage stack. As shown in Figure 33, the storage stack includes a tunneling oxide region 2984, a trapping 2986 region, and a blocking oxide 2985. As explained in the above patent, the single unit shown in Fig. 33 shares conductors 2980 and 2981 with the units arranged above and below. Fig. 34 shows another embodiment. Here there are spaced apart parallel conductors or input / output (such as conductor 2991) on one level, and parallel spaced apart conductors on the next level (such as conductor 2990). As described in the above cited patent, a guide post structure is manufactured between the conductors 2990 and 2991. However, the difference between the structures of Figs. 33 and 34 is that the storage stack including blocking oxide 2993, trapping region 2994, and tunneling oxide 2995 is disposed between the p region and the n region of the diode. Specifically, the p + region 2992 of the diode is in contact with the blocking oxide 2993, and the n-region 2996 is in contact with the tunneling oxide 2995. The thicknesses of the various regions shown in Figures 33 and 34, and the doping of polycrystalline silicon diodes, may be similar to the specific embodiments previously discussed in this application. The programming, reading and erasing of the structure of Figs. 33 and 34 are also the same as those described in the other embodiments. For the specific embodiments of Figs. 32, 33, and 34, the cell array is disposed on a substrate with peripheral circuits formed therein. II. Self-aligned EEPROM TFT Array Another unit configuration that is different from the guide post configuration is self-aligned TFT. The present inventors truly understand that the inclusion of the loss of emerald in order to allow the features on different layers to completely overlap will increase the area of the memory and logic unit. With this in mind, the inventors have developed a memory or logic cell structure that is perfectly aligned without misalignment tolerances. Therefore, such a unit structure has __- 57-_ per bit (ie, per unit). This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). Binding

Line 540086 A7 ___B7 V. Description of the invention (55 ~ small area and fewer masking steps. The fully aligned unit structure increases the density of the array and reduces the size and cost of the wafer. Also, as the case may be The cells can be stacked vertically in the Z direction to further increase the density of the array and further reduce the size and cost of the wafer. As described in the preferred embodiment of the present invention, there are several different ways to achieve full alignment or self-alignment. Memory or logic unit. Regarding the memory or logic unit containing EEPROM, it can be fully aligned by the self-alignment of the word line with the control gate. Preferably, the word line is approximately parallel to the source-channel of the EEPROM It extends in the direction of a drain, and the bit line extends approximately orthogonally to the source-channel-polar direction of the EEPROM. In this configuration, the bit line can be directly at the source and / or drain region of the EEPROMs. It is formed by aligning the gate (one or more) of the EEPROM on top, so no bit line contact pads (ie, source and drain electrodes) and bit line contact vias are needed. Moreover, EEPROMs are both completely self-contained. Alignment, then The bit lines and word lines may have a substantially planar upper surface; this improves the reliability of the device. Preferably, the EEPROMs are arranged in a three-dimensional virtual ground array (VGA) non-volatile flash memory. TFTs, and each vertically separated stage is separated from an adjacent stage by an interlayer insulation layer. However, EEPROMs can also be formed in a single-stage array or in a bulk semiconductor substrate. This specific embodiment In a better aspect, it can also be applied to non-volatile flash memory architectures other than VGA, such as NOR (inverted-OR) memory and dual-string NOR (DuSNOR) memory. Moreover, the present invention is not limited to TFT EEPROM memory. Flash memory array; within the scope of the present invention, other semiconductor devices are also covered. For example, self-aligned transistors can be MOSFETs in a large substrate, or shape 1 on an insulating substrate _______158J__ 一_ This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 540086 A7 B7 5. Description of the invention (56) non-EEPROM TFTs. These self-aligned transistors can be used as non-flash EEPROMs (that is, · , The included transistors are all Off-ground erase), UV (ultraviolet light) erasable PROMs, mask ROMs, dynamic random access memories (DRAMs), happy crystal displays (LCDs), field programmable gate arrays (FPGAs), and micro Processor. Figures 37-44 illustrate a method for manufacturing a TFT EEPROM non-volatile flash memory array 4001 according to the first preferred embodiment of the present invention. First, an insulating surface (ie, "Silicon On Insulator (SOI)" substrate for memory array formation. The substrate may include a semiconductor (ie, silicon 'GaAs, etc.) wafer, and the wafer is covered with an insulating layer (such as a silicon oxide layer or a silicon nitride layer, a glass substrate, a plastic substrate, or a ceramic substrate). In a preferred aspect of this first embodiment, the substrate is a monocrystalline bulk silicon substrate that has undergone previous processing steps, such as forming a CMOS (Complementary Metal Oxide Semiconductor) transistor in the substrate. These CMOS transistors can include peripheral or driver circuits for memory arrays. In the best aspect, the circuit includes column and row address decoders, row input / output (I / O's), and other logic circuits. However, when necessary, the driver circuit may be formed on an insulating substrate, such as a "silicon on insulator" substrate, a glass substrate, a plastic substrate, or a ceramic substrate. The "fragmentation on insulator" substrate can be formed by any conventional method, such as wafer bonding, "oxygen implant separation (SIMOX)", or an insulating layer formed on a silicon substrate. After the peripheral circuit is completed, an interlayer insulating layer 4003 shown in FIG. 37 is conformally deposited on the circuit. The interlayer insulating layer 4003 may include one or more of any suitable insulating layers, such as silicon oxide, nitride i, silicon oxynitride, PSG, BPSG, BSG, spin-on glass, and / or Polymer dielectric layer (such as polyimide, etc.) ^ The interlayer insulating layer 4003 should be planarized by chemical mechanical polishing (CMP); but in other specific implementations _-59-_ This paper standard applies to Chinese national standards (CNS ) A4 size (210 X 297 mm) binding

Line 540086 A7 B7 5. In the example of the invention (57), it can also be planarized by etch back and / or other means. A semiconductor active area surface layer 4005 is then deposited on the insulating layer 4003 to complete the SOI substrate. This semiconductor layer will be used to power the active area of the crystal. The layer 4005 can have any necessary thickness, such as 20 to 120 nm, and preferably 70 nm; the thickness is selected so that the space charge region under the transistor gate extends in the depletion region , Throughout the entire floor. Preferably, the semiconductor layer 4005 includes an amorphous or polycrystalline silicon layer doped with a first conductivity type dopant. For example, the layer 4005 may be doped in-situ during deposition, or implanted or diffused by ion after deposition to become P-type doped. If necessary, the semiconductor layer 4005 can be heated to improve its crystallinity. In other words, the amorphous silicon layer can be recrystallized to form polycrystalline silicon; or the crystal grain size of the polycrystalline silicon layer can be increased. This heating procedure includes ... heat or laser annealing of layer 4005. If necessary, the crystallinity of the layer 4005 can be improved by catalysis-induced crystallization. In this process, a catalyst element such as Ni, Ge, Mo, Co, Pt, Pd, its fragments, or other transition metal elements is applied to contact the semiconductor layer 4005. The layer 4005 is then subjected to thermal and / or laser annealing. During annealing, the catalyst elements may propagate through the silicon layer and leave large grain residues, or they may be used as seeds at the beginning of silicon crystallization. In the latter case, the amorphous silicon layer is crystallized laterally from a seed crystal by solid phase crystallization (SPC). It should be noted that if a single-crystal SOI substrate is used, the deposition of amorphous silicon or polycrystalline silicon layer 4005 may be omitted. In this case, using the SIMOX method, oxygen ions are deeply implanted in the single crystal silicon substrate 'to form a buried silicon oxide layer therein. Above the buried silicon oxide layer, a single crystal silicon layer remains. Secondly, the impurities on the surface of the active layer 4005 should be removed; and the natural -60-

Line 540086 A7 B7 V. Description of the invention (58) oxide. A charge storage region 4007 is then formed on the layer 4005. In the first preferred embodiment of the present invention, the charge storage region 4007 includes an oxide-nitride-oxide (ONO) dielectric triple layer. This dielectric contains a first (bottomed 0 2 layer (also known as tunneling oxide), a charge storage layer (X is 0 to 1), and a second (topped 0 2 layer (also called blocking). Oxide). The tunneling oxide may be formed by thermal oxidation and grow on the surface layer 4005 of the active area; or by chemical vapor deposition (APCVD, LPCVD, or PECVD) such as atmospheric pressure, low pressure, or plasma strengthening, or Other means, and deposited on the surface layer of the active region. The thickness of the tunneling oxide is 1.5 nm to 7 nm, and preferably 4.5 nm. The charge storage silicon nitride or oxynitride (Si3N4 .xOUx) layer is deposited on the tunneling oxide; its thickness is at least 5 nm, and preferably 5.15 nm, and most preferably 6 nm. The blocking oxide layer is arranged on the charge storage layer Above the surface, the thickness is 3.5 nm to 9.5 nm, and preferably 5.0 nm. The charge storage and blocking layer can be deposited by APCVD, LPCVD, PECVD, or other means (such as sputtering). It should be noted that Depending on the needs, different materials and different layer thicknesses can be used. For example, the formation of a charge storage layer does not have to be determined For example, in an alternative aspect of the first embodiment, the charge staggered layer is formed, and may be a plurality of electrically isolated nanocrystals, such as silicon, tungsten, or aluminum nanocrystals, dispersed in silicon oxide. , Silicon nitride, or silicon oxynitride insulating layer. If a nanocrystalline charge storage layer is used, tunneling and / or blocking of the oxide layer may be omitted if necessary. Form a charge storage region 4007 (ie, ΝΟΟ dielectric) ) After that, a first gate layer 4009 is deposited on the charge storage area ^ The first gate layer 4009 may contain any -61-This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) binding

540086 A7 B7 5. Description of the invention (59) Any conductive layer, such as n + doped polycrystalline silicon. Such a polycrystalline silicon layer may have any suitable thickness, such as 50 to 200 nanometers, preferably 100 nanometers; and any suitable dopant concentration, such as 1019-1021 / cm3, and 102G / cm3 Better. If necessary, a protective layer 4011, such as a protective silicon oxide layer, may be formed on the surface of the first gate layer 4009, as appropriate. The layer 4011 may have any suitable thickness, such as, for example, 3-10 nm, and preferably 5 nm. If necessary, materials other than silicon oxide may be used for the layer 4011. A sacrificial blocking layer 4013 is then deposited on the protective layer 4011. In a preferred aspect of the first specific embodiment, the blocking layer is made of any conductive or insulating material that can be selectively etched (while passing through other layers of the device). The blocking layer 4013 is preferably a silicon nitride-containing layer. The blocking layer can have any thickness. Preferably, the blocking layer 4013 is necessary for controlling all or the upper part of the gate. This will be explained in more detail below. For example, the layer 4013 is 100 to 250 nanometers thick, and more preferably 160 nanometers. Figure 37 shows the device cross section at this processing stage. Second, a reverse bit line mask is used to transfer the bit line pattern to the device wafer or substrate in the process, as shown in Figure 38. In this mask, transparent regions bound the metalines, while opaque (ie, dark) regions bounded the spaces between the metalines. For example, a positive photoresist layer (not shown in FIG. 38) is formed on the blocking layer 4013, exposed through the reverse bit line mask, and developed. Of course, if a negative photoresist is used, the transparent and opaque areas of the mask are reversed. The wart photoetching layer is used as a mask. The mask feature is etched into the blocking nitride 4013, the protective oxide 4011, and the first gate layer 4009 to form a plurality of gate stacks 4015. Onion dielectric 4007 is used as a barrier layer. Then, photoresistance -62- This paper size applies the Chinese National Standard (CMS) A4 specification (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (60) The layer is stripped from the gate gate stack 4015 as shown in the figure. The photoresist can be removed after the blocking nitride 4013 is etched. In this case, the nitride can be used as a hard mask for etching the first gate layer 4009. The gate stack 4015 includes a patterned first gate electrode 4009, an optional protective oxide 4011, and a patterned blocking layer 4013. If necessary, a thin layer of nitrided, oxynitrided, or silicon oxide may be grown to seal the sidewall of the first gate electrode 4009. The transistor source and drain regions 4017 are formed by self-aligned ion implantation using a gate stack 4015 as a mask. The photoresist layer can be left on the gate stack during this implantation or removed before implantation. This ion implanted through the ONO dielectric 4007. However, if necessary, the portion of the ONO dielectric 4007 between the gates 4009 can be removed before the ion implantation. The channel region 4019 of the active layer 4005 is located under the gate electrode 4009. The region 4017 is doped with a second conductivity type dopant, which is different from the first conductivity type dopant of the channel 4019. Therefore, if the channel 4019 is p-type doped, the source and drain regions 4017 are n-type doped and vice versa. Figure 38 shows the equipment in this processing stage. It should be noted that in the memory array, "source" and "drain" are arbitrarily specified. Therefore, the region 4017 can be regarded as a "source" or a "drain", and the terminal voltage depends on which bit line is provided. Moreover, in this memory array, field oxide regions are not used, and each region 4017 is located between two gate electrodes 4009. Therefore, for one gate, a certain area 40 can be regarded as "source"; for the other two gates 4009, it can be regarded as "drain". Secondly, a gate stack side wall spacer is formed on the side wall of the gate stack 4015 -63- This paper size applies to China National Standard (CNS) A4 (210X297 mm) binding

Line 540086 A7 B7 5. Description of the invention (61) 4021, as shown in Figure 39. Preferably, if the blocking layer 4013 includes silicon nitride, the spacer 4021 includes silicon oxide. However, the spacers may also contain any material that does not have substantial etching itself, allowing the blocking layer 4013 to be selectively etched. For example, if the blocking layer 4013 includes silicon oxide, the spacer 4021 may also include silicon nitride. The spacer 4021 is preferably formed by conformally depositing a silicon oxide layer on the stack 4015; thereafter, a non-isotropic oxide etching is performed. The spacer etch process ends with a 100N dielectric etch, and the source and drain regions 4017 are exposed. If necessary, at this time, the gate stack 4015 and the spacer 4021 can be used as masks, and self-aligned ion implantation can be used to increase the doping in the source and drain regions 4017. If so, they can be implanted before the spacers are formed to form a lightly doped source / drain (LDD) extension. A self-aligned silicide process is then used to form silicide regions 4023 in a self-aligned manner in the silicon source and drain regions 4017. The self-aligned silicide process consists of three steps. First, a layer of metal, such as Ti, W, Mo, Ta, or Co, Ni, Pt, or Pd, is blanket deposited on the exposed area 4017, the sidewall spacer 4021, and the blocking layer 4013 of the gate stack 4015. Transition metal. The device is annealed to perform silicidation by a direct metallurgical reaction; wherein the metal layer reacts with silicon in the region 4017, and a silicide region 4023 is formed on the region 4017. Unreacted metal remaining on the spacer 4021 and the blocking layer 4013 is removed by selective etching (such as using a Pirana solution). The silicide region 4023 and the doped silicon region 4017—both include bit lines 4025. Figure 39 shows the device in this manufacturing stage: Γ. A common insulating layer 4027 is then deposited to fill the trenches above the bit lines 4025 and between the sidewall spacers 4021. Insulating layer 4027 can include any insulating material -64-This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm)

Line 540086 A7 B7 V. Description of the invention (62) materials such as silicon oxide, silicon oxynitride, PSG, BPSG, BSG, spin-on glass, polymer, dielectric layer (such as polyimide, etc.), and / Or other insulating materials which must be different from the material of the blocking layer 4013. The insulating layer 4027 is then planarized by chemical mechanical polishing (CMP), etch back, and / or any other means to expose the upper surface of the silicon nitride blocking layer 4013 on the gate stack 4015. Figure 40 shows the device after this planarization step. Secondly, the blocking silicon nitride layer 4013 is selectively etched, and the spacer 4021 and the insulating layer 4027 are not etched appreciably. The protective oxide layer 4011, if present, is also removed by etching from the upper surface of the first gate 4009 in the stack 4015. These etching steps form a gate contact via 4029 over each gate 4009, as shown in FIG. The width of the gate contact vias 4029 is substantially the same as the width of the first gate electrode 4009, because the sidewalls of these vias are the inner sidewalls of the sidewall spacer 4021. The gate contact through-hole 4029 is then defined by the side wall spacer 4021 (extending above the gate 4009) and is thus aligned with the gate 4009. The formation of the gate contact through-hole 4029 does not require a lithographic masking step. Then, a second gate electrode conductive material 4031 is deposited on the entire device, as shown in FIG. 42. Preferably, the material 4031 includes a multi-layer stack including a first n + doped polycrystalline silicon layer 4033, a silicide layer 4035 (such as butadiene or WSi), and a second n + doped polycrystalline silicon layer. 4037. Polycrystalline silicon layers 4033 and 4037 are preferably 100-300 nanometers thick, such as 200 nanometers thick. The silicide layer 4035 is preferably 50 to 100 nanometers thick, such as 60 nanometers thick. Alternatively, the second gate material can also be formed of a single layer of an imaged compound or a metal; or-a thickly doped amorphous or polycrystalline silicon, silicide, or any other combination of metals, as long as it is combined with the first A gate electrode 4009 makes a good ohmic contact. -65- This paper size is applicable to China National Standard (CMS) A4 (210 X 297 mm) binding

Line 540086 A7 ___ _B7 V. Description of the Invention (63) Secondly, a light-resistant surname layer (not shown) is applied on the material 4031, exposed through a word line mask, and developed. The photoresist layer is used as a mask to etch the second gate electrode material 4031 to form a plurality of word lines 4041. The 〇NO stack 4007 and the exposed active area surface layer 4005 are masked by the word line 4041 and then etched. The photoresist layer may be left on the word line 4041 during this etching step, or may be removed before this etching step. A bottom insulating layer 4003 under the active area surface layer 4005 and a complete insulating layer 4027 above the bit line 4025 are used as a barrier layer. In this way, the second gate electrode material 4031 is patterned into a plurality of word lines 4041 and is covered with a complete insulating layer 4027 (as shown in FIG. 43); and the pattern is transformed into a first gate electrode upper portion 4043, where the material 4031 extends Into the through hole 4029 (as shown in Figure 44). Fig. 43 is a cross-sectional view taken along the line A-A in Fig. 42; Fig. 44 is a cross-sectional view taken along the line B-B in Fig. 42. The word line 4041 is then self-aligned to control the gate 4009/4043, and no lithography step is required to align the word line with the gate. If necessary, a thin layer of silicon nitride or silicon oxide (eg, thermal nitridation or thermal oxidation) can be grown on the exposed active area surface 4005 and the gate electrode 4009/4043 sidewalls to seal the exposed area. This completes the construction of the memory array. Then, an insulating layer is deposited on the word line 4041, if necessary, and planarized. The word line lithography step does not require misalignment tolerance, because the pattern of the word line uses the same mask as the charge storage region 4007 and the active layer 4005 (ie, the channel region 4019) of each TFT in the cell. Therefore, the word line 4041 is not only self-aligned with the control gate 4009/4043 of the TFT EEPROM because it is deposited in the self-aligned through-hole 4029; but also the word line 4041 is self-aligned with each cell. The charge staggered region 4007 and the channel region 4019. Using fully self-aligned memory cells reduces the number of expensive and time-consuming lithography steps. Moreover, since each unit is not required to be out of tolerance __— —_- 66 -___ This paper size is common Chinese National Standard (CNS) A4 specification (210 X 297 mm) binding

Line 540086 A7 B7 5. The description of the invention (64) is poor, the cell density increases. Another advantage of the device of the first embodiment is that: there is a thick and complete insulating layer 4027 between the bit line 4025 and the word line 4041, so the parasitic capacitance between the bit line and the word line and the chance of short circuit are reduced. 45 and 46 illustrate a method for manufacturing a TFT EEPROM non-volatile flash memory array according to a second preferred embodiment of the present invention. The method of this second preferred embodiment is the same as that of the first embodiment illustrated in Figs. 37-44, except that the sacrificial blocking layer 4013 is omitted. FIG. 45 illustrates a semiconductor device 4100 in a process according to a second preferred embodiment. The device 4100 illustrated in FIG. 45 is in the same processing stage as the device 4001 in FIG. 40. The device 4100 includes an interlayer insulating layer 4103, an active layer 4105, a charge storage region 4107 (eg, a nano crystal stacked or isolated), a source and drain region 4117, a channel region 4119, a silicide region 4123, and a bit line 4125. . The gate electrode 4109 of the device 4100 is made thicker than the gate electrode 4009 in the first embodiment. For example, the gate electrode 4109 may have any suitable thickness, such as 160 to 360 nm, and more preferably 260 nm. When the blocking layer 4013 is omitted, a gate sidewall spacer 4121 is formed on the patterned gate electrode 4109 after the source and drain regions 4117 are formed. The gate electrode 4109 is a protective silicon oxide layer (not shown). Out). The sidewall spacer 4121 extends to the top of the gate electrode 4109. Then, a metal layer is deposited and reacted with the source and drain regions 4117, thereby forming a silicide region 4123 on the source and drain regions 4117. On the gate electrode 4109 and the sidewall spacer 4121, no silicide is formed; the gate electrode 4109 is covered with a silicon oxide protective layer. Then, an insulating layer 4127 is deposited between the side wall spacers 4121 and above the gate electrode 4109. __- R7 -__ This paper size applies to China National Standard (CNS) Α4 size (210 × 297 mm) binding

Line 540086 A7 B7 V. Description of the Invention (65) The layer 4127 is preferably silicon oxide; but like the first embodiment, the layer 4127 may also include any other insulating material. Then, the layer 4127 is planarized to expose the upper surface of the gate electrode 4109. The insulating layer 4127 should be planarized by CMP, but can also be planarized by etch back and / or other means. During the planarization, the protective silicon oxide layer is also removed to expose the upper surface of the gate electrode 4109, as shown in Figure 45. The selective etching step of the nitride blocking layer 4013 is not performed in the second embodiment, and the spacer 4121 may be composed of silicon nitride instead of silicon oxide. The advantage of a silicon nitride spacer is that it conforms to the topography below the oxide spacer. During the planarization of the layer 4127, the spacer 4121 and the gate electrode 4109 can be used as a polishing or etching barrier layer. As with the array in the first preferred embodiment, the memory array in the second preferred embodiment is completed after the gate electrode 4109 is exposed. As in the first specific embodiment, one or more conductive layers are directly deposited on the sidewall spacer 4121 and the exposed gate electrode 4109. For example, the conductive layer (s) may include polycrystalline silicon layers 4133 and 4137 with a silicide 4135 in between. As shown in FIG. 46, the conductive layer is patterned to form a plurality of word lines 4141; the word line 4141 contacts the exposed gate electrode 4109. During the same patterning step, the charge storage area 4107 and the active layer 4105 are also patterned, as in the first embodiment. The word line 4141 is then self-aligned to control the gate electrode 4109. There is no need for a lithography step to align the word line with the gate. If necessary, a thin layer of silicon nitride or silicon oxide (for example, by thermal nitridation or thermal oxidation) can be grown on the exposed active area surface 4105 and the side wall of the gate electrode 4109, thereby sealing. This completes the construction of the memory array. Then, -68- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Order

540086 A7 B7 V. Description of the invention 6) An insulating layer is deposited on the word line 4141, if necessary and planarized. The word line lithography step does not require misalignment tolerance, because the patterning of the word line uses the same mask as the charge storage area 4107 and active layer 4105 of each TFT in the cell. Therefore, the word line 4141 not only self-aligns the control gate 4109 of the TFT EEPROM because it is directly deposited on the exposed upper surface of the gate 4109 and the spacer 4121: the word line 4141 also self-aligns the charge storage area 4107 of each cell And passage area 4119. Using fully self-aligned memory cells reduces the number of expensive and time-consuming lithography steps. Since no tolerance for misalignment is required, the element density is increased. In addition, the blocking nitride deposition and selective etching steps of the first embodiment are deleted, thereby reducing three steps; this simplifies the process flow. FIG. 47 illustrates a TFT EEPROM non-volatile flash memory array 4200 according to a third preferred embodiment of the present invention. The apparatus and method of the third preferred embodiment are the same as those of the first and second embodiments illustrated in FIGS. 37-46, except that the charge storage area includes an electrically isolated floating gate instead of The first and second preferred embodiments are in addition to nano-stacked or isolated nanocrystals. As shown in FIG. 47, the nonvolatile transistor (i.e., the TFT EEPROM) is constructed as a floating gate field effect transistor. In this case, a tunneling dielectric (such as a tunneling silicon oxide layer 4206) is used to replace the triple layer of dielectric consisting of an ONO stack or an oxide layer (including electrically isolated nanocrystals). The tunneling oxide 4206 is 5 to 10 nanometers thick, and preferably 7 nanometers. The through-oxide layer 4206 is formed on the active layer 4205, as in the first and second embodiments. The first gate electrode 4209 is formed and patterned on the tunneling oxide layer 4206, as in the first and second embodiments. However, in the third specific embodiment ___- fiQ- _ This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 540086 A7 B7 5. Description of the invention (67), the first gate electrode 4209 series Contains a floating gate instead of a control gate. Floating gate 4209. Self-aligned transistor channel 4219, as in the first and second embodiments. The device illustrated in FIG. 47 is in the same processing stage as the device in FIG. 42. The device includes a substrate 4203, a source and drain region 4217, a channel region 4219, a sidewall spacer 4221, a silicide region 4223, a bit line 4225, and an insulating layer 4227 adjacent to the sidewall of the floating gate 4209. Another difference from the first and second embodiments is that a control gate dielectric 4212 is formed on the floating gate 4209, as shown in FIG. 47. The control gate dielectric may have any suitable thickness, such as 8 to 20 nm, and preferably 12 nm. The control gate dielectric 4212 may be grown on the control gate by thermal oxidation, or may be deposited by CVD or other means. The control gate dielectric may include silicon oxide, silicon nitride, silicon oxynitride, or an ONO stack. Then, the control gate 4243 and the word line 4241 are deposited and patterned on the control gate dielectric 4212 (as in the first and second embodiments), and the device shown in FIG. 47 is completed. The control gate dielectric 4212 and the control gate 4243 are located inside the sidewall spacer 4221. 48A-C and 49A-C illustrate two alternative and preferred methods for manufacturing a TFT (ie, a cell) in the device 4200 shown in FIG. 47. According to the first preferred method, a gate stack 4215 is formed on the tunneling dielectric 4206, which includes a floating gate 4209, a protective layer 4211, and an optional sacrificial blocking layer 4213. Using the gate stacking stone 15 as a mask, the source and drain regions 4217 are planted into the active layer 4205 so that a channel region 4219 is formed under the tunneling dielectric 4206. Then, a side wall spacer 4221 is formed on the gate stack 4215. Adjacent to the spacer, ___- 70-_ This paper size applies to Chinese national standards (CNS> A4 specification (210 X 297 mm) 540086 A7 B7 V. Description of the invention (68) An insulating layer 4227 is formed and planarized. The blocking layer 4213 is exposed, as shown in FIG. 48A. Then, as shown in FIG. 48B, the protective layer 4211 and the blocking layer 4213 are removed by etching. Thus, a gate contact via 4229 is formed. The sidewall of the via 4229 is a sidewall spacer. The object 4221 extends above the floating gate 4209. By controlling the heat (for example), the floating gate 4209 exposed inside the through hole 4229 shown in FIG. 48C forms a control gate dielectric 4212. Then, one or more conductive layers are deposited on the gate contact through-hole 4229 and the insulating layer 4227. The layer (s) are patterned, and a control gate 4243 is formed in the through-hole 4229, and the layer A word line 4241 is formed on 4227. The control gate dielectric 4212 separates the control gate 4243 from the floating gate 4209. According to this second preferred method, a gate stack is formed on the tunneling dielectric 4206. 4215, which includes a floating gate 4209 and a control gate dielectric 42 12 and a sacrificial blocking layer 4213. Using the gate stack 4215 as a mask, the source and drain regions 4217 are implanted into the active layer 4205, so that a tunnel region 4219 is formed under the tunnel dielectric 4206. Then, A sidewall spacer 4221 is formed above the gate stack 4215. An insulating layer 4227 is formed adjacent to the spacer, and planarized to expose the blocking layer 4213, as shown in FIG. 49A. Then, as shown in FIG. 49B, the blocking layer 4213 is Etching is removed, and the control gate dielectric 4212 is exposed. Thus, a gate contact via 4229 is formed. The side wall of the via 4229 is an extension of the sidewall spacer 4221 above the floating gate 4209 and the dielectric 4212. 卩The Γ plug layer 4213 may be composed of a thickly doped polycrystalline silicon, and if necessary, may be left in the through hole 4229. As shown in FIG. 49C, above the gate contact through hole 4229 and the insulating layer 4227, Shen-71- This paper size applies to China National Standard (CNS) A4 (210X 297mm) binding

Line 540086 A7 B7 V. Description of Invention (69) One or more conductive layers are stacked. These layers (s) are patterned, and a control gate 4243 is formed in the through hole 4229, and a word line 4241 is formed above the layer 4227. The control gate dielectric 4212 separates the control gate 4243 from the floating gate 4209. In the method of FIGS. 48A-C and 49A-C, the word line 4241 is self-aligned to the control gate 4243, the control gate dielectric 4212, and the floating gate 4209. FIG. 50 illustrates a TFT EEPROM non-volatile flash memory array 4300 according to the first preferred aspect of the fourth preferred embodiment of the present invention. The device and method of the fourth preferred embodiment are the same as those of the third preferred embodiment illustrated in Fig. 47, except that the gate dielectric is controlled to be located on the side wall spacer. Furthermore, the blocking layer 4213 is omitted. As shown in FIG. 50, the side wall spacer 4221 extends to the top of the floating gate 4209, similar to the device of the second preferred embodiment. The control gate dielectric 4212 is deposited on the floating gate 4209, the sidewall spacer 4221, and the insulating layer 4227. Then, the word line 4241 is deposited and patterned on the control gate dielectric 4212, as in the first and second embodiments. In the device of FIG. 50, the word line 4241 functions as both a word line and a control gate. In this way, a separate control gate can be omitted. The word line 4241 is a self-aligned floating gate 4209. The word line 4241 may include one or more layers, such as polycrystalline silicon layers 4233 and 4237, with a silicide layer 4235 therebetween. FIG. 51 illustrates a TFT EEPROM non-volatile flash memory array 4300 according to a second preferred aspect of the fourth preferred embodiment of the present invention. The device and method in this preferred aspect are the same as those shown in FIG. 50, except that the upper part of the floating gate extends above the side wall spacer 《The device shown in FIG. The same processing stages. As shown in Figure 51, the device includes an interlayer insulation layer 4303, a tunneling dielectric 4306, a source and drain region 4317, and a channel region -72. This paper size applies to China National Standard (CNS) A4 (210X297 mm ) Binding

Line 540086 A7 B7 V. Description of the invention (70) domain 4319, silicide region 4323, bit line 4325, and insulating layer 4327. The apparatus illustrated in Fig. 51 includes the processing steps illustrated in Figs. 48A-B described above. In this way, the lower portion of the floating gate 4309 is exposed in the gate contact through hole 4329 between the side wall spacers, and the side wall spacer 4321 extends above the lower portion of the floating gate: this is similar to FIG. 48B. However, instead of forming the control gate dielectric 4312 in the through hole 4329, a floating gate upper portion 4310 is deposited. The upper part of the floating gate 4310 is formed by depositing a conductive layer (such as a doped polycrystalline silicon layer) on the through hole 4329, the spacer 4321, and the insulating layer 4327 so as to contact the exposed lower part of the floating gate in the through hole 4329. 4309. The conductive layer is patterned into a floating gate upper portion 4310 by lithography so as to extend vertically above the sidewall spacer 4321. Preferably, the conductive layer also extends horizontally above the sidewall spacer 4321. In this way, the gate upper part 4310 has a "T" shape. Then, the gate dielectric 4312 is controlled to be formed on the exposed upper surface of the upper portion of the floating gate 4310 by thermal growth, CVD, and / or other deposition techniques (such as gold plating). Then on the control gate dielectric 4312, one or more conductive layers 4333, 4335, 4337 are deposited and patterned into word lines 4341. For example, the conductive layers may be a silicide layer 4335 and sandwiched between the doped polycrystalline layers 4333 and 4337, as in the first preferred embodiment. In the fourth preferred embodiment, the word line 4341 is used as the control gate of the DFTs. Since the top surface of the floating gate 4309/4310 of the fourth embodiment is larger than that of the third embodiment, the area between the floating gate and the control gate / word line in the TFT in the fourth embodiment is larger than The third concrete example: In the example, it is increased ^ € The area between the floating gate and the control gate / word line is advantageous because it increases the floating gate and the control gate / word Capacitive coupling between lines. -73- This paper size applies to China National Standard (CNS) A4 (210X 297mm) binding

Line 540086 A7 _______B7 V. Description of the invention (71) In a preferred aspect of the fourth embodiment, the top surface of the upper part of the floating gate 4310 is roughened or roughened, which further increases the floating gate. Capacitive coupling with control gate / word line. For example, at least the upper part of the floating gate 4310 may be made of hemispherical broken grains (HSG), or the upper surface of the floating gate may be roughened by etching or rough grinding. In other words, the roughening or roughening of the upper part of the floating gate can be similar to the roughening or roughening of the conductive plate at the bottom of the DRAM capacitor. Although the first to fourth preferred embodiments are illustrative of XFT EEPROM non-volatile flash memory arrays, the present invention should not be construed as being limited thereto. For example, according to a preferred embodiment of the present invention, word lines are not necessarily self-aligned in a TFT EEPROM array, and any gate line can be self-aligned to a MOSFET (ie, metal oxide semiconductor field effect transistor) gate. pole. Moreover, the EEPROM array can be formed in a bulk silicon substrate without being over the interlayer insulating layer. The first to fourth preferred embodiments illustrate the intersection point array of word lines and bit lines on a horizontal level, and a method for manufacturing the same. Each memory cell is composed of a single programmable field effect transistor. (Ie, Ding FT), and the source and the drain of the transistor are respectively connected to the j-th bit line and the (j + 1) -th bit line, and the control gate is connected to or includes the k-th word line . This memory arrangement is identified as an "inverse or virtual ground (NVG) array" (referred to as VGA when referred to). If necessary, the memory array can also be arranged in a non-volatile flash memory architecture other than VGA. OR type memory or dual string inverse OR (DuSNOR) memory (for example). In the DliSNOR architecture, two adjacent ~ cell strings share a common source line, but use different non-polar lines: its warp It is described in KSDM, et al., IEDM-95 (1995), p. 263, and is incorporated herein by reference. System -74- This paper standard applies to China National Standards (CMS) A4 specification ( 21〇x 297 mm) '540086 A7 B7 V. Description of the invention (72) The DuSNOR memory can be manufactured using the same process as the VGA memory, except that it uses a masking step to pattern the active area surface layer. In order to separate the drain regions of adjacent cells, the first to third preferred embodiments of the present invention require only two lithographic masking steps. One masking step is used for gate patterning / Self-aligned bit line formation. Another masking step is used for word line patterning. The method of the preferred embodiment of the present invention uses self-alignment to reduce the alignment tolerance between the masks. The area of the memory cell obtained by the aforementioned process is about 4F2, where F is the minimum feature size (Ie, 0.18 microns in a 0.18 microns semiconductor process). The term "about" allows small deviations (10% or less) due to uneven process conditions, and other necessary Deviations in process parameters. If the charge storage medium used in the transistor is non-conductive-for example, formed from a nitride or oxynitride (ie, using a 0N0 charge storage medium) or an electrically isolated nanocrystal-it can be used The localized nature of charge storage, and each cell stores two bits. In this case, the effective cell area per bit is approximately equal to 2F2. The NVG arrays of the first to fourth preferred embodiments are very suitable for horizontal A vertical stack of planar NVG arrays. Figure 52 illustrates a three-dimensional memory array 4400 according to a fifth preferred embodiment of the present invention. The three-dimensional memory array includes a first, second, third, or fourth comparison. Jiaju The three-dimensional TFT EEPROMs array made in the embodiment. Each TFT EEPROM includes a channel 4419, a source and a drain region 4417, a control gate 4443, and a control gate sidewall spacer (not shown for the sake of clarity). Figure 52), and a second charge storage area 4407 (between the channel and the control gate 4409). The charge storage area may include a 100N dielectric, an isolated nanocrystal, or a floating gate. Paper size applies to China National Standard (CNS) Α4 (210X 297 mm) binding

Line 540086 A7 B7__ V. Description of the Invention (73) The memory array also includes a plurality of bit line rows 4425, and each bit line contacts a source or drain region 4417 of a plurality of TFT EEPROMs. The rows of bit lines 4425 extend approximately orthogonally to the source-channel-drain direction of the TFT EEPROMs (ie, the term "substantially orthogonal" includes a small deviation from the straight cross direction). It should be noted that the rows of bit lines 4425 can run through the entire array 4400 or only a part of the array 4400, and are approximately orthogonal to the source-channel-to-polarity direction of the TFT EEPROMs. The bit line shape in each device level is a guide rail and extends under the complete insulation layer. The bit lines include buried diffusion regions that are formed during the source and drain doping steps; and include overlying silicide layers. The source and drain regions are formed where the word lines intersect (ie, overwrite) the bit lines in the bit lines; the doped regions are located adjacent to the EEPROM channel region. The memory array also includes a plurality of word line columns 444 and each word line is in contact with a control gate 4443 (or the word line includes a control gate) of a plurality of TFT EEPROMs 4400. The columns of word lines extend approximately parallel to the source-channel-drain direction of the TFT EEPROMs (that is, the term "substantially parallel" includes a small deviation from the parallel direction). It should be noted that the columns of word lines 4441 can run through the entire array 4400 or only a part of the array 4400, and extend substantially parallel to the source-channel-drain direction of the TFT EEPROMs. TFT EEPROMs array's control gate 4443 (or, the word line itself contains the control gate " If the array contains floating gates instead of control gates, the word lines are self-aligned to the floating gate and control gate Electrical quality: Each device 'level 4445 of the array is separated and decoupled in the vertical direction by an interlayer insulating layer 4403. In each device level 4445, the individual word lines 4441 are below _ -76- This paper size Applicable to China National Standard (CNS) A4 (210 X 297 mm) binding

Line A7 B7 V. Description of the Invention (74) The active area surface 4405, the portion adjacent to the adjacent rare line 4441 will also be isolated by the interlayer insulation. In the generated three-dimensional memory array, the area of the unit of each bit is about 2F2 / N, where N is the number of device levels (that is, for a two-dimensional array, N = 1; for a three-dimensional array, N > 1) . Non-volatile memory device array 〇 Including a single stone three-dimensional memory device array. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each bottom level. Two-dimensional arrays are flourishing. They can be formed separately and assembled together to form non-monolithic memory devices. " Each of the cells in the -level 4445 of the memory array can be formed with only two lithographic masking steps; however, additional masking steps may be required to form a contact with the bit π line 4425 ^ In a sixth preferred embodiment of the present invention, a conductive layer is formed on the memory device array. The conductive layer is then patterned to form a plurality of contact lines or sub-line contact layers and at least one bit line contact layer (in contact with at least one of the plurality of bit lines). In this way, both the word line / word line contact and the bit line contact are formed by patterning the same conductive layer, and the separate bit line contact deposition and patterning steps can be avoided. Of course, if necessary, the word line / word line contacts and bit line contacts can be made from different materials and / or patterned with different masks. FIG. 53 illustrates a bit line contact 4447 according to a preferred aspect of the sixth preferred embodiment. In FIG. 53, a first doped polycrystalline silicon layer 4433 is formed on the inter-gate insulating layer 4427. A bit line contact via 4445Γ is then formed in the insulating layer 4427, and the top of the bit line 4425 is exposed therein. Then, a silicide layer 4435 and a doped polycrystalline silicon layer 4437 are deposited, so that the silicide layer obliquely contacts the bit line 4425 through the through hole. Layers 4433, 4435, and 4437 use the same mask again. -77 · This paper has a common Chinese painting standard (CNS) A4 specification (210 X 297 public love) 540086 A7 B7 5. Description of the invention (75) and lithography , Both a plurality of word lines 4441 and a plurality of bit line contacts 4447 are formed. Then, an upper interlayer insulating layer 4403 is formed on the word line 4441 and the bit line contact 4447. Word line contact vias 4451 and bit line contact vias 4453 are formed in the insulating layer 4403 for further contact formation. It should be noted that the word line 4441 and the bit line contact layer 4447 are not limited to the material. Layers 4441 and 4447 may include one or more polycrystalline silicon, silicide, or metal layers. Moreover, although the gate line 4441 and the contact 4447 are located in the same stage of the device, the contact 4447 can be extended into a lower stage of the array when necessary to contact a bit line or word line in the lower stage. . Figure 54 illustrates a bit line contact 4547 according to another preferred aspect of the sixth preferred embodiment. In this embodiment, at least one bit line contact via 4549 extends through at least one interlayer insulating layer 4503 between different levels of the array. In FIG. 54, the word line 4541 is first patterned; an interlayer insulating layer 4503 is deposited thereon. A word line contact via 4551 and a bit line contact via 4549 are formed in the insulating layer 4503. The bit line contact via 4549 extends through the complete insulating layer 4527 to the bit line 4525; the bit line 4525 includes a doped region 4517 and a silicide region 4523. Then, one or more conductive layers, such as a silicide layer 4555 and a doped polycrystalline silicon layer 4557, are deposited over the interlayer insulating layer 4503 and in the through holes 4551 and 4549. The one or more conductive layers 4555, 4557 are then lithographically patterned with the same mask, forming not only word line contacts 4559, bit line contacts 4547, but also the memory of the two L layers of memory shown. A plurality of word lines are formed in the body layer. These word line contacts and bit line contacts can be extended to lower levels (for example, each lower level, or several lower levels at the same time). The bit line connections in Figure 54 are- 78- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 540086 A7 B7 V. Description of the invention (76) The point 4547 and the word line contact 4559 are formed in the N + 1 level of the array, and Word lines 4541 and bit lines 4525 in the Nth stage of the array are connected. These word line contacts and bit line contacts are connected to word lines and bit lines with peripheral circuits, which are located in the array. In the semiconductor substrate below the first device level (or located elsewhere in the array, such as above or within the array, but it should be integrated or aligned vertically at least partially vertically). Manufactured in N + 1 level conductors A positioning pad is provided for the next-level contacts. Figures 55 to 61 illustrate a method for manufacturing a TFT EEPROM non-volatile flash memory array according to a seventh preferred embodiment of the present invention. The method of the seven preferred embodiments starts with the first, second, and The method of the third or fourth embodiment, except that it uses a sacrificial dummy block to replace the control gate in the manufacturing process. The transistor formed in this way is called a replacement gate transistor. The seventh embodiment The fabricated array can be formed into a three-dimensional array as shown in Fig. 52, and each bit has an effective cell area of about 2F2 / N. As in the previous embodiment, the process starts with the deposition of a semiconductor active area, such as: On the interlayer insulating layer 4603, an amorphous silicon or polycrystalline silicon layer 4605 is deposited, as shown in Fig. 55. Then, a plurality of sacrificial dummy blocks 4604 are formed on the active layer 4605, as shown in Fig. 56. The sacrificial dummy blocks 4604 can include one or more materials, at least one of which can be selectively etched to pass through the material of the complete insulating layer 4627 that will be formed later. For example, if the complete insulating layer 4627 contains silicon oxide, then these The dummy block may include silicon oxide, silicon oxynitride, polycrystalline silicon, or other materials that can be selectively etched with silicon oxide. Preferably, the active layer 4605 includes amorphous silicon, and the dummy block 4604 is made of a material. -79- paper Zhang scale is applicable to Chinese National Standard (CMS) A4 (210X 297mm) binding

Line 540086 A7 B7 V. Description of the invention (77) Deposition at a temperature below 600 ° C to prevent the amorphous silicon layer 4605 from recrystallizing into a polycrystalline broken layer with a small grain size. For example, a low-temperature PECVD silicon nitride layer can be deposited on the active layer 4605, and the silicon nitride layer can be patterned into a plurality of dummy blocks 4604 by lithography. In a preferred aspect of the seventh embodiment, the dummy block 4604 includes a plurality of layers including a sacrificial channel dielectric layer 4667, a sacrificial gate layer 4669, and a protective oxide layer 4671, as shown in FIG. 55. . Layers 4669 and 4671 are patterned with a reverse bit line mask (similar to the first preferred embodiment illustrated in Figure 38) to form dummy blocks 4604, as shown in Figure 56. Since the layers 4667, 4669, 4671 above the active layer are sacrificial, lower quality materials can be used for these layers. For example, for the channel dielectric layer 4667, low temperature silicon oxide (LTO) or PECVD silicon oxide can be used. In this way, the layer 4667 can be deposited at a low temperature (ie, below 600 ° C) to prevent the amorphous silicon active layer 4605 from recrystallizing into a polycrystalline silicon layer having a small grain size. When necessary, all layers of the dummy block 4604 can be deposited at a temperature below 600 ° C. In this case, the layer 4605 remains amorphous until subsequent self-aligned silicide is formed on the source and drain regions 4617. The silicide 4623 on the source and drain regions 4617 can be used as a catalyst for the lateral crystallization of the amorphous system in the source and drain regions 4617 to form a polycrystalline silicon active layer with a large grain size. 4605. Next, using the dummy blocks as a mask, the TFT source and drain regions 4617 are implanted into the active layer 4605. The channel layer 4619 is located in the layer 4605 between the regions 4617, and [under the dummy block 4604. If the dummy 15: block 4604 contains a polycrystalline silicon layer, a sidewall spacer 4621 should be formed on the sidewall of the dummy block 4604 to separate the silicide from the source / drain junction to prevent subsequent silicide formation on the dummy block. -80- This paper size is applicable to Chinese National Standard (CNS) A4 (21〇x 297mm) binding

Line 540086 A7 B7 V. Description of the invention (78) and improve the flexibility of adaptation in source / drain engineering. The spacer 4621 may be composed of silicon oxide or silicon nitride, or two different layers, as shown in FIG. 57. If necessary, the dummy block 4604 and the spacer 4621 can be used as a mask to line the source and drain regions 4617. If the dummy block 4604 does not contain polycrystalline silicon (that is, combined by silicon nitride), the spacer 4621 may be omitted. On the exposed area 4617 and the dummy block 4604, a metal layer such as ΊΠ, W, Mo, Ta, or a transition metal such as Co, Ni, Pt, or Pd is blanket deposited. The device is annealed to perform silicidation by a direct metallurgical reaction; the metal layer reacts with silicon in region 4617, and a silicide region 4623 is formed on region 4617, as shown in FIG. The unreacted metal remaining on the dummy block 4604 is removed by selective etching (such as using a Pirana solution). Then, using the silicide region 4623 as a catalyst, the active layer 4605 is recrystallized by laser or thermal annealing. If necessary, another option is to recrystallize the active layer 4605 and the silicide 4623 simultaneously, or recrystallize by laser or thermal annealing before the dummy block 4604 is formed. ‘After the buried bit lines 4625 including the source and drain regions 4617 and the silicide 4623 are formed, a conformal complete insulating layer 4627 is deposited between and on the dummy blocks 4604. Preferably, layer 4627 comprises silicon oxide (HDP oxide), as in other preferred embodiments. The layer 4627 is then planarized by CMP and / or etch-back to expose the top of the dummy block 4604. For example, if dummy block 4604 contains a silicon oxide protective layer 4671 and silicon oxide spacers 4621, these layers can be removed together during the planarization of the top layer 4627. In this case, the top of the sacrificial gate 4669 is exposed after planarization, as shown in FIG. 58. Secondly, the dummy block 4604 is selectively etched (ie, removed), and the complete insulation layer is -81-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm).

Line 540086 A7 B7 V. Description of the invention (79

4627 No appreciable etching. For example, if dummy block 4604 contains sacrificial polysilicon gates 4669., these sacrificial gates 4669 are selectively etched, while spacers 4621 and complete insulation layer 4627 are not etched appreciably. If the dummy block contains a sacrificial gate dielectric layer 4667, this layer 4667 can be removed by plasma etchback or wet etching. As shown in FIG. 59, in the previous position of the dummy block 4604, a plurality of through holes 4629 are formed. Immediately after the active layer 4605 surface of the channel region 4619 is exposed due to the removal of the dummy block material, a "real" or permanent gate dielectric material is grown and / or deposited on the exposed region. Preferably, the dielectric includes a charge storage region 4607, which is selected from an ono triple layer or a plurality of electrically isolated nanocrystals, as shown in FIG. 60. Alternatively, if the TFT EEPROM includes a floating gate 4609 (as shown in FIG. 61), the dielectric includes a tunneling dielectric 4606. The charge storage layer 4607 is located on the bottom of the through hole 4629 above the channel area 4619. The charge storage layer 4607 also includes a vertical portion on the side wall of the complete insulating layer 4627 (if there is a spacer 4621, it is on the side wall of the spacer); and a horizontal portion is located on the complete insulating layer 4627. ; As shown in Figure 60. Next, on top of the complete insulating layer 4627 and the charge storage region 4607, a conductive material is deposited. The conductive material may include polycrystalline silicon, or a combination of layers such as polycrystalline silicon 4633, 4637, and wheat compound 4635, as in other specific embodiments. The conductive material fills the through hole 4629 and covers the charge storage area 4607. The conductive material is patterned to form a plurality of word lines 4641, as in other specific embodiments. Then, the active layer 4605 and the charge storage region 4607 are patterned with the word line 4641 as a mask, as in other embodiments. The word line 4641 is located in the through-hole 4629. The blade contains the control gate 4609 of 4 TFT EEPROMs, as shown in Figure 60. If -82- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding

Line 540086 A7 B7 V. Description of the invention (80) It is necessary to make a floating gate TFT EEPROM. Before the control gate / word line 4641 is formed, a floating gate 4609 and a control are formed in the through hole 4629. The gate dielectric 4612 is shown in FIG. 61. In the eighth preferred embodiment of the present invention, the TFTs in the plurality of stages of the three-dimensional array of FIG. 52 simultaneously undergo recrystallization and / or dopant activation steps; this reduces the device fabrication time and cost. Furthermore, if each stage of the array undergoes separate crystallization and / or dopant activation annealing, the lower stage will undergo more annealing steps than the upper stage. The non-uniformity of the device may then be caused because the grain size in the lower-stage active area plane may be larger than the upper-stage and / or the dopant distribution in the lower-stage may be different from the upper-stage Level. Thus, in a preferred aspect of the eighth embodiment, the amorphous silicon or polycrystalline silicon active region surfaces of the TFTs in a plurality of stages are simultaneously recrystallized. Preferably, TFTs in all levels are recrystallized at the same time. This recrystallization may be affected by thermal annealing in a furnace or rapid thermal annealing (RTA) in an RTA system. The thermal annealing can be performed at 550 to 800 ° C for 6-10 hours, and preferably at 650 to 725eC for 7-8 hours. Moreover, the silicide layer 4423 contacts both the source and drain regions 4417, and the silicide can be used as a catalyst for crystallization, especially when nickel silicide, cobalt silicide, or molybdenum silicide are used. Metal atoms diffuse through the active area of the TFTs, leaving large polycrystalline silicon grains. In this way, after the deposition and metallization of the bit line, the recrystallization of the amorphous silicon or polycrystalline active layer results in larger grains, allowing lower recrystallization temperatures (such as 550 to 650 ° C). Moreover, metal-induced recrystallization does not require separate metal deposition and patterning. In this way, each grade of the array can be bound to the paper size of China National Standard (CNS) A4 (210 X 297 mm).

Line 540086 A7 B7 V. Description of the invention (81) After the bit line is metallized, it undergoes recrystallization annealing. Alternatively, after the bit line metallization has been formed at each stage of the array, all stages of the array may only undergo recrystallization annealing. Moreover, in an alternative aspect of the eighth embodiment, the silicidation / material formation step and the recrystallization step may be performed during the same annealing step of each stage of the array. In a second preferred aspect of the eighth embodiment, the doped regions in a plurality of stages are simultaneously activated. Preferably, the doped regions in all levels are activated simultaneously. The doped regions include the TFT source and drain regions in addition to any other doped regions formed in the three-dimensional array. Preferably, the doped regions are activated as the array undergoes RTA treatment. However, if necessary, thermal activation can be performed at about 700 to about 850 ° C for 20 to 60 minutes. This activation can be performed before or after the crystallization annealing. In a third preferred aspect of the eighth embodiment, the recrystallization and dopant activation are performed in the same annealing step of a plurality of stages or all stages of the array. This annealing step should not cause the source and drain region dopants to diffuse into the channel region of the TFTs, but be performed at a sufficiently high temperature for a sufficient time to activate the dopants and recrystallize the TFT active region surface. Preferably, the annealing step combining recrystallization and dopant activation includes an RTA treatment. In a fourth preferred aspect of the eighth embodiment, an additional lithographic masking step is provided to form a crystalline window for crystallization catalyst material deposition. Example Γ As shown in FIG. 62, the material 4722 used to form the sidewall spacer 4721 is patterned using a separate lithographic mask to form a crystal window 4701. In this way, in the method of replacing the gate transistor shown in Fig. 55-61, the crystallization window -84- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) binding

Line 540086 A7 B7 V. Description of the invention (82) 4701 is formed by etching the protective bit 4771 and sacrificial gate 4769 in the reverse bit line pattern, and then forming a low temperature oxide (LTO) layer for the manufacture of sidewall spacers. in. The crystalline mask features are etched into the oxide layer 4722 and the surface of the active layer 4705 is removed. Simultaneously, a sidewall spacer 4721 is formed on the sacrificial gate 4769. Then, the photoresist (not shown) is stripped. 63 and 64 illustrate cross sections along lines A-A and B-B in FIG. 62, respectively. If necessary, the processes of the first to fourth embodiments can also be added as the crystallization windows. In those embodiments, such windows will be formed during sidewall spacer formation. Second, a catalyst is deposited, such as Ni, Ge, Fe, Mo, Co, Pt, Pd, Rh, Ru, Os, Ir, Cu, Au, its petrified compounds, or other transition metal elements (or its silicides) ). This catalyst contacts the amorphous silicon active layer 4705 only in the open window 4701. The catalyst material is deposited as a solid layer or a catalyst solution. Alternatively, the catalyst may be implanted or diffused into the silicon active layer 4705. The device is then annealed for several hours at a temperature below 600 ° C; preferably 550 ° C. In order to minimize the spontaneous nucleation in the amorphous stone, this low annealing temperature is preferred. The polycrystalline silicon crystal grains in this embodiment grow from the seed region in the window 4701 and grow laterally. When the annealing is completed, the grain boundary 4702 is aligned as shown in FIG. 65. The catalyst was then removed. The solid catalyst layer can be removed by selective etching; and the catalyst atoms in the recrystallized polycrystalline stone can be removed by gettering, such as annealing the device in a gas containing gas. Then, the LTO oxide layer 4722 is removed by selective etching; the LTO oxide layer 4722 includes the boundary of the crystalline window 4701. As with other embodiments, the device is completed. It should be noted that the word line (WL in Figures 62 and 65) will be formed next to the crystal window 4701 where it was formed in the past _-85-_ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 A7 R7 5. Description of the invention (83) Above the area. The crystallization starts from the window 4701. However, in the region 4705 of the active layer between the word lines, a grain boundary 4702 parallel to the word line is located away from the window region. These 4705 regions of the active layer between the word lines were removed after the word lines were formed. Therefore, since the channel regions of the TFTs are located below the word line, these TFT channel regions contain fewer grain boundaries and contain substantially no grain boundaries parallel to the word line. III. Guide Rail Stacks and FTs The following preferred embodiments provide an array of TFTs with charge storage regions (such as EEPROM TFTs) arranged in a guide post configuration. The specific embodiments described herein address a non-volatile reprogrammable semiconductor memory, and methods of making and utilizing the same. Those skilled in the art will truly understand that the following detailed description of the specific embodiments of the present invention is for illustration only and is not intended to have any limitation. If such a person skilled in the art would benefit from this disclosure, he would immediately cite other specific embodiments of the present invention. Reference will now be made in detail to the implementation of the invention illustrated in the accompanying drawings. In the drawings and the following detailed description, the same or similar parts cited will always use the same reference numerals. For purposes of clarity, not all of the routine features of the implementations described herein are shown and described. It should be understood that in developing any such actual implementation, it is reasonable to make many decisions specified by the implementation in order to achieve the developer's specific goals, such as: in accordance with application and business-related constraints; and understand that these specific goals Will change with implementations and developers. It should also be understood that such development work can be complicated and time-consuming, but it is a regular engineering task for ordinary skillful persons skilled in the art who have benefited from this disclosure. This specific embodiment refers to a two-dimensional or (preferably) three-dimensional programmable multiple times. -86- The paper size applies to China National Standard (CNS) A4 (210X297 mm).

Order

Line 540086 A7 B7 5. Invention Description k) (MTP) non-volatile memory. The memory provides a 2F2 / N bit cell size, where F is the smallest feature size (eg, 0.18 microns in a 0.18 micron semiconductor process; 0.25 microns in a 0.25 micron semiconductor process), and N is the third The number of layers of the device in the (ie, vertical) dimension. Thus, for a 0.18 micron process in which eight devices are vertically stacked, the cell size of the effective bits projected on the substrate is only about .0081 square micrometers. As a result, in a 0.18 micron technology and under 8 layers of memory devices, if a 50 mm2 chip has an array efficiency of 50%, it will have approximately 3.1 billion memory cells, and when each cell stores two bits, It has a capacity of about 386 million bytes and 193 million bytes when storing one bit per cell. The three-dimensional version of the memory is a three-dimensional extension of the "virtual ground array" commonly used in monocrystalline silicon memory devices. The preferred memory architecture uses N + doped polysilicon rails in an intersection array, orthogonal to the P-doped polysilicon / charge trap layer / N + polysilicon rail stack, and the intersection array forms an NMOS transistor memory device. It has a SONOS charge trapping layer that can be replicated vertically. Similarly, it is of course possible to manufacture PMOS memory. Adjacent pairs of N + polycrystalline silicon rails are stacked with a P-doped polycrystalline silicon / charge trapping layer / N + doped polycrystalline silicon guide rail, defining the individual NMOS memory device. Source: pole, drain, and gate. Programming and erasing will change the threshold voltage of this NMOS. Programmable by thermo-electron injection, two bits per NMOS can be stored; either by thermo-hole injection or by Fowler-Nordheim tunneling, erasing can be performed. Referring now to FIG. 80, a method for integrating a memory device into a multi-level memory cell array according to a specific embodiment of the present invention will be described. At the beginning of manufacture, the system is mentioned -87- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 R7 V. Description of the invention (δ5) A substrate 5180 is to be formed on it. Storage device array. The substrate 5180 typically contains a thinly doped single crystal silicon substrate 5182 in which transistors such as metal oxide semiconductors (MOS) are formed. These transistors can be used, for example, to access transistors, or they can be coupled together into a circuit to form (for example) a charge pump or a sense amplifier for use in a manufactured memory device. The substrate 5180 typically also contains multilevel interconnects and interlayer dielectrics 5184, which are used to couple the transistors in the substrate 5182 together into a functional circuit. The top surface 5186 of the substrate 5180 typically contains an insulating layer or passivation. Layer to protect the underlying transistors and interconnects from contamination. The top surface 5186 typically contains electrical contact pads, and the multi-level memory device array of the present invention can be electrically coupled thereto for electrical contact with transistors in a silicon substrate 5182. In a specific embodiment of the present invention, the memory device is physically isolated and separated from the single crystal substrate by a multilevel interconnection and a dielectric 5184. The top surface of the passivation or insulation layer 5186 is typically planarized so that the multi-level memory device of the present invention can be manufactured uniformly and reliably. According to the present invention, the memory device is physically separated from the single crystal silicon substrate 5182. In an alternative embodiment of the invention, the memory device can be fabricated on a glass substrate 5180 (such as used in a flat panel display). According to a specific embodiment of the present invention, the process of forming a multi-level thin film transistor If (TFT) memory device array on a substrate begins by blanketly depositing a first conductor layer 5188 on the surface 5186 of the substrate 5180. The conductor 5188 may be any suitable conductor, such as (but not limited to) shattered titanium, doped polycrystalline silicon, or a metal such as aluminum thorium tungsten and its alloy (formed by suitable technology). The conductor 5188 is to be used as, for example, a bit line or a word line to couple a column or row of a memory device together. Secondly, a layer is deposited or grown on the conductor layer 5188. -88- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 R7 V. Description of the invention Q) An insulating layer (such as silicon oxide) to fill the spaces between the bit lines. The conventional chemical mechanical polishing (CMP) step completes the planarization and exposes the bit lines. Referring now to Figure 66, a previous perspective view illustrates a particular embodiment of the present invention. In this embodiment, a 2-dimensional memory array 5040 includes a first plurality of spaced apart conductors (such as N + doped polycrystalline silicon bit lines 5042 '5044, 5046, 5048), which are arranged in a first direction. On a substrate (not shown) at a first height (without contact). A second plurality of spaced-apart "rail stacks" 5050, 5052 are arranged at a second height above the substrate in a second direction different from the (preferably orthogonal) first direction, so that they are at bit lines 5042, 5044 , 5046, and 5048, and touch them at intersections 5054, 5056, 5058, 5060, 5062, 5064, 5066, 5068. The rail stacks 5050 and 5052 in this embodiment each include at least one layer of P-doped polycrystalline silicon 5070, which can be formed by, for example, an amorphous silicon film by chemical vapor deposition (CVD), and P Type impurities (eg, boron) are doped in-situ at a dopant density of about 1 X 1010 to about 1 X 1018 atoms / cm3. The amorphous silicon film can be converted into polycrystalline silicon through a subsequent annealing step. Alternatively, without in-situ doping, you can grow or deposit un-doped silicon first, and then use dopants for implantation or diffusion. On layer 5070, a charge-trapping layer 5072 is deposited, which contains the charge-trapping medium as discussed below; and a conductive word line 5074, which may include N + doping disposed on the charge-trapping layer 5072, is provided. (Or P + doped) polycrystalline silicon. In the spaces between and above adjacent bit lines and the rail stack, a planarized oxide material can be deposited (not shown in Figure 66). Conventional chemical mechanical polishing (CMP) processes can be used to complete the planarization. The memory array structure of Figure 66 can now be easily extrapolated to three dimensions. For this purpose, a planarized oxide layer is used on the word lines 5050 and 5052. The flattening-89- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A7 _ R7 V. The insulation layer (or interlayer insulation layer) of the invention description (87) prevents a group of words The line is shorted to the next set of bit lines. Then, another layer of bit lines 5042, 5044, 5046, 5048 is constructed on the insulation layer, followed by oxide deposition and CMP steps, and then another set of word lines is deposited. This process can be repeated several times if necessary. According to a specific embodiment of the present invention, the memory array is one layer stacked with eight layers (or more) on the other layer, and provides a bit density that is 8 times that of the non-three-dimensional version. Reference is now made to Fig. 67, which illustrates another particular embodiment of the present invention. In this embodiment, a 2-dimensional array 5076 includes an isolation layer 5078, which electrically isolates the array 5076 from a substrate (not shown). The insulation layer may be any conventional insulation / insulation layer, such as silicon oxide. Above the isolation layer 5078, a plurality of spaced-apart bit lines 5080, 5082, 5084, and 5086 are arranged. The bit lines 5080, 5082, 5084, and 5086 are preferably formed of N + doped polycrystalline silicon, but p + doped polycrystalline silicon and any suitable electrical conductor can also be used. A deposition step is used to fill the areas 5088, 5090, 5092 between adjacent bit lines 5080, 5082, 5084, and 5086 with a filler. The filler must be an electrical insulator. Similarly, although silicon oxide is convenient, other materials can also be used. Then a CMP step is used to planarize to expose the bit lines. Then, a layer of 5094 semiconductor material (such as P-doped polycrystalline silicon) is deposited on the bit lines 5080, 5082, 5084, 5086 by contact. An ONO layer 5096 is disposed on the semiconductor layer 5094; a conductive word line 5098 is disposed on the ONO layer 5096. According to a presently preferred embodiment, the bit lines 5080, 5082, 5084, 5086 and word line 5098 are formed of N + doped polycrystalline silicon. During thermal processing, N + outer diffusion regions 5100, 5102, 5104, and 5106 are formed in the P-doped semiconductor layer 5094. The channels 5108, 5110, and 5112 between adjacent N + outer diffusion regions become the channels of NMOS transistors, and the threshold voltage is controlled by -90.-This paper size applies the Chinese National Standard (CNS) Α4 specification (210X297 mm) 540086 A7 B7 V. Description of the invention (88) Whether there is trapped charge in the nitride layer of the dielectric stack 5096. Those skilled in the art will understand that semiconductors of the opposite conductivity type are also available. If there are conductors other than the doped polycrystalline silicon for the word lines and bit lines, the doped regions in the semiconductor layer 5094 must be formed there by means other than external diffusion. FIG. 68 is a top plan view of the memory array of FIG. 67. FIG. As shown in FIG. 68, the word lines 5098 are arranged as an intersection array above the bit lines 5080. Although the word line and the bit line are arranged at right angles to each other (i.e., at an angle of 90 degrees) in Fig. 68, the angle between the word line and the bit line may be different from 90 degrees. Moreover, outside the boundaries of the memory array, the word lines and bit lines can change angles and even be parallel to each other. Moreover, the terms "rail stacking" or "rail" should be used to refer to conductors arranged in a straight line. However, the rail stack or rails can be bent, twisted, or turned as necessary. Now see Figure 69. The memory array of Figure 67 is extrapolated to a single-stone three-dimensional array. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level. Two-dimensional arrays are very different. They can be formed separately and assembled together to form a non-monolithic memory device. Each device stage 5076 should be equivalent to that shown in Figure 67; and an isolation layer (ie, an interlayer insulation layer) 5078 is used to separate each stage. The dotted line in FIG. 69 outlines a single cell (ie, a small FT EEPROM) 5099. Cell 5099 is located at the device level "j", where the word lines (n, j) intersect the bit lines (m, j) and (m + l, j). Referring now to FIG. 70, another specific embodiment of the present invention is illustrated. In this concrete example, a bottom gate; f ^ TFTs array is formed. A two-dimensional memory array 5114 is disposed on a substrate. An isolation layer 5116 is configured so that the memory array 5114 is separated from the substrate (not shown) or another level (not shown) of the memory array -91-This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (21〇 x 297 mm) binding

Line V. Description of the Invention (89) Off. A plurality of spaced-apart word lines 5118 are arranged on the insulation layer 5116. Above the word line 5118, a charge trapping medium film 5120 is arranged, such as an ONO dielectric stack. Above the charge trapping medium 5120, a plurality of spaced-apart bit lines 5122, 5124, 5126, and 5128 are arranged. A semiconductor material film 5136 is arranged in the spaces 5130, 5132, 5134 between the bit lines 5122, 5124, 5126, and 5128. This film can be deposited into the spaces 5130, 5132, 5134; or it can be deposited or grown on the charge trapping medium 5120, and then etched through a mask. This is to form bit lines 5122, 5124, 5126, 5128 after it is formed Was formed. This memory array version roughly reverses the design on the upper side of Figure 69. Therefore, the bit lines are trenches to be filled with N + doped polycrystalline silicon. Prior to filling, η-type implantation is performed to form the source and drain of the MOS device. In addition, no dopants may be used at the bottom of the trenches, and instead a refractory metal may be used to form the source and drain electrodes. Now see Figure 71. The memory array of Figure 70 is extrapolated to a single-stone three-dimensional array. Each stage 5114 should be equivalent to that shown in Figure 70; and an isolation layer 5116 is provided to separate each stage. Referring now to Fig. 72, which illustrates another specific embodiment of the present invention, each bit line is used as a bit line for TFTs in two device levels. In this embodiment, a memory array 5140 includes a lower word line 5142 and an upper word line 5144. The bit lines 5146, 5148, 5150, and 5152 are arranged between the upper word line 5144 and the lower word line 5142. In a manner similar to FIG. 67 and FIG. 69, an upper semiconductor film 5154 is disposed between the bit lines 5146, 5148, 5150, and 5152 and the upper word line 5144. The lower semiconductor film 5156 is disposed between the bit lines 5146, 5148, 5150, and 5152 and the lower word line 5142. In the upper semiconductor film 5154 and the lower semiconductor _ -92-, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 540086 A7 B7 V. Description of the invention (90) In the body film 5156, the outer diffusion area The bit lines 5146, 5148, 5150, and 5152 are formed adjacent to each other. A lower charge storage medium film 5158 is disposed between the lower word line 5142 and the lower semiconductor film 5156. An upper charge storage medium film 5160 is disposed between the upper word line 5144 and the semiconductor film 5154. Note that the layers in this embodiment are mirrored. Now see Figure 73. The memory array of Figure 72 is extrapolated to a monolithic three-dimensional array. It is envisaged that each device level 5140 contains two word lines and two T-FT active regions, and a plurality of bit lines arranged between the active regions. Alternatively, it is conceivable that each device level 5140 is a single word line 5142 and is disposed between two TFT active regions. Thus, each device level may include one word line level and two bit line levels, or may include one bit line level and two word line levels. Each TFT active area shares a bit line and a word line with another TFT active area configured on a different level. An alternative embodiment of a bottom gate TFT is illustrated in FIGS. 81A-81H. The pathways of Figures 81A-81H are somewhat similar to those of Figure 70. The layer 5116 is an insulating layer such as an oxide, and separates the memory array structure 5114 from other memory array levels or from the substrate. The layer 5118 is a conductive word line layer. Layer 5120 is a 0-N-0 dielectric stack. The layer 5136 is a semi-conductive film material (the word line and the bit line are P-type when the N + polycrystalline is broken). In FIG. 81B, an oxide layer 5190 is deposited or grown. In FIG. 81C, the oxide layer 5190 is masked by a mask 5192 (ie, a photoresist mask). In FIG. 81D, the unmasked portion of the halide layer 5190 is etched in a conventional manner. In FIG. 81E, the mask 5192 is removed, and the semiconductor layer 5136 is implanted with η-type ions, and an N + implanted area is formed at the etching opening in the oxide layer 5190. -93- This paper size applies China National Standard (CNS) Α4 specification (210 × 297 mm) binding

Line 540086 A7 B7 V. Invention Description (91) 5194, as illustrated in Figure 81F. In FIG. 81G, an N + layer 5196 is deposited to fill the gap in the oxide, and contacts the N + implanted region 5194 to form an N + material bit line 5198 to provide a contact with the 0-N-0 layer 5120. In FIG. 81H, the N + layer 5196 is planarized to form bit lines 5198 as shown, and the NMOS TFT array is completed. Of course, the conductivity type of these layers and dopants can also be reversed to construct a PMOS TFT array. Forming more device levels and separating them with isolation layers can build a multi-layered version of the memory array of Figures 81A-81H. Figure 82A-82I illustrates a top gate TFT array instead of a specific embodiment . In FIG. 82A, an oxide or insulating layer 5200 is disposed on a substrate (not shown). In FIG. 82B, a layer of a first conductivity type 5202 semiconductor material is disposed on the oxide layer 5200. The semiconductor material may be P-doped amorphous silicon. On this layer in FIG. 82C, a hard nitride CMP barrier layer 5204 is deposited to prevent the CMP process from being ground into the layer 5202. In FIG. 82D, the memory array in this construction is masked by a mask 5206 (which is a photoresist mask). Etching is being performed in Fig. 82E to form the aperture or trench 5208 shown in Fig. 82F. In Fig. 82G, a conductive layer 5210, such as doped polycrystalline silicon, is deposited. In FIG. 82H, this layer 5210 is ground down by CMP, leaving N + bit lines 5212 with a P-doped region 5214 in between. After heat treatment, an outer diffusion region 5216 is formed, as shown in FIG. 821. The amorphous silicon layer 5202 is recrystallized into a polycrystalline silicon layer. In FIG. 821, a localized charge storage film 5218 is disposed on the bit line 5212: a conductive film 5220 is disposed on the localized charge storage film 5218. The conductive film 5220 is patterned to form a word line; the charge storage film 5218 is also patterned. So -94- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 B7 5. Description of the Invention (92) A rail stack including the word line and the charge storage film is formed. The charge storage medium film (also referred to herein as a "local charge storage film" as used herein) must be able to retain localized electrons, that is, it must be free of lateral conduction. In a specific embodiment, a charge trapping layer can be formed in a dielectric stack 5160 (as shown in FIG. 77). For example, the charge storage medium may be a dielectric stack 5160, which includes a first oxide layer 5162 adjacent to a polycrystalline silicon film 5164, a nitride layer 5166 adjacent to the first oxide layer 5162, and an adjacent The nitride layer 5166 is adjacent to the second oxide layer 5168 of a polycrystalline silicon control gate 5170. Such a dielectric stack 5160 is sometimes referred to as an ONO stack (oxide-nitride-oxide stack) when referenced. If necessary, other suitable charge trapping dielectric films can also be used, such as silicon implants or silicon-rich oxides. The charge storage medium may be formed of a plurality of electrically isolated nanocrystals 5172, as shown in FIG. 78. Nanocrystals are small groups or crystals of electrically conductive material that are electrically isolated from each other. The use of nanocrystals for charge storage media has an advantage: because they do not form a continuous film, they are self-isolating. Nanocrystalline 5172 enables multiple self-isolated charge storages to form. The nanocrystal 5172 may be formed of a conductive material such as silicon, tungsten, or aluminum. For self-isolation, nanometer crystals must have a material group size smaller than half the cell spacing to isolate the floating gates of vertically or horizontally adjacent cells. That is, the nanocrystal or material group 5172 must be small enough so that a single nanocrystal 5172 cannot bridge vertically or horizontally adjacent cells. By depositing silicon, the silicon has a very high surface diffusion rate relative to its adhesion coefficient, thereby forming silicon nanocrystals. For example, silicon nanocrystals can be chemically vapor deposited (CVD).

Line V. The description of the invention (93) is formed. This system decomposes the dream at a very low pressure (in the range of i mTorr to 200 mTorr) (H4), and the temperature is 2 micron. c Fan Park. In such a process I a very thin deposit (50-250 angstroms) will form a cut island. During the accumulation, if you shoot into it, you will get the power of money and still get nano crystals. In an alternative embodiment of the present invention, metal nanocrystals (such as crystals) can be formed. Second, they are formed from -metal standard plating, and the warm phase is at the temperature of the metal sulfidation temperature to sinter the metal. Nano crystals are formed. It can form crane nano crystals, which are reaction gases for making H source gas (such as wf6 and GeH4) by chemical vapor deposition under extremely low pressure; kun compound. In another embodiment of the present invention, a continuous floating gate material film can be deposited and then precipitated (by heating) to form a silicon bird in the film. '. It should be understood that nanometer crystals are better for floating gates because of the self-isolating quality of nanocrystals. Nevertheless, continuous films can still be used to form floating interrogators, such as (but not limited to) metal (Such as Xun, or financial film (such as polycrystalline or amorphous fragments converted to the necessary conductivity type, N + fragments are typical). If you use a connected film as a local charge storage film, you will The film is etched non-isotropically and its portion is removed in order to electrically isolate the strip of the film. Similarly, small floating gate materials (such as thickly doped polycrystalline silicon) are embedded in, for example, oxides. The layer of insulator is also published as a local charge storage medium. When using external diffusion in a multilayer device, there is one important point: different levels will be exposed to different heat treatments. That is, the bottom layer will be exposed to each heat treatment step. The top layer is only exposed to the last few heat treatment steps. Since the performance characteristics of the transistor of the MOS memory should not show substantial differences with the layer of the array, and not allowed to be immersed by lateral diffusion, the source / Used when the drain region is formed t 540086 A7 B7 five described (94) of the invention, the thermal budget (thermal budget) and mechanism of a a ^ (CNS) -96- mm) paper suitable scale. Where the bit line is doped with N + and the semiconductor film is doped with P-, the phosphorus may not be used as a dopant, but antimony may be used instead, because antimony exhibits a lower diffusivity than phosphorus. It is also possible to design the dopant settings in the bit line polycrystalline silicon to allow different out-diffusion. This point is shown schematically in FIG. 76. For the different thermal budgets of polycrystalline silicon deposition, after clarifying the characteristics of the polycrystalline silicon dopant diffusion effect, how far away from the N + doped material from the P-doped body region can be used to memorize in the array Body functions are easily determined. If necessary, the front can also be used here, and can be directly planted. In FIG. 76, the bit line indicated as ⑻ is closer to the top of the memory array than the bit line indicated as (b). In other words, bit line ⑷ is above bit line (b) in the array. During the heat treatment, the dopant in the bit line will diffuse upwards throughout the bit line and diffuse out into the P-polycrystalline silicon layer to form source and drain regions. In this way, the source and drain regions in the multiple stages will be mixed equally as shown in Figure 69. To program the first bit in the cell selected in Figure 69, WL (n, j) is high. Pulse (9-13 volts, high impedance), while BL (m, j) is grounded, and BL (m + l, j) is high pulse (three-sided 8 volts, low impedance). BL (m, j at level j) ) All BL's on the left remain grounded, and BL (m + 1, j) on the jth stage all BL's on the right remain at the same voltage as BL (m + 1, j). All other WL's on the jth stage remain grounded to ensure that all other MOS devices between BL (m, j) and BL (m + 1, j) are off. All other BL's and WL's on all other layers are allowed to float. This means that the selected unit MOS device is the only one that is on and energized, and optimizes the generation of hot carriers and the charge trapping dielectric near the drain (by BL (m + l , As defined in j)). _-97 -__ This paper size uses Chinese National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 B7 V. Description of the Invention (95) To read the first bit, BL (m + 1, j) is the source and BL (mj) is the drain. The former is grounded, the latter is raised to a readout voltage (~ 50 millivolts to 3 volts, preferably 1-3 volts), and WL (m, j) is pulsed to a readout voltage (~ 1-5 volts). Similarly, all BL's to the left of BL (m, j) remain at the same potential as BL (m, j), and all BL's to the right of BL (m + 1) j are grounded. All other WL's on the same level are grounded, and all other MOS devices between the two BL's are turned off. All other BL's and WL's at all other levels are allowed to float. To program and read the second bit in the same cell, the voltages on BL (m, j) and BL (m + 1, j) are reversed by comparing the above. Note that the main area of the MOS memory transistor is floating and can be made into a thin area (defined by the deposition tool, for example, several hundred angstroms is preferred). Making this area thin can prevent the device from returning quickly, and it can also prevent the programmed current from rising rapidly. Memory erasure can occur in the memory block, and slow Freud-Norhan tunneling and thermo-hole injection can be used in combination. Since the MOS body is floating and causes very small band-to-band tunneling and burst collapse, the erase current will be small. When erasing occurs, the word line is either grounded or held at a negative C * -5 volts) and all bit lines are held at a certain positive voltage. The erasing process will take more than 100 milliseconds, and can be performed at each memory level, or even the entire memory at one time. Non-selected bits with a shared word line should be able to withstand the worst-case period of the stylized voltage on that word line. Figure 74 shows a summary of this point in one level of the matrix. If each bit (ie, half a unit) takes time t to be programmed, and there are N units on each WL, the worst-case stylized bit will go through -98- this paper scale Applicable to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 ____ B7 V. Description of the invention (96) ~ (2N-l) t time (here the stylized voltage will be applied to the muscle). For any stylized unit, if Vt is not shifted by a "minimum" amount, the gate stress is programmed to disturb the situation; ^ Not evil. With the use of hot electrons to achieve programming, the time and voltage are shorter and smaller than the time and voltage required to tunnel out of the charge trap, respectively. In addition, during the stylization of selected cells, floating unselected bit lines can effectively reduce the total stress on any one bit. As a result, only the selected bit line of this ground will be subjected to a full programmed voltage across the dielectric. Non-selected bits that share a bit line with selected bits should be able to withstand the worst-case period of stylized electrical dust on the drain. Figure 75 shows a summary detail on this point, with a section shown along a one-bit line. Similarly 'if there are M units on any bit line, and any bit takes time t to be programmed, then the worst case on a stylized bit; and the extreme stress will be last (Ml) t. Therefore, after undergoing such stress, the Vt shift in the programmed bits should be minimal. If a unit generates enough hot carriers during a readout, and finally (over 10 years of life) program the previously erased (unwritten) bits, readout disturbance or "soft write (soft write) ". This is usually an accelerated test to ensure that the output voltage of the brake does not shift the threshold voltage of the neutral unit by more than a minimum amount. In the above device, the N + or p + -doped polycrystalline silicon should be doped with a dopant density of about 1 X 110i9 to about IX 1021 atoms / cm3, and preferably a thickness of about 500 Angstroms to about 1 Å. 〇〇〇angstrom range. ^ Or N-doped semiconductor film should be doped to a dopant density of about} X 10! 6 to about 1 X 1018 atoms / cm 3. • 99- This paper size applies to China National Standard (CNS) A4 (2l0x 297 mm)

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Line 540086 A7 B7 V. Description of the Invention (97) It should be understood that each semiconductor region shown can be manufactured with opposite polarity by inverting the conductivity type of each silicon region while maintaining the dopant concentration range. This makes it possible to manufacture not only NMOS devices, but also PMOS devices if necessary. In addition, the silicon film used for device formation can be recrystallized into single crystal silicon or polycrystalline silicon. In addition, the silicon film may be a silicon alloy film (such as a silicon germanium film), and ions with η-type or p-type conductivity are doped to a necessary concentration. If there is a polycrystalline broken word line and a bit line, whose lateral conductivity is necessary to be south, then a layer of conductive metal may be deposited in the word line or bit line, as illustrated in FIG. 79. In FIG. 79, the bit line 5174 is formed of a thick N + doped polycrystalline silicon .1766, and thus is electrically conductive. To further reduce the resistance, a layer of refractory conductive metal (such as titanium 5178 "can be placed within bit line 5174 or on one or more tables of polycrystalline silicon 5176. The laterally conductive polycrystalline fragment breaks down to form a wheat compound. IV. Flash memory array with rail stack configuration In previous embodiments, TFTs were arranged in a virtual ground array (VGA). In the VGA illustrated by the specific embodiment, each EEPROM is programmed by hot carrier injection. When hot carrier injection is performed, it crosses a diode (that is, the source and sink of a TFT EEPROM). Voltage is applied. The hot carriers (ie, hot electrons and holes) that travel from the source through the TFT EEPROM channel to the drain are injected into the channel near the configured charge storage area. This procedure is two Relatively high power events. _ In low power portable applications, both programming / erasing and readout power are important. The operation is based on Fowler-Norhan tunneling ("FN tunneling"). Flash non-volatile memory can be used for this Stylized and erase both the application. _ _ This paper -100- scale applicable Chinese National Standard (CNS) A4 size (210X 297 mm) stapling

Line 540086 A7 B7 V. Description of the Invention (98) FN tunneling is caused by the application of a voltage across the dielectric. Thus, in a TFT EEPROM, a voltage is applied between the control gate and the source and / or drain regions of the TFT for writing and erasing by the FT EEPROM. This is very different from the hot carrier injection stylization; in the hot carrier injection stylization, the voltage is applied between the source and drain regions. Flash memory arrays that are programmed and erased by FN tunneling operation are advantageous because thousands of bits can be programmed at the same time. Also, FN tunneling is a very efficient programming method because most (nearly 100%) current uses are to program the device. This is very different from hot carrier injection; in hot carrier injection, only about 1-2% of the source-drain current is used to program the device. Thus, in a preferred embodiment of the present invention, charge storage devices (such as TFT EEPROMs) are arranged in a flash memory array configuration. The TFT EEPROMs can be arranged in a guide post, self-aligned TFT, or rail stack configuration of previous embodiments. Preferably, the TFT EEPROMs are arranged in a rail stack configuration. VGA is not compatible with FN tunneling, because the entire channel polycrystalline silicon system is reversed along the length of the word line subject to high pulses, and other units other than one unit to be programmed are also programmed. Therefore, the FN tunneling rail stack (intersection) flash array is different from VGA, because in the FN tunneling array, the active polycrystalline silicon layer is shaped into a polycrystalline silicon island, and FN tunneling is allowed to be programmed. In this way, an additional lithographic masking step is added to the manufacturing process of the rail stack array, and the polycrystalline silicon active layer in each device unit is etched to form a polycrystalline silicon island. The charge storage area in each unit can be covered with the same photoresistance mask. _-101 -_ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 540086 A7 R7 V. Description of the invention (99 ) Defined (ie, etched). Fig. 83A illustrates a flash memory array with a rail stack configuration according to a preferred embodiment of the present invention. Fig. 83B shows a sectional view taken along line B-B in Fig. 83A. In FIG. 83A, the flash memory array 5230 is preferably formed on a planarized interlayer insulating layer 5231, such as a silicon oxide layer planarized by CMP. The layer 5231 is formed on a substrate (not shown) like the previous embodiment. Each device of the array (shown by dashed line 5232 in FIG. 83A) is a TFT because it is formed on an insulating layer. The array 5230 includes a first plurality of spaced apart conductive bit lines 5233, which are arranged at a first height above the substrate in a first direction. The array also contains a second plurality of spaced apart rail stacks 5235. The guide rails are stacked at a second height in a second direction different from the first direction. Preferably, the bit lines 5233 and the rail stack 5235 are arranged to be orthogonal to each other. The TFT EEPROM 5232 is formed at the intersection of the rail stack 5235 and the bit line 5233. Each of the rail stacks 5235 includes a plurality of semiconductor islands 5237; the semiconductor islands 5237 contain the active areas of the TFT EEPROMs 5232. One surface of the island 5237 contacts the bit line 5233. Each rail stack 5235 also includes a conductive word line 5239 and a charge storage region 5241 disposed between a second surface of a semiconductor island 5237 and the word line 5239. Semiconductor island 5237 preferably includes a first conductivity type (ie, P- or N-) polycrystalline silicon. However, these semiconductor islands may contain amorphous silicon if necessary. The polycrystalline silicon island 5237 includes a second conductivity type (ie, N + or P +) source and drain regions 5243. The source and drain regions 5243 are located between the bit line conductor 5233 and the rail stack 5235 _. 1Π9 -_ This paper size applies to China National Standard (CNS) A4 (210X 297 mm) binding

Line 540086 A7 R7 V. Intersection of the description of the invention (100). Bit line 5233 preferably includes a second conductivity type (ie, N + or P +) polycrystalline silicon. The bit line 5233 contacts the source and drain regions 5243. Preferably, the source and drain regions are formed by dopant diffusion from outside the bit line. Moreover, a metal or metal silicide layer (not shown in FIG. 83A) may be arranged as appropriate to contact the bit line 5233 to improve the conductivity of the bit line. The spaces between the spaced-apart bit line conductors 5233 are filled with a planarized insulating filler 5245, such as silicon oxide. The charge storage region 5241 may include a dielectric-isolated floating gate, electrically isolated nanocrystals, or a 0-N-0 dielectric stack, as in previous specific embodiments. In FIGS. 83A and B, an exemplary array having a dielectric-isolated floating gate is illustrated. Thus, in the example of FIGS. 83 A and B, the charge storage region 5241 includes: a polycrystalline silicon floating gate 5247, a tunneling dielectric 5249 (such as a silicon oxide layer), and a control gate dielectric 5251 ( Also called complete or medium polymer dielectrics, made of materials such as silicon oxide or ONO stacks. As shown in FIGS. 83A and B, the lateral side 5253 of both the tunneling dielectric 5249 and the floating gate 5247 are aligned with the lateral side 5255 of the semiconductor island 5237. The control gate dielectric 5251 extends between the semiconductor islands 5237 and contacts the planarized insulating material 5245 between the semiconductor islands 5237. When necessary, the floating gate 5247 can be made of hemispherical grains with a roughened surface. Crystal silicon is used to maximize the coupling between the control gate and the floating gate. Alternatively, horns or protrusions may be formed in the floating gate electrode or the surface of the floating M electrode may be roughened to increase the height of the floating gate electrode, thereby increasing the engagement. The word line 5239 includes a second conductivity type (ie, N + or P +) polycrystalline silicon layer, and a metal or metal silicide layer contacting the polycrystalline silicon layer. Word line 5239 is used as _-103-_ This paper size is applicable to China National Standard (CNS) Α4 specification (210 X 297 mm)

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Line 540086 A7 B7 V. Description of the Invention (⑻) The control gate of the TFT EEPROM, and the position is covered with a charge storage area 5241. In this way, each TFT does not need a separate control gate to be formed. In a preferred aspect of this specific embodiment, the rail stack 5235 is disposed on the bit line 5233, as shown in Figs. 83A and 83B. However, if necessary, the rail stack 5235 in each device level may be configured below the bit line 5233, as described in a previous specific embodiment with respect to FIG. 70 (ie, forming the bottom gate TFT EEPROMs) . As shown in FIG. 83B, the word line 5239, the charge storage region 5241, and the semiconductor island 5237 (i.e., the rail stack 5235) are aligned on a plane 5256 that is orthogonal to the substrate and parallel to the source-to-drain direction. The rail stack 5235 is separated by a second planarized insulating layer 5257, such as silicon oxide. Although the flash memory array may include a two-dimensional array, it is preferred that the flash memory array includes a single-stone three-dimensional array having a plurality of device levels. For example, three device levels are shown in FIG. 83A. These device levels are separated by an interlayer insulating layer 5259, such as a silicon oxide layer. When necessary, the layers 5257 and 5259 may include the same silicon oxide layer, and the silicon oxide layer is deposited on and between the guide stack 5235 and then planarized by CMP. To program the selected TFT EEPROM 5232, either ground its drain bit line or its source bit line 5233 (or both), and connect device 5232 (which is a high-impedance node) next to it. The selected word line 5239 is applied with a positive stylized voltage. All other word lines on the same level are grounded, and all other bit lines on the same device level can float or be placed at a slightly positive voltage. This means that only the selected unit 5232 is subjected to a stylized voltage across. Through capacitive coupling, the floating gate 5247 is pulled high and the source and / or drain 5243 are grounded. Electron from source __- 104-_ This paper size applies to China National Standard (CNS) A4 (210X 297 mm) binding

Line 540086 A7 B7 V. Description of the invention (102) and / or the drain 5243 tunnel to the floating gate 5247, and an inversion channel is formed in the silicon channel 5237. To program such a unit to obtain a threshold voltage shift of about 5 volts in about one millisecond, the required current is several picoamps. To erase the cell, the same bit line 5233 is grounded and a negative voltage pulse is applied to the selected word line 5239. All other word lines are either grounded or floating. All other bit lines are floating or placed on a slightly negative voltage. The plurality of word lines are pulsed to a high-negative value and all bit lines are grounded, thereby simultaneously erasing the plurality (or all) EEPR0M cells in the array. Alternatively, the selected word line is grounded, and the bit line of the selected cell is positively pulsed. All other word lines are floating or subject to a slight positive pulse, while all other bit lines are grounded. Programming and erasing with FN tunneling alone can use low currents and promote massive parallelism in programming and erasing. Many units 5232 can then be programmed in parallel. For example, to get a 5 volt shift, a thousand cells would require a total current of about 2 nanoamps, and on average each cell is programmed in about 1 microsecond. During programming and erasing, parasitic leakage current is small because large voltages are not applied across the polysilicon diode (ie, source / channel / drain junction). During the readout period, the parasitic leakage current is small because the source-to-drain voltage is small. These units can be programmed using a 10-20 volt programming voltage. In the above Figs. 83A and B, a small cell size is obtained. However, only the positive threshold voltage (which is reachable for NM CMOS J [FT EEPROMs] shown in Figures 83A and B "would cause a large number of bit line-to-bit line parasitic leaks. In a second preferred aspect of the flash memory (as shown in FIG. 84), an access transistor (ie, a TFT EEPR0M) is added to each cell so that a positive There is also a negative threshold voltage. -105- This paper size applies to China National Standard (CNS) A4 (210X297 mm) binding

Line 540086 A7 _R7_ V. Description of the Invention (103) Figure 84 illustrates one of the built-in access transistors 5261 in each cell, and the threshold voltage can be set to a slightly positive value. Using the access transistor 5261, the actual unit transistor (ie, the FT EEPROM 5232) can have a negative threshold voltage, without causing bit line leakage, and avoiding a special "erase and check" algorithm This algorithm is used to prevent excessive erasure. Furthermore, the access transistor can also reduce the band-to-band tunneling leakage of defect-based TFTs, which can occur at negative gate voltages and can be problematic in stylized cells (ie, floating gates can Full of electrons); see S-Hur [SH Hur] et al., "Polycrystalline Silicon Thin Film Transistor with Foldable Floating Gate, Erasable Programmable Read-Only Memory Cell" (A Poly-Si Thin -Film Transistor EEPROM Cell with Folded Floating Gate), IEEE Trans. Elect · Dev · Volume 46 (February 1999), pages 436-438, which are incorporated herein by reference. As shown in FIG. 84, the semiconductor island 5237 includes the channel regions 5263 and 5265 adjacent to the access transistor 5261 and the EEPROM 5232. The word line 5239 controls the formation of EEPROMs between the common source 5243A and the drain 5243B. The gate, and the gate electrode of the access transistor. An insulating layer 5251 forms a common EEPROM control gate dielectric and access transistor gate insulating layer. A floating gate 5247 and a tunneling dielectric 5249 are located between the word line 5239 and the channel area 5265 of the EEPROM 5232. To program the floating gate 5247 of a cell 5232/5261, ground its source bit line 523 A, make the drain bit line 5233B float, and apply a high positive to the word line of the selected cell Voltage. The electrons are then tunneled to the floating gate. All other bit lines on the same package JL level can be left floating or placed at a slightly positive voltage, while all other word lines on the same device level are grounded. To read it out, the paper size of _____- 106-_ shall be bound to the Chinese National Standard (CNS) A4 (210X 297 mm).

Line 540086 A7 R7 V. Description of the invention (104) The word line pulse of the selected cell reaches a read voltage higher than the threshold value of the electrical waste of the access transistor, and the source bit line of the cell is grounded and drained. The extreme bit lines are set at a low positive voltage, such as 1 to 3 volts. All other bit lines on the same device level can be left floating or grounded, while all other word lines on the same device level are grounded. To erase the cell, the word line is pulsed to a high negative voltage and the source bit line is grounded. To erase the entire array, all word lines are pulsed to a high negative voltage, and all source bit lines are grounded. In another preferred aspect of the flash memory array, a gate-to-drain offset region 5267 is provided to reduce the drain leakage of the TFT from band-to-band defects, as shown in FIG. Thus, in the example of FIG. 85, the word line 5239 and the charge storage region 5241 are offset from the drain region 5243B. A thick insulating layer 5269 is located between the semiconductor island 5237 and the word line 5239 in the offset region 5267. The floating gate 5247, the tunneling dielectric 5249 and the control gate dielectric 5251 have aligned lateral sides 5253A and B. Only the lateral side 5253A is aligned with the lateral side 5255A of the semiconductor island 5237. The width of the semiconductor island 5237 is larger than the width of the floating gate 5247, the tunneling dielectric 5249, and the control gate dielectric 5251. If necessary, in the specific embodiment of Figs. 84 and 85, a non-nano crystal charge storage region may be used instead of the floating gate charge storage region. Moreover, the devices of Figs. 84 and 85 may be formed with a bottom gate configuration (i.e., bit lines above word lines) when necessary. In the flash memory arrays of Figures A3A and B, the cell size of each bit is about 8F2 / N to about 10F2 / N, where F is the minimum feature size and N is the number of device levels in the array. In the flash memory arrays of FIGS. 84 and 85, the cell size of each bit is about 9F2 / N to about 11F2 / N. In this way, you can get the unit size of each bit _'_- 107-_ uΘ to do; * Tian You Yin Yin Xuan Zun Zhuan (CNS) A4 specifications (210X297 Gong)

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Line 540086 A7 R7 V. Description of the invention (105) inch is about 8F2 / N to about 11F2 / N. This unit size is more advantageous than commercially available flash memory arrays; commercially available unit sizes range from 7.7F2 to 13.9F2. If the effective cell size of a commercially available device is included in the access transistor and contacts, there are cell sizes ranging from 9.8F2 to 19.2F2 due to redundancy. In any case, if the flash memory array of this embodiment is formed as a three-dimensional array (i.e., N > 1), the cell size per bit is significantly smaller than that of the prior art. For example, when N = 2, the unit size is about 4F2 to 5.5F2. With N > 2, the cell size is even smaller. The method of manufacturing the flash memory array of FIGS. 83-85 is illustrated in FIG. 86. 86A-D illustrate a method of manufacturing the flash memory array, in which word lines in each device level are arranged on bit lines. A first conductive layer is etched with a first photoresist mask to form a plurality of spaced apart bit line conductors 5233 at a first height above a substrate (not shown). The bit line conductors 5233A and B extend in a first direction, as shown in FIG. 86A. Preferably, the bit lines contain polycrystalline silicon and a metal or metal debris layer. A first insulating layer 5245 is deposited on and between the bit line conductors 5233A, B. The insulating layer 5245 is planarized by CMP until the top surfaces of the bit line conductors 5233A and B are exposed. On the exposed bit line conductors 5233A, B and the planarized insulating layer 5245, a stack is deposited, which contains a first semiconductor layer 5237 and a charge storage film, as shown in FIG. 86B. The layer 5237 may be an amorphous silicon or polycrystalline silicon layer. In FIG. 86B, the charge storage film includes a tunneling dielectric layer 5249 and a floating gate layer polycrystalline silicon layer 5241. Alternatively, the charge storage film may be a nanocrystalline stacked or dielectrically isolated. A second photoresist layer (not shown) is formed on the stack, and the lithographic pattern is patterned into a mask. Use this photoresist layer as a mask, layers 5237, 5249 and 5247 stacks _-108-_ This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm)

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Line 540086 A7 B7 V. Description of the invention (H) 6) The stack is etched to form a plurality of first rail stacks 5271 (for clarity, only one such rail stack is shown in FIG. 86C). The first rail stack 5271 is on a plane parallel to the substrate and extends in the same direction as or substantially the same as the bit line conductor 5233. The first rail stack 5271 includes a semiconductor rail 5237 and a charge storage area rail 5247/5249. The first rail stack 5271 has at least one aligned lateral edge 5253/5255. In FIG. 86C, the same photoresist mask is used for patterning. The first rail stack 5271 has two such aligned lateral edges; the mask is removed after the etching step. If floating gate-type EEPROMs are to be formed, the control gate insulating layer 5251 is deposited on the first rail stack 5271 and the interval 5273 therebetween, as shown in FIG. 86D. Thus, the layer 5251 extends beyond the transverse edge of the first rail stack 5271. If nano-crystalline EEPROMs of 0N0 stack or dielectric isolation are to be formed, the U-series deposits a semiconductor layer 5237 and patterns it into a first rail stack 5271 after deposition. Then, on the patterned first rail stack 5271, a layer containing 0N0 stacks or dielectrically isolated nanocrystals is deposited, and then a conductive layer 5239 is deposited for word lines. A second conductive layer 5239 is deposited on the control gate insulating layer 5251. Preferably, layer 5239 includes polycrystalline debris and metal debris sublayers. A third photoresist mask (not shown) is formed on the second conductive layer 5239. The second conductive layer 5239, the control gate dielectric 5251, and the first rail stack 5271 are etched again, and a plurality of second rail stacks 5235 are formed, as shown in FIG. 86D. The second rail stacks include the patterned second conductive layer forming the word line 5239, a charge storage area island 5247/5249/5251, and a semiconductor island 5237. The formation of the source 5243A and the drain 5243B areas is based on a second conductivity type _____________-109-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 ____R7_ 5. Description of the invention (107) (ie, N + or P +) The dopant diffuses from the first plurality of spaced apart conductors into a first conductivity type (ie, P- or N-). Semiconductor island 5237. The source and non-electrode regions can be formed at any time in the manufacturing sequence after the semiconductor layer 5237 is deposited on the bit line conductors 5233A, 5233B. For example, after the second rail stack 5235 is formed, the device may be annealed to diffuse the dopant into the source and non-electrode regions' and recrystallize the amorphous fragmentation layer 5237 into a polycrystalline layer (or Increase the grain size of layer 5237). The external diffusion annealing and the recrystallization annealing may occur during the same or separate heating steps. For example, recrystallization annealing can occur immediately after layer 5237 is deposited. The alignment of the side surface of the second rail stack 5235 is on the flat surface that has been intersected with the substrate and is parallel to the length of the extending direction of the source electrode 5243 eight to the drain 52438, as shown in Figure 83B Show. A control gate dielectric 5251 is deposited between the word line 5239 and the first insulating layer 5245. The control gate dielectric 5251 is part of the second rail stack 5235, and the control gate dielectric is aligned on the flat surface that is always across the substrate and parallel to the source to drain direction, and is aligned with the semiconductor island 5237. , Tunneling dielectric 5249, floating gate 5247, and control gate 5239, as shown in Figure 83B. During the second rail stack 5235 etch, the first rail stack 5271 turns into an island. A second insulating layer 5257 'is then deposited on the first rail stack 5235 and planarized by CMP to the same level as the second rail stack, as shown in Figure 83β. An interlayer insulation layer 5259 is further deposited on the second insulation layer 5257 and the second conductor stack 52a. When necessary, a single insulating layer may be deposited on and between the first-rail stack 5235 to form a second insulating layer 5257 and an interlayer insulating layer 5259; the single layer is then planarized by CMP. If necessary, 'a plurality of additional devices can be formed monolithically on layer 5259 ---------- 110- ____ This paper size applies to China National Standard (CNS) Α4 specification (21〇X 297 Mm) Staple

Line 540086 A7 R7 5. Invention Description (108) level to form a three-dimensional monolithic array with at least three device levels, as shown in Figure 83A. The device level of each device level should be separated by an interlayer insulation layer. In an alternative method of manufacturing the flash memory array, the word lines in each device level may be formed under the bit line conductors (ie, the bottom gate TFT EEPROMs are formed instead of the top gate TFT EEPROMs) . In this alternative method, a second conductor stack is first formed, which includes a gate line 5239, a charge storage area 5251/5247/5249, and a semiconductor island 5237, as shown in FIG. 86E. Then, a first insulating layer 5245 is formed on the semiconductor island of the second rail stack 5235. If necessary, a first insulating layer 5245 may also be formed between the second rail stacks. Alternatively, before the first insulating layer 5245 is formed, another insulating layer is formed between the second rail stacks and planarized by CMP. A trench is then formed in the first insulating layer 5245. The source and drain regions 5243 are formed in semiconductor islands 5237 by implanting (or diffusing) dopant ions through the trenches. The photoresist layer (not shown) used during the trench etching can be removed before or after the ion implantation. A second conductive layer (which may contain polycrystalline silicon and silicide sublayers) is formed in the trench and above the first insulating layer, as shown in Figure 86F. The second conductive layer is planarized by CMP to form a bit line conductor 5233 covering the semiconductor island 5237. Alternatively, the source and drain regions 5243 may be formed by external diffusion from the bit line conductor 5233 without ion implantation. In a similar manner, a TFT EEPROMs flash memory array with an access transistor (as shown in Figure 84) or a drain-shift region (as shown in Figure 85) can be formed. In these methods, a stack including a tunneling dielectric 5249 and a floating gate layer 5247 is deposited on the first semiconductor layer 5237, as shown in FIG. 86B. The stack is then patterned to form the first rail stack 5271, which includes: half _-111 -_ This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 540086 A7 R7 5 Explanation of the invention (109) The conductor rail 5237 has a first width; and the charge storage area rail 5247/5249 has a second width smaller than the first width, for the purpose of stacking the first rail with an aligned lateral edge. And the drain portion of the semiconductor rail 5237 is exposed. Such a structure can be obtained by two different etching methods. The first etching method includes: forming a first light-resistant surname mask 5275 having a first width on the stack, as shown in FIG. 86G. The first semiconductor layer 5237, the tunneling dielectric layer 5249, and the floating gate layer 5247 are etched with a first photoresist mask 5275, as shown in FIG. 86G. A second photoresist mask 5277 is formed on the floating gate layer 5247, and has a second width smaller than the first width. Then, the tunneling dielectric layer 5249 and the floating gate layer 5247 (except the first semiconductor layer 5237) are etched with a second photoresist mask, as shown in FIG. 86H. The second surname engraving method includes: forming a first photoresistive surname mask 5279 having a first width on the stack; and using the first photoresistive mask 5279 to etch the tunnel dielectric layer 5249 and float The gate layer 5247 exposes a part of the first semiconductor layer 5237, as shown in FIG. 861. Then, a second photoresist mask 5281 is formed on the floating gate layer 5247 and the exposed portion of the first semiconductor layer 5237. The second photoresist mask 5281 has a second width greater than the first width (in layers 5281 and 5247/5249 May be misaligned). Then, the first semiconductor layer 5237 is etched with a second photoresist mask 5281, as shown in FIG. 86J. To form the TFT EEPROMs containing the access transistor 5261 in FIG. 84, the patterned floating gate 5247 and the exposed portion of the semiconductor rail 5237 of the first rail stack 5271 are formed to form a control gate dielectric. Layer 5251. Control. The gate dielectric layer 5251 acts on the exposed part of the semiconductor guide 5237. -112-This paper size is applicable to China National Standard (CNS) A4 (210X297 mm).

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Line 540086 A7 R7 V. Invention description (110) is the gate dielectric of the access transistor 5261. To form the TFT EEPROMs with the drain offset region 5267 in FIG. 85, the control gate dielectric layer 5251 is patterned with the floating gate 5247 and the tunneling dielectric layer 5249 at the same time to expose the semiconductive guide 5237. Drain part and part of channel silicon. A second insulating layer 5269 is formed between the semiconductor rails 5237 and the exposed portions of the control gate dielectric 5251 and the semiconductor rails 5237 to isolate the semiconductor rails from each other. The layer 5269 is relatively thick, the thickness being equal to or greater than the thickness of the charge storage region 5241. The layer 5269 is then planarized by CMP to expose the tops of the charge storage regions. Then, a word line 5239 is formed on the second insulating layer 5269 to form an offset region 5267. The non-volatile multi-programmable flash memory array of the preferred embodiment provides a multi-programmable unit in an intersection (ie, rail stack) array. It uses FN tunneling to program and erase. This enables parallel writing to many cells; and provides high-density, low-power file storage. In addition, the cell size of each layer is extremely advantageous compared to the cell size of commercially available flash memory. V. CMOS Arrays for Logic and Memory Circuits In previous embodiments, NMOS or PMOS device arrays were described. However, in another preferred embodiment of the present invention, a CMOS (inter-metal oxide semiconductor) transistor array is provided. Preferably, adjacent NMOS and PMOS transistors have a common gate. However, if necessary, adjacent NMOS and PMOS transistors can have separate gates. The CMOS device array may include a vertical pillar type CMOS device array, a self-aligned CMOS TFTs array, or a rail-stacked TFTs array, as described in any of the previous specific embodiments. These CMOS devices are preferably formed as a three-dimensional monolithic array on a substrate. However, -113- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 A7 R7 5. Description of the invention (m) These CMOS devices can also be inside or above the semiconductor substrate if necessary Formed in a two-dimensional array. The NMOS and PMOS transistors of the CMOS array can be formed in an alternating manner (that is, alternate NMOS and PMOS transistors), adjacent to each other in the same device level. However, in a preferred embodiment of the present invention, a charge carrier transistor (ie, NMOS or PMOS) is formed on another charge carrier transistor (ie, PMOS or NMOS). There is a common gate line (also called a word line in a memory device). Therefore, the array should include a plurality of vertically stacked, common-gate CMOS transistors. FIG. 87 illustrates one device level of a vertically stacked shared gate CMOS array in a rail stack configuration according to a preferred embodiment of the present invention. It should be noted that the array i can be arranged in the aforementioned self-aligned TFT or guide pillar configuration. The CMOS array of FIG. 87 is similar to the array illustrated in FIG. 73, except that different charge carrier type transistors are formed on either side of both sides of the gate line. In FIG. 87, the NMOS transistor system is arranged below the PMOS transistor. It should be understood, however, that PMOS transistors can be arranged under NMOS transistors if necessary. In FIG. 87, the CMOS device array 5300 is preferably formed on a planarized interlayer insulating layer 5301, such as a silicon oxide layer planarized by CMP. The layer 5301, like the previous embodiment, is formed on a substrate (not shown). Because it is formed on an insulating layer, each CMOS device is a CMOS TFT ^ However, these CMOS devices can be formed in a single crystal silicon substrate if necessary. The array includes a plurality of gate lines (ie, ytterbium lines) 5303 (only one gate line is shown in the cross-sectional view of FIG. 87). Preferably, the gate line includes a first N + polysilicon layer 5305 1. A silicide layer on the first polycrystalline silicon layer 5307 (Zhu-114- This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) 540086 A7 B7) 5. Description of the invention (112) such as TiSix4 WSix ), And a second P + polycrystalline silicon layer 5309 over the silicide layer. In each TFT, the gate line 5303 is used as a gate electrode. In this way, there is no need to have a separate gate electrode connected to the gate line. A first insulating layer 5311 is disposed adjacent to a first side of the gate electrode 5303. The insulating layer 5311 may be a conventional gate dielectric. Preferably, the insulating layer 5311 is a charge storage layer (ie, a charge trapping medium), such as an ONO stacked or isolated nanocrystal, to form charge storage CMOS TFTs, such as EEPROM CMOS TFTs. If floating gate type EEPROM CMOS TFTs are required, a floating gate and a control gate dielectric can be added between the insulating layer 5311 and the gate line 5303. A P-type semiconductor layer 5313 (such as a P-polycrystalline silicon layer) is disposed on the first insulating layer opposite to the other side of the gate electrode 5303. This layer contains the NMOS TFT body. The N + source and drain regions 5315 are disposed in the layer 5313. The part of the layer 5313 between the regions 5315 includes the NMOS TF channel region. Preferably, the source and drain regions 5315 are formed by diffusing out of the source and drain electrodes (ie, bit lines) 5317 by using N + type dopants. However, the area 5315 can be formed by any other method, such as masking and ion implantation. The electrode 5317 contacts the source and drain regions 5315 and is disposed on the bottom of the p-type semiconductor layer 5313 (Lang, on the other side of the layer 5313 opposite to the first insulating layer 5311). Preferably, the electrode 5317 includes an N + polysilicon track, and the N + polysilicon track extends in a direction orthogonal to the gate line 5303. If necessary, a metal or metal silicide layer 7 may be formed in contact with the electrode 5317 to improve its conductivity. However, if necessary, the electrode 5317 may contain a metal or a metal silicide instead of the heavily doped polycrystalline silicon. One-layer insulating filler layer 5318 (such as silicon oxide) -115- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 R7 ^ _ 5. Description of the invention (113) is arranged between the source and drain electrodes 5317. In this way, each NMOS TFT 5319 is located between the adjacent source and drain regions 5315 and includes layers 5305, 5311, 5313, and 5317, a portion of which is illustrated in FIG. 87. PMOS TFTs 5321 are located on top of NMOS TFTs 5319. The PMOS TFTs 5321 includes a second insulating layer 5323 adjacent to a second side of the gate electrode 5303. In FIG. 87, a layer 5323 is located on the p + polysilicon layer 5309 of the gate line 5303. The insulating layer 5323 may be a conventional gate dielectric. Preferably, the insulating layer 5323 is a charge storage layer (ie, a charge trapping medium) 'such as an ONO stacked or isolated nanocrystal to form charge trapping CMOS TFTs (such as EEPROM CMOS TFTs). If floating gate EEPROM CMOS TFTs are required, a floating gate and a control gate dielectric can be added between the insulating layer 5323 and the gate line 5303. An N-type semiconductor layer 5325 (such as an N-polycrystalline silicon layer) is disposed on the second insulating layer 5323. The layer 5325 is disposed on the layer 5323 opposite to the other side of the gate electrode 5303. The P + source and drain regions 5327 are arranged in the layer 5325 so that the region of the layer 5325 between the source and drain regions 5327 includes the channel region of PMOS TFTs. The source and drain electrodes 5329 are disposed on the N-polysilicon layer 5325 'and contact the source and drain regions 5327. In this way, the electrode 5329 is disposed on the N-polycrystalline silicon layer 5325 and is opposite to the second insulating layer 5323 on the other side of the β-plane insulating filler layer 5331 (such as silicon oxide) disposed on the source and drain electrodes 5329. between. If necessary, a metal or metal silicide layer may be formed as the contact electrode 5329 to improve its conductivity. _ So 'Each PMOS TFT 5321 is located between the adjacent source and drain regions 5327, and contains a part of layers 5309, 5323, 5325, and 5329, as shown in Figure 87 _____ -116- This paper scale applies to China Family Standards (CNS) M Specification (_ χ 297 Male Sauce) 540086 A7 ____R7_ V. The description of the invention (114). A TFT EEPROM CMOS device (5319 and 5321) is formed at each intersection of the first or third spaced apart electrodes or conductors 5317, 5329 and the common gate line 5303. When necessary, the CMOS structure can be inverted, and PMOS TFTs are formed under the NMOS TFTs. It should be understood that the NMOS and PMOS electrodes (ie, bit lines) need not fall directly on top of each other, although they should preferably have the same spacing. In this way, NMOS and PMOS transistors can have different channel lengths, but their spacing will be limited by the longer of the two channel lengths (thus the array size is also limited). In a preferred aspect, one conductivity type TFTs (i.e., NMOS or PMOS TFTs) contains a charge storage layer or region, while another conductivity type TFTs (i.e., PMOS or NMOS) does not have a charge storage region or layer. As such, the CMOS in this area includes an EEPROM TF and a non-EEPROM TFT. The TFT CMOS device array 5300 illustrated in FIG. 87 is highly planar and compact. The NMOS source and drain electrodes 5317 include polycrystalline silicon rails, and the polycrystalline silicon rails are on a first flat surface parallel to the surface of the substrate and extend above the interlayer insulating layer 5301. The p-type polycrystalline silicon layer 5313 is on a second plane, and extends over the source and drain electrodes 5317. The gate line 5303 is above a third plane and extends above the layers 5317, 5313, and 5311. The n-type polycrystalline silicon layer 5325 is on a fourth plane and extends above the gate line 5303. The PMOS source and drain electrodes 5329_ contain polycrystalline silicon conductors, and the polycrystalline silicon rails are tied on a fifth plane and extend above the N-type polycrystalline silicon layer 5325. The five planes do not intersect each other. The TFT d ^ IOS array 5300 is also self-aligned. The gate electrode 5303, the first insulating layer 5111, the p-type semiconductor layer 5313, the second insulating layer 5323, and the n-type semiconductor layer 5325 include a rail stack, which is positioned on a plane parallel to the substrate. _ -117- __ This paper size is in accordance with Chinese National Standard (CNS) A4 size (210X297 mm) 540086 A7 R7 5. Description of the invention (115) The rail stack extends perpendicular to the source and drain electrodes 5317, 5329. In this way, the gate electrode 5303, the first insulating layer 5111, the p-type semiconductor layer 5313, the second insulating layer 5323, and the n-type semiconductor layer 5325 are on a plane that is perpendicular to the substrate and parallel to the source-to-drain direction. Self-alignment is discussed in more detail below. The TFT CMOS array 5300 should be arranged in a monolithic three-dimensional array, and the three-dimensional array contains a plurality of device stages, which are vertically separated by one or more interlayer insulating layers. Each device level of the array contains a TFT CMOS device 5300, as in previous embodiments. A perimeter or driver circuit (not shown) is arranged in the substrate. It should be below the array and at least partially vertically aligned with the array, or it can be within or above the array and at least partially vertically aligned with the array. 88A-D illustrate a method of manufacturing a track stacked TFT CMOS array 5300 according to a preferred embodiment of the present invention. First, an N + polycrystalline silicon layer is deposited and patterned to form a source and drain electrode or conductor 5317. An insulating layer 5318 (such as a silicon oxide layer) is then deposited on and between the conductors 5317. Layer 5318 is then planarized by CMP to form a planarized block 5332, as shown in Figure 88A. The top surface of the conductor 5317 is exposed on the top surface of the block. A stack of several layers is then formed on block 5332. These layers include p-type polycrystalline silicon (or amorphous silicon) layer 5313, a first insulating or local charge storage film 5111, a gate layer 5303, a second insulating or local charge storage film 5323, and an n-type polycrystalline silicon (or Amorphous silicon) layer 5325. A photoresist mask (not shown) is then formed on this stack, and the stack is patterned to form a plurality of rail stacks 5333 (for clarity, only one rail stack 5333 is shown in ST88B). The mask can be removed after all layers have been patterned. Since all the layers in the rail stack 5333 are patterned during the same step, the layers in the rail stack 5333 have been handed over to the base _-118: _ This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 (Mm) 540086 A7 R7 5. Description of the invention (116) The plane of the board is self-aligned (ie, the side of the rail stack 5333 is flat). The rails are stacked to extend in a direction different from the direction of the electrode 5317. Preferably, the rail stack 5333 and the electrode 5317 extend in a perpendicular direction within the array, as shown in FIG. 88B. An insulating layer 5331 (such as a silicon oxide layer) is then deposited on the rail stack 5333 to fill the gap 5335 between the rail stacks 5333, as shown in FIG. 88C. The layer 5331 is then planarized by CMP. A photoresist mask (not shown) is formed on layer 5331, and parallel trenches 5339 are etched in layer 5331 using the mask. The trenches run parallel to the electrode 5317 and extend orthogonally to the rail stack 5333, as shown in Figure 88C. If necessary, sidewall spacers (not shown) may be formed on the sidewalls of the rail stack 5333 before the layer 5331 is deposited, as appropriate. Preferably, the spacers are made of a material different from the layer 5331. The spacers are preferably made of silicon nitride. These spacers protect the sidewalls of the rail stack 5333 during trench etch. This spacer prevents the trench etch from extending too far in the area between the gate lines beyond the top of the gate line, and is used to protect the gate against source / drain shorts. Under the layer 5331 and / or the photoresist is used as a mask, p-type ions (ie, boron or BF2) are implanted into the exposed n-type semiconductor layer 5325 via the trench 5339. A P + source and drain region 5327 is formed in the plasma branch layer 5325, as shown in FIG. 88D. Then, a p-type polycrystalline silicon layer is deposited on the layer 5331 and in the trench 5339. The polycrystalline rhenium layer is planarized by CMP or returned to ′ to form a plurality of spaced apart P + electrodes 5329 embedded in the planarized insulating layer 5331. The electrode 5329 is located above the rail stack 5333 and contacts the P + source and drain regions 5327. Since the electrical -119- this paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) binding

k 540086 A7 R7 V. Description of the Invention (117) The electrode 5329 and the source and drain regions 5327 are formed during the same lithography step, so there is no misalignment between the electrode 5329 and the source and drain regions 5327. Alternatively, instead of performing ion implantation on the trench 5339, the source and drain regions 5327 may be formed by external diffusion from the electrode 5329. The array is annealed to diffuse out from the N + electrode 5317 to form the N + source and drain regions 5315, and the amorphous or polycrystalline silicon semiconductor layers 5313 and 5325 are recrystallized. The external diffusion and recrystallization can be performed at any necessary time in the process, during the same or different annealing steps. When necessary, an interlayer insulating layer is formed on the array shown in FIGS. 87 and 88D; and another device level is formed monolithically thereon, which includes another 5300 array of TFT CMOS EEPROM devices. A routing metallization layer (preferably a non-aluminum metal layer) can be formed in the interlayer insulating layer. If necessary, additional interlayer insulation and device levels may be formed on the second level of the device to form at least three device layers. In another alternative aspect of this embodiment, a second rail stack including a gate line is directly formed on the top of the PMOS electrode 5329, without an interlayer insulating layer interposed therebetween. As such, the PMOS electrode 5329 will contain the source and drain regions in a two rail stack. In other words, a plurality of device levels can be formed without interlayer insulating layers therebetween to form a three-dimensional monolithic array. This arrangement provides f transistors with fewer processing steps, but its programming flexibility is less. As shown in Figure 89, the resulting TFT CMOS array is NMOf5319 and PMOS 5321 with a shared gate 5303. Installation moments. The array shown in Figure 89 is an unprogrammed or unset array. The array can be configured as a logic element or a memory device, which is based on the gate dielectric (ie, charge storage film or area). -120- This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm) 540086 A7 R7 V. Description of the invention (118) Breakdown to form a conductive connection connecting the gate line (ie, word line column) 5303 and the source and drain electrodes 5317, 5329 (ie, bit line) Chain; or the charge is stored in the charge storage area of either NMOS or PMOS transistor, and its threshold voltage is raised and kept closed forever. A 5300 array of FT CMOS EEPROM devices may be used to form logic elements or memory arrays. Moreover, in an unconfigured array, the same semiconductor device or system can be used as a non-fuse, or as an EPROM or EEPROM. According to a preferred embodiment of the present invention, a circuit is provided, which includes a plurality of charge storage devices and a plurality of non-fuse devices. The circuit can include a programmable gate array or a programmable logic device. Preferably, the plurality of charge storage devices and the plurality of non-fuse devices include the same assembly. This simplifies the manufacture of the circuit. When a first stylized voltage is applied to these devices, the threshold voltage of the device is increased, and the devices are then turned off. At this time, the device functions as a charge storage device. When a second stylized voltage higher than the first voltage is applied to these devices, the device also functions as a no-fuse. The second voltage may be any voltage sufficient to form a conductive chain through a charge storage region. For example, the first voltage (ie, the charge storage voltage) may be less than 5 volts, and the second voltage sufficient to form a conductive chain may be 5-50 volts, depending on the characteristics of the device. The dedicated voltage is supplied to the device by the driver or peripheral circuits. However, charge storage and non-fuse semiconductor devices with different structures can also be provided when necessary. In response, any charge storage device that functions as a non-fuse, and if a conductive chain is formed to pass through the charge storage area, it is within the scope of the present invention. In this way, if any device contains a semiconductor active area and is adjacent to the semiconductor active area -121-this paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Line 540086 A7

Charge storage region, a first electrode, and a second electrode of the conductive region, wherein when a first stylized voltage is applied to the first electrode and the second electrode, and when a conductive chain is formed across the charge storage region, the first electrode is A conductive path is formed between the first electrode and the third electrode. At this time, if the charge is stored in the charge storage area, these devices JL are all within the scope of the present invention. Therefore, it can be used as a non-fuse charge storage device, and is not limited to the rail stack πτ EEpR0Ms. Such a charge storage device includes not only EpROMs and EEPROMs formed in a single crystal semiconductor substrate, but also pillar-type or self-aligned DFT EEpROMs, as well as the two poles of the charge storage region of the previous specific embodiment. body. Figure 90 illustrates how a 4 by 4 (4x4) cell array of the circuit of Figure 89 can be programmed into an inverter 5343. First, a high voltage is applied between the gate (ie, word) line 5345 and the bit line 5347; the gate line 5345 and the bit line 5347 will be used to carry the voltage vQUi. This forms a conductive non-fuse chain 5348, which electrically connects wires 5345 to 5347. Then the 'driver circuit provides a stylized voltage to all other transistors 5350.' It raises its threshold voltage and turns it off, but Except for crystal 5355 and PM0S transistor 5357. The NM0S 5355 and PM0S 5357 transistors form the inverter. When a high voltage Vin is supplied to the gate line 5349, a low voltage Vc ^ is read, and vice versa. The voltage vss (ie, ground) and vDD (ie, power supply voltage) are pushed into the bit lines 5351 and 5353 connected to the transistors 53.55 and 5357. Figure 91 illustrates how the 4 by 4 cell array of the circuit of Figure 89 can be programmed into a two output inverse (NAND) gate 5360. First, a high voltage is applied between the gate (ie, word) line S3 and the bit line 5347; the gate line 5345 and the bit line 5347 will be used to carry out the voltage. This forms a conductive non-fuse chain 5348, which electrically connects wires 5345 and 5347. Then, the driver circuit provides a stylized voltage to all of them.

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540086 A7 R7 5. Description of the invention (120) His transistor 5350 is turned off by increasing its threshold voltage, except for PMOS transistors 5361, 5365 and NMOS transistors 5363, 5367. Transistors 5361, 5363, 5365, and 5367 form the NAND gate. The input voltage Vinl and Vin2 are supplied to the gate lines 5369 and 5371. The CMOS 5361/5363 is connected to the gate line 5369, and the transistors 5365 and 5367 are connected to the gate line 5371. The voltages Vss and VDD are supplied to the bit lines 5373 and 5375. NMOS 5367 is connected to bit line 5375, while PMOS 5361 and 5365 are connected to bit line 5373. The output voltage can be read from line 5345 or 5347; line 5345 or 5347 is connected to a blown non-fuse 5348. Figure 92 illustrates how the 5 by 6 cell array of the circuit of Figure 89 can be programmed into a static random access memory (SRAM) 5380. First, a high voltage is applied between the gate (ie, word) lines 5381 and 5383 and the bit lines 5385, 5386, 5387, and 5388. This forms a conductive non-fuse chain 5348, which electrically connects wires 5381 to 5385 and 5386, and electrically connects wires 5383 to 5387 and 5388. The driver circuit then provides a programmed voltage to all other transistors 5350, increasing their threshold voltage to turn them off, except for transistors 5389, 5390, 5391, 5392, 5393, and 5394. Transistors 5389 and 5390 are SRAM access transistors, while transistors 5391, 5392, 5393, and 5394 are alternating and turning inverters. To access the cell, a positive voltage is placed on word line 5395. The data is input to and read from BL and BL-bar, and BL and BL-bar are supplied to bit bee 5396 and 5397, respectively. The voltages Vss and VDD are supplied to bit lines 5398 and 5399. Figures 89-91 show various exemplary configurations that can be programmed. It should be noted that the above system can also be used to program any necessary logic or memory device, such as a NOR gate. Since all logic functions can be implemented by basic components (such as NAND gates), any logic circuit can be programmed into this array type. -123- This paper size applies to China National Standard (CMS) A4 specification (210X 297 mm) 540086 A7 _R7 5. Description of the invention (121). Moreover, the logic and memory devices can be programmed into the same circuit if necessary. For a logic device, the logic block size is generally (x + I) 2 times the cell area, where ⑻ is the number of inputs on the logic gate. Since the cell area can be as small as 4F2 (here F is the minimum feature size [half pitch]), for micrometers, the area per logic gate is at least 4 (F (x + l)) 2, or 2. For input NAND or NOR gate, it is 2.25 microns square. Preferably, the area of each logic gate is 4 (F (x + I)) 2 to 5 (F (x + I)) 2. This size contains one "isolated" column and row on each edge of the block and shares it with the next block. VI. Metal-Induced Crystallization A preferred embodiment of the present invention refers to a non-volatile thin film transistor (TFT) memory or logic device, which is constructed on a substrate and includes a source and a drain. And pass to the area, and this area is made by the deposition or growth of amorphous broken or polycrystalline wheat crystallized by the transition metal induced lateral crystallization (MILC) process. One or two dimensions or more, preferably three-dimensional multi-time programmable (MTp) non-volatile memory or logic consisting of such a thin-film transistor memory device β According to the first aspect of this embodiment, non-volatile based on TFT If the memory or logic early is formed in a deposited thin layer of wheat (such as amorphous stone or polycrystalline silicon), the improvement of its performance characteristics is appropriate. If the grain size of the a_Si or polycrystalline silicon is increased like single crystal silicon, this improvement can be achieved. In the past, there have been several ways to achieve the crystallization of a-Si. According to a first approach, a3i can be partially crystallized to form polycrystalline fragments by an annealing step at about g00 ° C for several tens of hours. This approach is not advantageous because the device formed in the material has low performance characteristics and requires a relatively long time to manufacture. ___ -124__ Applicable to this paper standard @National Standard (CNS) A4 Specification (21 () > < 297 Public Publishing)-540086 A7 _B7_ V. Description of the Invention (122) In this case, a transition metal or germanium catalyst can be used To induce lateral crystallization at the seed site 'to enhance crystallization. Unfortunately, most transistor-based devices made in this way have relatively poor performance characteristics (relative to single crystalline silicon); and exhibit orders of magnitude in the order of 100's (millivolts / ten-fold interval) Threshold (subthreshold) slope value and Idsat (table threshold current) of 10 's microamps / micron. The metal-induced lateral crystallization (MILC) is performed at a temperature of about 400 ° C to about 700 ° C to obtain a lateral growth rate of several micrometers (or more) per hour. To further expand the area of silicon crystals to hundreds of microns, an annealing step (eg, 900 ° C for 30 minutes) with a relatively short duration and high temperature is added to simultaneously crystallize multiple layers of a-Si (or another semiconductor) material). Note that when the crystallization temperature range is about 750 ° C to 975 ° C, if the annealing time is adjusted accordingly, there will also be desirable results. This short-duration high-temperature annealing does not saturate the diffusion region of the device covered in this article; and it can be performed once for multi-stage devices just like the low-temperature annealing step. An example of a process for recrystallizing a deposited a-Si layer according to a specific embodiment of the present invention is now illustrated and illustrated with reference to FIGS. 93-95. Those of ordinary skill in the art will now truly understand that many routine modifications to the process illustrated here are possible without affecting the concepts of the invention described herein. Referring now to Figures 93-95, a flowchart of a process for depositing (or growing) an a-Si layer for crystallization is illustrated in Figure 93. FIGS. 94A-94H illustrate vertical cross-sectional views of a Shixi wafer prepared according to the process of FIG. 93. Figure 95 illustrates the effect of a metal-induced lateral crystallization (MILC) through a seed window (seeding \ ¥ ratio 〇1〇 \ ¥ 5 plant 3424). The seed window 5424 is embedded on a standard silicon wafer. The oxide is based on a-Si. -125- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 540086 A7 B7 V. Description of the invention (123) The first step of process 5408 5406 Is to grow (or deposit) a thick oxide layer 5410 (Figure 94A) (eg, 3000 angstroms) on a standard silicon wafer substrate 5412. The next step 5414 is to bury the oxide layer 5410 A thin amorphous silicon (a-Si) layer 5416 (eg, 1000 angstroms) is deposited thereon. For example, using SiH4 as a silicon source at a flow rate of 70 SCCM and a pressure of 300 millitorr, at 550 ° C Low pressure chemical vapor deposition (LPCVD) can achieve this goal. Alternatively, layer 5416 may include a polycrystalline silicon layer. The next step 5418 is to deposit a sacrificial low temperature oxide layer (LTO) layer 5420 (eg, 3000 angstroms) ); Then in step 5419, it is patterned and etched with a mask 5422 to expose the transition metal seed Mouth 5424. These seed windows can have a slot width of about 2 microns, as shown in Figure 95. The mask 5422 can now be removed in step 5426, which is to deposit a transition metal layer 5428 on top of the LTO layer 5420 ( For example, Ni [nickel] at 100 angstroms. Although Ni is currently preferred, other transition metals can also be used. Other transition metals that can be used but are not as good as Ni are: Fe (iron), Co (cobalt), Ru (Ruthenium), Rh (rhodium), Pd (palladium), Os (rhenium), Ir (iridium), Pt (platinum), Cu (copper), and Au (gold). Germanium can also be used. The transition metal The seed window can also be introduced by implantation and other mechanisms familiar to those skilled in the art. The next step 5430 is annealing for initial lateral crystallization. This step is illustrated in Figure 94F. It is implemented within a temperature and time range. For example, annealing in a radon atmosphere at 560 ° C for 20 hours will work. Lower temperatures require longer back-off times, and higher temperatures require more annealing. Time; ordinary artisans will now recognize that it can be optimized in terms of productivity. This step is done It can meet the requirements of some devices, and provide several micrometers to tens of micrometers. 126- This paper size applies to China National Standard (CNS) A4 specification (210 × 297 mm) 540086 A7 R7 5. Silicon crystal of invention description (124) Grain size. For other devices that require higher performance and a grain size of hundreds of microns, the high temperature annealing step discussed below is required. The next step 5432 is to strip the remaining transition metal layer 5428; H2S〇4 can be used: H2O2 (4: 1), performed at 70 ° C. Then step 5434, which strips the LTO layer 5420 with HF. Finally, if necessary, a high temperature annealing step 5436 (for example, in a N2 atmosphere at 900 ° C for 30 minutes) to further crystallize the partially crystallized a-Si to form even larger grains Silicon crystal (size > 100 microns). This step gives the crystalline a-Si layer (i.e., a large grain polycrystalline silicon layer) performance characteristics similar to the conventional SOI (silicon on insulator) CMOS technology. Note that the transition metal crystalline semiconductor materials used in this article will contain detectable trace transition metals to facilitate crystallization. In normal semiconductor processing, trace amounts of transition metals (typically Fe and Ni) will escape the structure of the semiconductor manufacturing equipment (usually containing stainless steel), and will be embedded in the TFT channel to form the semiconductor film. Normally, these transition metal stocks are at levels of less than about 1014 atoms / cc. However, in the transition metal crystallization, more trace metals exceeding about 1014 atoms / cc and up to about 1018 atoms / cc are left in the crystalline semiconductor material after processing. There is usually no pollution problem; however, if a gradient of such pollution is required, the gettering material can be placed in the source and / or drain region of the D-FT to increase the pollution at the respective source and / Or the concentration in the drain region, thereby reducing the concentration of such contamination in the channel region. Due to excessive transition metal contamination, device formation should be avoided in the seed window region 5424+. The above-mentioned metal-induced crystallization method can be used to recrystallize the active semiconductor layer of any of the above devices. In this way, in the recrystallized a-Si or polycrystalline silicon, each can be formed. _-127-_ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm).

Line 540086 A7 R7 V. Description of the invention (125) Different configurations of pillar-type TFTs, self-aligned TFTs, rail-stacked TFTs, and diodes (ie, active semiconductor layers with one or more pn junctions ). VII. Metallization In the different embodiments described above, a metal silicide layer is formed, such as a polycrystalline word line or a bit line, and contacts the first layer. A better method is to use a silicon cap and a TiN layer to form a titanium silicide layer and contact a silicon layer. The titanium silicide layer is formed on an undoped amorphous silicon cap layer. The capping layer is formed on a thickly doped silicon layer, such as a polycrystalline silicon or an amorphous silicon layer, and the doping concentration exceeds 1019 / cm3 (such as 1019 / cm3 to 1021 / cm3). . The capping layer should preferably be based on a P + polycrystalline silicon or N + amorphous silicon layer. The N + amorphous silicon can be recrystallized into N + polycrystals in a subsequent annealing step. A method for forming a titanium silicide (TiSi2) layer includes the following steps. A doped polycrystalline silicon layer is deposited. For example, the P + polycrystalline silicon layer may be boron, and the doping concentration is 5 × 102G / cm3, and the thickness is about 1400 Angstroms. A capping layer of undoped amorphous silicon is deposited on the P + polycrystalline silicon layer. The cover may be 600 angstroms thick, for example. A titanium layer is deposited on the cover. The titanium layer can be, for example, 250 Angstroms thick. A titanium nitride layer is deposited on the titanium layer. The titanium nitride layer can be, for example, 100 angstroms thick. If necessary, other layer thicknesses can be used. These layers are annealed at a temperature below 650 ° C for less than five minutes. The titanium reacts with the silicon in the cap to form a Ti49 layer in the C49 phase. For example, annealing can be performed at 60 ° F for 1 minute: if necessary, based on another P + polycrystalline silicon layer on the stack, and the stack is etched into a thin "wire" or "rail" ", Such as word lines or bit lines. The line or track width can be 0.25 mm or less -128- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 540086 A7 R7 V. Description of the invention (126). The titanium silicide is then annealed at a high temperature (that is, above 650 ° C) to transform from C49 to C54 phase. For example, it can be annealed at 800 ° C for one minute before or after on-line or rail pattern patterning. Each Si / Ti / TiN film stack is annealed below 650 ° C, which minimizes dopant diffusion and the formation of thermal grooves on SiSi2. Multiple film stacks are sequentially based and etched. The description of the present invention presented above is for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed; it is possible to seek corrections and alterations made by uploading the teachings, or the invention is actually required. The drawings and descriptions are chosen to explain the principle of the present invention and its practical application. These diagrams are not necessarily proportional, and the arrays are illustrated in an outline block format. It is intended that the scope of the invention be defined by the appended patent claims and their equivalents. -129- This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

A8 B8 C8 D8 Patent Application No. 090119945 Chinese Patent Application Replacement (January 1992) ----- Patent Application Scope 1 • A memory device including: a first input / output conductor formed in a One or more of the substrates is above or above a first plane; a second input / output conductor; a semiconductor region between the first input / output conductor and the second input / output conductor at the intersection of their projections; A charge storage medium; wherein the charge stored in the charge storage medium affects the amount of current flowing between the first input / output conductor and the second input / output conductor. 2. The memory device according to item 1 of the patent application scope, wherein the charge storage medium is formed between the intersection of the first input / output conductor and the second input / output conductor. 3. The memory device of claim 2 in which the charge storage medium is formed directly on the semiconductor region. 4. The memory device of claim 1 in which the charge storage medium is formed adjacent to the semiconductor region. 5. The memory device according to item 4 of the patent application scope, further comprising a control gate formed adjacent to the charge storage medium. 6. The memory device according to item 1 of the patent application range, wherein the current flows orthogonally in the direction of the plane of the substrate and flows through the semiconductor region. 7. The memory device of claim 1 in which the semiconductor region contains doped silicon. 8. A memory device comprising: a first input / output conductor formed on a first flat surface of a substrate 540086 A8 B8 C8 D8 A patent application scope or above; a second input / output conductor formed on the first input / output conductor and having a projection intersection with the first input / output conductor; a silicon body located on the first An input / output conductor and the second input / output conductor are directly aligned with the intersection of the first and second input / output conductors; a charge storage medium; wherein the readout current is at the first input / output The body flows between the conductor and the second input / output conductor, and the direction is orthogonal to the plane of the substrate, and the charge stored in the charge storage medium affects the first input / output conductor and the second input / output. The amount of current flowing at a given voltage between conductors. 9. The memory device of claim 8 in which the charge storage medium is formed directly on the silicon body and is directly aligned with the intersection of the first and second input / output conductors. 10. The memory device of claim 8 in which the charge storage medium is formed adjacent to the silicon body. 11. The memory device according to item 8 of the patent application scope, further comprising a control gate formed adjacent to the charge storage medium. 12. A memory device comprising: a first input / output conductor formed on or above a first flat surface of a substrate; and a third input / output conductor formed on the first input / output conductor. Upper; -2- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Hold 々, the scope of patent application-a third input / output conductor "is formed on the second input / output conductor; a first semiconductor region is located at the intersection of the projection of the first input / output conductor and the second input / output conductor Between a second semiconductor region and a projection intersection of the second input / output conductor and the third input / output conductor; and a first charge storage medium that affects the first input / output conductor The amount of current flowing to and from the second input / output conductor. 13. A memory device comprising: a diode having a first region and a second region; a first charge storage region; an insulating region disposed adjacent to the charge storage region; a first contact Contacting the first region; and a second contact; one of the predetermined potentials across the first and second contacts causes a current to flow through the diode, the insulation region, and the electrical storage region. 14. The memory device according to item 13 of the patent application scope, which includes a second insulation region, which is disposed adjacent to the second contact and the storage region, and is opposed to the first insulation region. 15. The memory device as claimed in claim 13, wherein the insulating region is an oxide region. 16. The memory device of claim 13 in which the storage area contains a nitrogen-containing compound. Π. If the memory device under the scope of the patent application is applied for item 16, the compound contains -3- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A8 B8 C8 D8, patent scope oxygen. 18. The memory device of claim 16 in which the compound comprises Shi Xi. 19. The memory device of claim 16 in which the storage area contains alumina. 20. The memory device of claim 13 in which the diode includes a substrate region. 21. The memory device of claim 14 or 15, wherein the diode includes a layer disposed on a substrate. 22. The memory device of claim 15 in which the oxide region is about 1-5 nanometers thick. 23. The memory device of claim 22, wherein the oxide region is about 2-3 nanometers thick. 24. A non-volatile read-write memory cell, comprising: an N-doped region; a P-doped region; a storage element disposed between the N-doped region and the P-doped region And some conductors for passing a current through the N-doped region, the P-doped region, and the storage element. 25. The memory unit of claim 24, wherein the storage element includes a first oxide region. 26. The memory cell of claim 25, wherein the storage element includes a second oxide region. -4- This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) Pretend 540086 A8 B8 C8 D8 々. Patent application scope 27. For example, the memory unit of the patent application scope item 25, wherein the storage element includes a nitrogen-containing region. 28. The memory cell of claim 27, wherein the storage element includes a second oxide region. 29. The memory cell of claim 24, wherein the storage element is in direct electrical contact with at least one doped region. 30. The memory unit according to item 24 of the patent application, wherein the storage element includes $ X. 31. The memory unit of claim 25, wherein the storage element comprises alumina. 32. For example, in the memory unit of claim 24, at least one doped region is arranged in a substrate. 33. For example, in the memory unit of claim 24, at least one doped region is disposed on a substrate. 34. A method for operating a memory cell having a diode element and a charge storage element containing a charge storage region, the method comprising applying a forward bias to the diode element such that The cell conducts electricity to program the cell, and when a forward current passes through the charge storage region, 'captures electricity in the region, and applies a forward bias to the diode element, so that The cell conducts electricity to read the cell and determines whether a current higher than a predetermined current threshold passes through the charge storage region. -5- This paper size applies to China National Standard (CNS) A4 (210X297 mm). Amendment Supplement Date 540086 Α8 Β8 C8 D8 VI. Application for patent scope 35. For the method of applying for the scope of patent No. 34, a current flows in the first direction to program and read the unit. 36. The method of claim 35, further comprising applying a reverse bias to the diode element to erase the cell, and causing a current to flow through the charge storage region in a second direction. . 37. The method of claim 36, wherein the stylizing step includes: passing a current through the storage element in a first direction. 38. The method of claim 37, wherein the erasing step comprises: passing a current through the storage element in a second direction. 39. An improved structure with a diode and an oxide region, which exhibits a negative resistance characteristic when the diode is subjected to a forward bias, the improved structure includes ... A region is disposed adjacent to the oxide region so that a current passing through the diode and the oxide region passes through the storage region. 40. The improved structure of claim 39, wherein the storage area contains a nitrogen-containing compound. 41. The improved structure of claim 40, wherein the compound contains oxygen. 42. The improved structure according to item 41 of the application, wherein the compound comprises silicon. 43. The improved structure of claim 39, wherein the storage area contains alumina. 44. A memory cell array, comprising: -6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A plurality of cells include at least one semiconductor region and a storage region for trapping electric charges; and a B component for controlling a current flow through the semiconductor region and the storage region. 45. The array of claim 44 in which the control unit is arranged in a unit. 46. The array of claim 44 in which at least one semiconductor region is N-type. 47. The array of claim 46, wherein the control member includes a p-type semiconductor region and is disposed adjacent to the N-type semiconductor region. 48. The array of claim 47, wherein the storage member includes an oxide region. 49. The array of claim 48, wherein the storage member comprises a nitrogen-containing compound. = An array of 44 scope of patent application, wherein the control member is arranged outside the unit. 51. The array according to item 44 of the patent application, wherein the semiconductor region of the unit is arranged in the substrate. 52. The array of claim 44 in which the semiconductor region of the unit is formed by polycrystalline debris. 53. The array of claim 47, wherein the storage member includes an n-channel% effect transistor ' with the N-type region. 54. — A memory array with N-level (N is greater than or equal to 2), manufactured on a substrate 'each level contains ... 540086 AB c D Parallel to the first plane above the substrate; second spaced apart conductors above a second plane parallel to the substrate and above the first plane; a plurality of units, one by one arranged on each pair of first and Between the two conductors, each cell includes: a guide element that is more conductive in one direction; and a storage stack containing the first and second oxide regions, and stored in one of the oxide regions Area; wherein the guide element and the storage stack are between the first and second conductors, so that a current from one conductor passes through the guide element, the first oxide, the storage area, and the second oxide before reaching the second conductor 055. As for the memory array of the scope of application for patent No. 54, a second conductor in a level N-1 is shared by the units above and below it. 56. The memory array according to item 54 of the application, wherein the guide element includes a P-type region and an n-type region, and the storage stack contacts at least the N-type doped region. 57. A three-dimensional memory array having a plurality of stages arranged on a substrate, each stage having a non-linear element, the array further comprising: a storage stack, uniting each of the non-linear elements, including a The storage region for trapping charges is arranged between the oxide regions so that a current passing through a non-linear element passes through one of the oxide regions, the storage region, and the other oxide region. -8- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 AS B8 C8 ',. D8 VI. Patent application range 58. If applied, please apply for the memory array of item 57 in which the charge passes through a first direction at a current of at least a first predetermined density and traps Obtained in the storage area. 59. For example, a memory array according to item 58 of the application, wherein the electric charge trapped in the storage area passes in a first direction by a current smaller than a second predetermined density, and the second density is less than The first density. 60. For example, the memory array of the patent application No. 59, wherein the trapped charges are neutralized by passing a current through the storage area in a pair of directions opposite to the first direction. 61. The memory array of claim 60, wherein when the current flows in a first direction, the non-linear element is forward biased. 62. The memory array of claim 61, wherein the storage area includes a nitrogen-containing compound. 63. The memory array of claim 62, wherein the non-linear element includes an N-type semiconductor region adjacent to one of the oxides. 64. A memory comprising: a single crystalline substrate having a plane; a first contact on or above the substrate; a main body on the first contact; a second contact Point on the main body, wherein the second contact point is aligned substantially vertically above the first contact point; a charge storage medium is adjacent to the charge point, and a readout current is at the first contact point and the second contact point. Flow between points, the direction is orthogonal to the plane of the substrate; and -9- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Device 540086 A B c D 々, patent application scope A control gate, adjacent to the charge storage medium. 65. The memory of claim 64, wherein the subject comprises silicon. 66. The memory of claim 64, wherein the main body includes a dielectric film surrounded by a silicon film. 67. The memory of claim 64, wherein the charge storage medium comprises a dielectric stack. 68. For example, the memory of claim 64, wherein the charge storage medium includes a floating gate, which is separated from the main body by a dielectric. 69. The memory of claim 64, wherein the charge storage medium includes a floating gate formed of a conductive nanocrystal and separated from the body by a dielectric. 70. A memory comprising: a silicon crystal substrate having a flat surface; a first silicon film having a first conductivity type and a first concentration of one of the first conductivity type dopants to form On the substrate; a second silicon film having a second conductivity type and a second concentration of one of the second conductivity type dopants, wherein the first concentration is greater than the second concentration 9 a third silicon A film having the first conductivity type and a third concentration of the first conductivity type dopant, wherein the first silicon film and the third silicon film are aligned substantially perpendicularly; a charge storage medium adjacent to The second silicon film; and a control gate, which is adjacent to the charge storage medium. 71. If you apply for the memory of item 70 of the patent scope, where the charge storage medium -10- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 540086 A8 B8 C8 D8, the scope of patent application includes a 100NO film. 72. The memory of claim 70, wherein the charge storage medium includes a first dielectric layer adjacent to the second broken film; a floating gate adjacent to the first dielectric layer; And, a second dielectric layer is between the floating gate and the control gate. 73. The memory of claim 72, wherein the floating gate comprises a nanocrystal. 74. The memory of claim 72, wherein the floating gate includes a continuous silicon film. 75. According to the memory of claim 70, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. 76. A memory comprising: a first metal contact formed on a substrate; a silicon film having a first conductivity type formed on the first metal contact and connected to the first metal contact A metal contact forms a Schottky interface; a second metal contact is formed on the silicon film and forms a second Schottky interface with the silicon film; a charge storage medium is adjacent to the silicon A membrane; and a control gate adjacent to the charge storage medium. 77. The memory of claim 76, wherein the charge storage medium comprises a 100N film. 78. The memory of claim 76, wherein the charge storage medium includes a first dielectric, adjacent to the broken film; a floating gate, adjacent to the first dielectric; and Two dielectrics, at the floating gate-11-This paper size applies the Chinese National Standard (CNS) Α4 specification (210 X 297 mm) Pretend 540086 A B c D is not enough, but only after the year f. Between the scope of patent application and the control gate. 79. The memory of claim 78, wherein the floating gate comprises a nanocrystal. 80. For example, the memory of claim 78, wherein the floating gate is a silicon floating gate. 81. For example, the memory of claim 78, wherein the first conductivity type is a P-type conductivity. 82. A memory comprising: a first broken film having a first conductivity type formed on a substrate; a first dielectric layer formed on the first silicon film; a first Two silicon films having the first conductivity type are formed on the first dielectric layer; a third stone film is adjacent to and contacts the first broken film, the first dielectric layer, and the first dielectric layer; Two silicon films, wherein the third silicon film has a second conductivity type opposite to the first conductivity type; a charge storage medium adjacent to the third silicon film; and a control gate adjacent to the charge storage media. 83. The memory of claim 82, wherein the charge storage medium is a 100N film. 84. The memory of claim 82, wherein the charge storage medium includes a second dielectric adjacent to the third silicon film; a floating gate adjacent to the second dielectric; and, A third dielectric is between the floating gate and the control gate. -12- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 范围. Scope of patent application 85. The memory of item 84 of the patent application scope, wherein the floating gate is formed of a nanocrystal. 86. The memory of claim 84, wherein the floating gate is formed of silicon. 87. For example, the memory of claim 82, wherein the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. 88. A memory, comprising: a substrate, a first silicon film, having a first conductivity type and a first concentration of the first conductivity type dopant on the substrate; a second A silicon film having a second concentration of one of the first conductivity type dopants, and on the first silicon film, wherein the second concentration is less than the first concentration; a third silicon film having a second conductivity A rate type is formed on the second silicon film; a charge storage medium is adjacent to the second silicon film; and a control gate is adjacent to the charge storage medium. 89. The memory of claim 88, wherein the charge storage medium comprises a 100N film. 90. The memory of claim 88, wherein the charge storage device includes a first dielectric material adjacent to the second broken film; a floating gate electrode adjacent to the first dielectric material; and, A second dielectric is between the floating gate and the control gate. 91. If you apply for the memory of item 90 of the patent scope, where the floating gate is made of -13- This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) binding m 540086 A BCD VI. Patent application Range of rice crystals formed. 92. The memory of claim 90, wherein the floating gate is formed of silicon. 93. For example, the memory of claim 88, wherein the first conductivity type is P-type conductivity, and the second conductivity type is N-type conductivity. 94. A memory, comprising: a single crystal substrate having a plane; a dielectric formed on the plane of the single crystal silicon substrate; a first contact formed on the dielectric A main body formed on the first contact; a second contact formed on the main body; a charge storage medium adjacent to the main body; and a readout current at the first contact and The directions between the second contacts are orthogonal to the plane of the substrate: and a control gate is adjacent to the charge storage medium. 95. A memory, comprising: a first guide post, including a first contact, a main body on the first contact, and a second contact on the main body; a second guide A post formed on the first guide post, the second guide post including a third contact, a second body formed on the third contact, and a fourth body formed on the second body A contact; a first charge storage medium adjacent to the first guide pillar; a second charge storage medium adjacent to the second guide pillar; and a continuous film control gate formed on the first charge storage medium and The -14- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 540086 A B c D 6. Scope of patent application The second charge storage medium is adjacent. 96. The memory of claim 95, wherein the first charge storage medium includes a nanocrystal-containing film. 97. A memory, comprising: a first guide post, including a first contact, a main body on the first contact, and a second contact on the main body; a second guide A post formed on the first guide post, the second guide post including a third contact, a second body formed on the third contact, and a fourth body formed on the second body A contact; a first dielectric formed on a side wall of the first and second guide pillars; a nanocrystalline film formed on the first dielectric adjacent to the first and second guide pillars In nature and near; a second dielectric formed in the nano crystal Zheng Jin; a first control gate formed in the vicinity of the first guide pillar in the vicinity of the second dielectric; and a second control The gate is formed adjacent to the second conductive pillar and adjacent to the second dielectric. 98. The memory of claim 97, wherein the first control gate and the second control gate are formed of a continuous film. 99. A semiconductor device comprising: a monolithic three-dimensional charge storage device array formed in an amorphous or polycrystalline semiconductor layer on a single crystalline semiconductor substrate; and a driver circuit formed at least partially in the substrate And below the array 15- This paper size applies to China National Standard (CNS) A4 (210 X297 mm) 540086 A B c D 々, patent application scope, within or above the array. 100. The semiconductor device of claim 99, wherein the driver circuit includes at least one sense amplifier and a charge pump, which are formed in the substrate and below the array. 101. For a semiconductor device under the scope of patent application 99, at least one surface between two consecutive device levels is planarized by chemical mechanical polishing. 102. For a semiconductor device under the scope of patent application 101, where The array contains four or more device levels. 103. For example, the semiconductor device under the scope of patent application 102, wherein each charge storage device is selected from the group consisting of: a pillar-type TFT EEPROM, a pillar-type diode having a charge storage region, and a self-alignment Semi-TFT EEPROM, and rail-stacked TFT EEPROM. 104. The semiconductor device of claim 103, wherein each stage of the array is separated from the other stage of the array by a polished, planar interlayer insulating layer. 105. In the case of the semiconductor device under the scope of the patent application No. 104, the relationship between each device level and the adjacent device level is flat. 106. A three-dimensional semiconductor device, comprising a plurality of device stages, each of which includes: an active semiconductor region; an electric storage region, a first electrode; a second electrode; of which -16- this paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) 540086 A8 B8 C8 A first side of the active semiconductor region is aligned with a first side of one of the first and second electrodes. 107. The semiconductor device according to claim 106, wherein the -second GJ plane of the active semiconductor region is aligned with the second side of the other one of the -th and -th electrodes. 108. The semiconductor device as claimed in claim 107, wherein: the active semiconductor region includes a vertical guide pillar including a channel, a source, and a drain region; 泫 the first and second electrodes contact the One of a source region and a drain region; and the device further includes a gate electrode. 109. The semiconductor device according to claim 107, wherein: the active semiconductor region includes a vertical p-n junction guide post; and the first and second electrodes contact the p_n junction? One of the n and n regions, a method of manufacturing a three-dimensional semiconductor device having a plurality of device stages, the method of manufacturing each stage includes: forming an active semiconductor region; forming a charge storage region; forming a first electrode; forming A first electrode; and patterning at least two sides of the active semiconductor region and the first electrode during the same lithography step. 111 · If the method of applying for the scope of patent No. 110, which uses a first mask to -17- this paper size SS Family Group (CNS) A4 size (21G X297 public love) ------ 540086 AB c D 6. Scope of Patent Application — Etching the active semiconductor region and the first electrode. 112. The method according to item m of the patent application, further comprising: using a second mask to etch the second electrode and the active semiconductor region. 113. The method of claiming in the scope of patent application, wherein: the active semiconductor region includes a vertical guide pillar including a channel, a source, and a drain region; the first and second electrodes contact the source and drain One of the electrode regions and the method further includes forming a gate electrode. 114. The method according to item 1 of the patent application range, wherein: the active semiconductor region includes a vertical pn junction guide post; and the first and second electrodes contact one of the p region and the n region of the p_n junction . 115 · a semiconductor device comprising: an active semiconductor region including a channel, a source and a drain region 9 a gate insulating layer; a source electrode; a drain electrode; and a gate electrode; The first side of the active semiconductor region is aligned with only one side of the gate electrode in the channel portion of the active semiconductor region. 116. The device of claim 115, wherein the gate insulating layer includes a portion of a charge storage region. -18-This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) 540086 AB c D Patent application scope 117. The device of patent application scope item 116 includes a self-aligning device TFT 'is incorporated into a monolithic three-dimensional device array. 118 · —A method for manufacturing a semiconductor device, comprising: forming an active semiconductor region including a channel, a source, and a drain region; forming a gate insulating layer; forming a source electrode; forming a drain electrode Forming a gate layer; and patterning source and drain regions (except channel regions) of the gate layer and the active semiconductor layer during the same lithography step. 119. The method of claim 118, wherein: a first mask is used to etch the active semiconductor region and the gate layer; and the gate insulating layer includes a portion of a charge storage region. 120. The method of claim 119, further comprising: forming a monolithic two-dimensional charge storage device array including the patterned active semiconductor layer. 121 · —a type of field effect transistor, which includes: a source electrode and a non-polar electrode—a channel and a gate with at least one insulating layer between the gate and the channel; and • 19- This paper size applies to the Chinese National Standard (CNS ) A4 specification (210X297 mm) 6. The scope of patent application is a gate line, which extends approximately parallel to the source-channel and an electrode direction, contacts the gate and self-aligns to the gate. 122. For example, the transistor of claim 121, wherein the source electrode, the drain electrode, and the channel are formed in a polycrystalline silicon active layer, and the crystalline silicon active layer is located on an interlayer insulating layer. 123. If the transistor of the scope of patent application No. 122, wherein: the transistor includes an EEPROM; the gate includes a control gate; and the at least one insulating layer is located between the control gate and the channel Charge storage area. 124. The transistor of claim 123, wherein the charge storage region includes a 100N dielectric film or an insulating layer containing a conductive nanocrystal. 125. The transistor of claim 123, wherein the charge storage region includes: a tunneling dielectric above the channel; a floating gate above the tunneling dielectric; and The gate dielectric is controlled above the floating gate. 126. For example, the transistor of the scope of application for patent No. 123 further includes: some side wall spacers located adjacent to the side wall of the gate and having a height approximately the same as that of the gate; and an interlayer insulation layer located at the side wall intervals Objects are adjacent and above the source and drain electrodes and have approximately the same height as the sidewall spacers. 127. For the transistor with the scope of patent application No. 126, where: the gate line is located on the side wall spacers and the interlayer insulation layer -20- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 540086 AB c D 6. The scope of patent application; and the gate line contacts the gate through an opening between the sidewall spacers. 128. For example, the transistor of claim 127 further includes: a first bit line in contact with the source; and a second bit line in contact with the drain; wherein the first and second bits The element line is located under the interlayer insulation layer and extends approximately orthogonally in the direction of the source, the channel, and the pole. 129. For example, the transistor of claim 124, wherein the gate includes: a first part that contacts the charge storage area; and a second part that is above the first part; wherein the first part The first and second gate portions include separate layers. 130. The transistor according to the scope of application for patent No. 126, wherein: the gate line includes a word line including a petrochemical layer between the two polycrystalline silicon layers included; and The gate line is directly on top of the interlayer insulation layer and the sidewall spacers. 131. For example, the transistor of claim 123, wherein the gate line includes a word line self-aligned to the channel and the charge storage area. 132. A three-dimensional non-volatile device array, comprising: a plurality of vertically separated device stages, each stage including an array of TFT EEPROMs, and each TFT EEPROM includes a channel, a source and a drain region, and an adjacent The charge storage area of this channel; a plurality of bit line rows in each device level, each bit line is in contact with -21-this paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 范围 The scope of patent application Source or drain regions of TFT EEPROMs; multiple word line columns in each device level; and at least one interlayer insulation layer between each device level. 133. If the array of the scope of patent application 132, wherein: in at least one device level, the bit line rows are arranged on the TFT EEPROM channel opposite to the other side of the word line columns; each TFT EEPROM The channels include amorphous silicon or polycrystalline silicon; the bit line rows are approximately orthogonal to the source-channel of the TFT EEPROMs-extending in the direction of no pole; each word line contacts the gate of the TFT EEPROMs, or each word line does It is a gate of TFT EEPROMs, and the word line columns extend substantially parallel to the source-channel-electrode direction of TFT EEPROMs; and the word lines are self-aligned to the control gates of the TFT EEPROMs array, and the word lines Self-align the channels and charge storage areas of the TFT EEPROMs located below them. 134. The array of the scope of application for item 133, wherein each charge storage region includes a 0N0 dielectric film or an insulating layer containing a conductive nanocrystal. 135. The array of the scope of application for item 133, wherein each charge storage region includes: a tunneling dielectric above the channel; a floating gate above the tunneling dielectric; and The gate dielectric is controlled above the floating gate. 136. For example, the array of the scope of application for patent No. 133 further includes: some side wall spacers located on the side walls of the control gate of the TFT EEPROMs-22- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 540086 AB c D 邻近, the scope of patent application is adjacent, and it is about the same height as the gate; and an interlayer insulation layer in each device layer, located between the sidewall spacers, and between the TFT EEPROMs Above the source and drain regions, there is approximately the same height as the sidewall spacers. 137. The array of the scope of application for patent No. 136, wherein: in each device level, the word lines are located above the sidewall spacers and the interlayer insulation layer; and the word lines contact their respective TFTs through an opening between the sidewall spacers. Control gate of EEPROM. 138. For the array of patent application No. 137, the bit lines in each device level include guide rails extending below the interlayer insulation layer. 139. If the array of the scope of patent application is No. 138, wherein: the guide rails include a silicide layer on the doped semiconductor region: and the doped semiconductor regions include the TFT EEPROM source and drain regions, which are The doped semiconductor region is adjacent to the area where the TFT EEPROM channel is located. 140. If the array of the scope of application for the patent No. 132, each control gate includes a first part contacting the charge storage area; and a second part above the first part; wherein the first The first and second gate portions include separate layers. 141. If the array of the scope of application for the patent No. 132, further includes word line contacts and bit line contacts connecting word lines and bit lines to peripheral circuits, these weeks-23- This paper standard applies to China Standard (CNS) A4 (210X 297 mm) 540086 A B c D 6. Scope of Patent Application The side circuit is located in the semiconductor substrate under the first stage of the array. 142. For the array of the scope of application for patent No. 141, the word line contacts and bit line contacts extend between a plurality of device layers. 143. For example, the array of the scope of application for the patent No. 132, wherein: each memory cell includes a TFT EEPROM; and the size of each memory cell is about (2F2) / N, where F is a minimum feature size, N is the number of device layers in the third dimension, and N > 1. 144. An EEPROM comprising: a channel; a source; a drain; a tunneling dielectric on the channel; a floating gate on the tunneling dielectric; some sidewall spacers Objects are located adjacent to the side wall of the floating gate; a word line is located above the floating gate; and a control gate dielectric is located between the control gate and the floating gate; wherein the control gate A dielectric is located above the sidewall spacers. 145. If the EEPROM of the scope of application for patent No. 144, wherein: the sidewall spacers extend to the top of the floating gate; and the control gate dielectric is located on the top surface of the floating gate and the sidewall spacers on. 146. The EEPROM of the scope of application for patent No. 144, wherein the floating gate extends vertically above the sidewall spacers. -24- This paper size applies to China National Standard (CNS) A4 (210X 297mm) 540086 A B c D 6. Scope of patent application 147. If you apply, the EEPROM of item 146 of the patent scope, where the floating gate extends laterally above the side wall spacers, so that the floating gate has a "T" shape. 148. For example, the EEPROM of the scope of patent application No. 147, wherein: the control gate dielectric is located on the top surface of the floating gate extending above the side wall spacer; and the word line is located on the control gate dielectric So that the word line is used as the control gate of the EEPROM. 149. For example, the EEPROM with the scope of application No. 146, wherein the top surface of the floating gate electrode 妁 is roughened or roughened. 150. For example, the EEPROM for which the scope of the application is No. 144, wherein the source, the drain, and the channel are formed in a polycrystalline silicon active layer, which is located on an interlayer insulating layer, so that the EEPROM includes a TFT. 151. A three-dimensional memory array, comprising: a plurality of vertically separated device stages, each stage comprising an array of TFT EEPROMs with a scope of application for patent No. 150; a plurality of bits in each device stage Element line rows, each bit line contacts the source or drain region of the TFT EEPROMs, and the bit line rows extend approximately perpendicular to the source-channel-drain direction of the TFT EEPROMs; in each device level A plurality of word line columns, the word line columns extending substantially parallel to the source-channel-drain direction of the TFT EEPROMs; and at least one interlayer insulating layer located between the device stages. 152. If you apply for the array of the scope of patent application No. 150, of which: -25- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 540086 A BCD patent application scope These word lines are self-aligned to the channels and floating gates of TFT EEPROMs; and the bit lines in each device level include guide rails that extend below the interlayer insulation. 153. A non-volatile memory cell array, wherein each memory cell contains a semiconductor device Λ, and the size of each memory cell is about 2F2 / N Here, F is a storm | feature size, and N is the number of device layers in the third dimension, and the meaning is 154. For example, the array of patent application 1 ¾ 153, where: the array contains a single stone three-dimensional memory An array including a plurality of vertically separated device stages, where N> 1; and the semiconductor device includes a TFT EEPROM including a channel, a source and a drain region, and a charge storage region. 155. The array of the scope of application for patent 154, further comprising: a plurality of bit line rows in each device level, each bit line contacting the source and drain regions of the TFT EEPROMs, and the bits The row of element lines extends approximately orthogonally to the source-channel one-pole direction of the TFT EEPR0Ms6 ^ j; a plurality of word line columns in each device level, and the word line columns are approximately parallel to the source-channel of the TFT EEPROMs Extending in a drain direction; and at least one interlayer insulating layer between the device stages. 156. If the array of the scope of patent application is No. 155, wherein: the TFT EEPROMs include control gates; and the plurality of word lines are self-aligned to their respective TFTs located below them. ) A4 size (210 x 297 mm) 540086 AB c D c, patent control EEPROMs, gate area of each TFT EEPROMs, and charge storage area of each TFT EEPROMs. 157. The array according to the scope of application for patent No. 156, wherein the tft EEPROMs further include: sidewall spacers located adjacent to the gate sidewalls of the TFT EEPROMs and having a height approximately equal to the gate; and at each device layer One of the interlayer insulation layers is located between the sidewall spacers and above the source and drain regions of the TFT EEPROMs, and has a height approximately the same as the sidewall spacers. 158 · An array of 157 items, wherein: the word lines are located above the sidewall spacers and the interlayer insulating layer in each device level; and the word lines contact the control gates of their respective TFT EEPROMs through an opening between the sidewall spacers. 159. The array of claim 155, wherein the TFT EEPROMs further include: floating gates located in the charge storage areas; sidewall spacers located adjacent to the sidewalls of the floating gates of the TFT EEPROMs; and An interlayer insulating layer in the device layer between the sidewall spacers and above the source and non-electrode regions of the TFT EEPROMs, wherein the interlayer insulating layer has a height approximately the same as the sidewall spacers; and a control gate dielectric The electric property is located above the sidewall spacers and the interlayer insulation layer, and below the word lines. -27- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 540086 Patent Application Park 160. For the array of the scope of the patent application item · 159, the floating gates are on the side walls The spacers extend vertically and laterally so that the floating gates are "T" shaped. 161. If the array of the scope of application for patent No. 155, it further includes word line contacts and bit line contacts connecting word lines and bit 7G lines to peripheral circuits, which are located below the first level of the array A semiconductor substrate; wherein the bit line contacts extend between a plurality of device layers. 162. A method for manufacturing EEPROM, comprising: providing a semiconductor active area surface; forming a charge storage area on the active area surface; forming a conductive gate layer on the remaining electricity storage area; patterning The gate layer is used to form a control gate covering the charge storage area; the active gate surface is doped with a control gate mask to form source and non-electrode regions in the active region surface; A first insulating layer is formed on and adjacent to the gate; the portion of the top of the control gate that is not lithographically exposed is exposed; and a word line that contacts the exposed top of the control gate is formed so that the word line is self-aligned Control gate. 163. The method of claim 162, further comprising: forming a blocking layer on the gate layer; patterning the blocking layer during the step of patterning the gate layer; and A sidewall spacer is formed adjacent to the control gate and the sidewall of the blocking layer-28-540086 164. The method according to item 163 of the patent application scope, wherein: the blocking layer includes a material different from the sidewall spacers and different from the control gate; the step of exposing the top of the control gate includes: planarizing the first An insulating layer is used to expose the blocking layer, and the blocking layer is selectively removed from between the side wall spacers to form a gate contact through hole; and the step of forming a rare wire includes: on the first insulating layer and The word line is arranged in the gate contact via, so that a portion of the word line in the gate contact via forms the top of the control gate. 165. The method of claiming range 162 of the patent application, wherein the word line is formed on the first insulating layer so that the word line has a substantially flat upper surface. 166. The method of claim 162, wherein: the step of exposing the top of the control gate includes: planarizing the first insulating layer to expose the control gate; and the step of forming a word line includes: The word line is disposed on an insulating layer so that it contacts the exposed control gate. 167. The method according to item 162 of the patent application scope, wherein: the step of providing an active area surface includes: forming a polycrystalline silicon active layer on an interlayer insulating layer; the step of forming a charge storage area includes: forming a 0N〇mediation A dielectric film 'or an insulating layer containing a conductive nanocrystal; and the step of forming a bare wire includes: arranging at least one conductive layer on the first insulating layer and the exposed control gate, and on the at least one -29- The paper size is suitable for SS Home Standard (CNS) A4 specification (21 × 297). 6. The scope of the patent application is to form a first photoresist mask on the conductive layer, and etch the at least one conductive layer. Layer to form the word line. 168. If the method according to item 167 of the patent application scope, further comprising: using the word line as a mask, engraving the active area surface and the charge storage area so that the word line is self-aligned to an EEPROM channel and the charge storage area . 169. The method according to claim 168, further comprising: forming sidewall spacers adjacent to the sidewalls of the control gate; at the control gate, the sidewall spacers, and the doped source and drain regions A metal layer is formed thereon; the metal layer is heated to form metal lithoate regions on the source and non-electrode regions; and the metal layer is selectively removed from the sidewall spacers. 170. The method of claim 169, wherein: the doped source and drain regions and the silicide region include bit lines extending substantially orthogonally to the source-channel and an electrode direction; and The word line extends substantially parallel to the source-channel-drain direction. 171. The method of claim 170, wherein the step of forming a polycrystalline silicon active layer includes: forming an amorphous chip layer or a polycrystalline chip layer; heating the EEPROM after forming the metal layer, and using the metal layer as The catalyst recrystallizes the amorphous silicon layer or the polycrystalline silicon layer. 172. The method of claim 162, wherein the EEPROM is formed by two lithographic masking steps. 173. — A method for manufacturing EEPROM, including: -30- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) The scope of the Chinese patent provides a semiconductor active area surface; a tunneling dielectric layer is formed on the active area surface; a conductive gate layer is formed on the dentition tunnel dielectric layer; Forming a floating gate covering the tunneling dielectric layer; The active gate surface is doped with the floating gate electrode mask to form source and drain regions in the active region surface; side wall spacers are formed adjacent to the side wall of the floating gate electrode; and above the side wall spacers A first insulating layer is formed on and adjacent to the source and drain regions; a control gate dielectric layer is formed on the floating gate; and the first insulation is formed on the control gate dielectric and the first insulation A word line is formed on the layer. 174. The method of claim 173, further comprising: forming a blocking layer on the gate layer, wherein the blocking layer includes a material different from the sidewall spacers and different from the gate layer ; During the step of patterning the gate layer, patterning the blocking layer; forming a sidewall spacer so that it is located adjacent to the side wall of the floating gate, and also adjacent to the side wall of the blocking layer; planarizing the A first insulating layer to expose the blocking layer; selectively removing the blocking layer from between the sidewall spacers to form a gate contact via; and configuring a portion of the word line in the gate contact via In the hole, a control gate is formed in the gate contact through hole above the control gate dielectric -31-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 A8 B8 C8 D8 Patent application scope pole 0 Π5. The method of patent application scope item 173 further includes: planarizing the first insulation layer to expose the top of the floating gate; on top of the first insulation layer, the Equilateral space Above, and the floating gate is formed above a control gate dielectric; and a dielectric electrode a word line formed above the control gate, the word line is made for the control gate electrode EEPROM. 176. The method according to item 75 of the patent application scope, further comprising: forming a floating gate upper portion ', which extends vertically and laterally above the sidewall spacers. 177. The method of claim 176, further comprising: forming a hemispherical grain broken floating gate upper portion. 178. The method according to claim 177, further comprising: roughening an upper surface of an upper portion of the floating gate. 179. The method of claim 173, further comprising: forming a metal layer on the floating gate, the sidewall spacers, and the doped source and drain regions; heating the metal layer, and Metal debris regions are formed over the source and non-electrode regions; and the metal layer is selectively removed from the sidewall spacers. 180 · The method according to item No. Π9 of the scope of patent application, wherein the doped source and drain regions and the silicide regions include bit lines extending substantially orthogonal to the source-channel-drain direction ; And the current line extends approximately parallel to the source-channel-pole direction. -32- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 540086 A8 B8 C8 181. A method for forming a non-volatile memory array, comprising: forming a semiconductor active layer; forming a first insulating layer on the active layer; forming a plurality of gate electrodes on the first insulating layer; The child gate electrode is used as a mask to dope the active layer, and a plurality of source and drain regions are formed in the active layer, and a plurality of bit lines extending substantially orthogonal to the source-drain direction are formed; A second insulating layer is formed on and adjacent to the gate electrode and above the source region, the drain region, and the bit line; the second insulating layer is planarized; and the second insulating layer is formed on the second insulating layer A plurality of word lines are formed, which extend substantially parallel to the source-drain direction. 182. The method of claim 181, wherein each unit at the device level includes a gate electrode, a source, a pole, a channel, a portion of a word line, and a portion of two bit lines. Copies are made by two lithographic masking steps. 183. The method of claim 182 of the patent scope includes: forming sidewall spacers adjacent to the sidewalls of the gate electrodes; , The sidewall spacers, the doped source and non-electrode regions, and the bit lines to form a metal layer; the metal layer is heated, and the source and drain regions and the bits are heated Metal silicide regions are formed over the element wires; and the metal layer is selectively removed from the sidewall spacers. 184. If the method of applying for the scope of patent No. 181, where the gate electrode includes -33- This paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm) 540086 AB c D VI. Patent scope EEPROM control Electrode, and the insulating layer includes EEPROM charge storage region 〇18 :). For example, the method of claim 184, wherein the word lines are self-aligned to the control electrodes. 186. The method of claim 181, wherein the gate electrodes include EEPROM floating electrodes, and the insulating layer includes a penetrating dielectric layer. 187. For example, the method of applying for the scope of patent application No. 181, wherein the step of forming a word line includes: disposing at least one conductive layer on the fourth insulation layer; forming a first layer on at least one conductive layer A photoresist mask; and etching the at least one conductive layer to form a word line. 188. The method of claim 187, further comprising: engraving the active layer and the first insulating layer with the word line as a mask, so that the word line is self-aligned, and several of the word line are located at the source and the source. EEPROM channel in active layer between pole regions. 189. The method of claim 181, further comprising: forming an interlayer insulating layer on the word line, and forming at least one additional device level on the interlayer insulating layer. 190. The method of claiming scope 189, further comprising: forming a first through hole in the second insulating layer to extend to a first word line or bit line; forming at least one conductive layer; and The conductive layer is patterned to form a plurality of word lines or word line contact layers, and at least one bit line contact layer in contact with at least one of the plurality of word lines or bit lines via the first through hole. -34- 191 'The method according to item 190 of the scope of patent application, wherein the Z through-hole teeth extend beyond the second insulating layer and also extend through the first rural marginal layer; and the at least one conductive type is shaped The layer contains: in the N + 1th of the array :, Mao Cheng?夂 Several word lines are in contact with I, and the Nth level of the queue forms a soil) a word line or bit line contact layer. The method as described in Patent Application No. 189, which further includes: activating the coupled source and drain regions in a plurality of device stages of the array during the same & fire step period. 193. If applied The method of the scope of patent No. 189, further comprising: recrystallizing the activation layers in the plurality of device stages of the array during the same annealing step. 194. The method of the scope of patent application No. 193, which further includes Package |: At the same time and during the re-annealing annealing step, the doped source electrode is activated in the plurality of devices and stages of the array; and the electrode region. 195. —A method for manufacturing an EEPROM array, including: Provide a semiconductor active area surface; form a plurality of dummy blocks on the active area surface; use the dummy blocks as a mask to dope the active area surface, and form source and drain regions in the active area surface; A complete insulating layer is formed on and between the dummy blocks; the complete insulating layer is planarized to expose the top of the dummy blocks; the dummy blocks are selectively removed from each part of the planarized complete insulating layer 'While in A plurality of through-holes are formed between each part of the finished insulating layer; -35- This paper is suitable for size @ @ 家 鲜 (CNS) x 297 公 爱) ~ ': ----- A charge storage region J is formed on the active region surfaces of the plurality of through holes, and a conductive gate layer is formed on the charge storage regions; and the conductive gate layer is patterned to form a charge storage region. Control the gate. 196. For example, the method of applying scope of item 195, wherein the charge storage area comprises a dielectric film of 100N0, or an insulating layer containing conductive nanocrystals. 197. Method, wherein the charge storage region includes a trapping electrode between a tunneling dielectric and a control gate dielectric. 198. The method of claim 195, wherein the dummy blocks Contains PECVD silicon nitride. 199. The method of applying scope of item 195, wherein the dummy blocks include a sacrificial conductive gate and a protective insulating layer. 200. The method of applying scope of item 199, further Include: A sidewall spacer is formed on the sidewall of the substrate. 201. The method according to item 195 of the patent application, wherein: the surface of the active region includes an amorphous broken or polycrystalline stone layer formed on an interlayer insulating layer; and a dummy block The material is arranged at a temperature lower than 600 ° C. 202. The method according to item 201 of the patent application scope further includes: forming on the dummy blocks and on the source and drain regions exposed in the active area surface to form A metal layer; the metal layer is annealed to form silicidation on the source and drain regions -36- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ; And selectively remove unreacted portions of the remaining metal layer above the dummy block. 203. The method of claim 202, further comprising: using the silicide regions as a catalyst to recrystallize the active region surface. 204. The method of claim 202, wherein the silicide regions include buried bit lines extending approximately perpendicular to the source-channel-drain direction. 205. For example, the method of applying scope 204 of the patent application, wherein the step of patterning the conductive gate layer includes: forming a plurality of control gates in the through holes above the charge storage regions, and forming an interlayer insulating layer A plurality of word lines are formed thereon. 206. The method according to item 195 of the patent application, wherein each charge storage region includes a first horizontal portion above the surface of the active region in the via; some vertical portions are adjacent to the sidewall of the complete insulation layer And a second horizontal portion above the complete insulation layer. 207. The method according to claim 195, further comprising: forming a complete insulating layer on the EEPROM array, and forming at least one additional EEPROM array on the complete insulating layer. 208. A method for forming a TFT EEPROM, comprising: forming a TFT EEPROM including an amorphous silicon or polycrystalline silicon active layer, a charge storage region, and a control gate; providing a crystallization catalyst and the active layer Contact; and after the step of providing the catalyst and recrystallizing the active layer with the catalyst-37- This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 540086 A BCD The active layer is heated. 209. The method of claim 208, further comprising: forming a plurality of crystallization windows on the active layer; and supplying the crystallization catalyst into the crystallization windows. 210. The method of claim 209, wherein the step of forming a plurality of crystalline windows includes: forming an insulating layer on the TFT EEPROM; and patterning the insulating layer while simultaneously forming crystals. Window borders and sidewall spacers. 211. The method of claim 210, wherein the sidewall spacers are formed on a sacrificial pole. 212. The method according to claim 211, further comprising: removing the sacrificial gate; and forming the charge storage region and the control gate after the sacrificial gate is removed and after the heating step. 213. The method according to claim 208, wherein the catalyst comprises Ni, Ge, Mo, Co, Pt, Pd or a rare product thereof. 214. The method according to claim 208, further comprising: forming a source and a drain region in the active layer; forming a metal silicide crystallization catalyst to contact the source and drain regions; and using The metal silicide is a catalyst for crystallization and recrystallizes the active layer. 215. A method for forming a three-dimensional TFT EEPROM array includes: (%) Binding # 540086 AB c D 6. The scope of patent application forms a first TFT EEPROM, which includes an amorphous silicon or a polycrystalline silicon active layer, a charge storage area and a control gate; a crystalline catalyst is provided to contact the activity Layer; heating the active layer after the step of providing the catalyst to at least partially recrystallize the active layer of the catalyst; forming at least one interlayer insulating layer on the first TFT EEPROM; and over the at least one interlayer insulating layer Forming a plurality of second TFT EEPROMs 〇216. For example, the method of claim 215 of the patent application scope further includes: in the same annealing step Between, in a plurality of stages of the array of the device, the active layer of the TFTs recrystallization. 217. The method of claim 216, further comprising: simultaneously activating the doped source and drain regions of the TFT in the plurality of device stages of the array during the recrystallization annealing step. 218. A memory array of a semiconductor device arranged on a substrate, comprising: a first plurality of spaced apart conductors arranged in a first direction to a first height above the substrate; and Two or more spaced apart rail stacks are arranged at a second height in a second direction different from the first direction, and each rail stack includes: a semiconductor film, and a first surface thereof contacts the first plurality Spaced-apart conductors; a conductive film; and -39- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Ii) Scope of patent application A localized charge storage film is disposed between a second surface of one of the semiconductor films and the conductive film. 219. For example, the memory array of the scope of patent application 218, wherein the second plurality of spaced apart guide rails are stacked on the first plurality of spaced apart conductors; 220. For the memory of scope 218 of the patent application A volume array, wherein the spaces between the spaced apart conductors comprise a planarized oxide material. 221. The memory array of claim 218, wherein the semiconductor film includes polycrystalline fragments. 222. The memory array of claim 221, wherein the polycrystalline silicon is P-doped. 223. For example, a memory array of the scope of application for patent No. 222, wherein the P-doped polycrystalline silicon includes an N + outer diffusion region at the contact intersection between the spaced apart conductors and the spaced apart rail stacks. 224. The memory array of claim 218, wherein the local charge storage film includes a charge trapping medium. 225. The memory array of claim 224, wherein the charge trapping medium includes a dielectric-isolated floating gate. 226. The memory array of claim 224, wherein the charge trapping medium comprises an electrically isolated nanocrystal. 227. The memory array of claim 224, wherein the charge trapping medium comprises a charge trapping layer in a dielectric stack. 228. The memory array of claim 227, wherein the dielectric stack includes a 0-N-0 dielectric stack. -40- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 6. Patent application scope 229. For example, the memory array of the patent application scope item 224, where the conductive film contains conductive polycrystalline silicon. 230. The memory array of claim 229, wherein the conductive film includes a film containing a conductive material. 231. The memory array of the scope of application for patent No. 218, wherein the spaced apart conductors include polycrystalline fragments. 232. In the case of the memory array of claim 231, the spaced apart conductors include a film containing a conductive material. 233. For example, the memory array of claim 231, wherein the polycrystalline silicon of the spaced-apart conductors includes a second conductivity type polycrystalline silicon. 234. The memory array according to the scope of application for item 233, wherein the second conductivity type polycrystalline chip is N + doped. 235. The memory array of claim 218, wherein the semiconductor film comprises polycrystalline silicon. 236. The memory array of claim 235, wherein the first conductivity type is P-doped. 237. For example, the memory array of claim 236, wherein the P-doped semiconductor film includes an N + outer diffusion region, and the first plurality of spaced apart conductors and the second plurality of spaced apart rail stacks Contact between intersections. 238. The memory array of claim 218, wherein: the first plurality of spaced apart conductors include polycrystalline fragments doped with a first conductivity type, and an adjacent layer contains metal or metal fragments; and The conductive film contains the first conductivity type doped polycrystalline silicon and has an adjacent -41-this paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm) 6 8ο 40 5 A BCD Metals or metal fragments. 239. A semiconductor device array arranged on a substrate, comprising: a first plurality of spaced apart conductors arranged in a first direction to a first height above the substrate; and a second plurality of The spaced-apart rail stacks are arranged at a second height in a second direction different from the first direction. Each rail stack contains: a semiconductor film, and a first surface of the rail stack contacts the first plurality of spaces. A separate conductor; a conductive film; and a localized charge storage film disposed between a second surface of the semiconductor film and the conductive film; an insulating film; a third plurality of spaced apart conductors in a first Direction is arranged to a third height above the insulation film; a fourth plurality of spaced apart guide rail stacks are arranged to a fourth height above the insulation film in a second direction different from the first direction, Each rail stack includes: a semiconductor film, and a first surface thereof is in contact with the third plurality of spaced apart conductors; a conductive film; and a localized charge storage film disposed on the semiconductor film Between a second surface and the conductive film. 240. For example, the memory array of the scope of application for patent No. 239, wherein: the second plurality of spaced apart guide rails are arranged in the first plurality -42- This paper size is applicable to China National Standard (CNS) A4 specification (210X297) (Centimeter) 540086 AB c D 6. The patent application scope is on the spaced apart conductors; the insulation film is arranged on the second plurality of spaced apart rail stacks; the third plurality of spaced conductors is placed on the insulation film The fourth plurality of spaced apart guide rails are stacked on the third plurality of spaced apart conductors. 241. For example, the memory array under the scope of patent application No. 239, wherein the space between the spaced apart conductors includes a planar oxide material. 242. The memory array of claim 239, wherein the semiconductor film comprises P-doped polycrystalline silicon. 243. For example, the memory array of the patent application No. 242, wherein the P-doped polycrystalline silicon includes an N + outer diffusion region at the contact intersection between the spaced apart conductors and the spaced apart rail stacks. 244. The memory array of claim 239, wherein the local charge storage film includes a charge trapping medium. 245. The memory array of claim 244, wherein the charge trapping medium includes a dielectric-isolated floating gate. 246. The memory array of claim 244, wherein the charge trapping medium comprises an electrically isolated nanocrystal. 247. The memory array of claim 244, wherein the charge trapping medium comprises a charge trapping layer in a dielectric stack. 248. For example, the memory array of claim 247, wherein the dielectric stack includes a 0-N-0 dielectric stack. 249. If you apply for a memory array with the scope of patent application No. 244, where the conductive film package -43- This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) 540086 A B c D 6. Scope of patent application Contains conductive polycrystalline silicon. 250. The memory array of claim 249, wherein the conductive film includes a film containing a conductive material. 251. In the case of a memory array under patent application No. 239, wherein the spaced apart conductors include polycrystalline silicon. 252. If the memory array of the scope of application for patent No. 251, wherein the spaced apart conductors include a film containing a conductive material. 253. For example, the memory array of claim 251, wherein the polycrystalline silicon of the spaced-apart conductors includes a second conductivity type polycrystalline silicon. 254. The memory array according to item 253 of the application, wherein the second conductivity type polycrystalline is N + doped. 255. The memory array of claim 239, wherein the semiconductor film includes polycrystalline fragments. 256. For example, the memory array of the scope of application for patent No. 255, wherein the semiconductor film polycrystalline is P-doped. 257. For example, the memory array of the scope of application for patent No. 256, wherein the P-doped semiconductor film includes an N + outer diffusion region, and the first plurality of spaced apart conductors and the second plurality of spaced apart rail stacks are stacked. Contact between intersections. 258. For example, the memory array of the scope of application for patent No. 239, wherein: the first and third spaced apart conductors comprise a first conductivity type doped polycrystalline silicon, and an adjacent layer comprises a metal or a metal silicide; And the conductive film contains the first conductivity type doped polycrystalline silicon and has an adjacent -44-. This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm). 540086 A B c D 々, patent application layer The layer contains metal or metal fragments. 259. A memory array arranged on a substrate, comprising: a first plurality of spaced apart guide rail stacks, arranged in a first direction to a first height above the substrate, each first Each of the rail stacks includes a conductive film; a localized charge storage film disposed on the conductive film; and a semiconductor film disposed on the localized charge storage film; a second plurality of spaced apart conductors in a different Arranged in a second direction of the first direction to a second height above the first height; and a third plurality of spaced apart rail stacks arranged in a first direction to a third above the second height At a height, each third rail stack includes: a semiconductor film; a localized charge storage film disposed on the semiconductor film; and a conductive film disposed on the localized charge storage film. 260. The memory array of claim 259, wherein the second plurality of spaced apart conductors contact the semiconductor films in the first and third rail stacks. 261. The memory array of claim 260, wherein the second plurality of spaced apart conductors contact the doped source and non-electrode regions in the semiconductor films of the first and third rail stacks. 262. —A memory array arranged on a substrate, comprising: a first plurality of spaced apart guide rail stacks, arranged in a first direction -45- This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) 6. At the first level above the substrate, each rail stack includes a conductive film; a localized charge storage film is disposed on the conductive film; and a semiconductor film is disposed on the substrate. Over a domain charge storage film; and a second plurality of spaced apart conductors arranged in a second direction different from the first direction to a second height above the first height, the spaced apart conductors are covered The upper semiconductor film contains regions of impurities that form electrical connections between the spaced-apart conductors and the local charge storage film. 263. For example, the memory array of the scope of application for patent No. 262, further comprising: a third plurality of spaced apart rail stacks arranged in the first direction to a third height above the second height, each rail The stack all includes a semiconductor film; a localized charge storage film disposed on the conductive film; and a second semiconductor film disposed on the localized charge storage film; and a fourth plurality of spaced apart conductors, The second direction is disposed to one of the fourth height above the third height. The spaced-apart conductors are covered with the regions containing impurities in the second semiconductor film. The areas form the spaced-apart conductors and the local charge. Electrical connection between storage films. 264. For example, the memory array of claim 262, wherein the space between the spaced apart conductors includes a planar oxide material. 265. A memory array disposed on a substrate, comprising: a first plurality of spaced apart rail stacks, each of which is disposed in a first direction at a first height above the substrate, All contain a conductive film; and a localized charge storage film, which is arranged on the conductive film; a second plurality of spaced apart conductors, which is different from the first direction -46- Standard (CNS) A4 specification (210 X 297 mm) 6. The patent application scope is arranged in two directions to one of the first height and the second height. The spaced-apart conductors cause the intersection with the rail stack contacts. Such that the spaced-apart conductors directly contact the local electrical storage films at the contact intersections, and a semiconductor film is disposed in the spaced-apart areas in an area above the contact intersections. Between conductors and above these local charge storage films. 266. For example, the memory array under the scope of patent application No. 265, wherein the space between the spaced apart conductors includes a planar oxide material. 267. The memory array according to claim 265, wherein the semiconductor film includes polycrystalline silicon. 268. The memory array of claim 267, wherein the polycrystalline silicon semiconductor film is P-doped. 269. For example, a memory array with a scope of patent application No. 268, wherein the P-doped polycrystalline silicon includes an N + outer diffusion region, adjacent to the spaced-apart conductors. The local charge storage film includes a charge trapping medium. 271. The memory array of claim 270, wherein the charge trapping medium includes a dielectric-isolated floating gate. 272. The memory array of claim 270, wherein the charge trapping medium comprises an electrically isolated nanocrystal. 273. The memory array of claim 270, wherein the charge trapping medium includes a charge trapping layer in a dielectric stack. -47- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 540086 A BCD VI. Application scope of patent 274. For example, the memory array with scope of patent application No. 273, where the dielectric The stack includes a 0-N-0 dielectric stack. 275. The memory array of claim 270, wherein the conductive film comprises conductive polycrystalline silicon. 276. The memory array of claim 275, wherein the conductive film includes a film containing a conductive material. 277. In the case of a memory array under application No. 265, the spaced apart conductors include polycrystalline silicon. 278. In the case of a memory array under patent application No. 277, wherein the spaced apart conductors comprise a film containing a conductive material. 279. For example, the memory array of claim 277, wherein the polycrystalline silicon of the spaced apart conductors includes a second conductivity type polycrystalline silicon. 280. For example, the memory array of the scope of application for patent No. 277, wherein the second conductivity type polycrystalline silicon is N + doped. 281. The memory array of claim 265, wherein the semiconductor film includes polycrystalline fragments. 282. The memory array of claim 281, wherein the semiconductor film polycrystalline is P-doped. 283. According to the memory array of claim 282, wherein the P-doped semiconductor film includes an N + outer diffusion region, the second plurality of spaced apart conductors and the first plurality of spaced apart guide rails Where the contacts between the stacks intersect. 284. For example, the memory array of the scope of application for patent No. 265, wherein: the first plurality of spaced apart conductors include the first conductivity type doping -48- This paper is applicable to China National Standard (CNS) A4 specification (210 x 297 mm) 540086 A B c D 々, patented polycrystalline silicon, and an adjacent layer containing metal or metal silicide; and the conductive film comprises a first conductivity type doped polycrystalline silicon, and an adjacent layer contains metal or metal silicide. 285. The memory array of claim 265, wherein the array includes a single-stone three-dimensional array. 286. A method for stylizing a memory cell (having two bit information) of a three-dimensional NMOS memory cell array, the memory cell array is arranged on a substrate and includes a first plurality (Z) of memories At the body level, the zth memory level includes a second plurality (X) bit line conductors and a third plurality (Y) word line conductors. These memory cells have a local charge storage medium. The method includes : Providing a first potential, a second potential, and a third potential, the first potential is smaller than the second potential, and the second potential is smaller than the third potential; a memory cell is selected for programming, and it is located at the word Lines y and z are defined, and are arranged between bit lines X and x + 1; the first of the two bits is stylized by: A bit line equal to X applies the second power to all bit lines greater than X on the Z level; applies the third power to the word line y on the z level; and applies the first power to the z level All non-y word lines and all word and bit lines on levels other than z; and The formula of the second two bytes of: applying the first power is greater than X, all located on the first bit line level z; -49-- This applies China National Standard Paper Scale (CNS) A4 size (210X297 mm) 540086 8 8 8 8 A BCD Sixth, the scope of the patent application applies the second line located on the z-th bit line y less than or equal to X applies the second line on the z-th word line y; and applies the The first electric line is located on all non-y word lines on the z-th stage and all word lines and bit lines on the non-z-th stage. 287. The method of claim 286, wherein the second potential is in the range of about 3 to about 8 volts and is greater than the first potential. 288. According to the method of claim 287, the third potential is in the range of about 9 to about 13 volts, which is greater than the first potential. 289. A method of stylizing a memory cell (having two bit information) of a three-dimensional PMOS memory cell array, the memory cell array is arranged on a substrate and includes a first plurality of (Z) memories At the body level, the zth memory level includes a second plurality (X) bit line conductors and a third plurality (Y) word line conductors. These memory cells have a local charge storage medium. The method includes : Providing a first potential, a second potential, and a third potential, the first potential is greater than the second potential, and the second potential is greater than the third potential; a memory cell is selected for programming, and it is located at the word Lines y and z are defined, and are arranged between bit lines X and x + 1; the first of the two bits is stylized by: A bit line j equal to X applies the second line to all bit lines greater than X on the Z-th level; applies a third line to the word line y on the z-th level, and -50- This paper size applies to China Standard (CNS) A4 (210X 297 mm) 540086 AB c D 6. The scope of the patent application is that the first electric line is located on all non-y word lines on the z-th level and all word lines and bit lines on the non-Z-th level; and the two bits are stylized by the following The second element: the first line is located on all bit lines greater than X on the z-th level; the second line is located on all bit lines less than or equal to X on the z-th level; the third line is located on The word line y on the z-th stage; and the first electric line is located on all non-y word lines on the z-th stage and all word lines and bit lines on the non-z-th stage. 290. The method of claim 289, wherein the second potential is in the range of about 3 to about 8 volts, which is smaller than the first potential. 291. According to the method of claim 290, the third potential is in the range of about 9 to about 13 volts, which is smaller than the first potential. 292. —A method for reading the contents of a memory cell (which stores two bit information) of a three-dimensional NMOS memory cell array, the memory cell array is arranged on a substrate and includes a first plurality (Z ) Memory level. The zth memory level contains a second plurality (X) bit line conductors and a third plurality (Y) word line conductors. These memory cells have a local charge storage medium. The method includes: providing a first potential, a second potential, and a third potential, the first potential is less than the second potential, and the second potential is less than the third potential; selecting a memory cell to read, and It is located at the line defined by word line y and level z, and is arranged between bit line X and x + 1; the second power is located at all bit lines less than or equal to X on level z; -51-this paper Standards apply to China National Standard (CNS) A4 specifications (210X 297 mm) 6. The scope of the patent application applies the bit line where the first power is located on the z-th level greater than X; applies the word line y where the third power is located on the z-th level; and applies the first power located on the z-level all Non-y word lines and all word lines and bit lines on levels other than z; and applying the second power to all bit lines greater than X on level z; applying the first power on level z All bit lines less than or equal to X; the word line y on the z-th level of the second electric power, and the word line y on the z-th level and all non-y word lines on the z-th level All word lines and bit lines. 293. The method of claim 292, wherein the second potential is greater than the first potential in a range of about 50 millivolts to about 3 volts. 294. According to the method of claim 293, the third potential is in the range of about 1 to about 5 volts, which is greater than the first potential. 295. —A method for reading the content of a memory cell (which stores two bit information) of a three-dimensional PMOS memory cell array, the memory cell array is arranged on a substrate and includes a first plurality (Z ) Memory level. The zth memory level contains a second plurality (X) bit line conductors and a third plurality (Y) word line conductors. These memory cells have a local charge storage medium. The method includes: providing a first potential, a second potential, and a third potential, the first potential is greater than the second potential, and the second potential is greater than the third potential; selecting a memory cell to read, and It is located at the line defined by word line y and level z, and is arranged between bit line X and x + 1; the second power is located at all bit lines less than or equal to X on level z; -52- scale of this paper Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 6. Scope of patent application: The first line is located on the Z-th level and all bit lines greater than X; The second line is on the second level. Word line y, and all the non-y word lines and non-y all word lines and bit lines on level z; and all bit lines greater than X on the z-th level; all bits less than or equal to X on the z-th level Line; the third line is located on the z-th word line; and the first line is located on all the non-y word lines on the z-th level and all word lines and bit lines on the non-z-th level. 296. The method according to claim 295, wherein the second potential is in the range of about 50 millivolts to about 3 volts and is smaller than the first potential. 297. The method according to claim 296, wherein the third potential is in the range of about 1 to about 5 volts and is smaller than the first potential. 298. —A method for erasing the contents of all the memory cells in the three-dimensional NMOS memory cell array (each memory cell stores two bit information), the memory cell array is arranged on a substrate and includes a first plural number (Z) memory levels, the zth memory level contains a second plurality (X) bit line conductors and a third plurality (Y) word line conductors, these memory cells have a localized charge A storage medium, the method comprising: providing a first potential and a second potential, the first potential being less than the second potential; applying the second power to all bit lines; and applying the first power to all words line. 299. If the method of applying for the scope of patent No. 298, wherein the second potential is about 5 -53- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) In the range of 15 volts, it is greater than the first potential. 300. —A method for erasing the contents of all the memory cells (each memory cell stores two bit information) of the three-dimensional PMOS memory cell array, the memory cell array is arranged on a substrate and includes a first plural number (Z) memory levels, the zth memory level contains a second plurality (X) bit line conductors and a third plurality (Y) word line conductors, these memory cells have a localized charge A storage medium, the method comprising: providing a first potential and a second potential, the first potential being greater than the second potential; applying the second power to all bit lines; and applying the first power to all words line. 301. The method of claim 300, wherein the second potential is in a range of about 5 to about 15 volts and is smaller than the first potential. 302. —A method for erasing a single bit of a memory cell (having two bit information) of a three-dimensional NMOS memory cell array, the memory cell array is arranged on a substrate and includes a first plurality of (Z) memory levels, the zth memory level contains a second plurality (X) bit line conductors and a third plurality (Y) word line conductors, these memory cells have a local charge storage Media, the method includes: providing a first potential, a second potential, and a third potential, the first potential is less than or equal to the second potential, and the second potential is less than the third potential; selecting a memory unit One of the memory storage locations for erasing, the memory unit is located at the word line y and level z, and is arranged at the bit lines X and -54. (Mm) 々. The scope of patent application is between χ + 1, and the storage location is adjacent to the bit line χ + 1; the content of a memory storage location of a memory unit is read out, and the memory unit is located on the word line y, Defined by level z, configured on bit line x + Between 1 and x + 2, and the storage location is adjacent to the bit line χ + 1; storing the content in a memory storage; applying the first power to the word line y; applying the second power to all non-x + 1 bit line; applying the second power on word line χ + 1, floating all non-y word lines; applying the first power on all word lines and bit lines on non-z level, or floating non- all word lines and bit lines on the z-level; retrieve the content from the memory storage; and write the content to the memory storage location of the memory unit, which is located on the word line y, level The position defined by z is arranged between the bit line x + 1 and x + 2, and the storage position is adjacent to the bit line x + bu 303. For example, in the method of the 302th aspect of the patent application, wherein the second potential is about 0 In the range of about 5 volts, it is greater than the first potential. 304. According to the method of claim 303, the third potential is in a range of about 5 to about 15 volts, which is greater than the first potential. 305. —A method for erasing a single bit of a memory cell (having two bit information) of a three-dimensional PMOS memory cell array, the memory cell array is disposed on a substrate and includes a first plurality of (Z) memory level, the ζth memory level contains a second plurality (X) bit line conductors and a third plurality (Υ) word line conductors. These memory cells have a local charge storage -55- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 6. Patent application media, the method includes: providing a first potential, a second potential, and a third potential, the first A potential is greater than or equal to the second potential, and the second potential is greater than the third potential. One of the memory storage locations of a memory cell is selected for erasing, and the memory cell is located at the boundary defined by the word line y and level z. , Located between bit line X and x + 1, and the storage position is adjacent to bit line x + 1; read out the content of a memory storage position of a memory cell, which is located on word line y, level Defined by z, placed on bit line between x + 1 and χ + 2, and the storage location is adjacent to the bit line x + 1; storing the content in a memory storage; applying the first power to the word line y; applying the second power to all Bit lines that are not x + 1, or floating all bit lines that are not x + 1; applying the third power to the word line x + 1; floating all non-y word lines; applying the first power to the non-z level All word lines and bit lines; retrieving the content from the memory storage; and writing the content to the memory storage location of the memory cell, which is located at the line defined by the word line y, level z Is disposed between the bit lines x + 1 and x + 2, and the storage position is adjacent to the bit line x + 1. 306. The method according to claim 305, wherein the second potential is in the range of about 0 to about 5 volts and is smaller than the first potential. 307. For the method of applying for the item No. 306 of the patent scope, wherein the third potential is about 5 -56- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 AB c D 6. Application The range of the patent is about 15 volts, which is smaller than the first potential. 308. A method for manufacturing a three-dimensional TFT memory cell array, comprising: (a) disposing an insulating layer on a substrate; (b) disposing a first plurality of spaces on the insulating layer in a first direction; Separated conductors; (c) an insulating layer is disposed on the first plurality of spaced apart conductors, and the insulation material is used to fill the spaces between the spaced apart conductors (d) planarize the insulation layer to expose The first plurality of spaced apart conductors; (e) contacting the first plurality of spaced apart conductors, and disposing a second plurality of spaced apart rail stacks in a second direction, the rail stacks including the first A first conductivity type semiconductor material, a second layer containing a localized charge storage film, and a third conductive layer. 309. If the method according to the scope of application for patent No. 308, further includes: (f) repeating ⑻, (b), (c), ⑷ and (e) as many times as necessary to form the necessary number of DFT memory cell levels. 310. The method according to the scope of patent application, wherein the step of planarizing includes CMP. 311. The method according to the scope of patent application, 310, further includes: planarizing the insulation layer by CMP. 312. The method according to claim 308, further comprising: (g) a second conductivity type doped polycrystalline silicon conductor separated from the first plurality of spaces, an outer diffusion source and a drain dopant Into the first layer and half -57- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 A B c D 6. Scope of patent application Conductor materials. 313. If the method of applying for item 312 of the patent scope further comprises: repeating (a), (b), (c), (d), (e), (f), and (g) as many times as necessary to form the necessary Number of TFT memory cell levels. 314. A method for manufacturing a three-dimensional TF memory cell array, comprising: (a) disposing an insulation layer on a substrate; 上面 disposing the insulation layer on the insulation layer, and disposing a first plurality of intervals in a first direction; (C) contact on the first plurality of spaced apart conductors, and arrange the local charge storage film guide in the first direction; (d) contact on the local charge storage film, and in a second direction A second plurality of spaced apart conductors are arranged, and the conductors are formed of a first conductivity type polycrystalline shredded material; (e) A second conductivity type semiconductor film is arranged between the second plurality of spaced apart conductors. (F) an insulating layer is disposed on the semiconductor film and on the second plurality of spaced apart conductors, and the insulation material is used to fill the spaces between the second spaced apart conductors; (g) planarize the Insulation. 315. If the method according to the scope of application for patent No. 314, further includes: ⑻ repeating ⑻, (b), ⑷, ⑷, (e), (f), and (g) as many times as necessary to form the necessary number of TFT memories Unit level. 316. A method for manufacturing a three-dimensional TFT memory cell array, comprising: (a) disposing an insulating layer on a substrate; -58- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 540086 8 8 8 8 AB c D 々, the scope of patent application (b) on the insulation layer, and the first plurality of spaced apart conductors are arranged in a first direction; (c) the first plurality of spaced apart conductors On the conductor, a first local charge storage film is arranged; (d) On the local charge storage film, a first layer of first conductivity type semiconductor material is arranged; (e) On the first layer of semiconductor material, and A second plurality of spaced apart conductors are arranged in a second direction, the conductors are formed of a semiconductor material doped with a second conductivity type; (f) an insulating layer is arranged on the second plurality of spaced apart conductors, and The insulating material fills the spaces between the second spaced apart conductors; (g) Planes to expose the second spaced apart conductors; 配置 A second layer is arranged on the second spaced apart conductors A first conductivity type semiconductor material; (i) a second localized charge storage film is disposed on the second layer of semiconductor material; (J) a second localized charge storage film is disposed on the second localized charge storage film, and the first is disposed in the first direction Multiple rooms Conductors separated; the intersection between the conductor and (k) the first and second layers of a first conductivity type semiconductor material separate from the regular intervals, are formed outside the diffusion region. 317. The method of claiming scope 316 of the patent application, further comprising: ⑴ repeating (c), ⑹, (e), (f), (g), ⑻, (i), ①, and (k) as many times as necessary, To form the necessary number of TFT memory cell levels. -59- This paper size applies to China National Standard (CNS) A4 (210X297 mm) 6. Application scope 318. A method for manufacturing a TFT memory cell array, comprising: disposing an insulating layer on a substrate; and disposing a first plurality of guide rail stacks on the insulating layer in a first direction, The rail stacks include a conductive film layer; a localized charge storage film layer disposed on the conductive film surface layer; and a first conductivity type semiconductor film layer disposed on the localized charge storage film layer; An oxide layer is disposed on the stacks of the guide rails; the oxide layer is masked; the oxide layer is etched; the oxide layer is removed; a second conductivity-type impurity is implanted and passed through the oxide layer An aperture is inserted into the semiconductor film layer; a conductive film is disposed in the aperture; and the conductive layer is planarized. 319. A method for manufacturing a TFT memory cell array, comprising: disposing an isolation layer on a substrate; disposing a first conductive amorphous layer on the isolation layer; disposing a nitride CMP barrier Layer on the amorphous layer; mask the silicon nitride layer; etch into the insulating layer to form the aperture defined by the mask; deposit a conductive layer of a second conductive type semiconductor material in and above the aperture ; Planarize the conductive layer so far to the CMP barrier layer; configure a regional charge storage film on the CMP barrier layer; and -60- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) 540086 A BCD 6. The scope of the patent application is to configure a conductive film on the charge storage film. 320. A memory array disposed on a substrate, comprising: an insulator layer; a first plurality of spaced apart conductors disposed in the insulator layer in a first direction; some first conductivity type semiconductors A region arranged between the spaced apart conductors adjacent to and in contact with the area; and a second plurality of guide rail stacks arranged in a second direction on the first plurality of spaced apart conductors and in contact with each other, each A rail stack includes a localized charge storage film and a conductive film disposed on the localized charge storage film. 321. The memory array according to item 320 of the application, wherein the semiconductor film includes polycrystalline fragments. 322. The memory array according to the scope of patent application No. 321, wherein the polycrystalline silicon is P-doped. 323. For example, the memory array of claim 322, wherein the P-doped polycrystalline silicon includes N + outer diffusion regions at the junctions between the spaced-apart conductors and the semiconductor regions. 324. The memory array of claim 320, wherein the local charge storage film includes a charge trapping medium. 325. The memory array of claim 324, wherein the charge trapping medium includes a dielectric-isolated floating gate. 326. The memory array of claim 324, wherein the charge trapping medium comprises an electrically isolated nanocrystal. -61-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 6. Scope of patent application 327. For the memory array of patent application No. 324, wherein the charge trapping medium includes a charge trapping layer in a dielectric stack. 328. For example, the memory array of claim 327, wherein the dielectric stack includes a 0-N-0 dielectric stack. 329. The memory array of claim 324, wherein the conductive film comprises conductive polycrystalline silicon. 330. The memory array of claim 329, wherein the conductive film includes a film containing a conductive material. 331. For example, the memory array of the scope of application for item 320, wherein the spaced apart conductors include polycrystalline silicon. 332. In the case of the memory array of claim 331, the spaced apart conductors include a film containing a conductive material. 333. For example, the memory array of claim 331, wherein the spaced-apart conductor polycrystalline silicon includes a second conductivity type polycrystalline silicon. 334. The memory array according to item 333 of the application, wherein the second conductivity type polycrystalline silicon is N + doped. 335. The memory array of claim 320, wherein the semiconductor film includes polycrystalline fragments. 336. The memory array of claim 335, wherein the first conductivity type is P-doped. 337. For example, the memory array with the scope of application patent No. 320, further comprising: an insulation film disposed on the second plurality of rail stacks; a third plurality of spaced apart conductors disposed on the first direction In the insulation film; -62- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X297 mm) 々. Patent application range: Multiple first conductivity type semiconductor regions, which are arranged in the adjacent areas of the conductors separated by these intervals And a fourth plurality of rail stacks arranged in a second direction on and contacting the third plurality of spaced apart conductors, each rail stack including a local charge storage film and a A conductive film disposed on a local charge storage film. 338. — Kind of FT CMOS, comprising: a gate electrode; a first insulating layer adjacent to the first side of the gate electrode; a first semiconductor layer having a first conductivity type and disposed on the first The insulating layer is opposite to the other side of the gate electrode; the first source and drain regions of the second conductivity type are arranged in the first semiconductor layer; the first source and drain electrodes contact the first source And a drain region, which are disposed on the other side of the first semiconductor layer opposite to the first insulating layer; a second insulating layer adjacent to the second side of the gate electrode; a second semiconductor layer having a second Conductivity type, and is disposed on the second insulating layer opposite to the other side of the gate electrode; the second source and drain regions of the first conductivity type are disposed in the second semiconductor layer; and the second source The electrode and the drain electrode contact the second source and drain regions, and are disposed on the other side of the second semiconductor layer opposite to the second insulating layer. 339. If the TFT CMOS of the patent application No. 338, further includes: a semiconductor substrate; an interlayer insulating layer between the substrate and the TFT CMOS; -63- This paper size applies to China National Standard (CNS) A4 Specifications (210 X297 mm) 540086 A BCD VI. Patent application scope-a first planar insulating filler layer disposed between the first source electrode and the non-polar electrode; and a second planar insulating filler layer disposed at the second source Between the electrode and the drain electrode. 340. For example, the FT CMOS of claim 339, wherein: the first source electrode and the drain electrode include a second conductivity type polycrystalline silicon guide rail, which extends above a first plane and above the interlayer insulation layer; The first semiconductor layer includes a polycrystalline broken layer, which extends above a second plane and extends above the first source and non-electrode electrodes; the gate electrode includes a first polycrystalline silicon layer of a second conductivity type A fragmented material layer on the first polycrystalline fragmented layer and a second polycrystalline fragmented layer of the first conductivity type, wherein the gate electrode extends above the first insulating layer on a third plane; The two semiconductor layers include a polycrystalline silicon layer, which extends above the gate electrode on a fourth plane; the second source and drain electrodes include a first conductivity type polycrystalline broken track, which is on a fifth Extending above the second semiconductor layer; the first to fifth planes do not overlap each other. 341. For example, the TFT CMOS of the scope of application for patent No. 340, wherein: the gate electrode, the first insulating layer, the first semiconductor layer, the second insulating layer, and the second semiconductor layer include a rail stack, which is parallel to The flat top surface of the substrate extends perpendicular to the first and second source and drain electrodes; and the gate electrode, the first insulating layer, the first semiconductor layer, and the second insulation -64- This paper standard applies to Chinese national standards ( CNS) A4 size (210 x 297 mm) 540086 A B c D 6. Scope of patent application The layer and the second semiconductor layer are aligned on a plane perpendicular to the substrate and parallel to the source-to-drain direction. 342. If the TFT CMOS of the scope of application for the patent No. 340, further includes: a first charge storage region including a first insulating layer; a second charge storage region including a second insulating layer; TFT CMOS of scope item 342, wherein: the first charge storage region includes a 0-N-0 stack, an isolated nanocrystal, or a floating gate between the first insulating layer and a control gate dielectric And the second charge storage region includes a 0-N-0 stack, an isolated nanocrystal, or a floating gate, between the second insulating layer and a control gate dielectric. 344. For example, the TFT CMOS under the scope of application for patent No. 340, wherein the first insulating layer includes a part of a charge storage area, and the second insulating layer does not include a part of a charge storage area. 345. — A monolithic three-dimensional array, including a plurality of device stages vertically separated by one or more interlayer insulating layers, each of which includes a plurality of application FT CMOS CMOS devices. 346. An array of semiconductor devices arranged on a substrate, comprising: a first plurality of spaced apart conductors arranged in a first direction to a first height above the substrate; and a second plurality of spaces The separate rail stacks are arranged at a second height above the first height in a second direction different from the first direction, and each rail stack includes: a first semiconductor film of a first conductivity type, Contains multiple second guides -65- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 540086 AB c D 々, the source and drain regions of the patent application rate type, and contact the first plurality of spaced apart conductors; a first localized charge storage film disposed on the first semiconductor film; A gate line disposed on the first local charge storage film; a second local charge storage film disposed on the gate line; a second semiconductor film of a second conductivity type including a plurality of A source and drain region of a first conductivity type; and a third plurality of spaced apart conductors contacting the source and drain regions of the first conductivity type, wherein the third plurality of spaced apart conductors are arranged to A third height above one of the second plurality of spaced apart rail stacks. 347. The array of the scope of application for patent No. 346, wherein the space between the spaced-apart conductors includes a planar deposited insulating layer. 348. The array according to the scope of application for patent No. 347, wherein the first and second semiconductor films include polycrystalline debris layers. 349. The array of claim 348, wherein the first and second charge storage films include a charge trapping medium. 350. The array of the scope of application for patent No. 349, wherein the charge trapping medium includes a dielectric-isolated floating gate, electrically isolated nanocrystals, or a 0-N-0 dielectric stack. 351. For example, the array of the scope of application for patent No. 350, wherein the gate line includes a first polycrystalline silicon layer of a second conductivity type, adjacent to the first charge storage film; a petrochemical layer, on the first polycrystalline silicon Above the layer; and a second polycrystalline silicon layer of the first conductivity type, above the silicide layer, and adjacent to the second charge storage -66- This paper size applies to China National Standard (CNS) A4 specifications (210 X (297 mm) 540086 A8 B8 C8 patent application scope j52. For the array of patent application scope item 351, in which: the first spaced apart conductors include polycrystalline fragments of the second conductivity type: and the third plurality of spaces The separate conductors include polycrystalline fragments of a first conductivity type. 353. The array of claim 1, wherein the first and third spaced apart conductors further comprise a metal or silicide layer. 354. An array according to item 353 of the scope of patent #Russian, wherein the source sums of the second conductivity types; and the electrode regions include outer diffusion regions. 355. An array as claimed in patent application No. 346, wherein a π eeprqm CMOS device is formed at each intersection of the first and third spaced apart conductors with the gate line. 356 · —a single-stone three-dimensional array containing a plurality of interlayer insulation layers The vertically separated device stages, each of which includes an array of patent application scope item 346. 357. An array as described in Patent Application No. 356, wherein the array includes three or more device stages. 358. For example, the array of the scope of patent application No. 357 further includes a driver package path 'arranged in the substrate below the array, and at least partially vertically aligned with the array. 359. The array of the scope of application for patent No. 358, wherein: the charge storage film includes at least one insulating layer capable of storing electric charges; and the driver circuit is a conductor that is mated and spaced apart at one level of the same level -67- paper size Applicable country standards (CNS) Α4 · (21 () χ297 public love) — 6. Provide a sufficient voltage between the scope of the patent application and a gate line to form a conductor between the conductor and the gate line. Conductive key. 360. The array according to the scope of patent application No. 359, wherein at least one conductive chain is formed between at least one conductor and at least one gate line. 361. For example, the array of the scope of patent application No. 360, wherein the array includes at least one logic circuit. 362. The array of the scope of application for patent No. 361, wherein the at least one logic circuit includes an inverter or a NAND gate. 363. For example, the array of the patent application No. 360, wherein the array includes a static random access memory. 364. A circuit comprising a plurality of charge storage devices and a plurality of non-fuse devices, wherein the circuit is used for programming as a gate array, a logic device or a memory device. 365. If the circuit in the scope of application for patent No. 364, wherein the plurality of charge storage devices and the plurality of non-fuse devices include the same group of devices, when a first stylized voltage is applied to the devices, the device functions as a charge Storage device: When a second stylized voltage higher than the first voltage is applied to these devices to form a conductive chain and pass through a charge storage area, the device functions as a fuseless device. 366. For the circuit in the scope of application for patent No. 365, the non-fuse devices include: a device formed by a conductive chain passing through the charge storage area. 367. The circuit of claim 365, wherein the charge storage devices include a semiconductor diode including a charge storage region. 368. If you apply for a circuit in the scope of patent application item 367, of which: -68- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 540086 AB c D Diodes include polycrystalline silicon or amorphous silicon diodes, arranged in a three-dimensional monolithic array, the array containing at least three device levels separated by an interlayer insulating layer, the array being arranged on a substrate; And the charge storage region includes a stack of insulating layers located between the p-doped and n-doped regions of the diodes, or near the p-doped and n-doped regions of the diodes. . 369. For the circuit in the scope of patent application No. 365, wherein the charge storage devices include EEPROM transistors. 370. If the circuit of the scope of application for patent No. 369, wherein: the transistors include polycrystalline broken or amorphous broken thin film transistors' arranged in a three-dimensional monolithic array, the array contains at least three interlayer insulation At the device level separated by layers, the array is arranged on a substrate; and the charge storage region includes a stack of insulating layers between the channels of the thin film transistors and the control gate. 371. The circuit of claim 370, wherein at least one device level of the three-dimensional monolithic array includes: a first plurality of spaced apart conductors arranged in a first direction to a first height above the substrate; And a second plurality of spaced apart rail stacks arranged at a second height in a second direction different from the first direction, each rail stack contains a semiconductor film that contacts the first plurality of spaced apart conductors A localized charge storage film disposed on the first semiconductor film; and a conductive film disposed on the local charge storage film. 372. If the circuit in the scope of application for patent No. 365, it further includes a driver -69- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 540086 AB CD VI. Patent application circuit, which is connected to provide a first stylized voltage to a first group of charge storage devices, increase a threshold voltage of the first group of charge storage devices, and thereby turn off the first A set of charge storage devices; and providing a second stylized voltage to a second set of charge storage devices to form a conductive chain passing through a charge storage region of the second set of charge storage devices to convert the second group The charge storage device becomes a non-fuse device. 373. For example, the circuit in the scope of patent application No. 372, wherein the circuit includes a programmable gate array or a programmable logic circuit. 374. For example, the circuit of the patent application No. 373, wherein the circuit is programmed to function as an inverter, a NAND gate, or a SRAM. 375. For the circuit under the scope of patent application No. 373, the area of each logic gate in the circuit is 4 (F (x + I)) 2 to 5 (F (x + I)) 2, where F is the minimum feature size , And X is the number of inputs on the logic gate. 376. A method of programming a circuit, comprising: providing a circuit including a plurality of charge storage devices; applying a first stylized voltage to a first group of charge storage devices to improve the first group of charge storage devices A threshold voltage to turn off the first group of charge storage devices; and applying a second stylized voltage to a second group of charge storage devices to form a conductive chain and pass a charge through the second group of charge storage devices A storage area to convert the second set of charge storage devices into a fuseless device. 377. The method according to the scope of application for patent No. 376, wherein the first and second sets of charge storage devices comprise the same set of charge storage devices. 378. For the method of applying for the scope of patent No. 377, in which the charge storage devices -70- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (2) The scope of patent application includes semiconductor diodes with a charge storage area. 379. The method according to item 378 of the patent application, wherein: the diodes include polycrystalline silicon or amorphous silicon diodes arranged in a three-dimensional monolithic array, the array containing at least three interlayer insulating layers In the separated device level, the array is disposed on a substrate; and the charge storage region includes a stack of insulating layers between the p-doped and n-doped regions of the diodes, or adjacent to the Equi-diode ρ-doped and η-doped regions. 380. The method of claiming scope 379, wherein the charge storage devices include EEPROM transistors. 381. The method of applying for item 380 of the patent scope, wherein: the transistors include polycrystalline silicon or amorphous silicon thin film transistors arranged in a three-dimensional monolithic array containing at least three interlayer insulating layers In a separate device level, the array is disposed on a substrate; and the charge storage region includes a stack of insulating layers between the channels of the thin film transistors and the control gate. 382. For the circuit in the scope of application for item 376, the circuit is programmed and functions as a logic gate. 383. For example, the circuit in the scope of patent application No. 376, wherein the circuit is programmed and functions as a static random access memory. 384. A semiconductor device comprising: a semiconductor active region; a charge storage region adjacent to the semiconductor active region; a first electrode; and -71-this paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 540086 AB c D 6. Patent application scope-a second electrode; where a first stylized voltage is applied between the first and second electrodes, the charge is stored in the charge storage area; And when a second stylized voltage higher than the first voltage is applied between the first and second electrodes, a conductive chain is formed to pass through the charge storage region and is formed between the first and second electrodes. A conductive path. 385. For the device under the scope of patent application No. 384, wherein the first stylized voltage increases a threshold voltage of the device, thereby turning off the device. 386. The device under the scope of patent application No. 384, wherein the devices include a semiconductor diode including a charge storage region. 387. The device under the scope of application for patent No. 386, wherein: the diode includes polycrystalline or amorphous broken diodes arranged in a three-dimensional monolithic array, the array containing at least three interlayer insulation In the device-level separated device array, the array is disposed on a substrate; and the charge storage region includes a stack of insulating layers between the p-doped and n-doped portions of the semiconductor active region of the diode. Or the p-doped and n-doped portions of the semiconductor active region adjacent to the diode. 388. The device of claim 385, wherein the charge storage device comprises an EEPROM transistor. 389. The device of the scope of application for patent No. 388, wherein: the semiconductor active region of the transistor includes a polycrystalline silicon or amorphous silicon film disposed on an insulating layer; the transistor is arranged in a three-dimensional monolithic array The array contains at least three device levels separated by an interlayer insulation layer. The array is configured in a -72- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 540086 A B c D 6. The scope of the patent application is on the substrate; and the charge storage region includes an insulating layer stack located between a channel in the semiconductor active region and a control gate of the transistor. 390. For the device under the scope of patent application No. 384, the device is arranged in a programmable gate array or a programmable logic device. 391. A method of manufacturing a semiconductor device array arranged on a substrate, comprising: forming a first plurality of spaced apart conductors, arranged in a first direction to a first height above the substrate; A first insulating layer is formed on and between the first conductors; the first insulating layer is planarized to expose the first conductors; a stack including the following layers is formed: a first semiconductor layer of a first conductivity type Contacting the first plurality of spaced apart conductors; a first localized charge storage film disposed on the first semiconductor layer; a gate line disposed on the first localized charge storage film; a second A local charge storage film is disposed on the gate line; and a second semiconductor layer of a second conductivity type is on the second local charge storage film; the stack of the layers is patterned to form A second plurality of spaced apart guide rail stacks are disposed at a second height above the first height in a second direction different from the first direction; a second insulating layer is formed on and between the rail stacks Planarization The second insulating layer; forming a plurality of trenches in the second insulating layer; forming a conductive layer among the trenches and above the second insulating layer; -73- This paper size applies to Chinese national standards (CNS ) A4 size (210X297 mm) 540086 A8 B8 C8 D8 6. Scope of patent application and planarization of the conductive layer to form a third plurality of spaced apart conductors, arranged to a third height above the second plurality of spaced apart rail stacks. 392. The method according to claim 391, wherein the first and second semiconductor layers include a polycrystalline debris layer. 393. The method according to claim 392, wherein the first and second charge storage films include a charge trapping medium. 394. The method of claim 393, wherein the charge trapping medium comprises a dielectric-isolated floating gate, electrically isolated nanocrystals, or a 0-N-0 dielectric stack. 395. The method of claim 395, wherein the gate line includes a first polycrystalline silicon layer of a second conductivity type, which is adjacent to the first charge storage film; Above the layer; and a second polycrystalline silicon layer of a first conductivity type, above the silicide layer, adjacent to the second charge storage film. 396. The method of claiming scope 391, further comprising: diffusing a second conductivity type dopant from the first conductors into the first semiconductor layer to form a source or drain region. 397. If the method according to the scope of patent application No. 391, the method further comprises: implanting first conductivity type ions into the trenches, and forming source and drain regions in the second semiconductor layer. 398. If the method according to the scope of application for patent No. 391, further comprises: forming a side wall space on the side wall of the guide rail stack before forming the second insulating layer -74- This paper standard applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) 540086 A B c D Six, patent application scope. 399. The method of claim 391, wherein the second plurality of guide rail stacks are arranged to intersect the first and third plurality of spaced apart conductors. 400. The method of claim 391, further comprising: monolithically forming a plurality of additional array device stages to form a three-dimensional monolithic array including at least three device stages. 401. A flash memory array arranged on a substrate, comprising: a first plurality of spaced apart conductive bit lines arranged in a first direction to a first height above the substrate; and A second plurality of spaced apart rail stacks are arranged at a second height in a second direction different from the first direction, and each rail stack includes: a plurality of semiconductor islands, a first surface of which contacts the first plurality Spaced apart conductive bit lines; a conductive word line; and some charge storage regions, disposed between the second surface of the semiconductor islands and the word line. 402. The array according to item 401 of the patent application scope, wherein the semiconductor islands include a first conductivity type polycrystalline silicon. 403. For example, the array of the scope of patent application No. 402, wherein the polycrystalline silicon islands include a second conductivity type external diffusion source and drain region, and conductive bit lines separated at the intervals are stacked with the separated guide rails Contact between intersections. 404. For an array with the scope of patent application No. 403, wherein the spaced apart conductive bit lines include the second conductivity type polycrystalline silicon, and contact the source and the non-electrode -75- This paper applies Chinese National Standard (CNS) A4 size (210 X 297 mm) A B c D 540086 VI. Patent application area. 405. For example, an array with a scope of patent application No. 404, which further comprises a metal or metal silicide layer, and contacts the bit lines. 406. For example, the array of the scope of application for patent No. 401, wherein the interval between the spaced-apart conductive line includes a planar insulating material. 407. For example, the array of the scope of application for patent No. 406, wherein the charge storage regions include a dielectric-isolated floating gate, electrically isolated nano-crystals, or a 0-N-0 dielectric stack. 408. If the array of the scope of application for patent No. 407, wherein the charge storage regions include a floating gate between a tunneling dielectric and a control gate dielectric; the tunneling dielectric The lateral side of the semiconductor island is aligned with the lateral side of the floating gate; and the control gate dielectric extends between the semiconductor islands and contacts the planarized insulating material between the semiconductor islands. 409. For example, the array of patent application No. 407, wherein the charge storage region includes a floating gate, which is made of hemispherical grain polycrystalline silicon, has a roughened surface, and is located in a tunneling dielectric and a control Between the gate dielectrics 410. For example, the array of the scope of application patent No. 401, wherein the word line includes a second conductivity type polycrystalline silicon layer, and a metal or metal silicide layer contacting the polycrystalline silicon layer. 411. For the array of the scope of application for patent No. 401, the guide rails are stacked on the bit lines. -76- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 540086 A8 B8 C8 D8 VI. Application for patent scope 412 · For the array of patent scope No. 401, where the guide rails are stacked Configured below these bit lines. 413 · How about the 401th item in the scope of patent application? J, where the word line and the charge storage region are offset from the drain region in the semiconductor island. 414. The array according to item 413 of the patent application, wherein an insulating layer is located between the semiconductor island and the word line in an offset region. 415. If the array is in the scope of patent application No. 401, the semiconductor islands are located at the intersection of the rail stack and the bit line. 416. The array according to the scope of patent application No. 415, wherein the TFT EEPROMs are formed at the intersection of the rail stack and the bit line. 417. The array according to item 416 of the patent application scope, further comprising an access transistor, which is located at the intersection of the rail stack and the bit line. 418. The array according to the scope of application for patent No. 417, wherein: the semiconductor islands include a channel region adjacent to the access transistor and EEPROM 'between a common source and drain region; m the word lines Forming the control gates of the EEPROMs and the gate electrodes of the access transistors; a first insulation layer forming a common, control gate dielectric of the EEPROMs and the gate insulation layer of the access transistors; and A floating gate and a tunneling dielectric are located between the word line and the channel area of the EEPROMs. 419. If the array of the scope of application for patent No. 416, one of the EEPROM cells in the array is stylized when its source bit line is grounded, its bit line is either floating or grounded, and there is a High positive voltage -77- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 6. Patent application range Pulses are applied to the word line of the selected EEPROM cell, and all on the same device level The other bit lines are allowed to float or be placed at a slightly positive voltage, while all other word lines on the same device level are grounded. 420. For the array of patent application No. 419, a plurality of EEPROM cells are programmed at the same time. 421. For an array with a scope of patent application No. 420, the programmed voltage is 10 to 20 volts. 422. For example, the array of the scope of patent application No. 419, wherein: The erasure of an EEPROM cell in the array is by: pulsing its word line to a high negative value, and its source and drain bit lines Ground; or the erasure of an EEPROM cell in the array by: grounding its word line, and at least one of its source and impulse pulses to a high positive value. 423. If the array of the scope of application for patent No. 422, wherein: the plurality of EEPROM cells in the array are erased at the same time, by: pulse a plurality of word lines to a high negative value, and all bit lines are grounded Or simultaneously erase the plurality of EEPROM cells in the array by: grounding their word lines, and at least one of their source and impulse pulses to a high positive value. 424. A single-stone three-dimensional array, including a plurality of stages, each of which includes an array in the scope of patent application No. 415. 425. For example, the array of the scope of application for patent No. 424, in which the unit size of each bit in the array is about 8F2 / N to about 11F2 / N, where F is a minimum feature size and N is a device layer in the array number. -78- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm). 々Applicable patent scope 426. For an array of patent application scope item No. 424, it further includes: an interlayer insulation layer. A second plurality of spaced apart guide rail stacks; a third plurality of spaced apart conductive bit lines arranged in a first direction to a third height above the substrate; and a fourth plurality of spaced apart guide rails The stack is arranged at a fourth height in a second direction different from the first direction, and each rail stack includes: a plurality of semiconductor islands, the first surface of which is in contact with the third plurality of spaced apart conductive bit lines A conductive word line; and some charge storage regions, disposed between the second surface of the semiconductor islands and the word line. 427. For example, the array of the scope of application for patent No. 426, further comprising: an interlayer insulating layer on the fourth plurality of spaced apart guide rail stacks; the fifth plurality of spaced apart conductive bit lines on a first The direction is arranged to a fifth height above the interlayer insulation layer; and the sixth plurality of spaced apart guide rail stacks are arranged in a second direction different from the first direction to a sixth height, each guide rail is stacked Both include: a plurality of semiconductor islands, the first surface of which is in contact with the fifth plurality of spaced apart conductive bit lines; a conductive word line; and some charge storage regions arranged on the second surface of the semiconductor islands and the word Between the lines. -79- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 540086 AB c D 6. Application for patent scope 428. For an array with patent scope item No. 424, among which the word lines of these guide rails are stacked The charge storage region and the semiconductor island are aligned on a plane that is perpendicular to the substrate and parallel to the source-to-electrode direction. 429. For the array of the scope of application for patent No. 428, the word lines, charge storage areas and semiconductor islands of the guide rail stacks are aligned on two planes perpendicular to the substrate and parallel to the source-to-animation directions. 430. A method of manufacturing a flash memory array arranged on a substrate, comprising: forming a first plurality of spaced apart conductors, arranged in a first direction to a first height above the substrate; Forming a first insulating layer between the first conductors; forming a stack including the following layers: a first semiconductor layer and a charge storage film; patterning the stack to form a plurality of first rail stacks, Both contain a semiconductor rail and a charge storage rail and have at least one aligned lateral edge y forming a source and drain region in the semiconductor rails; forming a second conductive layer; and patterning the second conductive layer And the first guide rails are stacked to form a plurality of second guide rail stacks, each including a word line, a charge storage area island, and a semiconductor island, wherein the second guide rails are stacked perpendicular to the substrate and parallel to the source electrode Align the polar plane. 431. If the method of applying for the scope of patent No. 430, wherein: the step of forming a first insulating layer between the first conductors includes: in the first -80- this paper size applies the Chinese National Standard (CNS) A4 specification (210X297) %) 6. A first insulation layer is formed on and between the conductors in the scope of patent application, and the first insulation layer is planarized to expose the first conductor; and the step of forming several layers of stacks includes: the exposed first conductor and the planarization A stack of these layers is formed on the first insulating layer. 432. The method of claiming scope 431 of the patent application, wherein the step of forming the source and drain regions comprises: diffusing a first plurality of spaced apart conductors, and diffusing a second conductivity type dopant into the first conductivity Rated semiconductor island. 433. If the method of applying for patent No. 430, wherein: the step of forming a first insulating layer includes: forming a first insulating layer on a semiconductor island on which a second rail is stacked; and the step of forming a first conductor includes: A trench is formed in an insulating layer, a second conductive layer is deposited in the trenches and above the first insulating layer, and the second conductive layer is planarized. 434. The method according to claim 430, wherein: the first conductor includes a polycrystalline debris layer and a metal or metal debris layer; and the word line includes a polycrystalline debris layer and a metal or metal debris material Floor. 435. The method of claim 430, wherein the charge storage area islands include a dielectrically isolated floating gate, electrically isolated nanocrystals, or a 0-N-0 dielectric stack. 436. The method of claiming item 435, wherein: the step of forming the stack includes: forming a tunneling dielectric layer and a floating gate layer on the first semiconductor layer; and patterning the stack. Contains: -81 formed on the floating gate layer-This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 540086 A BCD VI. Patent application scope-Photoresistive mask and etch the stack To form a plurality of first rail stacks, which contain semiconductor rails and charge storage rails and have at least one aligned transverse edge, and these charge storage rails contain tunneling dielectrics and floating gates 0 437. Such as applying for a patent The method of scope item 436, further comprising: forming a control gate dielectric layer on the floating gates of the first rail stack, wherein the control gate dielectric layer extends beyond a horizontal direction of the first rail stack. Yuan 438. For example, the method of claim 437, wherein the step of patterning the second conductive layer and the stacking of the first rail further includes: patterning the gate dielectric layer to control The gate dielectric is disposed between the word line and the first insulating layer; and, the gate dielectric is controlled to align with the semiconductor island and tunnel through a plane perpendicular to the substrate and parallel to the source-to-drain direction. Dielectrics, floating gates and control gates. 439. The method of claiming item 435, wherein: the step of forming the stack includes: forming a tunneling dielectric layer and a floating gate layer on the first semiconductor layer; and patterning the stack. Including: etching the stack to form a plurality of first rail stacks, which include semiconductor rails and charge storage rails and have at least one aligned lateral edge, the semiconductor rails have a first width, and the charge storage rails include tunneling The dielectric and floating gates are smaller than the first width; so that the first rail stack includes: an aligned semiconductor rail, tunneling dielectric, and floating gates -82- This paper size applies to China Standard (CNS) A4 (210 x 297 mm) 540086 AB c D 6. Scope of patent application; and an exposed part of one of the semiconductor guide rails. 440. The method of claiming scope 439 of the patent application, wherein the step of patterning the stack includes: forming a first photoresist mask on the stack, which has a first width y and uses the first photoresist A mask, which etches the first semiconductor layer, the tunneling dielectric layer, and the floating gate layer; forming a second photoresist mask on the floating gate layer, which has a second width smaller than the first width; and The second photoresist mask etches the tunnel dielectric layer and the floating gate layer, except for the first semiconductor layer. 441. For the method of applying for the scope of patent No. 439, wherein the step of patterning the stack includes: forming a first photoresistive mask on the stack, which has a first width using the first photoresistive mask To etch through the tunnel dielectric layer and the floating gate layer to expose a portion of the first semiconductor layer; a second photoresist mask is formed on the floating gate layer and on the exposed portion of the first semiconductor layer A mask having a second width greater than the first width; and etching the first semiconductor layer with the second photoresist mask. 442. If the method of the scope of application for patent No. 439, further includes: on the floating gate layer and the exposed part of the semiconductor rail stacked on the first rail -83- This paper standard applies to China National Standard (CNS) A4 (210X297 mm) 540086 A8 B8 C8 _ _ D8 6. The scope of patent application is to form a control gate dielectric layer, wherein the control gate dielectric layer is used to access the transistor on an exposed part of one of the semiconductor guide rails. Gate dielectric. 443. The method of claim 442, wherein the control gate dielectric layer extends beyond the lateral edge of the first rail stack. 444. According to the method of applying for item 443 of the patent scope, the patterning step of stacking the second conductive layer and the first guide rail further includes: patterning the gate dielectric layer to control the gate dielectric layer Arranged between the word line and the first insulating layer; and, the gate dielectric is aligned on the semiconductor island, the tunnel dielectric, and floats on a plane perpendicular to the substrate and parallel to the source-drain direction. Gate and control gate. 445. The method according to claim 439, further comprising: forming a second insulating layer ′ between an exposed portion of one of the semiconductor rails and the word line to form an offset region. 446. The method according to the scope of patent application for item 445, further comprising: forming a second insulation layer between the semiconductor guide rails to isolate the semiconductor track 447. The method, including the scope of patent application 430, further comprising: : Monolithically forming a plurality of additional array device stages to form a three-dimensional monolithic array having at least three device stages. 448. The method of claiming scope 447 of the patent application, further comprising: forming an interlayer insulating layer between the device levels. 449. A charge storage device disposed on a substrate, comprising: a first layer of transition metal crystalline silicon disposed on a substrate; 540086 A B c D 6. Scope of patent application-p-n junction; and a local charge storage film, which is arranged adjacent to the first layer. 450. —A single-stone three-dimensional array, including a plurality of device scopes of patent application No. 449, wherein the pn junction includes: a junction between a source region and a channel, or a junction between a drain region and a channel Butt. 451. A memory array arranged on a substrate, comprising: a first plurality of spaced apart conductors arranged in a first direction to a first height above the substrate; and a second plurality of spaces The separated rail stacks are arranged at a second height in a second direction different from the first direction, and each rail stack includes: a semiconductor film of a first conductivity type that contacts the first plurality of spaced apart A conductor; a localized charge storage film disposed adjacent to the semiconductor film; and a conductive film disposed near the localized charge storage film; each of the semiconductor films at least partially using a transition metal to conduct a lateral crystallization process crystallization. 452. A method of manufacturing a charge storage device, comprising: providing a first amorphous silicon or polycrystalline silicon layer on a substrate; providing a transition metal catalyst into the first layer; forming in the first layer A pn junction; and forming a local charge storage film disposed adjacent to the first layer. 453. The method of claiming range 452 of the patent application, wherein the crystallization is performed in a temperature range of about 400 ° C to about 700 ° C; further comprising: annealing at a higher temperature of about 750 ° C to 975 ° C Temperature range to crystallize the first layer. -85- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A B c D 540086 6. Scope of Patent Application 454. For the method of applying for the scope of patent application No. · 452, it further includes: forming a gate electrode arranged near the local charge storage film. 455. The method of claim 454, further comprising: forming a plurality of device grades containing transition metal crystalline silicon TFTs. 456. A semiconductor device comprising a monolithic three-dimensional charge storage device array, the array comprising a plurality of device stages, of which at least one surface between two consecutive device stages is planarized by chemical mechanical polishing. 457. The semiconductor device of claim 456, wherein the array includes four or more device stages. 458. For the semiconductor device under the scope of application for patent No. 457, each of the charge storage devices includes a pillar type TFT EEPROM. 459. The semiconductor device of claim 457, wherein each charge storage device comprises a post-type diode having a charge storage region. 460. For the semiconductor device under the scope of application No. 457, each of the charge storage devices includes a self-aligned TFT EEPROM. 461. For the semiconductor device under the scope of patent application No. 457, each of the charge storage devices includes a rail-stacked TFT EEPROM. 462. In the case of a semiconductor device under patent application No. 457, the surface of the insulating or conductive layer in each device level is planarized by chemical mechanical polishing. 463. In the case of the semiconductor device under the scope of application for patent No. 457, the surface of the interlayer insulating layer located between the two levels is planarized by a chemical mechanical polishing method. 464. The semiconductor device according to the scope of application for patent No. 457, wherein the surface peak-to-peak roughness planarized by the chemical mechanical polishing method is 4000 angstroms or less. 465. For the semiconductor device with the scope of patent application No. 457, it further contains -86- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) C8 D8 6. The scope of patent application / partially formed The driver circuits in the substrate are below the array, within the array, or above the array. 466. The semiconductor device of claim 465, wherein the driver circuit includes at least one of a sense amplifier and a charge pump, and is formed in the substrate and below the array. An ant-type method for manufacturing a monolithic three-dimensional charge storage device array, which comprises a basic device containing a plurality of first charge storage devices; a monolith forms at least one upper device level and includes a plurality of second charge storage devices The device is on the lower device level, such at least one upper device level layer is directly placed on the lower device level layer; and at least one surface is planarized between the lower device level and the at least one upper device level by a chemical mechanical polishing method. 468. The method according to the scope of application for patent No. 467, which further includes: forming four or more device levels including a lower device level and at least one upper device level; and by chemical mechanical polishing method, at least three consecutive At least one surface is planarized between the device levels. 469 · The method according to the scope of application for patent No. 468, wherein each of the first and second charge storage devices is selected from the group consisting of: a guide post type ErpROM, a guide post having a charge storage area Type diode, self-aligned Kai EEPROM, and rail-stacked TFT EEPROM 〇470, such as the method of patent application No. 468, wherein the planarization of at least one surface between the lower device level and at least one upper device level The steps include planarizing the lower device and a surface of the first insulating layer by chemical mechanical polishing. -87- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) A BCD 540086 VI. Application for patent scope 471. For the method of applying for patent scope No. 468, which planarizes the lower device level and The step of at least one surface between at least one upper device stage includes planarizing a surface of the lower device and a middle conductive layer by chemical mechanical polishing. 472. If the method of applying scope of patent No. 468, wherein the step of planarizing at least one surface between the lower device stage and at least one upper device stage includes planarizing the lower device by chemical mechanical polishing, the At least one surface of an interlayer insulation layer between device stages. 473. The method according to claim 468, further comprising: forming a driver circuit at least partially in the substrate, and below the array, within the array, or above the array. 474. The method of claim 473, wherein the driver circuit includes at least one of a sense amplifier and a charge pump, formed in a substrate and below the array. This paper size applies to China National Standard (CNS) A4 (210x 297 mm)