JP4908901B2 - 不揮発性メモリの製造方法 - Google Patents
不揮発性メモリの製造方法 Download PDFInfo
- Publication number
- JP4908901B2 JP4908901B2 JP2006108408A JP2006108408A JP4908901B2 JP 4908901 B2 JP4908901 B2 JP 4908901B2 JP 2006108408 A JP2006108408 A JP 2006108408A JP 2006108408 A JP2006108408 A JP 2006108408A JP 4908901 B2 JP4908901 B2 JP 4908901B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- insulating film
- lower electrode
- forming
- electrode wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims description 82
- 238000000034 method Methods 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000002427 irreversible effect Effects 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 57
- 239000011229 interlayer Substances 0.000 description 21
- 239000012535 impurity Substances 0.000 description 12
- 239000004020 conductor Substances 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 9
- 230000001066 destructive effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/91—Diode arrays, e.g. diode read-only memory array
Landscapes
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Description
2 メモリセル
3、23、33 上部電極(上部電極配線)
4、24、34 下部電極(下部電極配線)
5、6、7、26、27、36 ポリシリコン
8、8a、8b、28a、28b、38a、38b PN接合部
9a、9b、9c、29、39 層間絶縁膜
10 シリコン基板
11 接続導体
12 トランジスタ入出力導線
20 ビアホール
Claims (4)
- 状態変化が1度だけ可能な不可逆性の状態変化部を備えた不揮発性メモリの製造方法において、
シリコン基板上にトランジスタを設けた上層に第1絶縁膜を形成する工程と;
前記第1絶縁膜上に下部電極配線を形成する工程と:
前記下部電極配線の上に第2絶縁膜を形成する工程と;
前記下部電極配線と接続可能な前記第2絶縁膜の所定箇所にビアホールを設ける工程と;
前記ビアホール内にCVDによる成膜とエッチングとを繰り返す事により下方から上方に向かって順に、P型又はN型の第3半導体層、前記第3半導体と異なる導電型の第4半導体層、および第3半導体層を積層して前記ビアホールを埋め込んだ状態変化部を形成する工程と;
前記状態変化部の最上層の前記第3半導体層に接続させて上部電極配線を形成する工程とを含むことを特徴とする不揮発性メモリの製造方法。 - 状態変化が1度だけ可能な不可逆性の状態変化部を備えた不揮発性メモリの製造方法において、
シリコン基板上にトランジスタを設けた上層に第1絶縁膜を形成した後、下部電極配線を形成する工程と;
前記下部電極配線の上に第2絶縁膜を形成する工程と;
前記下部電極配線の上部全面に、下方から上方に向かって順にP型又はN型の第3半導体層、前記第3半導体と異なる導電型の第4半導体層、および第3半導体層を積層した積層半導体を形成する工程と;
前記積層半導体を、前記下部電極配線と接続させた所定箇所を残してエッチングして、残された部分をメモリセルとして形成する工程と;
前記積層半導体の前記エッチングにより取り除かれた領域に絶縁膜を埋め込む工程と;
前記積層半導体の最上層の前記第3半導体層に接続させて上部電極配線を形成する工程とを含むことを特徴とする不揮発性メモリの製造方法。 - 状態変化が1度だけ可能な不可逆性の状態変化部を備えた不揮発性メモリの製造方法において、
シリコン基板上にトランジスタを設けた上層に第1絶縁膜を形成した後、P型又はN型の第3半導体により下部電極配線を形成する工程と;
前記下部電極配線の上に第2絶縁膜を形成する工程と;
前記下部電極配線と接続可能な前記第2絶縁膜の所定箇所にビアホールを設ける工程と;
前記ビアホールをCVD法により前記第3半導体と異なる導電型の第4半導体層で埋め込む工程と;
前記第4半導体層に接続させて第3半導体により上部電極配線を形成する工程とを含むことを特徴とする不揮発性メモリの製造方法。 - 前記第3半導体はP型ポリシリコンまたはN型ポリシリコンのいずれか一方であり、
前記第4半導体はP型ポリシリコンまたはN型ポリシリコンの他方であることを特徴とする請求項1乃至3の何れか1項に記載の不揮発性メモリの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006108408A JP4908901B2 (ja) | 2006-04-11 | 2006-04-11 | 不揮発性メモリの製造方法 |
US11/656,934 US7349248B2 (en) | 2006-04-11 | 2007-01-24 | Non-volatile memory |
KR1020070014290A KR101347624B1 (ko) | 2006-04-11 | 2007-02-12 | 비휘발성 메모리, 그 제조 방법, 및 당해 메모리의 기록 및판독 방법 |
CN200710078734.1A CN101055874B (zh) | 2006-04-11 | 2007-02-17 | 非易失性存储器、其制造方法及该存储器的写入读出方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006108408A JP4908901B2 (ja) | 2006-04-11 | 2006-04-11 | 不揮発性メモリの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007281332A JP2007281332A (ja) | 2007-10-25 |
JP4908901B2 true JP4908901B2 (ja) | 2012-04-04 |
Family
ID=38661027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006108408A Expired - Fee Related JP4908901B2 (ja) | 2006-04-11 | 2006-04-11 | 不揮発性メモリの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7349248B2 (ja) |
JP (1) | JP4908901B2 (ja) |
KR (1) | KR101347624B1 (ja) |
CN (1) | CN101055874B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8735885B2 (en) | 2007-12-14 | 2014-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Antifuse memory device |
EP2751807A4 (en) * | 2011-09-02 | 2015-02-18 | Hewlett Packard Development Co | DEVICE FOR STORING DATA AND METHOD FOR READING MEMORY CELLS |
JP6479533B2 (ja) * | 2015-03-31 | 2019-03-06 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5856981B2 (ja) * | 1979-08-09 | 1983-12-17 | 日本電信電話株式会社 | プログラマブル読出専用半導体記憶回路装置 |
US4646266A (en) * | 1984-09-28 | 1987-02-24 | Energy Conversion Devices, Inc. | Programmable semiconductor structures and methods for using the same |
JPH01189958A (ja) * | 1988-01-26 | 1989-07-31 | Toshiba Corp | 半導体記憶装置 |
JPH022669A (ja) * | 1988-06-15 | 1990-01-08 | Nec Corp | 半導体記憶装置 |
JP3344598B2 (ja) * | 1993-11-25 | 2002-11-11 | 株式会社デンソー | 半導体不揮発メモリ装置 |
US6034882A (en) | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
EP1312120A1 (en) * | 2000-08-14 | 2003-05-21 | Matrix Semiconductor, Inc. | Dense arrays and charge storage devices, and methods for making same |
US6847047B2 (en) * | 2002-11-04 | 2005-01-25 | Advanced Micro Devices, Inc. | Methods that facilitate control of memory arrays utilizing zener diode-like devices |
US7132350B2 (en) * | 2003-07-21 | 2006-11-07 | Macronix International Co., Ltd. | Method for manufacturing a programmable eraseless memory |
US7314815B2 (en) * | 2004-10-21 | 2008-01-01 | Macronix International Co., Ltd. | Manufacturing method of one-time programmable read only memory |
US7071533B1 (en) * | 2005-02-04 | 2006-07-04 | Polar Semiconductor, Inc. | Bipolar junction transistor antifuse |
-
2006
- 2006-04-11 JP JP2006108408A patent/JP4908901B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-24 US US11/656,934 patent/US7349248B2/en not_active Expired - Fee Related
- 2007-02-12 KR KR1020070014290A patent/KR101347624B1/ko not_active IP Right Cessation
- 2007-02-17 CN CN200710078734.1A patent/CN101055874B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101055874B (zh) | 2015-04-22 |
US7349248B2 (en) | 2008-03-25 |
KR20070101118A (ko) | 2007-10-16 |
CN101055874A (zh) | 2007-10-17 |
JP2007281332A (ja) | 2007-10-25 |
KR101347624B1 (ko) | 2014-01-09 |
US20070258285A1 (en) | 2007-11-08 |
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