JP6479533B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 216
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000010410 layer Substances 0.000 claims description 133
- 239000012212 insulator Substances 0.000 claims description 131
- 239000002344 surface layer Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000000052 comparative effect Effects 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 238000004088 simulation Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 238000009826 distribution Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 239000004020 conductor Substances 0.000 description 5
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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Description
図1は、本発明の実施形態に係る半導体装置1の構成を示す断面図である。半導体装置1は、基板層11、絶縁体層12およびN型半導体層13が積層されて構成されるSOI(Silicon on Insulator)基板10を含んで構成されている。
以下に、本発明の第2の実施形態に係る半導体装置の製造方法について説明する。図9は、本発明の第2の実施形態に係る半導体装置の製造方法を示す断面図である。
図10(a)〜図10(d)は、絶縁体ピラーの形態のバリエーションを示す図であり、ゲート長方向およびゲート幅方向に平行な平面における絶縁体ピラーの構成を示す。
12 絶縁体層
13 N型半導体層
20 絶縁体ピラー
33 フィールド酸化膜
41 ゲート絶縁膜
42 ゲート電極
43 P型ベース領域
44 N型エミッタ領域
45 P型コレクタ領域
102 トレンチ
Claims (16)
- N型半導体層の表層部に設けられたP型ベース領域と、
前記P型ベース領域の内側に設けられたN型エミッタ領域と、
前記N型半導体層の表層部に前記P型ベース領域と離間して設けられたP型コレクタ領域と、
前記N型半導体層の表面に設けられ、前記P型ベース領域および前記N型エミッタ領域に接するゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、
前記N型半導体層の内部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられ、一端が前記N型半導体層の表層部に延在するN型半導体に接続され、且つ前記N型半導体層の深さ方向に伸びる絶縁体を有する柱状構造物と、
を含み、
前記柱状構造物の前記N型半導体に接続された一端が、前記P型ベース領域の底部よりも上方に位置していることを特徴とする半導体装置。 - 前記N型半導体層の表層部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられた絶縁体領域を更に含み、
前記柱状構造物は、前記絶縁体領域との間に前記N型半導体を挟んで前記絶縁体領域から離間していることを特徴とする請求項1に記載の半導体装置。 - 前記N型半導体層は、絶縁体層の上に形成され、
前記柱状構造物の他端は、前記絶縁体層に接続されていることを特徴とする請求項1または請求項2に記載の半導体装置。 - N型半導体層の表層部に設けられたP型ベース領域と、
前記P型ベース領域の内側に設けられたN型エミッタ領域と、
前記N型半導体層の表層部に前記P型ベース領域と離間して設けられたP型コレクタ領域と、
前記N型半導体層の表面に設けられ、前記P型ベース領域および前記N型エミッタ領域に接するゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、
前記N型半導体層の内部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられ、一端が前記N型半導体層の表層部に延在するN型半導体に接続され、且つ前記N型半導体層の深さ方向に伸びる絶縁体を有する柱状構造物と、
を含み、
前記柱状構造物は、前記P型ベース領域と前記P型コレクタ領域とが並ぶ方向であるゲート長方向に沿って分割されていることを特徴とする半導体装置。 - 前記柱状構造物は、前記P型ベース領域と前記P型コレクタ領域とが並ぶ方向と交差する方向であるゲート幅方向に沿って分割されていることを特徴とする請求項1から請求項3のいずれか1項に記載の半導体装置。
- N型半導体層の表層部に設けられたP型ベース領域と、
前記P型ベース領域の内側に設けられたN型エミッタ領域と、
前記N型半導体層の表層部に前記P型ベース領域と離間して設けられたP型コレクタ領域と、
前記N型半導体層の表面に設けられ、前記P型ベース領域および前記N型エミッタ領域に接するゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、
前記N型半導体層の内部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられ、一端が前記N型半導体層の表層部に延在するN型半導体に接続され、且つ前記N型半導体層の深さ方向に伸びる絶縁体を有する柱状構造物と、
前記N型半導体層の表層部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられた絶縁体領域と、
を含み、
前記柱状構造物は、前記絶縁体領域との間に前記N型半導体を挟んで前記絶縁体領域から離間しており、前記絶縁体領域と前記柱状構造物との距離は、0.1μm以上2μm以下であることを特徴とする半導体装置。 - N型半導体層の表層部に設けられたP型ベース領域と、
前記P型ベース領域の内側に設けられたN型エミッタ領域と、
前記N型半導体層の表層部に前記P型ベース領域と離間して設けられたP型コレクタ領域と、
前記N型半導体層の表面に設けられ、前記P型ベース領域および前記N型エミッタ領域に接するゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、
前記N型半導体層の内部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられ、一端が前記N型半導体層の表層部に延在するN型半導体に接続され、且つ前記N型半導体層の深さ方向に伸びる絶縁体を有する柱状構造物と、
前記N型半導体層の表層部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられた絶縁体領域と、
を含み、
前記柱状構造物は、前記絶縁体領域との間に前記N型半導体を挟んで前記絶縁体領域から離間しており、前記P型ベース領域と前記P型コレクタ領域とが並ぶ方向であるゲート長方向における前記柱状構造物の幅は、前記絶縁体領域の前記ゲート長方向における長さの6.7%以上29.2%以下であることを特徴とする半導体装置。 - N型半導体層の表層部に設けられたP型ベース領域と、
前記P型ベース領域の内側に設けられたN型エミッタ領域と、
前記N型半導体層の表層部に前記P型ベース領域と離間して設けられたP型コレクタ領域と、
前記N型半導体層の表面に設けられ、前記P型ベース領域および前記N型エミッタ領域に接するゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、
前記N型半導体層の内部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられ、一端が前記N型半導体層の表層部に延在するN型半導体に接続され、且つ前記N型半導体層の深さ方向に伸びる絶縁体を有する柱状構造物と、
前記N型半導体層の表層部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられた絶縁体領域と、
を含み、
前記柱状構造物は、前記絶縁体領域との間に前記N型半導体を挟んで前記絶縁体領域から離間しており、
前記P型ベース領域と前記P型コレクタ領域とが並ぶ方向であるゲート長方向における前記柱状構造物の幅は、4μm以上17.5μm以下であることを特徴とする請求項2または6に記載の半導体装置。 - N型半導体層の表層部に設けられたP型ベース領域と、
前記P型ベース領域の内側に設けられたN型エミッタ領域と、
前記N型半導体層の表層部に前記P型ベース領域と離間して設けられたP型コレクタ領域と、
前記N型半導体層の表面に設けられ、前記P型ベース領域および前記N型エミッタ領域に接するゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、
前記N型半導体層の内部の、前記P型ベース領域と前記P型コレクタ領域との間に設けられ、一端が前記N型半導体層の表層部に延在するN型半導体に接続され、且つ前記N型半導体層の深さ方向に伸びる絶縁体を有する柱状構造物と、
を含み、
前記P型ベース領域と前記柱状構造物との距離は、4μm以下であることを特徴とする半導体装置。 - 前記柱状構造物と前記P型ベース領域との距離は、前記柱状構造物と前記P型コレクタ領域との距離よりも短いことを特徴とする請求項1から請求項9のいずれか1項に記載の半導体装置。
- N型半導体層の表面から前記N型半導体層の深さ方向に伸びるトレンチを形成する工程と、
前記トレンチの内部に絶縁体を埋め込んで柱状構造物を形成する工程と、
前記トレンチの内部の前記柱状構造物の上部をN型半導体で埋める工程と、
前記N型半導体層の表面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上にゲート電極を形成する工程と、
前記ゲート絶縁膜に接するように、前記N型半導体層の表層部にP型ベース領域を形成する工程と、
前記ゲート絶縁膜に接するように前記P型ベース領域の内側にN型エミッタ領域を形成する工程と、
前記P型ベース領域との間に前記柱状構造物を挟むように、前記N型半導体層の表層部にP型コレクタ領域を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記柱状構造物との間に前記N型半導体を挟むように、前記N型半導体層の表層部に絶縁体領域を形成する工程を更に含むことを特徴とする請求項11に記載の製造方法。
- 前記N型半導体層は、絶縁体層の上に形成されており、
前記柱状構造物を前記絶縁体層に接続することを特徴とする請求項11または請求項12に記載の製造方法。 - 前記トレンチの内部の前記柱状構造物の上部を前記N型半導体で埋める工程は、前記トレンチの側壁から前記N型半導体の結晶を成長させる工程を含むことを特徴とする請求項11から請求項13のいずれか1項に記載の製造方法。
- 前記トレンチの内部の前記柱状構造物の上部を前記N型半導体で埋めた後に、前記N型半導体層の表面を平坦化する工程を更に含むことを特徴とする請求項11から請求項14のいずれか1項に記載の製造方法。
- 前記N型半導体層は、シリコンを含み、
前記トレンチの内部の前記柱状構造物の上部を前記N型半導体で埋める前に、前記N型半導体層の上にシリコン窒化膜を形成する工程と、
前記トレンチの内部の前記柱状構造物の上部を前記N型半導体で埋めた後に、前記シリコン窒化膜を除去して前記N型半導体層の表面を露出させる工程および露出した前記N型半導体層の表面を平坦化する工程
を更に含むことを特徴とする請求項11から請求項15のいずれか1項に記載の製造方法。
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