WO2010046795A1 - Semiconductor device and method of manufacturing such a device - Google Patents

Semiconductor device and method of manufacturing such a device Download PDF

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Publication number
WO2010046795A1
WO2010046795A1 PCT/IB2009/054362 IB2009054362W WO2010046795A1 WO 2010046795 A1 WO2010046795 A1 WO 2010046795A1 IB 2009054362 W IB2009054362 W IB 2009054362W WO 2010046795 A1 WO2010046795 A1 WO 2010046795A1
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Prior art keywords
region
semiconductor device
trenches
junction
segments
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PCT/IB2009/054362
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French (fr)
Inventor
Jan Sonsky
Anco Heringa
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Nxp B.V.
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Publication of WO2010046795A1 publication Critical patent/WO2010046795A1/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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Definitions

  • the present invention relates to a semiconductor device comprising a first doped region, a second doped region and a doped active region between the first region and the second region, the active region comprising a p-n junction, a plurality of laterally extending trenches filled with an insulating material, the depth of said trenches exceeding the depth of the doping profile in the active region, and a plurality of active stripes separated by said trenches.
  • the present invention further relates to a method of manufacturing such a device.
  • a number of structures are known that can deliver better results than the 1 D limit. Such structures are typically known as reduced surface field (RESURF) structures. Junction shaping, or field shaping using field plates or semi- insulating films can be used.
  • RESURF reduced surface field
  • the present invention seeks to provide a semiconductor device exhibiting an improved breakdown voltage.
  • the present invention further seeks to provide a method of manufacturing a semiconductor device exhibiting an improved breakdown voltage.
  • a semiconductor device comprising a first doped region, a second doped region and a doped active region between the first region and the second region, the active region comprising a p-n junction; a plurality of laterally extending trenches filled with an insulating material, the depth of said trenches at least matching the depth of the doping profile in the active region, each of said trenches comprising a plurality of segments separated by portions of said active region; and a plurality of active stripes separated by said trenches.
  • each segment has a predetermined width, the respective widths of the segments of each trench decreasing in a lateral direction away from the p-n junction. This gives the active stripes between the trenches a largely tapered shape, which generates the same behavior as caused by a lateral doping gradient without the need to implant a graded doping profile.
  • the distance between the segments at the same lateral position of any of two neighboring trenches is as small as possible, but at least equals the shortest distance between the segment of one of said neighboring trenches and a neighboring segment of the other of said neighboring trenches, said neighboring segment having a lateral position further away from the p-n junction. It has been found that if this spacing relationship is obeyed, a very effective reduction in the peak electrical field across the semiconductor device is obtained.
  • the lateral dimension of the segments and the spacing between the segments of each trench preferably is as small as possible in a given technology to maximize the effect of the electrical field distribution.
  • the semiconductor device may be a diode or a device having a control terminal such as a gate or base, and may be a transistor such as a bipolar transistor or a MOSFET, a thyristor and so on.
  • the first region and the second region are of a first conductivity type, with the active region comprising a first further region separated from a second further region by the p-n junction, said first further region being located between the first region and the second further region.
  • the first region is a source region and the second region is a drain region
  • the active region comprises a channel region separated from a drain extension region by the p-n junction, said channel region being located between the source region and the drain extension region.
  • each trench terminates in the second further region, e.g. the drain extension region.
  • the second further region e.g. the drain extension region.
  • This may have several advantages. For instance, if the end portions facing the p-n junction terminate in the drain extension region at a predefined distance from the p-n junction, this has the advantage that thinning of an oxide layer over the first further region, e.g. the channel region caused by the overlap with the corners of said end portions is - A -
  • this embodiment yields a semiconductor device that has an improved lifetime if an oxide dielectric is used.
  • the dielectric layer e.g. a gate dielectric layer of a MOSFET, extends over the channel region and a part of the drain extension region, said gate dielectric layer comprising a void covering the trench ends facing the p-n junction.
  • the void ensures that overlap between the dielectric layer and the trench corners is avoided whereas the portion of the dielectric layer over the second further region, e.g. the drain extension region, allows for the formation of a dummy control terminal such as a dummy gate, which reduces the peak electrical field near the p-n junction due to the dummy terminal potential driving the current deeper into the semiconductor device, such that a further improvement in breakdown voltage as well as a reduction in hot carrier injection into the dielectric layer is obtained.
  • the end portions facing the second region may terminate in the second further region at a predefined further distance from the second region. This increases the amount of charge available near the second region, thus avoiding premature charge depletion in an on-state of the semiconductor device, thus reducing the electrical field near the second region. This provides a better safe- operating area and improves the on resistance (R 0n ) of the semiconductor device.
  • the semiconductor device of the present invention may be incorporated into an integrated circuit.
  • Such an IC benefits from the relatively small footprints of the semiconductor devices of the present invention, such that a high voltage portion of the IC can be realized whilst requiring limited silicon area, thus limiting the overall size and cost of the IC.
  • suitable applications include dc-dc converters, power management units and display drivers.
  • a method of manufacturing a semiconductor device comprising providing a substrate; providing a mask; applying said mask to form a plurality of segmented laterally extending trenches in a substrate region, said trenches defining a plurality of active stripes there between; implanting said substrate with respective doping profiles, thereby forming a first region and a second region on opposite sides of the substrate region such that the trenches laterally extend between the first region and the second region; and implanting a further doping profile in the substrate region, thus forming a p-n junction in the substrate, the depth of the trenches at least matching the depth of the further doping profile.
  • the steps of the method of the present invention ensure that a semiconductor device of the present invention may be obtained in a standard process using the same mask step to form both a shallow trench isolation around the semiconductor device as well as the segmented trenches.
  • Fig. 1 schematically depicts a semiconductor device according to an embodiment of the present invention
  • Fig. 2 shows a detail of a diode according to an embodiment of the present invention together with the respective electrical fields generated in this diode and a prior art diode;
  • Fig. 3 shows the electrical field profile of a prior art diode (left pane) and a diode according to an embodiment of the present invention (right pane);
  • FIG. 4 schematically depicts a semiconductor device according to another embodiment of the present invention
  • Fig. 5 schematically depicts a semiconductor device according to yet another embodiment of the present invention
  • Fig. 6 schematically depicts a prior art semiconductor device
  • Fig. 7 schematically depicts a semiconductor device according to a first further embodiment of the present invention
  • Fig. 8 schematically depicts a semiconductor device according to a second further embodiment of the present invention
  • Fig. 9 shows an electrical field profile of the semiconductor device of Fig. 8;
  • Fig. 10 schematically depicts a mask for use in an embodiment of the method of the present invention.
  • Fig.1 shows a first embodiment of a semiconductor device of the present invention.
  • the semiconductor device is a diode having a heavily doped n-type drain region 16, a heavily doped p-type source region 18, and an active region in between the source and drain regions defined by a p-type region 42 forming a p-n junction 24 with an n-type region comprising a plurality of active stripes 14.
  • the active stripes 14 are defined by a plurality of trenches filled with a suitable insulating material such as silicon oxide or another dielectric material e.g. silicon nitride.
  • Each segment 12 has a length D x and a width D y .
  • the spacing between neighboring segments 12 in the same lateral position, e.g. two neighboring segments 12i, defines the width W of the active stripes 14 in between the trenches.
  • the depth of each trench is at least equal, but preferably exceeds the depth of the doping profile of the active stripes 14 such that the insulating material in the trenches effectively insulates the active stripes 14 from each other.
  • the nearest distance between the corners of two laterally displaced segments in neighboring trenches, e.g. segment 12i in a first trench and segment 12 2 in a neighboring trench, as shown in Fig. 1 is defined as C.
  • the semiconductor device of the present invention is a modified version of the semiconductor device of WO2006/136979 such that the teachings of this PCT patent application are also applicable to the corresponding features of the semiconductor device of the present invention.
  • Fig. 2 a schematic representation of a semiconductor device, a p-n junction diode in this example, is given.
  • the semiconductor device comprises a shallow trench insulation segment 12 in the n-doped active region 14.
  • the effect of this segment is demonstrated in the right pane of Fig. 2, in which the electrical field generated by a voltage across the p-n terminals 16 and 18 is shown for a diode without a segmented shallow trench as well as for the diode of Fig. 2.
  • Fig. 3 shows a 2-D TCAD (technology computer aided design) simulation of a regular diode (left pane) and a diode comprising a segment 12 in its drain extension 14 (right pane). The reduced electrical field and enhanced depletion caused by the presence of the segment 12 is clearly visible in the right pane.
  • the device breakdown can further be controlled by the spacing in between the segments 12i -n . It has been found that in the direction perpendicular to the lateral drain extension, the spacing W should preferably be smaller than the I D- depletion width corresponding to breakdown voltage for the actual doping profile in the drain extension 14 to allow effective doping dilution in the active stripes. In the direction parallel to the drain extension, i.e. the lateral direction, the spacing A should be the smallest possible in a given technology, e.g. 0.14 micron CMOS, to maximize the influence of the electrical field distribution. For the same reason, the dimensions D x of the segments 12 should as small as possible, while the dimension D y is selected by the targeted breakdown voltage.
  • the segments 12 of the shallow trench insulation are spaced along the drain extension such that W is constant between all neighboring segments 12.
  • STI shallow trench insulation
  • Fig. 4 shows an alternative embodiment in which the width of the active stripes 14 increases towards the drain region 16.
  • W n+ i i.e. the width of an active stripe 14 between segments 12 n +i
  • W n i.e. the width of an active stripe 14 between segments 12 n
  • C n +i i.e. the shortest distance between a segment 12 n +i and a segment 12 n +2 of a neighboring STI
  • C n i.e. the shortest distance between a segment 12 n and a segment 12 n +i of a neighboring STI.
  • the active stripes 14 have an overall tapered shape, which emulates doping gradient and improves potential distribution across the drain extension region.
  • such a tapered profile reduces R 0n of the semiconductor device.
  • the device performance of the semiconductor device of the present invention may be further optimized.
  • the device performance may be optimized by ensuring that W, or W-i, and
  • C, or C-I i.e. the dimensions applicable to the segments nearest to the p-n junction 24, are smaller than the I D-depletion width at breakdown for the given doping concentration. This constraint is not applicable to the respective dimensions of the segments 12 that are further removed from the p-n junction 24. A further improvement in performance is obtained when D x and the spacing X between the segments 12 in the lateral direction is as small as possible in a given technology.
  • design rules may be considered when designing the trench segments 12: (i) The distance X, which is the distance between trench segments 12 along the drain extension should be as small as possible, and should not exceed the 1 D breakdown depletion width for the doping profile of the drain extension region; (ii) Both dimensions W and C must be smaller than 1 D breakdown depletion width for the doping profile of the drain extension region; (iii) D x should be as small as possible; and
  • (iv) Dy may be varied depending on the required breakdown capability.
  • Fig. 1 and 4 depict semiconductor devices in which the segmented trenches do not extend beyond the p-n junction 24 by way of non-limiting example only. Devices in which the segmented trenches extend into the p-type region 42 are equally feasible. Moreover, the segmented trenches may extend up to the drain region 16 such that the final segment 12 n may contact the drain region 16. Although Fig. 1 and 4 do not depict a shallow trench insulation (STI) surrounding the semiconductor device, it will be understood that such a STI may be present without departing from the teachings of the present invention. It is further reiterated that the present invention is not limited to diodes but may be applied to any semiconductor device comprising a p-n junction, such as a MOSFET or bipolar transistor.
  • STI shallow trench insulation
  • Fig. 5 depicts an embodiment of a transistor according to the present invention, wherein an n-type source region 18 and an n-type drain region 16 are present.
  • the channel region 42 is formed by a p-well and is separated from the drain region 16 by a drain extension region comprising active stripes 14 separated by insulating trenches, each trench comprising a plurality of segments 12- ⁇ -n.
  • the channel region 42 including the p-n junction 24 is covered by a gate (not shown) including a gate dielectric layer 20 that insulates the conductive gate terminal from the underlying channel region 42 and p-n junction 24.
  • the presence of the segments 12 redistributes the electrical field through the device as explained in the context of Fig. 2 and 3 such that the electrical field in the vicinity of the p-n junction 24 is reduced. This increases the breakdown voltage of the transistor, as previously explained.
  • the segmented lateral trenches extend into the channel region 42, as demonstrated by the segments 12i crossing the p-n junction 24 into the channel region 42. It is however pointed out that such an arrangement may cause more pronounced TDDB behavior if the gate dielectric layer 20 is a gate oxide, as will be explained in more detail with the aid of Fig. 6, in which a prior art semiconductor device is shown.
  • the prior art semiconductor device differs from the device in Fig. 5 in that it has unsegmented trenches 12.
  • Fig. 6 depicts cross sections of the prior art device along the lines A-A and B-B shown in Fig. 5.
  • the end portions of the shallow trenches of the prior art device are covered by the gate oxide 20, as can be seen along the line A-A, in which the gate oxide 20 separates the channel region 42 and the trench 12 from the conductive portion 25 of a gate 30. Consequently, the corners of the end portions of the shallow trenches 12 overlap with the gate oxide 20, as indicated by circles 22 in the view along the line B-B. This overlap suffers thinning of the gate oxide 20. This thinning increases the risk of the occurrence of TDDB effects, as previously explained.
  • Fig. 7 An embodiment of such a semiconductor device is shown in Fig. 7, in which the first segments 12i of the lateral shallow trenches terminate before they reach the gate dielectric layer 20, such that the shallow trenches are separated by a distance A from the p-n junction 24 formed by the p-well 42 and the doping implants in the drain extension region.
  • the gate dielectric layer 20 By avoiding an overlap of the gate dielectric layer 20 with the corners of the shallow trench segments 12i, thinning of the gate dielectric layer 20 such as a gate oxide layer is avoided, thereby ensuring that the semiconductor device has excellent TDDB lifetime.
  • the distance A does not exceed the width W of the active stripes 14. More preferably, the active width W does not exceed the 1 D depletion width limit, such that A ⁇ W ⁇ 1 D. If this relationship is obeyed in the layout of the semiconductor device of the present invention, the semiconductor device is capable of performing beyond the previously explained 1 D limit because it is guaranteed that the total amount of charge available in the drain extension region near the gate 30 can be depleted before a critical electrical field can develop in this location. This benefit is of course further amplified by the distribution of the electrical field as caused by the segmentation of the laterally extending trenches defining the active stripes 14.
  • the gate dielectric layer 20 comprises a void 56 separating a first gate dielectric region 52 from a second gate dielectric region 54 such that the corners of the first segments 12i of the shallow trenches 12 facing the p-n junction 24 are positioned under the void 56.
  • the first gate dielectric portion 52 acts as a dielectric for the gate 30 whereas the second dielectric portion 54 acts as the dielectric for a dummy gate extending over the shallow trenches and the active stripes 14.
  • the first gate dielectric portion 52 and the second dielectric portion 54 are interconnected.
  • the void 56 may extend across the full width of these portions such that the void 56 disconnects the first gate dielectric portion 52 from the second dielectric portion 54.
  • This embodiment has a number of advantages over the prior art.
  • the shallow trenches terminate under the void 56, there is no overlap between the corners of the segments 12i and the gate dielectric region 52, such that the gate 30 including the gate dielectric region 52 does not suffer from an increased risk of TDDB effect caused by the thinning of the gate dielectric, e.g. gate oxide, under the gate conductor 25.
  • the presence of the dummy gate relaxes the required alignment accuracy between the p-well 42 and the edges of the shallow trench segments 12i facing the p-well 42, which makes this embodiment better suitable for less advanced semiconductor technologies.
  • Fig. 9 In which the electrical field generated in a semiconductor device comprising a dummy gate (light line) is compared with the electrical field generated in a single gate device (dark line).
  • the solid arrow in Fig. 9 indicates the location of the p-n junction 24, whereas the dashed arrow indicates the location of the dummy gate. It is immediately apparent that the electrical field in the dummy gate semiconductor device in the vicinity of the p-n junction 24 is substantially smaller than in a single gate device, thus providing clear evidence of the better HCI reliability of such a dummy gate device.
  • the segmented trenches are terminated in the drain extension region close to the p-n junction 24.
  • a further benefit may be obtained by terminating the final segments 12 n of the insulating trenches at some distance from the drain region 16, e.g. as shown in Fig. 1 , i.e. the STI regions do not extend up to the heavily doped N+ drain region.
  • Such a configuration provides for an extra depletion charge near the drain, the amount of which is controlled by the distance B between the final segments 12 n and the drain region 16 for a given implantation. This allows for the suppression of the Kirk-effect in the semiconductor device, hence improving its safe-operating-area.
  • Fig. 7 and 8 depict active stripes 14 having a constant width W
  • embodiments in which the active stripes 14 have a tapered shape, e.g. as shown in Fig. 4, are equally feasible.
  • An advantage of the present invention is that the manufacturing of the semiconductor devices of the present invention may be achieved by a method of the present invention that is compatible with conventional manufacturing processes, thus maintaining the benefits of the method described in WO 2006/136979.
  • a substrate 40 may be provided, as well as a STI mask 60 as shown in Fig. 10.
  • the solid region 61 of the mask defines an active region of the finished device, which includes the source region 18, the drain region 16, the drain extension region including the active stripes 14 and the channel region 42.
  • the solid region 61 is surrounded by pattern elements 64 which are openings that define the location of the shallow trench surrounding the active region. Pattern elements 63 are openings that define the locations of the segments 12i -n of the shallow trenches defining the active stripes 14 in the finished device.
  • the location of the gate dielectric 20 over the channel region in the finished device is indicated by dashed box 62.
  • the gate dielectric 20 is formed over the channel region following the formation of the shallow trenches 12 and the various doping profiles in the substrate 40.
  • the STI patterning step which is standard in many semiconductor processes such as the Philips/NXP 0.25 micron, 180 nm, 120 nm and Crolles2 Alliance 90/65/45 nm CMOS processes, can be used to form both a shallow trench isolation around the active region of the semiconductor device and the laterally extending segmented trenches 12. After forming these trenches, processing may continue using the standard process to complete the device. As has been explained in WO 2006/136979 STI trenches are normally used to separate different semiconductor devices from each other.
  • shallow trenches 12 are used for a different purpose, namely to dilute the doping profile in an active region such as a drain extension region of a MOSFET.
  • the p-type region 42 may be manufactured using the standard mask and implant step normally used to implant the p-well.
  • the drain extension region cannot be manufactured using a normal n-well process, since the depth of that process is too deep.
  • the n-type region 14 is manufactured using the processing steps normally used to adjust the voltage threshold of p-type field effect transistors which implants n-type dopant to a depth of about 200 nm.
  • Contact regions of the source region 18 and the drain region 16 may be implanted using the standard steps used to implant contact regions.
  • a gate 30 comprising a conductive layer 25, e.g. metal, suicide or poly-Si separated from the channel region by a gate dielectric 20, is provided over the channel region 42.
  • the gate dielectric 20 may be a gate oxide or another suitable material, e.g. a high-k dielectric material.
  • the shallow trenches it is not necessary to fill the shallow trenches with oxide, or oxide alone, and other materials such as silicon nitride, or low doped (preferably undoped) polysilicon, and combinations thereof, may be used.
  • k 3.9 for silicon dioxide, 7.5 for silicon nitride, and 11.7 for low doped polysilicon.
  • the substrate 40 used need not be silicon and alternatives such as gallium arsenide, indium phosphide, gallium nitride and many others may also be used.
  • the semiconductor body can be a single crystal, a single crystal with an epi layer formed on top, or other technologies such as silicon on insulator, silicon on sapphire etc may also be used.
  • pn junction this is intended to include “p-i-n junctions” in which p-type material is separated from n- type material by intrinsic material, or lowly doped p- or n-type material. In such cases, the p-n junction and its depth are as defined by the whole p-i-n structure.
  • any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim.

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Abstract

The present invention discloses a semiconductor device comprising a first doped region (18), a second doped region (16) and a doped active region between the first region and the second region, the active region comprising a p- n junction (24); a plurality of laterally extending trenches (121; 122; 12n) filled with an insulating material, the depth of said trenches at least matching the depth of the doping profile in the active region, each of said trenches comprising a plurality of segments (121, 122, 12n) separated by portions of said active region; and a plurality of active stripes (14) separated by said trenches. The present invention further disclosed a method of manufacturing such a device.

Description

DESCRIPTION
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
SUCH A DEVICE
FIELD OF THE INVENTION
The present invention relates to a semiconductor device comprising a first doped region, a second doped region and a doped active region between the first region and the second region, the active region comprising a p-n junction, a plurality of laterally extending trenches filled with an insulating material, the depth of said trenches exceeding the depth of the doping profile in the active region, and a plurality of active stripes separated by said trenches.
The present invention further relates to a method of manufacturing such a device.
BACKGROUND OF THE INVENTION
In semiconductor devices including p-n junctions, including for example simple diodes as well as more complex devices such as field effect transistors, bipolar transistors or thyhstors, high doping levels reduce the series resistance. However, on the other hand, low doping levels allow high reverse voltages to be applied. There is a trade-off between these quantities, and the maximum achievable trade off for a simple diode is known as the 1 D silicon limit.
A number of structures are known that can deliver better results than the 1 D limit. Such structures are typically known as reduced surface field (RESURF) structures. Junction shaping, or field shaping using field plates or semi- insulating films can be used.
An alternative approach bridges the junction using a dielectric layers - EP 519 741 A2 is an example of this technique. However, these approaches all significantly add to the complexity of the manufacturing process and in particular they are not generally compatible with standard processes since they require additional mask and processing steps not present in the standard processes. There is a significant cost in adding such additional process steps.
A method for manufacturing such a RESURF device in a simplified manner has been disclosed in PCT patent publication WO2006/136979, which discloses a semiconductor device of the opening paragraph as well as a method of manufacturing such a device. However, for certain application domains, the breakdown voltages of these known devices may not suffice to warrant safe operation of an integrated circuit (IC) including such devices.
SUMMARY OF THE INVENTION
The present invention seeks to provide a semiconductor device exhibiting an improved breakdown voltage.
The present invention further seeks to provide a method of manufacturing a semiconductor device exhibiting an improved breakdown voltage.
According to an aspect of the present invention, there is provided a semiconductor device comprising a first doped region, a second doped region and a doped active region between the first region and the second region, the active region comprising a p-n junction; a plurality of laterally extending trenches filled with an insulating material, the depth of said trenches at least matching the depth of the doping profile in the active region, each of said trenches comprising a plurality of segments separated by portions of said active region; and a plurality of active stripes separated by said trenches.
It has been found that the segmentation of the trenches defining the active stripes in the active region of the semiconductor device reduces the peak electrical field across the semiconductor device, thus increasing the voltage at which the electrical field reaches its critical value at which the semiconductor device breaks down. In other words, the segmentation of the trenches increases the breakdown voltage of the semiconductor device. In an embodiment, each segment has a predetermined width, the respective widths of the segments of each trench decreasing in a lateral direction away from the p-n junction. This gives the active stripes between the trenches a largely tapered shape, which generates the same behavior as caused by a lateral doping gradient without the need to implant a graded doping profile.
Preferably, the distance between the segments at the same lateral position of any of two neighboring trenches is as small as possible, but at least equals the shortest distance between the segment of one of said neighboring trenches and a neighboring segment of the other of said neighboring trenches, said neighboring segment having a lateral position further away from the p-n junction. It has been found that if this spacing relationship is obeyed, a very effective reduction in the peak electrical field across the semiconductor device is obtained.
The lateral dimension of the segments and the spacing between the segments of each trench preferably is as small as possible in a given technology to maximize the effect of the electrical field distribution. The semiconductor device may be a diode or a device having a control terminal such as a gate or base, and may be a transistor such as a bipolar transistor or a MOSFET, a thyristor and so on. In an embodiment of such a device, the first region and the second region are of a first conductivity type, with the active region comprising a first further region separated from a second further region by the p-n junction, said first further region being located between the first region and the second further region.
In an embodiment, the first region is a source region and the second region is a drain region, and wherein the active region comprises a channel region separated from a drain extension region by the p-n junction, said channel region being located between the source region and the drain extension region.
Advantageously, at least one end portion of each trench terminates in the second further region, e.g. the drain extension region. This may have several advantages. For instance, if the end portions facing the p-n junction terminate in the drain extension region at a predefined distance from the p-n junction, this has the advantage that thinning of an oxide layer over the first further region, e.g. the channel region caused by the overlap with the corners of said end portions is - A -
avoided. Since such thinning can cause time-dependent dielectric breakdown (TDDB) effects, this embodiment yields a semiconductor device that has an improved lifetime if an oxide dielectric is used.
In an embodiment, the dielectric layer, e.g. a gate dielectric layer of a MOSFET, extends over the channel region and a part of the drain extension region, said gate dielectric layer comprising a void covering the trench ends facing the p-n junction. The void ensures that overlap between the dielectric layer and the trench corners is avoided whereas the portion of the dielectric layer over the second further region, e.g. the drain extension region, allows for the formation of a dummy control terminal such as a dummy gate, which reduces the peak electrical field near the p-n junction due to the dummy terminal potential driving the current deeper into the semiconductor device, such that a further improvement in breakdown voltage as well as a reduction in hot carrier injection into the dielectric layer is obtained. The end portions facing the second region may terminate in the second further region at a predefined further distance from the second region. This increases the amount of charge available near the second region, thus avoiding premature charge depletion in an on-state of the semiconductor device, thus reducing the electrical field near the second region. This provides a better safe- operating area and improves the on resistance (R0n) of the semiconductor device.
The semiconductor device of the present invention may be incorporated into an integrated circuit. Such an IC benefits from the relatively small footprints of the semiconductor devices of the present invention, such that a high voltage portion of the IC can be realized whilst requiring limited silicon area, thus limiting the overall size and cost of the IC. Non-limiting examples of suitable applications include dc-dc converters, power management units and display drivers.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising providing a substrate; providing a mask; applying said mask to form a plurality of segmented laterally extending trenches in a substrate region, said trenches defining a plurality of active stripes there between; implanting said substrate with respective doping profiles, thereby forming a first region and a second region on opposite sides of the substrate region such that the trenches laterally extend between the first region and the second region; and implanting a further doping profile in the substrate region, thus forming a p-n junction in the substrate, the depth of the trenches at least matching the depth of the further doping profile.
The steps of the method of the present invention, which may be executed in any suitable order, ensure that a semiconductor device of the present invention may be obtained in a standard process using the same mask step to form both a shallow trench isolation around the semiconductor device as well as the segmented trenches.
BRIEF DESCRIPTION OF THE EMBODIMENTS
Embodiments of the invention are described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein
Fig. 1 schematically depicts a semiconductor device according to an embodiment of the present invention;
Fig. 2 shows a detail of a diode according to an embodiment of the present invention together with the respective electrical fields generated in this diode and a prior art diode;
Fig. 3 shows the electrical field profile of a prior art diode (left pane) and a diode according to an embodiment of the present invention (right pane);
Fig. 4 schematically depicts a semiconductor device according to another embodiment of the present invention; Fig. 5 schematically depicts a semiconductor device according to yet another embodiment of the present invention;
Fig. 6 schematically depicts a prior art semiconductor device; Fig. 7 schematically depicts a semiconductor device according to a first further embodiment of the present invention; Fig. 8 schematically depicts a semiconductor device according to a second further embodiment of the present invention; Fig. 9 shows an electrical field profile of the semiconductor device of Fig. 8; and
Fig. 10 schematically depicts a mask for use in an embodiment of the method of the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts. Fig.1 shows a first embodiment of a semiconductor device of the present invention. In this embodiment, the semiconductor device is a diode having a heavily doped n-type drain region 16, a heavily doped p-type source region 18, and an active region in between the source and drain regions defined by a p-type region 42 forming a p-n junction 24 with an n-type region comprising a plurality of active stripes 14. The active stripes 14 are defined by a plurality of trenches filled with a suitable insulating material such as silicon oxide or another dielectric material e.g. silicon nitride.
Each trench is formed of n segments 12, with n being an integer having a value of at least two. In Fig. 1 , n=3 by way of non-limiting example only. Each segment 12 has a length Dx and a width Dy. The spacing between neighboring segments 12 in the same lateral position, e.g. two neighboring segments 12i, defines the width W of the active stripes 14 in between the trenches. The depth of each trench is at least equal, but preferably exceeds the depth of the doping profile of the active stripes 14 such that the insulating material in the trenches effectively insulates the active stripes 14 from each other. The nearest distance between the corners of two laterally displaced segments in neighboring trenches, e.g. segment 12i in a first trench and segment 122 in a neighboring trench, as shown in Fig. 1 , is defined as C.
It will be appreciated that the semiconductor device of the present invention is a modified version of the semiconductor device of WO2006/136979 such that the teachings of this PCT patent application are also applicable to the corresponding features of the semiconductor device of the present invention.
The effect of the segmentation of the lateral trenches will be explained in more detail with the aid of Fig. 2. In the left pane of Fig. 2, a schematic representation of a semiconductor device, a p-n junction diode in this example, is given. The semiconductor device comprises a shallow trench insulation segment 12 in the n-doped active region 14. The effect of this segment is demonstrated in the right pane of Fig. 2, in which the electrical field generated by a voltage across the p-n terminals 16 and 18 is shown for a diode without a segmented shallow trench as well as for the diode of Fig. 2.
It will be immediately apparent from the generated electrical fields that the presence of the segment 12 causes a redistribution of the electrical field away from the p-n junction 24, and a more homogeneous distribution of the electrical field through the active region of the diode. This is explained as follows. The segments 12 impact the usual triangular electrical field, so that an additional peak field appears instead of just a tailing electrical field. This effect can be repeated by inserting multiple segments 12 along the drain extension with an appropriate spacing. The resulting profile contributes to a significant increase of the breakdown voltage of the device. Fig. 3 shows a 2-D TCAD (technology computer aided design) simulation of a regular diode (left pane) and a diode comprising a segment 12 in its drain extension 14 (right pane). The reduced electrical field and enhanced depletion caused by the presence of the segment 12 is clearly visible in the right pane.
The device breakdown can further be controlled by the spacing in between the segments 12i-n. It has been found that in the direction perpendicular to the lateral drain extension, the spacing W should preferably be smaller than the I D- depletion width corresponding to breakdown voltage for the actual doping profile in the drain extension 14 to allow effective doping dilution in the active stripes. In the direction parallel to the drain extension, i.e. the lateral direction, the spacing A should be the smallest possible in a given technology, e.g. 0.14 micron CMOS, to maximize the influence of the electrical field distribution. For the same reason, the dimensions Dx of the segments 12 should as small as possible, while the dimension Dy is selected by the targeted breakdown voltage.
In the embodiment shown in Fig. 1 , the segments 12 of the shallow trench insulation (STI) are spaced along the drain extension such that W is constant between all neighboring segments 12. However, it should be understood that other arrangements are also feasible.
Fig. 4 shows an alternative embodiment in which the width of the active stripes 14 increases towards the drain region 16. In other words, Wn+i (i.e. the width of an active stripe 14 between segments 12n+i) is larger than Wn (i.e. the width of an active stripe 14 between segments 12n), and Cn+i (i.e. the shortest distance between a segment 12n+i and a segment 12n+2 of a neighboring STI) is larger than Cn (i.e. the shortest distance between a segment 12n and a segment 12n+i of a neighboring STI). In this embodiment, the active stripes 14 have an overall tapered shape, which emulates doping gradient and improves potential distribution across the drain extension region. In addition, such a tapered profile reduces R0n of the semiconductor device.
The device performance of the semiconductor device of the present invention may be further optimized. Considering that the effective doping in the active stripes 14 is governed by: effective doping = DOSE x Dy/(W+Dy) in case of a semiconductor device having active stripes with a constant width W, and effective dopingn = DOSE x Dy,n/(Wn+Dy,n) in case of a semiconductor device having tapered active stripes 14, wherin DOSE is the dopant dosage to which the drain extension region is exposed. The device performance may be optimized by ensuring that W, or W-i, and
C, or C-I, i.e. the dimensions applicable to the segments nearest to the p-n junction 24, are smaller than the I D-depletion width at breakdown for the given doping concentration. This constraint is not applicable to the respective dimensions of the segments 12 that are further removed from the p-n junction 24. A further improvement in performance is obtained when Dx and the spacing X between the segments 12 in the lateral direction is as small as possible in a given technology.
In summary, one or more of the following design rules may be considered when designing the trench segments 12: (i) The distance X, which is the distance between trench segments 12 along the drain extension should be as small as possible, and should not exceed the 1 D breakdown depletion width for the doping profile of the drain extension region; (ii) Both dimensions W and C must be smaller than 1 D breakdown depletion width for the doping profile of the drain extension region; (iii) Dx should be as small as possible; and
(iv) Dy may be varied depending on the required breakdown capability.
At this point, it is noted that Fig. 1 and 4 depict semiconductor devices in which the segmented trenches do not extend beyond the p-n junction 24 by way of non-limiting example only. Devices in which the segmented trenches extend into the p-type region 42 are equally feasible. Moreover, the segmented trenches may extend up to the drain region 16 such that the final segment 12n may contact the drain region 16. Although Fig. 1 and 4 do not depict a shallow trench insulation (STI) surrounding the semiconductor device, it will be understood that such a STI may be present without departing from the teachings of the present invention. It is further reiterated that the present invention is not limited to diodes but may be applied to any semiconductor device comprising a p-n junction, such as a MOSFET or bipolar transistor.
Fig. 5 depicts an embodiment of a transistor according to the present invention, wherein an n-type source region 18 and an n-type drain region 16 are present. The channel region 42 is formed by a p-well and is separated from the drain region 16 by a drain extension region comprising active stripes 14 separated by insulating trenches, each trench comprising a plurality of segments 12-ι-n. The channel region 42 including the p-n junction 24 is covered by a gate (not shown) including a gate dielectric layer 20 that insulates the conductive gate terminal from the underlying channel region 42 and p-n junction 24. The presence of the segments 12 redistributes the electrical field through the device as explained in the context of Fig. 2 and 3 such that the electrical field in the vicinity of the p-n junction 24 is reduced. This increases the breakdown voltage of the transistor, as previously explained.
As shown in Fig. 5, the segmented lateral trenches extend into the channel region 42, as demonstrated by the segments 12i crossing the p-n junction 24 into the channel region 42. It is however pointed out that such an arrangement may cause more pronounced TDDB behavior if the gate dielectric layer 20 is a gate oxide, as will be explained in more detail with the aid of Fig. 6, in which a prior art semiconductor device is shown. The prior art semiconductor device differs from the device in Fig. 5 in that it has unsegmented trenches 12. Fig. 6 depicts cross sections of the prior art device along the lines A-A and B-B shown in Fig. 5.
The end portions of the shallow trenches of the prior art device are covered by the gate oxide 20, as can be seen along the line A-A, in which the gate oxide 20 separates the channel region 42 and the trench 12 from the conductive portion 25 of a gate 30. Consequently, the corners of the end portions of the shallow trenches 12 overlap with the gate oxide 20, as indicated by circles 22 in the view along the line B-B. This overlap suffers thinning of the gate oxide 20. This thinning increases the risk of the occurrence of TDDB effects, as previously explained.
This may be remedied by ensuring that the segments 12i terminate in the drain extension region, such that an overlap between the gate dielectric layer 20 and the corners of the segments 12i is avoided. An embodiment of such a semiconductor device is shown in Fig. 7, in which the first segments 12i of the lateral shallow trenches terminate before they reach the gate dielectric layer 20, such that the shallow trenches are separated by a distance A from the p-n junction 24 formed by the p-well 42 and the doping implants in the drain extension region.
By avoiding an overlap of the gate dielectric layer 20 with the corners of the shallow trench segments 12i, thinning of the gate dielectric layer 20 such as a gate oxide layer is avoided, thereby ensuring that the semiconductor device has excellent TDDB lifetime.
In a preferred embodiment, the distance A does not exceed the width W of the active stripes 14. More preferably, the active width W does not exceed the 1 D depletion width limit, such that A < W < 1 D. If this relationship is obeyed in the layout of the semiconductor device of the present invention, the semiconductor device is capable of performing beyond the previously explained 1 D limit because it is guaranteed that the total amount of charge available in the drain extension region near the gate 30 can be depleted before a critical electrical field can develop in this location. This benefit is of course further amplified by the distribution of the electrical field as caused by the segmentation of the laterally extending trenches defining the active stripes 14.
In an alternative embodiment shown in Fig. 8, the gate dielectric layer 20 comprises a void 56 separating a first gate dielectric region 52 from a second gate dielectric region 54 such that the corners of the first segments 12i of the shallow trenches 12 facing the p-n junction 24 are positioned under the void 56. The first gate dielectric portion 52 acts as a dielectric for the gate 30 whereas the second dielectric portion 54 acts as the dielectric for a dummy gate extending over the shallow trenches and the active stripes 14. In Fig. 8, the first gate dielectric portion 52 and the second dielectric portion 54 are interconnected. However, it is emphasized that the void 56 may extend across the full width of these portions such that the void 56 disconnects the first gate dielectric portion 52 from the second dielectric portion 54.
This embodiment has a number of advantages over the prior art. First of all, due to the fact that the shallow trenches terminate under the void 56, there is no overlap between the corners of the segments 12i and the gate dielectric region 52, such that the gate 30 including the gate dielectric region 52 does not suffer from an increased risk of TDDB effect caused by the thinning of the gate dielectric, e.g. gate oxide, under the gate conductor 25. In addition, the presence of the dummy gate relaxes the required alignment accuracy between the p-well 42 and the edges of the shallow trench segments 12i facing the p-well 42, which makes this embodiment better suitable for less advanced semiconductor technologies.
In addition, the presence of a dummy gate forces the current flow near the gate 30 deeper into the substrate 40, and causes the electrical field near the gate 30 to be reduced compared to a single gate device. This has the advantage that the risk of hot carrier injection (HCI) into the gate dielectric region 52 is further reduced in addition to the beneficial effect of the segmentation of the lateral shallow trenches.
This is further demonstrated in Fig. 9, in which the electrical field generated in a semiconductor device comprising a dummy gate (light line) is compared with the electrical field generated in a single gate device (dark line). The solid arrow in Fig. 9 indicates the location of the p-n junction 24, whereas the dashed arrow indicates the location of the dummy gate. It is immediately apparent that the electrical field in the dummy gate semiconductor device in the vicinity of the p-n junction 24 is substantially smaller than in a single gate device, thus providing clear evidence of the better HCI reliability of such a dummy gate device.
In the embodiments of the semiconductor device shown in Fig. 7 and 8, the segmented trenches are terminated in the drain extension region close to the p-n junction 24. However, it is pointed out that a further benefit may be obtained by terminating the final segments 12n of the insulating trenches at some distance from the drain region 16, e.g. as shown in Fig. 1 , i.e. the STI regions do not extend up to the heavily doped N+ drain region. Such a configuration provides for an extra depletion charge near the drain, the amount of which is controlled by the distance B between the final segments 12n and the drain region 16 for a given implantation. This allows for the suppression of the Kirk-effect in the semiconductor device, hence improving its safe-operating-area.
This may be explained as follows. At high Vds in the device on-state (high Vg8), the additional charge originating from the flowing current results in redistribution of potential and a shift of the electrical field towards drain. This effect can be remedied by an increasing doping near the drain. This adds more positive charge in the depletion region that compensates the moving charge in on-state conditions. Previously, the implementation of such an increasing doping towards the drain would require an additional implant/mask step in the manufacturing process of such a semiconductor device. However, in the present invention, the same effect is achieved by terminating the segmented trenches short of the drain region 16, thus avoiding the need for an additional implant/mask step.
It will be understood that although Fig. 7 and 8 depict active stripes 14 having a constant width W, embodiments in which the active stripes 14 have a tapered shape, e.g. as shown in Fig. 4, are equally feasible.
An advantage of the present invention is that the manufacturing of the semiconductor devices of the present invention may be achieved by a method of the present invention that is compatible with conventional manufacturing processes, thus maintaining the benefits of the method described in WO 2006/136979.
In accordance with an embodiment of the present invention, a substrate 40 may be provided, as well as a STI mask 60 as shown in Fig. 10. The solid region 61 of the mask defines an active region of the finished device, which includes the source region 18, the drain region 16, the drain extension region including the active stripes 14 and the channel region 42. The solid region 61 is surrounded by pattern elements 64 which are openings that define the location of the shallow trench surrounding the active region. Pattern elements 63 are openings that define the locations of the segments 12i-n of the shallow trenches defining the active stripes 14 in the finished device. The location of the gate dielectric 20 over the channel region in the finished device is indicated by dashed box 62. The gate dielectric 20 is formed over the channel region following the formation of the shallow trenches 12 and the various doping profiles in the substrate 40.
The presence of the pattern elements 64 and the pattern elements 63 in a single mask 60 means that the STI patterning step, which is standard in many semiconductor processes such as the Philips/NXP 0.25 micron, 180 nm, 120 nm and Crolles2 Alliance 90/65/45 nm CMOS processes, can be used to form both a shallow trench isolation around the active region of the semiconductor device and the laterally extending segmented trenches 12. After forming these trenches, processing may continue using the standard process to complete the device. As has been explained in WO 2006/136979 STI trenches are normally used to separate different semiconductor devices from each other. However, as taught by WO 2006/136979 and the present invention, shallow trenches 12 are used for a different purpose, namely to dilute the doping profile in an active region such as a drain extension region of a MOSFET. The p-type region 42 may be manufactured using the standard mask and implant step normally used to implant the p-well. The drain extension region cannot be manufactured using a normal n-well process, since the depth of that process is too deep. Accordingly, the n-type region 14 is manufactured using the processing steps normally used to adjust the voltage threshold of p-type field effect transistors which implants n-type dopant to a depth of about 200 nm. Contact regions of the source region 18 and the drain region 16 may be implanted using the standard steps used to implant contact regions. A gate 30 comprising a conductive layer 25, e.g. metal, suicide or poly-Si separated from the channel region by a gate dielectric 20, is provided over the channel region 42. The gate dielectric 20 may be a gate oxide or another suitable material, e.g. a high-k dielectric material.
Those skilled in the art will appreciate that many modifications to the processes described in the specific embodiment are possible. For example, it is not necessary to fill the shallow trenches with oxide, or oxide alone, and other materials such as silicon nitride, or low doped (preferably undoped) polysilicon, and combinations thereof, may be used. Such materials can have a lower or a higher dielectric constant k than silicon dioxide (k= 3.9 for silicon dioxide, 7.5 for silicon nitride, and 11.7 for low doped polysilicon). In such case, only the laterally extending trenches 12 are filled with the dielectric material having a different dielectric constant, while the shallow trenches 10 are filled with the standard insulator. The substrate 40 used need not be silicon and alternatives such as gallium arsenide, indium phosphide, gallium nitride and many others may also be used.
Although the embodiments of the semiconductor device of the present invention use a p-type channel region and n-type source and drain, it will be appreciated that the invention is just as applicable to a device using an n-type channel, and/or p-type sources and drains. The semiconductor body can be a single crystal, a single crystal with an epi layer formed on top, or other technologies such as silicon on insulator, silicon on sapphire etc may also be used.
Although the description and claims use the term "pn junction", this is intended to include "p-i-n junctions" in which p-type material is separated from n- type material by intrinsic material, or lowly doped p- or n-type material. In such cases, the p-n junction and its depth are as defined by the whole p-i-n structure. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A semiconductor device comprising a first doped region (18), a second doped region (16) and a doped active region between the first region and the second region, the active region comprising: a p-n junction (24); a plurality of laterally extending trenches (12-ι; 122; 12n) filled with an insulating material, the depth of said trenches at least matching the depth of the doping profile in the active region, each of said trenches comprising a plurality of segments (12i, 122, 12n) separated by portions of said active region; and a plurality of active stripes (14) separated by said trenches.
2. The semiconductor device of claim 1 , wherein each segment (12-ι, 122, 12n) has a constant length (Dx) and constant width (Dy), the respective widths of the segments of each trench decreasing in a lateral direction away from the p-n junction (24).
3. The semiconductor device of claim 2, wherein the distance (Wn+i) between the segments (12i, 122, 12n) at the same lateral position of any of two neighboring trenches at least equals the shortest distance (Cn) between the segment of one of said neighboring trenches and a neighboring segment of the other of said neighboring trenches, said neighboring segment having a lateral position further away from the p-n junction
4. The semiconductor device of any of claims 1-3, wherein the lateral dimension (Dx) of the segments (12-ι, 122, 12n) and the spacing between the segments of each trench is as small as possible in a given technology.
5. The semiconductor device of any of claims 1-4, wherein the first doped region (18) and the second doped region (16) have opposite type dopants.
6. The semiconductor device of any of claims 1-4, wherein the first region and the second region are of a first conductivity type and wherein the active region comprises a first further region (42) separated from a second further region by the p-n junction (24), said first further region being located between the first region and the second further region.
7. The semiconductor device of claim 6, wherein the first region is a source region (16), the second region is a drain region (18), the first further region is a channel region (42) and the second further region is a drain extension region.
8. The semiconductor device of claim 6 or 7, wherein at least one end portion of each trench terminates in the second further region.
9. The semiconductor device of claim 8, wherein the end portions facing the p-n junction (24) terminate in the second further region at a predefined distance from the p-n junction (24).
10. The semiconductor device of claim 9, further comprising a control terminal (30) having a conductive portion (25) separated from the first further region by a dielectric layer (20), said dielectric layer not covering the trench ends facing the p-n junction (24).
11. The semiconductor device of claim 10, wherein the dielectric layer (20) extends over the first further region and a part of the second further region, said dielectric layer comprising a void (56) covering the trench ends facing the p-n junction (24).
12. The semiconductor device of any of claims 8-11 , wherein the end portions facing the second region terminate in the second further region at a predefined further distance from the second region (16).
13. An integrated circuit comprising the semiconductor device of any of claims 1-12.
14. A method of manufacturing a semiconductor device, comprising: providing a substrate (40); providing a mask (60); applying said mask (60) to form a plurality of segmented laterally extending trenches (12i; 122; 12n) in a substrate region, said trenches defining a plurality of active stripes (14) there between; implanting said substrate (40) with respective doping profiles, thereby forming a first region (18) and a second region (16) on opposite sides of the substrate region such that the trenches (12i; 122; 12n) laterally extend between the first region (18) and the second region (16); and implanting a further doping profile in the substrate region, thus forming a p-n junction (24) in the substrate, the depth of the trenches at least matching the depth of the further doping profile.
15. The method of claim 14, wherein each segment (12-ι, 122, 12n) has a constant length (Dx) and a constant width (Dy), the respective widths of the segments of each trench decreasing in a lateral direction away from the p-n junction (24).
PCT/IB2009/054362 2008-10-20 2009-10-06 Semiconductor device and method of manufacturing such a device WO2010046795A1 (en)

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US8373227B2 (en) 2008-10-20 2013-02-12 Nxp B.V. Semiconductor device and method having trenches in a drain extension region
JP2013069777A (en) * 2011-09-21 2013-04-18 Lapis Semiconductor Co Ltd Semiconductor device and manufacturing method of the same
JP2013532382A (en) * 2010-06-17 2013-08-15 日本テキサス・インスツルメンツ株式会社 High voltage transistor with thinned drain
JP2016192479A (en) * 2015-03-31 2016-11-10 ラピスセミコンダクタ株式会社 Semiconductor device and method for manufacturing the same
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US8373227B2 (en) 2008-10-20 2013-02-12 Nxp B.V. Semiconductor device and method having trenches in a drain extension region
JP2013532382A (en) * 2010-06-17 2013-08-15 日本テキサス・インスツルメンツ株式会社 High voltage transistor with thinned drain
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