TWI555120B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI555120B
TWI555120B TW103135549A TW103135549A TWI555120B TW I555120 B TWI555120 B TW I555120B TW 103135549 A TW103135549 A TW 103135549A TW 103135549 A TW103135549 A TW 103135549A TW I555120 B TWI555120 B TW I555120B
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sidewall
gate
gate structure
layer
shallow trench
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TW103135549A
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TW201614765A (en
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朱建隆
陳俊宏
邱達乾
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力晶科技股份有限公司
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Priority to TW103135549A priority Critical patent/TWI555120B/zh
Priority to CN201510008095.6A priority patent/CN105826378B/zh
Priority to US14/602,283 priority patent/US9397183B2/en
Publication of TW201614765A publication Critical patent/TW201614765A/zh
Priority to US15/175,008 priority patent/US9620368B2/en
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Publication of TWI555120B publication Critical patent/TWI555120B/zh

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Description

半導體元件及其製作方法
本發明是關於一種半導體元件，尤指一種非揮發性記憶體及其製作方法。
快閃記憶體(flash memory)係一種非揮發性(non-volatile)記憶體，其在缺乏外部電源供應時，亦能夠保存儲存在記憶體中的資訊內容。近幾年來，由於快閃記憶體具有可重複寫入以及可被電抹除等優點，因此，已被廣泛地應用在行動電話(mobile phone)、數位相機(digital camera)、遊戲機(video player)、個人數位助理(personal digital assistant,PDA)等電子產品或正在發展中的系統單晶片(system on a chip,SOC)中。
一般而言，現今快閃記憶體架構中由於閘極主動面積(active area)的設計，特別是在大面積的情況下時常影響記憶體的整體效能。因此如何藉由改變製程來改良現有記憶體架構以提升快閃記憶體的整體效能即為現今一重要課題。
本發明較佳實施例是揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一第一閘極層、一第一介電層以及一淺溝隔離(shallow trench isolation,STI)環繞該基底、該第一閘極層 及該第一介電層。然後去除該第一介電層、形成一第一側壁子於第一閘極層上方之淺溝隔離側壁以及利用第一側壁子為遮罩去除部分第一閘極層及部分基底以形成一第一開口並同時定義出一第一閘極結構及一第二閘極結構。
本發明另一實施例揭露一種半導體元件，其包含一基底、一第一閘極結構與一第二閘極結構設於基底上、一側壁子設於部分基底中以及第一閘極結構與第二閘極結構之間、一淺溝隔離設於第一閘極結構與第二閘極結構周圍以及一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層設於淺溝隔離、側壁子、第一閘極結構及第二閘極結構上。
本發明又一實施例揭露一種半導體元件，包含一基底、一第一閘極結構與一第二閘極結構設於基底上、一淺溝隔離設於第一閘極結構與第二閘極結構周圍、一介電層設於第一閘極結構與第二閘極結構之間以及部分基底中，且介電層之上表面低於淺溝隔離之上表面以及一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層設於淺溝隔離、介電層、第一閘極結構及第二閘極結構上。
12‧‧‧基底
14‧‧‧記憶體單元區
16‧‧‧周邊區
18‧‧‧閘極介電層
20‧‧‧第一閘極層
22‧‧‧第二閘極層
24‧‧‧介電層
26‧‧‧介電層
28‧‧‧淺溝隔離
30‧‧‧側壁子
32‧‧‧圖案化光阻
34‧‧‧開口
36‧‧‧第一閘極結構
38‧‧‧第三閘極結構
40‧‧‧第二閘極結構
42‧‧‧第四閘極結構
44‧‧‧側壁子
46‧‧‧側壁子
48‧‧‧圖案化光阻
50‧‧‧氧化物-氮化物-氧化物堆疊層
52‧‧‧介電層
54‧‧‧側壁子
56‧‧‧開口
58‧‧‧介電層
60‧‧‧多晶矽閘極
第1圖至第7圖為本發明較佳實施例製作半導體元件的方法示意圖。
第8圖至第9圖為本發明第二實施例製作一半導體元件之方法示意圖。
第10圖至第11圖為本發明第三實施例製作一半導體元件之方法示意圖。
第12圖至第15圖為本發明第四實施例製作一半導體元件之方法示 意圖。
請參照第1圖至第7圖，第1圖至第7圖為本發明較佳實施例製作半導體元件的方法示意圖。如第1圖所示，首先提供一基底12，且基底12上定義有一記憶體單元區14與一周邊區(periphery region)16。記憶體單元區14與周邊區16上各具有一閘極介電層18、一第一閘極層20設於閘極介電層18上、一第二閘極層22設於第一閘極層20上、一介電層24設於第二閘極層22上、另一介電層26設於記憶體單元區14的介電層24與第二閘極層22之間以及一淺溝隔離(shallow trench isolation,STI)28設於部分基底12內並環繞閘極介電層18、第一閘極層20、第二閘極層22、介電層24及介電層26。
在本實施例中，閘極介電層18、介電層26與淺溝隔離28較佳由氧化矽所構成，第一閘極層20較佳由不摻雜之多晶矽所構成，第二閘極層22較佳由摻雜之多晶矽所構成，而介電層24較佳由氮化矽所構成，但不侷限於此。而施作方式，可例如先於基底12表面依序全面性形成一閘極介電材料層(圖未示)、一第一閘極材料層(圖未示)、一第二閘極材料層(圖未示)、一介電材料層(圖未示)、另一介電材料層(圖未示)，接著利用一蝕刻製程來圖案化各材料層以於部分基底12內形成淺溝隔離(shallow trench)(圖未示)，最後再填入一介電材料(圖未示)並加以平坦化之，但亦不侷限於此。
如第2圖所示，接著完全去除記憶體單元區14及周邊區16的介電層24與介電層26，然後於記憶體單元區14及周邊區16 內分別形成一側壁子30於各第二閘極層22上方的淺溝隔離28側壁。在本實施例中，形成側壁子30的方法可先沉積一由氮化矽所構成的介電材料(圖未示)於淺溝隔離28與第二閘極層22上，然後進行一回蝕刻製程，去除部分該介電材料以形成側壁子30。
如第3圖所示，隨後先形成一圖案化光阻32並覆蓋周邊區16，然後利用圖案化光阻32及記憶體單元區14的側壁子30為遮罩進行一蝕刻製程，去除記憶體單元區14內部分第二閘極層22、部分第一閘極層20、部分閘極介電層18及部分基底12以形成一開口34。在本實施例中，形成開口34的動作較佳將第一閘極層20與第二閘極層22同時分割為左右兩邊，並藉此定義出兩組浮動閘極(floating gate)結構，包括左邊的第一閘極結構36與設於其上的第三閘極結構38以及右邊的第二閘極結構40與設於其上的第四閘極結構42。另外，開口34由閘極介電層18底部至開口34底部的距離較佳介於1000埃至1500埃，且開口34的底部較佳切齊淺溝隔離28的底部。
然後如第4圖所示，先去除周邊區16的圖案化光阻32，接著可沉積一由氧化矽所構成的介電層(圖未示)於記憶體單元區14及周邊區16並搭配進行一回蝕刻製程，以於記憶體單元區14的開口34底部形成一側壁子44，並同時於周邊區16的側壁子30旁形成側壁子44。需注意的是，形成側壁子44之前又可選擇性進行一氧化(oxidation)製程，以形成另一薄氧化層於記憶體單元區14及周邊區16，此實施例也屬本發明所涵蓋的範圍。隨後再進行另一沉積與回蝕刻製程，例如沉積一由氮化矽所構成的介電層(圖未示)於記憶體單元區14及周邊區16並搭配進行一回蝕刻製程，以於記憶體 單元區14的側壁子44上形成一另一側壁子46，並同時於周邊區16的側壁子44旁形成側壁子46。
隨後如第5圖所示，先形成一圖案化光阻48並覆蓋周邊區16，接著以圖案化光阻48為遮罩進行一乾蝕刻或濕蝕刻製程，去除部分記憶體單元區14的淺溝隔離28，使剩餘之淺溝隔離28上表面較佳介於第三閘極結構38(等同於第四閘極結構42)的上下表面之間。
之後如第6圖所示，先去除周邊區16的圖案化光阻48並進行一蝕刻製程，例如以濕蝕刻方式去除周邊區16由氧化矽所構成的側壁子44。緊接著進行另一蝕刻製程，例如以乾蝕刻或濕蝕刻完全去除記憶體單元區14與周邊區16由氮化矽所構成的側壁子46與側壁子30，進而暴露出記憶體單元區14底部的側壁子44及第三閘極結構38與第四閘極結構42上表面。
然後如第7圖所示，先以濕蝕刻去除部分第三閘極結構38與第四閘極結構42側壁以形成一傾斜面，接著再全面性形成一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層50於記憶體單元區14的淺溝隔離28、側壁子44、第三閘極結構38及第四閘極結構42上與周邊區16的淺溝隔離28及第二閘極層22上，至此即完成本發明較佳實施例製作一半導體元件的方法。
請再參照第7圖之記憶體單元區14，其另揭露一種記憶體元件結構。其中記憶體元件主要包含一基底12、一第一閘極結構36與一第二閘極結構40設於基底12上、一第三閘極結構38與一 第四閘極結構42分別設於第一閘極結構36與第二閘極結構40上、一側壁子44設於部分基底12中以及第一閘極結構36與第二閘極結構40之間、一淺溝隔離28設於基底12中並環繞第一閘極結構36與第二閘極結構40以及一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層50設於淺溝隔離28、側壁子44、第三閘極結構38及第四閘極結構42上。
在本實施例中，側壁子44底部較佳與淺溝隔離28底部齊平，第一閘極結構36與第二閘極結構40較佳包含不摻雜之多晶矽，而第三閘極結構38與第四閘極結構42則包含摻雜之多晶矽，但不侷限於此。
請繼續參照第8圖至第9圖，第8圖至第9圖為本發明第二實施例製作一半導體元件之方法示意圖，其中第二實施例原則上係變更記憶體單元區14之製程步驟，而不影響周邊區16最終結構，因此圖示僅繪示記憶體單元區14之製程步驟但不包含周邊區16之相關製程細節。如第8圖所示，首先進行前述實施例中第1圖至第3圖於記憶體單元區之製程，例如以記憶體單元區14的側壁子30為遮罩形成一開口34並將第一閘極層20與第二閘極層22同時分割為兩組閘極結構後，形成一介電層52並填滿開口34，其中介電層52較佳由氧化矽所構成。接著利用化學機械研磨(chemical mechanical polishing,CMP)製程等平坦化方式或蝕刻製程去除部分淺溝隔離28、部分介電層52及部分側壁子30，使淺溝隔離28與剩餘的介電層52與側壁子30表面齊平。
然後如第9圖所示，進行一蝕刻製程，去除由氧化矽所構 成的部分淺溝隔離28與部分介電層52，使剩餘的淺溝隔離28上表面約略介於第三閘極結構38以及第四閘極結構42的上表面與下表面之間，而剩餘的介電層52上表面則略低於第三閘極結構38以及第四閘極結構42的下表面。在本實施例中，剩餘的介電層52上表面較佳低於淺溝隔離28的上表面，且低於淺溝隔離的高度則可示製程需求調整，此為本發明所涵蓋的範圍。接著進行另一蝕刻製程，去除由氮化矽所構成的側壁子30並暴露出第三閘極結構38與第四閘極結構42表面，之後再全面性形成一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層50於淺溝隔離28、介電層52、第三閘極結構38及第四閘極結構42上。
請繼續參照第10圖至第11圖，第10圖至第11圖為本發明第三實施例製作一半導體元件之方法示意圖。如前述之實施例，本實施例同樣僅繪示記憶體單元區14之製程步驟但不包含周邊區16之相關製程細節。如第10圖所示，首先進行前述實施例中第1圖至第2圖於記憶體單元區14之製程，例如於記憶體單元區14形成一側壁子54於第一閘極層20上方之淺溝隔離28側壁。需注意的是，由於本實施例僅採用單一閘極層，較佳由不摻雜之多晶矽所構成，因此側壁子54的高度較佳高於前述實施例之側壁子30高度。其次，本實施例形成側壁子54時較佳先沉積一由摻雜之多晶矽所構成的材料層於淺溝隔離28與第一閘極層20上，然後進行一回蝕刻製程，藉由調整摻雜與不摻雜多晶矽的蝕刻選擇比，去除部分該材料層以形成側壁子54，因此所形成之側壁子較佳由摻雜之多晶矽所構成。
如第11圖所示，接著進行一蝕刻製程，去除部分第一閘 極層20、部分閘極介電層18及部分基底12以形成一開口56，並同時將第一閘極層20分割為第一閘極結構36與第二閘極結構40。在本實施例中，形成開口56時較佳同時去除部分側壁子54，因此側壁子54於開口56形成後的高度較佳低於淺溝隔離28上表面，且剩餘由多晶矽所構成的側壁子54亦可用來當作第三閘極結構38與第四閘極結構42。之後可比照前述實施例去除部分淺溝隔離28並形成氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層於淺溝隔離28及兩組閘極結構上，在此不另加贅述。
請繼續參照第12圖至第15圖，第12圖至第15圖為本發明第四實施例製作一半導體元件之方法示意圖。如前述之實施例，本實施例同樣僅繪示記憶體單元區14之製程步驟但不包含周邊區16之相關製程細節。如第12圖所示，首先進行第1圖至第2圖於記憶體單元區之製程，例如於記憶體單元區14形成一側壁子54於第一閘極層20上方之淺溝隔離28側壁，其中側壁子54較佳由氮化矽所構成。如同前述第三實施例，由於本實施例僅採用單一閘極層，因此側壁子54的高度較佳高於前述實施例之側壁子30高度。
然後如第13圖所示，進行一蝕刻製程，去除部分第一閘極層20、部分閘極介電層18及部分基底12以形成一開口56，並同時將第一閘極層20分割為第一閘極結構36與第二閘極結構40。
如第14圖所示，隨後形成一介電層58並填滿開口56，其中介電層58較佳由氧化矽所構成。接著利用CMP製程等平坦化方式或蝕刻製程去除部分淺溝隔離28、部分介電層58及部分側壁子54，使淺溝隔離28與剩餘的介電層58與側壁子54表面齊平。
如第15圖所示，接著進行另一蝕刻製程，完全去除由氮化矽所構成的側壁子54以形成二凹槽(圖未示)，再形成一由多晶矽所構成的材料層於淺溝隔離28上並填入凹槽內，然後進行CMP等平坦化製程去除部分多晶矽材料層以形成二多晶矽閘極60(亦即為前述各實施例之第三閘極結構38與第四閘極結構42)。之後可比照前述實施例去除部分淺溝隔離28並形成氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層於淺溝隔離28及兩個閘極結構上，在此不另加贅述。
綜上所述，本發明較佳在不使用額外光罩的情況下將原始記憶體單元的閘極層分割為至少兩組閘極結構，如此即可藉由降低閘極的主動面積來提升記憶體單元的整體效能。此外，以上述第7圖本發明之較佳實施例為例，本發明可利用第三閘極結構與第四閘極結構的傾斜側壁搭配側壁子的弧形側壁輪廓來提升ONO堆疊層沈積的效率，使ONO堆疊層覆蓋於淺溝隔離與閘極結構時可同時輕易覆蓋側壁子的表面。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧記憶體單元區
16‧‧‧周邊區
18‧‧‧閘極介電層
20‧‧‧第一閘極層
22‧‧‧第二閘極層
28‧‧‧淺溝隔離
36‧‧‧第一閘極結構
38‧‧‧第三閘極結構
40‧‧‧第二閘極結構
42‧‧‧第四閘極結構
44‧‧‧側壁子
50‧‧‧氧化物-氮化物-氧化物堆疊層

Claims (11)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底上具有一第一閘極層、一第一介電層以及一淺溝隔離(shallow trench isolation,STI)設於該基底內並環繞該第一閘極層及該第一介電層；去除該第一介電層；形成一第一側壁子於該第一閘極層上方之該淺溝隔離側壁；以及利用該第一側壁子為遮罩去除部分該第一閘極層及部分該基底以形成一第一開口並同時定義出一第一閘極結構及一第二閘極結構。
  2. 如申請專利範圍第1項所述之方法，其中該第一閘極層包含不摻雜之多晶矽。
  3. 如申請專利範圍第1項所述之方法，另包含一第二閘極層設於該第一閘極層及該第一介電層之間。
  4. 如申請專利範圍第3項所述之方法，其中該第二閘極層包含摻雜之多晶矽。
  5. 如申請專利範圍第3項所述之方法，另包含：形成該第一側壁子於該第二閘極層上方之該淺溝隔離側壁；利用該第一側壁子為遮罩去除部分該第二閘極層、部分該第一閘極層及部分該基底以形成該第一開口，並形成該第一閘極結構及該第二閘極結構於該基底上以及一第三閘極結構及一第四閘極結構分別設於該第一閘極結構及該第二閘極結構上； 形成一第二側壁子於該第一開口內；形成一第三側壁子於該第二側壁子上；去除部分該淺溝隔離；去除該第一側壁子及該第三側壁子；以及形成一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層於該淺溝隔離、該第二側壁子、該第一閘極結構及該第二閘極結構上。
  6. 如申請專利範圍第1項所述之方法，其中該第二側壁子包含氧化矽。
  7. 如申請專利範圍第1項所述之方法，其中該第三側壁子包含氮化矽。
  8. 如申請專利範圍第1項所述之方法，另包含；形成一第二介電層並填滿該第一開口；去除部分該淺溝隔離、部分該第二介電層及部分該第一側壁子，使該淺溝隔離與該第一側壁子表面齊平；去除部分該淺溝隔離及部分該第二介電層；去除剩餘之該第一側壁子；以及形成一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆疊層於該淺溝隔離、該第二介電層、該第一閘極結構及該第二閘極結構上。
  9. 如申請專利範圍第1項所述之方法，另包含利用一化學機械研磨製程或一蝕刻製程去除部分該淺溝隔離、部分該第二介電層及部分 該第一側壁子。
  10. 如申請專利範圍第1項所述之方法，其中該第一側壁子包含多晶矽。
  11. 如申請專利範圍第1項所述之方法，另包含：形成一第二介電層並填滿該第一開口；去除該第一側壁子以形成一第二開口及一第三開口暴露出該第一閘極結構及該第二閘極結構；以及形成一多晶矽層並填滿該第二開口及該第三開口。
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US20160104785A1 (en) 2016-04-14
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US9397183B2 (en) 2016-07-19
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