CN102812552B - 半导体存储器装置及用于对半导体存储器装置进行偏置的方法 - Google Patents
半导体存储器装置及用于对半导体存储器装置进行偏置的方法 Download PDFInfo
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Abstract
本发明揭示用于提供半导体存储器装置的技术。在一个特定示范性实施例中,所述技术可实现为一种半导体存储器装置,所述半导体存储器装置包括以行及列的阵列布置的多个存储器单元。每一存储器单元包括第一区域、第二区域及体区域,所述体区域电容性地耦合到至少一个字线且安置在所述第一区域与所述第二区域之间。每一存储器单元还包括第三区域,其中所述第三区域可与所述第一区域、所述第二区域及所述体区域不同地掺杂。
Description
相关申请案的交叉参考
本专利申请案主张2010年3月15日申请的第61/313,986号美国临时专利申请案的优先权,所述临时申请案的全部内容特此以引用的方式并入本文中。
技术领域
本发明大体上涉及半导体存储器装置,且更特定来说,涉及用于提供无结半导体存储器装置的技术。
背景技术
半导体工业已经历允许半导体存储器装置的密度及/或复杂性的增加的技术进步。并且,所述技术进步已允许各种类型的半导体存储器装置的功率消耗及封装尺寸的减小。存在使用改善性能、减少泄漏电流且增强总体缩放的技术、材料及装置来利用及/或制造先进半导体存储器装置的持续趋势。绝缘体上硅(SOI)及大块衬底为可用于制造此类半导体存储器装置的材料的实例。举例来说,此类半导体存储器装置可包括部分耗尽(PD)装置、完全耗尽(FD)装置、多栅极装置(例如,双栅极、三栅极或环绕栅极)及鳍式FET(Fin-FET)装置。
半导体存储器装置可包括存储器单元,所述存储器单元具有带有其中可存储电荷的电浮动体区域的存储器晶体管。当过量多数电荷载流子存储在电浮动体区域中时,存储器单元可存储逻辑高(例如,二进制“1”数据状态)。当电浮动体区域耗尽多数电荷载流子时,存储器单元可存储逻辑低(例如,二进制“0”数据状态)。并且,半导体存储器装置可制造在绝缘体上硅(SOI)衬底或大块衬底上(例如,启用体隔离)。举例来说,半导体存储器装置可制造为三维(3D)装置(例如,多栅极装置、鳍式FET装置及垂直柱装置)。
在一种常规技术中,半导体存储器装置的存储器单元可通过植入工艺来制造。在常规植入工艺期间,可能在半导体存储器装置的存储器单元的各种区域的硅晶格中产生缺陷结构。在植入工艺期间形成的缺陷结构可减少存储在半导体存储器装置的存储器单元中的多数电荷载流子的保持时间。并且,在常规植入工艺期间,存储器单元的各种区域可能以非所要的掺杂浓度来掺杂。所述非所要的掺杂浓度可因此产生用于半导体存储器装置的存储器单元的非所要的电性质。此外,所述常规植入工艺可能面临横向及垂直缩放挑战。
鉴于以上内容,可以理解,可能存在与用于提供半导体存储器装置的常规技术相关联的显著问题及缺点。
发明内容
揭示一种半导体存储器装置,其包含以行及列的阵列布置的多个存储器单元,每一存储器单元包含:第一区域;第二区域;体区域,其电容性地耦合到至少一个字线且安置在所述第一区域与所述第二区域之间;及第三区域,其中所述第三区域与所述第一区域、所述第二区域及所述体区域不同地掺杂。
另外,揭示一种用于对半导体存储器装置进行偏置的方法。所述包含以下步骤:将多个电压电位施加到以行及列的阵列布置的多个存储器单元,其中将所述多个电压电位施加到所述多个存储器单元包含:将第一电压电位施加到所述多个存储器单元中的每一者的第一区域;将第二电压电位施加到所述多个存储器单元中的每一者的第二区域;经由所述阵列的电容性地耦合到体区域的至少一个相应字线将第三电压电位施加到所述多个存储器单元中的每一者的所述体区域;及将第四电压电位施加到第三区域。
附图说明
为了促进对本发明的更完整的理解,现在参考附图,其中相同的元件以相同的标号来参考。这些图式不应理解为限制本发明,而是意在仅为示范性的。
图1展示根据本发明的实施例的包括存储器单元阵列、数据写入及感测电路以及存储器单元选择及控制电路的半导体存储器装置的框图。
图2展示根据本发明的实施例的图1中展示的存储器单元的横截面图。
图3展示根据本发明的替代实施例的图1中展示的存储器单元的横截面图。
图4展示根据本发明的实施例的图1中展示的存储器单元的横截面图。
图5展示根据本发明的替代实施例的图1中展示的存储器单元的横截面图。
图6展示根据本发明的实施例的图1中展示的存储器单元阵列的至少一部分的横截面图。
图7展示根据本发明的替代实施例的图1中展示的存储器单元阵列的至少一部分的横截面图。
图8展示根据本发明的替代实施例的图1中展示的存储器单元阵列的至少一部分的横截面图。
图9展示根据本发明的替代实施例的图1中展示的存储器单元阵列的至少一部分的横截面图。
图10展示根据本发明的实施例的用于对图2中展示的存储器单元执行写入操作的控制信号电压波形。
图11展示根据本发明的实施例的用于对图2中展示的存储器单元执行读取操作的控制信号电压波形。
具体实施方式
参考图1,展示根据本发明的实施例的包含存储器单元阵列20、数据写入及感测电路36以及存储器单元选择及控制电路38的半导体存储器装置10的框图。存储器单元阵列20可包含多个存储器单元12,其各自经由字线(WL)28及载流子注入线(EP)34耦合到存储器单元选择及控制电路38,且经由位线(CN)30及源极线(EN)32耦合到数据写入及感测电路36。可了解,位线(CN)30及源极线(EN)32为用于区分两个信号线的名称,且其可互换使用。
数据写入及感测电路36可从所选择的存储器单元12读取数据且可将数据写入到所选择的存储器单元12。在示范性实施例中,数据写入及感测电路36可包括多个数据感测放大器电路。每一数据感测放大器电路可接收至少一个位线(CN)30及电流或电压参考信号。举例来说,每一数据感测放大器电路可为交叉耦合类型的感测放大器,以感测存储在存储器单元12中的数据状态。数据写入及感测电路36可包括可将数据感测放大器电路耦合到至少一个位线(CN)30的至少一个多路复用器。在示范性实施例中,所述多路复用器可将多个位线(CN)30耦合到数据感测放大器电路。
每一数据感测放大器电路可利用电压及/或电流感测电路及/或技术。在示范性实施例中,每一数据感测放大器电路可利用电流感测电路及/或技术。举例来说,电流感测放大器可将来自所选择的存储器单元12的电流与参考电流(例如,一个或一个以上参考单元的电流)进行比较。根据所述比较,可确定所选择的存储器单元12存储逻辑高(例如,二进制“1”数据状态)还是存储逻辑低(例如,二进制“0”数据状态)。所属领域的技术人员可了解,各种类型或形式的数据写入及感测电路36(包括使用电压或电流感测技术来感测存储在存储器单元12中的数据状态的一个或一个以上感测放大器)可用于读取存储在存储器单元12中的数据。
存储器单元选择及控制电路38可通过将控制信号施加于一个或一个以上字线(WL)28及/或载流子注入线(EP)34上来选择且/或启用一个或一个以上预定存储器单元12以促进从所述存储器单元12读取数据。存储器单元选择及控制电路38可从地址信号(举例来说,行地址信号)产生此类控制信号。此外,存储器单元选择及控制电路38可包括字线解码器及/或驱动器。举例来说,存储器单元选择及控制电路38可包括一个或一个以上不同的控制/选择技术(及其电路)以选择且/或启用一个或一个以上预定存储器单元12。明显地,所有此类控制/选择技术及其电路(不管是现在已知的还是稍后开发的)都意在落在本发明的范围内。
在示范性实施例中,半导体存储器装置10可实施两步骤写入操作,借此可通过首先执行“清除”或逻辑低(例如,二进制“0”数据状态)写入操作来将一行存储器单元12中的所有存储器单元12写入为预定数据状态,借此所述行存储器单元12中的所有存储器单元12被写入为逻辑低(例如,二进制“0”数据状态)。此后,可选择性地将所述行存储器单元12中的所选择的存储器单元12写入为预定数据状态(例如,逻辑高(二进制“1”数据状态))。半导体存储器装置10还可实施一步骤写入操作,借此可选择性地将一行存储器单元12中的所选择的存储器单元12写入为逻辑高(例如,二进制“1”数据状态)或逻辑低(例如,二进制“0”数据状态)而不需要首先实施“清除”操作。半导体存储器装置10可利用本文中描述的示范性写入、准备、保持、刷新及/或读取技术中的任一者。
存储器单元12可包含N型、P型及/或这两种类型的晶体管。处于存储器单元阵列20的外围的电路(举例来说,感测放大器或比较器、行及列地址解码器以及线驱动器(本文中未说明))也可包括P型及/或N型晶体管。不管存储器单元阵列20的存储器单元12中使用的是P型晶体管还是N型晶体管,本文中都将进一步描述用于从存储器单元12进行读取的合适电压电位(举例来说,正或负电压电位)。
参考图2,展示根据本发明的实施例的图1中展示的存储器单元12的横截面图。存储器单元12可包含第一N-区域120、第二N-区域122、第三N-区域124及/或P-区域126。第一N-区域120、第二N-区域122、第三N-区域124及/或P-区域126可以连续相邻关系安置在平面配置内,所述平面配置可水平延伸或与由氧化物区域128及/或P-衬底130界定的平面平行而延伸。在示范性实施例中,第二N-区域122可为存储器单元12的经配置以积累/存储电荷的电浮动体区域,所述电浮动体区域可与字线(WL)28间隔开且电容性地耦合到字线(WL)28。
存储器单元12的第一N-区域120可经由第一N+多晶硅插塞(polyplug)232耦合到源极线(EN)32。第一N+多晶硅插塞232可直接耦合到存储器单元12的第一N-区域120。存储器单元12的第二N-区域122可经由栅极区域228耦合到字线(WL)28。栅极区域228可电容性地耦合到存储器单元12的第二N-区域122。存储器单元12的第三N-区域124可经由第二N+多晶硅插塞230耦合到位线(CN)30。第二N+多晶硅插塞230可直接耦合到存储器单元12的第三N-区域124。存储器单元12的P-区域126可经由P+区域234耦合到载流子注入线(EP)34。P+区域234可直接耦合到存储器单元12的P-区域126。
第一N-区域120、第二N-区域122及第三N-区域124可由相同材料或不同材料形成。并且,第一N-区域120、第二N-区域122及第三N-区域124可由具有各种掺杂浓度的相同材料形成。在示范性实施例中,第一N-区域120、第二N-区域122及第三N-区域124可由包含施主杂质(例如,氮、砷及/或磷)的半导体材料(例如,硅)形成。在示范性实施例中,第一N-区域120、第二N-区域122及/或第三N-区域124可由带有具有1015原子/cm3到1018原子/cm3的浓度的施主杂质的硅材料形成。
P-区域126可由包含受主杂质的半导体材料(例如,本征硅)形成。举例来说,P-区域126可由掺杂有硼杂质的硅材料形成。在示范性实施例中,P-区域126可由带有具有1015原子/cm3到1018原子/cm3的浓度的受主杂质的硅材料形成。在另一示范性实施例中,P-区域126可由未掺杂半导体材料(例如,本征硅)形成。
第一N+多晶硅插塞232及第二N+多晶硅插塞230可由相同材料或不同材料形成。第一N+多晶硅插塞232及第二N+多晶硅插塞230可由金属材料、多晶硅材料、二氧化硅材料及/或其组合形成。第一N+多晶硅插塞232及第二N+多晶硅插塞230可将来自源极线(EN)32及位线(CN)30的电压电位分别耦合到存储器单元12的第一N-区域120及第三N-区域124。在另一示范性实施例中,第一N+多晶硅插塞232及第二N+多晶硅插塞230可由钨、钛、氮化钛、多晶硅或其组合形成。第一N+多晶硅插塞232及第二N+多晶硅插塞230可具有分别从第一N-区域120及第三N-区域124延伸到源极线(EN)32及位线(CN)30的高度。
栅极区域228可由多晶硅化物(polycide)材料、硅材料、金属材料及/或其组合形成。在另一示范性实施例中,栅极区域228可由经掺杂硅层形成。栅极区域228可由包含受主杂质的半导体材料(例如,硅)形成。举例来说,栅极区域228可由掺杂有硼杂质的硅材料形成。
P+区域234可由包含受主杂质的半导体材料(例如,硅)形成。举例来说,P+区域234可由掺杂有硼杂质的硅材料形成。在示范性实施例中,P+区域234可掺杂有具有1020原子/cm3或更高的浓度的受主杂质。
氧化物层128可形成在P-衬底130上。举例来说,氧化物层128可由绝缘材料形成。氧化物层128可包括配置在P-衬底130上方的连续平面区域。在示范性实施例中,氧化物层128可由绝缘氧化物材料形成。氧化物层128可形成沟道区域,所述沟道区域可具有用于适应其中一个或一个以上存储器单元12的横截面形状。举例来说,所述沟道区域可具有可适应一个或一个以上存储器单元12的正方形、矩形、圆柱形及/或其它形状的横截面形状。
在示范性实施例中,P-衬底130可由包含受主杂质的半导体材料(例如,硅)制成,且可形成存储器单元阵列20的基部。在替代示范性实施例中,多个P-衬底130可形成存储器单元阵列20的基部,或单个P-衬底130可形成存储器单元阵列20的基部。并且,P-衬底130可以P阱衬底的形式来制造。
绝缘层132可形成在氧化物层128的顶部上。举例来说,绝缘层132可由绝缘材料、氧化物材料及/或电介质材料形成。在示范性实施例中,绝缘层132可由氮化硅材料形成。绝缘层132可形成在氧化物层128上方,以电绝缘第一N+多晶硅插塞232、栅极区域228、第二N+多晶硅插塞230及/或P+区域234。
参考图3,展示根据本发明的替代实施例的图1中展示的存储器单元12的横截面图。图3中说明的存储器单元12可类似于图2中说明的存储器单元12,除了存储器单元12可包含多个未掺杂区域之外。所述多个未掺杂区域可包含耦合到对应第一N+多晶硅插塞232的第一未掺杂区域320、电容性地耦合到对应栅极区域228的第二未掺杂区域322及/或耦合到对应第二N+多晶硅插塞230的第三未掺杂区域324。
所述多个未掺杂区域可由相同材料或不同材料形成。举例来说,所述多个未掺杂区域(例如,第一未掺杂区域320、第二未掺杂区域322及/或第三未掺杂区域324)可由未掺杂半导体材料(例如,本征硅)形成。
参考图4,展示根据本发明的实施例的图1中展示的存储器单元12的横截面图。图4中说明的存储器单元12可类似于图2中说明的存储器单元12,除了所述存储器单元12可包含第一P-区域420、第二P-区域422、第三P-区域424及/或N-区域426之外。第一P-区域420、第二P-区域422、第三P-区域424及/或N-区域426可以连续相邻关系安置在平面配置内,所述平面配置可水平延伸或与由氧化物区域128及/或P-衬底130界定的平面平行而延伸。在示范性实施例中,第二P-区域422可为存储器单元12的经配置以积累/存储电荷的电浮动体区域,所述电浮动体区域可与字线(WL)28间隔开且电容性地耦合到字线(WL)28。
存储器单元12的第一P-区域420可经由第一P+多晶硅插塞432耦合到源极线(EN)32。第一P+多晶硅插塞432可直接耦合到存储器单元12的第一P-区域420。存储器单元12的第二P-区域422可经由栅极区域428耦合到字线(WL)28。栅极区域428可电容性地耦合到存储器单元12的第二P-区域422。存储器单元12的第三P-区域424可经由第二N+多晶硅插塞430耦合到位线(CN)30。第二N+多晶硅插塞430可直接耦合到存储器单元12的第三P-区域424。存储器单元12的N-区域426可经由N+区域434耦合到载流子注入线(EP)34。N+区域434可直接耦合到存储器单元12的N-区域426。
第一P-区域420、第二P-区域422及第三P-区域424可由相同材料或不同材料形成。并且,第一P-区域420、第二P-区域422及第三P-区域424可由具有各种掺杂浓度的相同材料形成。在示范性实施例中,第一P-区域420、第二P-区域422及第三P-区域424可由包含受主杂质的半导体材料(例如,硅)形成。举例来说,第一P-区域420、第二P-区域422及/或第三P-区域424可由掺杂有硼杂质的硅材料形成。在示范性实施例中,第一P-区域420、第二P-区域422及/或第三P-区域424可由带有具有1015原子/cm3到1018原子/cm3的浓度的受主杂质的硅材料形成。
N-区域426可由包含施主杂质的半导体材料(例如,本征硅)形成。举例来说,N-区域426可由掺杂有氮、砷及/或磷杂质的硅材料形成。在示范性实施例中,N-区域426可由带有具有1015原子/cm3到1018原子/cm3的浓度的施主杂质的硅材料形成。在另一示范性实施例中,N-区域426可由未掺杂半导体材料(例如,本征硅)形成。
第一P+多晶硅插塞432及/或第二P+多晶硅插塞430可由相同材料或不同材料形成。第一P+多晶硅插塞432及第二P+多晶硅插塞430可由金属材料、多晶硅材料、二氧化硅材料及/或其组合形成。第一P+多晶硅插塞432及/或第二P+多晶硅插塞430可将来自源极线(EN)32及位线(CN)30的电压电位分别耦合到存储器单元12的第一P-区域420及第三P-区域424。在另一示范性实施例中,第一P+多晶硅插塞432及/或第二P+多晶硅插塞430可由钨、钛、氮化钛、多晶硅或其组合形成。第一P+多晶硅插塞432及/或第二P+多晶硅插塞430可具有分别从第一P-区域420及第三P-区域424延伸到载流子注入线(EP)34及位线(CN)30的高度。
栅极区域428可由多晶硅化物材料、硅材料、金属材料及/或其组合形成。在另一示范性实施例中,栅极区域428可由经掺杂硅层形成。栅极区域428可由包含受主杂质的半导体材料(例如,硅)形成。举例来说,栅极区域428可由掺杂有硼杂质的硅材料形成。
N+区域434可由包含施主杂质的半导体材料(例如,硅)形成。举例来说,N+区域434可由掺杂有氮、砷及/或磷杂质的硅材料形成。在示范性实施例中,N+区域434可由带有具有1020原子/cm3或更高的浓度的施主杂质的硅材料形成。
参考图5,展示根据本发明的替代实施例的图1中展示的存储器单元12的横截面图。图5中说明的存储器单元12可类似于图4中说明的存储器单元12,除了所述存储器单元12可包含多个未掺杂区域之外。所述多个未掺杂区域可包含耦合到对应第一P+多晶硅插塞432的第一未掺杂区域520、电容性地耦合到对应栅极区域428的第二未掺杂区域522及/或耦合到对应第二N+多晶硅插塞430的第三未掺杂区域524。
所述多个未掺杂区域可由相同材料或不同材料形成。举例来说,所述多个未掺杂区域(例如,第一未掺杂区域420、第二未掺杂区域422及/或第三未掺杂区域424)可由未掺杂半导体材料(例如,本征硅)形成。
参考图6,展示根据本发明的实施例的图1中展示的存储器单元阵列20的至少一部分的横截面图。图6说明存储器单元阵列20的至少一部分的沿着位线(CN)30的横截面图,及存储器单元阵列20的至少一部分的沿着字线(WL)28的横截面图。存储器单元阵列20的存储器单元12可以具有各种区域的垂直配置来实施。举例来说,存储器单元12可包含第一N-区域620、第二N-区域622、第三N-区域624及/或P+区域626。第一N-区域620、第二N-区域622、第三N-区域624及/或P+区域626可以连续相邻关系安置,且可从由P-衬底130界定的平面垂直延伸。在示范性实施例中,第二N-区域622可为存储器单元12的经配置以积累/存储电荷的电浮动体区域,且可与多个字线(WL)28间隔开且电容性地耦合到多个字线(WL)28。
存储器单元12的第一N-区域620可耦合到源极线(EN)32。存储器单元12的第二N-区域622可电容性地耦合到字线(WL)28。存储器单元12的第三N-区域624可耦合到位线(CN)30。存储器单元12的P+区域626可耦合到载流子注入线(EP)34。
第一N-区域620、第二N-区域622及第三N-区域624可由相同材料或不同材料形成。并且,第一N-区域620、第二N-区域622及第三N-区域624可由具有各种掺杂浓度的相同材料形成。在示范性实施例中,第一N-区域620、第二N-区域622及第三N-区域624可由包含施主杂质(例如,氮、砷及/或磷)的半导体材料(例如,硅)形成。在示范性实施例中,第一N-区域620、第二N-区域622及/或第三N-区域624可由带有具有1015原子/cm3到1018原子/cm3的浓度的施主杂质的硅材料形成。
P+区域626可由至少一个层形成。在示范性实施例中,P+区域626可包含多个层。举例来说,P+区域626的第一层可由多晶硅材料或二氧化硅材料及/或其组合形成。在另一示范性实施例中,P+区域626的第一层可由包含受主杂质的半导体材料(例如,本征硅)形成。举例来说,P+区域626的第一层可由掺杂有硼杂质的硅材料形成。在示范性实施例中,P+区域626的第一层可由带有具有1018原子/cm3或以上的浓度的受体杂质的硅材料形成。P+区域626的第二层可由金属材料、多晶硅材料、二氧化硅材料及/或其组合形成。在示范性实施例中,P+区域626的第二层可由钨、钛、氮化钛、多晶硅或其组合形成。
源极线(EN)32可由金属材料形成。在另一示范性实施例中,源极线(EN)32可由多晶硅化物材料(例如,金属材料与硅材料的组合)形成。在其它示范性实施例中,源极线(EN)32可由N+掺杂硅层形成。源极线(EN)32可将电压电位提供到存储器单元12的第一N-区域620。举例来说,源极线(EN)32可耦合到多个存储器单元12(例如,存储器单元阵列20的一列或一行存储器单元12)。源极线(EN)32可配置在第一N-区域620的侧部分上。
字线(WL)28可电容性地耦合到第二N-区域622。字线(WL)28可在存储器单元阵列20的行方向上定向,且耦合到多个存储器单元12。字线(WL)28可布置在存储器单元12(例如,位于存储器单元阵列20的行方向上的存储器单元12)的侧部分上。举例来说,字线(WL)28可布置在存储器单元12的第二N-区域622的两个侧部分处。
举例来说,字线(WL)28可由多晶硅化物材料(例如,金属材料与硅材料的组合)、金属材料及/或多晶硅化物材料与金属材料的组合形成。在另一示范性实施例中,字线(WL)28可由N+掺杂硅材料形成。在示范性实施例中,字线(WL)28可将存储器单元选择及控制电路38的电压/电流源电容性地耦合到存储器单元12的第二N-区域622。在示范性实施例中,第一字线(WL)28可对存储器单元12实施写入逻辑低(例如,二进制“0”数据状态)操作,而第二字线(WL)28可实施写入逻辑高(例如,二进制“1”数据状态)操作。
位线(CN)30可耦合到存储器单元12的第三N-区域624。位线(CN)30可由金属材料形成。在另一示范性实施例中,位线(CN)30可由多晶硅化物材料(例如,金属材料与硅材料的组合)形成。在其它示范性实施例中,位线(CN)30可由N+掺杂硅层形成。举例来说,位线(CN)30可耦合到多个存储器单元12。位线(CN)30可配置在第三N-区域624的侧部分上。在示范性实施例中,位线(CN)30可配置在与源极线(EN)30相对的侧部分上。
氧化物层128可形成在P-衬底130上。举例来说,氧化物层128可由绝缘材料形成。在示范性实施例中,氧化物层128可由绝缘氧化物材料形成。氧化物层128可包括由绝缘氧化物材料形成的多个势垒壁。所述多个势垒壁可在存储器单元阵列20的列方向及行方向上定向。举例来说,多个势垒壁中的第一势垒壁可在列方向上定向。多个势垒壁中的第二势垒壁可在行方向上定向。在示范性实施例中,在列方向上定向的第一势垒壁及在行方向上定向的第二势垒壁可交叉以形成沟道区域。氧化物层128可形成沟道区域,所述沟道区域可具有用于适应其中一个或一个以上存储器单元12的横截面形状。举例来说,所述沟道区域可具有可适应一个或一个以上存储器单元12的正方形、矩形、圆柱形及/或其它形状的横截面形状。
在示范性实施例中,P-衬底130可以P阱衬底的形式来制造。在另一示范性实施例中,P-衬底130可由包含受主杂质的半导体材料(例如,硅)制成,且可形成存储器单元阵列20的基部。在替代示范性实施例中,多个P-衬底130可形成存储器单元阵列20的基部,或单个P-衬底130可形成存储器单元阵列20的基部。
绝缘层132可形成在P+区域626的顶部。举例来说,绝缘层132可由绝缘材料、氧化物材料及/或电介质材料形成。在示范性实施例中,绝缘层132可由氮化硅材料形成。绝缘层132可形成在P+区域626上方以电绝缘P+区域626。
参考图7,展示根据本发明的替代实施例的图1中展示的存储器单元阵列20的至少一部分的横截面图。图7说明存储器单元阵列20的至少一部分的沿着位线(CN)30的横截面图,及存储器单元阵列20的至少一部分的沿着字线(WL)28的横截面图。存储器单元阵列20的存储器单元12可以具有各种区域的垂直配置来实施。举例来说,存储器单元12可包含第一N-区域720、第二N-区域722、第三N-区域724及/或P+区域726。第一N-区域720、第二N-区域722、第三N-区域724及/或P+区域726可以连续相邻关系安置,且可从由N+衬底130界定的平面垂直延伸。在示范性实施例中,第二N-区域722可为存储器单元12的经配置以积累/存储电荷的电浮动体区域,且可与多个字线(WL)28间隔开且电容性地耦合到多个字线(WL)28。
存储器单元12的第一N-区域720可耦合到源极线(EN)32。存储器单元12的第二N-区域722可电容性地耦合到字线(WL)28。存储器单元12的第三N-区域724可耦合到位线(CN)30。存储器单元12的P+区域726可耦合到载流子注入线(EP)34。
第一N-区域720、第二N-区域722及第三N-区域724可由相同材料或不同材料形成。并且,第一N-区域720、第二N-区域722及第三N-区域724可由具有各种掺杂浓度的相同材料形成。在示范性实施例中,第一N-区域720、第二N-区域722及第三N-区域724可由包含施主杂质(例如,氮、砷及/或磷)的半导体材料(例如,硅)形成。在示范性实施例中,第一N-区域720、第二N-区域722及/或第三N-区域724可由带有具有1015原子/cm3到1018原子/cm3的浓度的施主杂质的硅材料形成。
P+区域726可以P阱区域的形式来制造。在另一示范性实施例中,P+区域726可由包含受主杂质的半导体材料(例如,硅)制成,且可形成一个或一个以上存储器单元12的基部。举例来说,P+区域726可形成存储器单元阵列20的一行或一列存储器单元12的基部。P+区域726可包含配置在N+衬底130上方的连续平面区域。P+区域726还可包含形成在所述连续平面区域上的多个势垒壁。P+区域726的多个势垒壁可在存储器单元阵列20的列方向及/或行方向上定向。
源极线(EN)32可由至少一个层形成。在示范性实施例中,源极线(EN)32可包含多个层。举例来说,源极线(EN)32的第一层可由多晶硅材料或二氧化硅材料及/或其组合形成。在另一示范性实施例中,源极线(EN)32的第一层可由包含施主杂质的半导体材料(例如,本征硅)形成。举例来说,源极线(EN)32的第一层可由掺杂有氮、砷及/或磷杂质的硅材料形成。在示范性实施例中,源极线(EN)32的第一层可由带有具有1018原子/cm3或以上的浓度的受体杂质的硅材料形成。源极线(EN)32的第二层可由金属材料、多晶硅材料、二氧化硅材料及/或其组合形成。在示范性实施例中,源极线(EN)32的第二层可由钨、钛、氮化钛、多晶硅或其组合形成。举例来说,源极线(EN)32可耦合到多个存储器单元12(例如,存储器单元阵列20的一列或一行存储器单元12)。源极线(EN)32可配置在第一N-区域720上方。
字线(WL)28可电容性地耦合到第二N-区域722。字线(WL)28可在存储器单元阵列20的行方向上定向,且耦合到多个存储器单元12。字线(WL)28可布置在存储器单元12(例如,位于存储器单元阵列20的行方向上的存储器单元12)的侧部分上。举例来说,字线(WL)28可布置在存储器单元12的第二N-区域722的两个侧部分处。
举例来说,字线(WL)28可由多晶硅化物材料(例如,金属材料与硅材料的组合)、金属材料及/或多晶硅化物材料与金属材料的组合形成。在另一示范性实施例中,字线(WL)28可由N+掺杂硅材料形成。在示范性实施例中,字线(WL)28可将存储器单元选择及控制电路38的电压电位/电流源电容性地耦合到存储器单元12的第二N-区域722。在示范性实施例中,第一字线(WL)28可对存储器单元12实施写入逻辑低(例如,二进制“0”数据状态)操作,而第二字线(WL)28可实施写入逻辑高(例如,二进制“1”数据状态)操作。
位线(CN)30可耦合到存储器单元12的第三N-区域724。位线(CN)30可由金属材料形成。在另一示范性实施例中,位线(CN)30可由多晶硅化物材料(例如,金属材料与硅材料的组合)形成。在其它示范性实施例中,位线(CN)30可由N+掺杂硅层形成。举例来说,位线(CN)30可耦合到多个存储器单元12。位线(CN)30可配置在第三N-区域724的侧部分上。
氧化物层128可形成在P+区域726及/或N+衬底130上。举例来说,氧化物层128可由绝缘材料形成。在示范性实施例中,氧化物层128可由绝缘氧化物材料形成。氧化物层128可包括由绝缘氧化物材料形成的多个势垒壁。所述多个势垒壁可在存储器单元阵列20的列方向及行方向上定向。举例来说,多个势垒壁中的第一势垒壁可在列方向上定向。多个势垒壁中的第二势垒壁可在行方向上定向。在列方向上定向的第一势垒壁可具有与在行方向上定向的第二势垒壁不同的高度。在示范性实施例中,在列方向上定向的第一势垒壁及在行方向上定向的第二势垒壁可交叉以形成沟道区域。氧化物层128可形成沟道区域,所述沟道区域可具有用于适应其中一个或一个以上存储器单元12的横截面形状。举例来说,所述沟道区域可具有可适应一个或一个以上存储器单元12的正方形、矩形、圆柱形及/或其它形状的横截面形状。
在示范性实施例中,N+衬底130可以N阱衬底的形式来制造。在另一示范性实施例中,N+衬底130可由包含施主杂质的半导体材料(例如,硅)制成,且可形成存储器单元阵列20的基部。在替代示范性实施例中,多个N+衬底130可形成存储器单元阵列20的基部,或单个N+衬底130可形成存储器单元阵列20的基部。
绝缘层132可形成在第一N-区域720的顶部。举例来说,绝缘层132可由绝缘材料、氧化物材料及/或电介质材料形成。在示范性实施例中,绝缘层132可由氮化硅材料形成。绝缘层132可形成在第一N-区域720上方以电绝缘源极线(EN)32。
参考图8,展示根据本发明的实施例的图1中展示的存储器单元阵列20的至少一部分的横截面图。图8说明存储器单元阵列20的至少一部分的沿着位线(CN)30的横截面图,及存储器单元阵列20的至少一部分的沿着字线(WL)28的横截面图。存储器单元阵列20的存储器单元12可以具有各种区域的垂直配置来实施。举例来说,存储器单元12可包含第一P-区域820、第二P-区域822、第三P-区域824及/或N+区域826。第一P-区域820、第二P-区域822、第三P-区域824及/或N+区域826可以连续相邻关系安置,且可从由N+衬底130界定的平面垂直延伸。在示范性实施例中,第二P-区域822可为存储器单元12的经配置以积累/存储电荷的电浮动体区域,且可与多个字线(WL)28间隔开且电容性地耦合到多个字线(WL)28。
存储器单元12的第一P-区域820可耦合到源极线(EN)32。存储器单元12的第二P-区域822可电容性地耦合到字线(WL)28。存储器单元12的第三P-区域824可耦合到位线(CN)30。存储器单元12的N+区域826可耦合到载流子注入线(EP)34。
第一P-区域820、第二P-区域822及第三P-区域824可由相同材料或不同材料形成。并且,第一P-区域820、第二P-区域822及第三P-区域824可由具有各种掺杂浓度的相同材料形成。在示范性实施例中,第一P-区域820、第二P-区域822及第三P-区域824可由包含受主杂质的半导体材料(例如,硅)形成。第一P-区域820、第二P-区域822及/或第三P-区域824可由掺杂有硼杂质的硅材料形成。在示范性实施例中,第一P-区域820、第二P-区域822及/或第三P-区域824可由带有具有1015原子/cm3到1018原子/cm3的浓度的受主杂质的硅材料形成。
N+区域826可由至少一个层形成。在示范性实施例中,N+区域826可包含多个层。举例来说,N+区域826的第一层可由多晶硅材料或二氧化硅材料及/或其组合形成。在另一示范性实施例中,N+区域826的第一层可由包含施主杂质的半导体材料(例如,本征硅)形成。举例来说,N+区域826的第一层可由掺杂有硼杂质的硅材料形成。在示范性实施例中,N+区域826的第一层可由带有具有1018原子/cm3或以上的浓度的施主杂质的硅材料形成。N+区域826的第二层可由金属材料、多晶硅材料、二氧化硅材料及/或其组合形成。在示范性实施例中,N+区域826的第二层可由钨、钛、氮化钛、多晶硅或其组合形成。
源极线(EN)32可由金属材料形成。在另一示范性实施例中,源极线(EN)32可由多晶硅化物材料(例如,金属材料与硅材料的组合)形成。在其它示范性实施例中,源极线(EN)32可由P+掺杂硅层形成。源极线(EN)32可将电压电位提供到存储器单元12的第一P-区域820。举例来说,源极线(EN)32可耦合到多个存储器单元12(例如,存储器单元阵列20的一列或一行存储器单元12)。源极线(EN)32可配置在第一P-区域820的侧部分上。
字线(WL)28可电容性地耦合到第二P-区域822。字线(WL)28可在存储器单元阵列20的行方向上定向,且耦合到多个存储器单元12。字线(WL)28可布置在存储器单元12(例如,位于存储器单元阵列20的行方向上的存储器单元12)的侧部分上。举例来说,字线(WL)28可布置在存储器单元12的第二P-区域822的两个侧部分处。
举例来说,字线(WL)28可由多晶硅化物材料(例如,金属材料与硅材料的组合)、金属材料及/或多晶硅化物材料与金属材料的组合形成。在另一示范性实施例中,字线(WL)28可由P+掺杂硅材料形成。在示范性实施例中,字线(WL)28可将存储器单元选择及控制电路38的电压/电流源电容性地耦合到存储器单元12的第二P-区域822。在示范性实施例中,布置在第二P-区域822的侧部分上的第一字线(WL)28可对存储器单元12实施写入逻辑低(例如,二进制“0”数据状态)操作,而布置在第二P-区域822的相对侧部分上的第二字线(WL)28可实施写入逻辑高(例如,二进制“1”数据状态)操作。
位线(CN)30可耦合到存储器单元12的第三P-区域824。位线(CN)30可由金属材料形成。在另一示范性实施例中,位线(CN)30可由多晶硅化物材料(例如,金属材料与硅材料的组合)形成。在其它示范性实施例中,位线(CN)30可由P+掺杂硅层形成。举例来说,位线(CN)30可耦合到多个存储器单元12。位线(CN)30可配置在第三P-区域824的侧部分上。在示范性实施例中,位线(CN)30可配置在与源极线(EN)30相对的侧部分上。
氧化物层128可形成在N+衬底130上。举例来说,氧化物层128可由绝缘材料形成。在示范性实施例中,氧化物层128可由绝缘氧化物材料形成。氧化物层128可包括由绝缘氧化物材料形成的多个势垒壁。所述多个势垒壁可在存储器单元阵列20的列方向及行方向上定向。举例来说,多个势垒壁中的第一势垒壁可在列方向上定向。多个势垒壁中的第二势垒壁可在行方向上定向。在示范性实施例中,在列方向上定向的第一势垒壁及在行方向上定向的第二势垒壁可交叉以形成沟道区域。氧化物层128可形成沟道区域,所述沟道区域可具有用于适应其中一个或一个以上存储器单元12的横截面形状。举例来说,所述沟道区域可具有可适应一个或一个以上存储器单元12的正方形、矩形、圆柱形及/或其它形状的横截面形状。
在示范性实施例中,N+衬底130可以N阱衬底的形式来制造。在另一示范性实施例中,N+衬底130可由包含施主杂质的半导体材料(例如,硅)制成,且可形成存储器单元阵列20的基部。在替代示范性实施例中,多个N+衬底130可形成存储器单元阵列20的基部,或单个N+衬底130可形成存储器单元阵列20的基部。
绝缘层132可形成在N+区域826的顶部。举例来说,绝缘层132可由绝缘材料、氧化物材料及/或电介质材料形成。在示范性实施例中,绝缘层132可由氮化硅材料形成。绝缘层132可形成在N+区域826上方以电绝缘N+区域826。
参考图9,展示根据本发明的替代实施例的图1中展示的存储器单元阵列20的至少一部分的横截面图。图9说明存储器单元阵列20的至少一部分的沿着位线(CN)30的横截面图,及存储器单元阵列20的至少一部分的沿着字线(WL)28的横截面图。存储器单元阵列20的存储器单元12可以具有各种区域的垂直配置来实施。举例来说,存储器单元12可包含第一P-区域920、第二P-区域922、第三P-区域924及/或N+区域926。第一P-区域920、第二P-区域922、第三P-区域924及/或N+区域926可以连续相邻关系安置,且可从由P+衬底130界定的平面垂直延伸。在示范性实施例中,第二P-区域922可为存储器单元12的经配置以积累/存储电荷的电浮动体区域,且可与多个字线(WL)28间隔开且电容性地耦合到多个字线(WL)28。
存储器单元12的第一P-区域920可耦合到位线(CN)30。存储器单元12的第二P-区域922可电容性地耦合到字线(WL)28。存储器单元12的第三P-区域924可耦合到源极线(EN)32。存储器单元12的N+区域926可耦合到载流子注入线(EP)34。
第一P-区域920、第二P-区域922及第三P-区域924可由相同材料或不同材料形成。并且,第一P-区域920、第二P-区域922及第三P-区域924可由具有各种掺杂浓度的相同材料形成。在示范性实施例中,第一P-区域920、第二P-区域922及第三P-区域924可由包含受主杂质的半导体材料(例如,硅)形成。举例来说,第一P-区域920、第二P-区域922及/或第三P-区域924可由掺杂有硼杂质的硅材料形成。在示范性实施例中,第一P-区域920、第二P-区域922及/或第三P-区域924可由带有具有1015原子/cm3到1018原子/cm3的浓度的受主杂质的硅材料形成。
N+区域926可以N阱区域的形式来制造。在另一示范性实施例中,N+区域926可由包含施主杂质的半导体材料(例如,硅)制成,且可形成一个或一个以上存储器单元12的基部。举例来说,N+区域926可形成存储器单元阵列20的一行或一列存储器单元12的基部。N+区域926可包含配置在P+衬底130上方的连续平面区域。N+区域926还可包含形成在所述连续平面区域上的多个势垒壁。N+区域926的多个势垒壁可在存储器单元阵列20的列方向及/或行方向上定向。
位线(CN)30可由至少一个层形成。在示范性实施例中,位线(CN)30可包含多个层。举例来说,位线(CN)32的第一层可由多晶硅材料或二氧化硅材料及/或其组合形成。在另一示范性实施例中,位线(CN)30的第一层可由包含施主杂质的半导体材料(例如,本征硅)形成。举例来说,位线(CN)30的第一层可由掺杂有氮、砷及/或磷杂质的硅材料形成。在示范性实施例中,位线(CN)30的第一层可由带有具有1018原子/cm3或以上的浓度的施主杂质的硅材料形成。位线(CN)30的第二层可由金属材料、多晶硅材料、二氧化硅材料及/或其组合形成。在示范性实施例中,位线(CN)30的第二层可由钨、钛、氮化钛、多晶硅或其组合形成。举例来说,位线(CN)30可耦合到多个存储器单元12(例如,存储器单元阵列20的一列或一行存储器单元12)。位线(CN)30可配置在第一P-区域920上方。
字线(WL)28可电容性地耦合到第二P-区域922。字线(WL)28可在存储器单元阵列20的行方向上定向,且耦合到多个存储器单元12。字线(WL)28可布置在存储器单元12(例如,位于存储器单元阵列20的行方向上的存储器单元12)的侧部分上。举例来说,字线(WL)28可布置在存储器单元12的第二P-区域922的两个侧部分处。
举例来说,字线(WL)28可由多晶硅化物材料(例如,金属材料与硅材料的组合)、金属材料及/或多晶硅化物材料与金属材料的组合形成。在另一示范性实施例中,字线(WL)28可由N+掺杂硅材料形成。在示范性实施例中,字线(WL)28可将存储器单元选择及控制电路38的电压电位/电流源电容性地耦合到存储器单元12的第二P-区域922。在示范性实施例中,第一字线(WL)28可对存储器单元12实施写入逻辑低(例如,二进制“0”数据状态)操作,而第二字线(WL)28可实施写入逻辑高(例如,二进制“1”数据状态)操作。
源极线(EN)32可耦合到存储器单元12的第三P-区域924。源极线(EN)32可由金属材料形成。在另一示范性实施例中,源极线(EN)32可由多晶硅化物材料(例如,金属材料与硅材料的组合)形成。在其它示范性实施例中,源极线(EN)32可由P+掺杂硅层形成。举例来说,源极线(EN)32可耦合到多个存储器单元12。源极线(EN)32可配置在第三P-区域924的侧部分上。
氧化物层128可形成在N+区域926及/或P+衬底130上。举例来说,氧化物层128可由绝缘材料形成。在示范性实施例中,氧化物层128可由绝缘氧化物材料形成。氧化物层128可包括由绝缘氧化物材料形成的多个势垒壁。所述多个势垒壁可在存储器单元阵列20的列方向及行方向上定向。举例来说,多个势垒壁中的第一势垒壁可在列方向上定向。多个势垒壁中的第二势垒壁可在行方向上定向。在列方向上定向的第一势垒壁可具有与在行方向上定向的第二势垒壁不同的高度。在示范性实施例中,在列方向上定向的第一势垒壁及在行方向上定向的第二势垒壁可交叉以形成沟道区域。氧化物层128可形成沟道区域,所述沟道区域可具有用于适应其中一个或一个以上存储器单元12的横截面形状。举例来说,所述沟道区域可具有可适应一个或一个以上存储器单元12的正方形、矩形、圆柱形及/或其它形状的横截面形状。
在示范性实施例中,P+衬底130可以P阱衬底的形式来制造。在另一示范性实施例中,P+衬底130可由包含受主杂质的半导体材料(例如,硅)制成,且可形成存储器单元阵列20的基部。在替代示范性实施例中,多个P+衬底130可形成存储器单元阵列20的基部,或单个P+衬底130可形成存储器单元阵列20的基部。
绝缘层132可形成在第一P-区域920的顶部。举例来说,绝缘层132可由绝缘材料、氧化物材料及/或电介质材料形成。在示范性实施例中,绝缘层132可由氮化硅材料形成。绝缘层132可形成在第一P-区域920上方以电绝缘位线(CN)30。
参考图10,展示根据本发明的实施例的用于对图2中展示的存储器单元12执行写入操作的控制信号电压波形。举例来说,各种控制信号可经配置以执行写入逻辑低(例如,二进制“0”数据状态)操作及/或写入逻辑高(例如,二进制“1”数据状态)操作。在示范性实施例中,可将各种控制信号施加到存储器单元12,以向一个或一个以上所选择的存储器单元12执行一个或一个以上写入逻辑低(例如,二进制“0”数据状态)操作。举例来说,可向一个或一个以上所选择的存储器单元12执行写入逻辑低(例如,二进制“0”数据状态)操作,以便耗尽可能已经积累/存储在所述一个或一个以上所选择的存储器单元12的浮动体区域中的电荷载流子。可将各种电压电位施加到存储器单元12的各种区域。在示范性实施例中,施加到第一N-区域120、第三N-区域124及/或P-区域126的电压电位可维持在0V。施加到可电容性地耦合到第二N-区域122的字线(WL)28的电压电位可从在保持操作期间施加的电压电位上升。在示范性实施例中,施加到可电容性地耦合到第二N-区域122的字线(WL)28的电压电位可上升到-0.5V。
在此偏置下,第一N-区域120与第二N-区域122之间的结及第二N-区域122与第三N-区域124之间的结可被正向偏置。第三N-区域124与P-区域126之间的结可被反向偏置或较弱地正向偏置(例如,在反向偏置电压之上且在正向偏置阈值电压电位之下)。可能已经积累/存储在第二N-区域122中的空穴电荷载流子可流到第一N-区域120及/或第三N-区域124。因此,可能已经积累/存储在第二N-区域122中的空穴电荷载流子可经由第一N-区域120及/或第三N-区域124来耗尽。通过移除可能已经积累/存储在第二N-区域122中的空穴电荷载流子,可将逻辑低(例如,二进制“0”数据状态)写入到存储器单元12。
在执行写入逻辑低(例如,二进制“0”数据状态)操作之后,控制信号可经配置以执行保持操作,以便维持存储在存储器单元12中的数据状态(例如,逻辑高(二进制“1”数据状态))。特定来说,控制信号可经配置以执行保持操作,以便使存储在存储器单元12中的数据状态(例如,逻辑低(二进制“0”数据状态))的保持时间最大化。并且,用于保持操作的控制信号可经配置以消除或减少存储器单元12内的活动或场(例如,可导致电荷泄漏的在结之间的电场)。在示范性实施例中,在保持操作期间,可将负电压电位施加到可电容性地耦合到存储器单元12的第二N-区域122的字线(WL)28,同时可将恒定电压电位经由源极线(EN)32施加到第一N-区域120、经由位线(CN)30施加到第三N-区域124且/或经由载流子注入线(EP)34施加到P-区域126,且可维持在0V。
举例来说,施加到字线(WL)28(例如,电容性地耦合到存储器单元12的P-区域122)的负电压电位可为-2.0V。在保持操作期间,可反向偏置第一N-区域120与第二N-区域122之间的结及第三N-区域124与第二N-区域122之间的结,以便保持存储在存储器单元12中的数据状态(例如,逻辑高(二进制“1”数据状态)或逻辑低(二进制“0”数据状态))。
在另一示范性实施例中,控制信号可经配置以将逻辑高(例如,二进制“1”数据状态)写入到存储器单元阵列20的一个或一个以上所选择的行的一个或一个以上所选择的存储器单元12。举例来说,可对存储器单元阵列20的一个或一个以上所选择的行或整个存储器单元阵列20执行写入逻辑高(例如,二进制“1”数据状态)操作。在另一示范性实施例中,写入逻辑高(例如,二进制“1”数据状态)操作可具有经配置以引起空穴电荷载流子积累/存储在第二N-区域122中的控制信号。
在示范性实施例中,经由源极线(EN)32施加到存储器单元12的第一N-区域120的电压电位及经由位线(CN)30施加到第三N-区域124的电压电位可维持在与保持操作期间的电压电位相同的电压电位。举例来说,经由源极线(EN)32施加到第一N-区域120及经由位线(CN)30施加到第三N-区域124的电压电位可维持在0V。施加到可电容性地耦合到第二N-区域122的字线(WL)28的电压电位也可维持在与保持操作期间的电压电位相同的电压电位。举例来说,施加到可电容性地耦合到第二N-区域122的字线(WL)28的电压电位可维持在-2.0V。
经由载流子注入线(EP)34施加到P-区域126的电压电位可从在保持操作期间施加的电压电位上升。在示范性实施例中,经由载流子注入线(EP)34施加到P-区域126的电压电位可从0V上升到约0.7V到0.9V。
在此偏置下,第三N-区域124与P-区域126之间的结可变为正向偏置。举例来说,多数电荷载流子(例如,空穴)可经由第三N-区域124从P-区域126流向第二N-区域122。因此,预定量的空穴电荷载流子可经由P+区域126及第三N-区域124而积累/存储在N-区域122中。积累/存储在第二N-区域122(例如,电容性地耦合到字线(WL)28)中的预定量的电荷载流子可表示逻辑高(例如,二进制“1”数据状态)可被写入在存储器单元12中。
参考图11,展示根据本发明的实施例的用于对图2中展示的存储器单元12执行读取操作的控制信号电压波形。在示范性实施例中,控制信号可经配置以执行对存储在存储器单元阵列20的一个或一个以上所选择的行的一个或一个以上所选择的存储器单元12中的数据状态(例如,逻辑低(二进制“0”数据状态)及/或逻辑高(二进制“1”数据状态))的读取操作。
控制信号可经配置为预定电压电位以经由位线(CN)30实施读取操作。在示范性实施例中,经由源极线(EN)32施加到第一N-区域120的电压电位及经由载流子注入线(EP)34施加到P-区域126的电压电位可维持在0V。施加到可电容性地耦合到第二N-区域122的字线(WL)28的电压电位及施加到第三N-区域124的电压电位可从在保持操作期间施加的电压电位上升。在示范性实施例中,施加到可电容性地耦合到第二N-区域122的字线(WL)28的电压电位可从-2.0V上升到-1.0V。经由位线(CN)30施加到第三N-区域124的电压电位可从0V上升到1.0V。
在此偏置下,当将逻辑低(例如,二进制“0”数据状态)存储在存储器单元12中时,在保持操作期间积累/存储在第二N-区域122中的预定量的空穴电荷载流子可流向第三N-区域124。流到第三N-区域124的预定量的空穴电荷载流子可引起来自第三N-区域124的电子电荷载流子的注入。来自第三N-区域124的电子电荷载流子的注入可引起电流尖峰且可改变位线(CN)30上的电压电位。数据写入及感测电路36中的数据感测放大器可经由耦合到第三N-区域124的位线(CN)30而检测到小量的电压电位或电流(例如,与参考电压电位或电流相比)或检测不到电压电位或电流。
当将逻辑高(例如,二进制“1”数据状态)存储在存储器单元12中时,积累/存储在第二N-区域122中的预定量的空穴电荷载流子(例如,其可表示逻辑高(例如,二进制“1”数据状态))可流向第三N-区域124。注入到第三N-区域124中的预定量的空穴电荷载流子还可引起电子电荷载流子注入到第三N-区域124中。电子电荷载流子注入到第三N-区域124中可引起电流尖峰且可改变位线(CN)30上的电压电位。数据写入及感测电路36中的数据感测放大器可经由位线(CN)30检测所产生的电压电位或电流(例如,与参考电压电位或电流相比)。
在这里,应注意,提供用于提供根据如上文描述的本发明的半导体存储器装置的技术通常涉及某种程度上的输入数据的处理及输出数据的产生。此输入数据处理及输出数据产生可以硬件或软件来实施。举例来说,特定电子组件可在半导体存储器装置或类似或相关电路中使用以用于实施与提供根据如上文描述的本发明的半导体存储器装置相关联的功能。或者,根据指令进行操作的一个或一个以上处理器可实施与提供根据如上文描述的本发明的半导体存储器装置相关联的功能。如果情况是这样的,那么在本发明的范围内的是,此类指令可存储在一个或一个以上处理器可读媒体(例如,磁盘或其它存储媒体)上,或经由体现在一个或一个以上载波中的一个或一个以上信号发射到一个或一个以上处理器。
本发明在范围上不应由本文中描述的特定实施例限制。而是,除了本文中所描述的那些之外,所属领域的技术人员将从前述描述及附图中容易明白本发明的其它各种实施例及对本发明的修改。因此,此些其它实施例及修改意在落在本发明的范围内。此外,虽然本文中已出于特定目的而在特定环境中在特定实施方案的上下文中描述了本发明,但所属领域的技术人员将认识到,本发明的有用性不限于此,且本发明可有利地出于任何数目的目的在任何数目的环境中实施。因此,所附权利要求书应在如本文中描述的本发明的整个广度及精神的背景下理解。
Claims (27)
1.一种半导体存储器装置,其包含:
以行及列的阵列布置的多个存储器单元,每一存储器单元包含:
第一区域,其耦合到源极线;
第二区域,其耦合到位线;
体区域,其电容性地耦合到至少一个字线且安置在所述第一区域与所述第二区域之间;及
第三区域,其耦合到载流子注入线;
其中所述第一区域、所述第二区域和所述体区域具有共同的第一掺杂极性;
其中所述第三区域具有与所述第一掺杂极性不同的第二掺杂极性。
2.根据权利要求1所述的半导体存储器装置,其中所述第一区域耦合到第一多晶硅插塞,且所述第二区域耦合到第二多晶硅插塞。
3.根据权利要求1所述的半导体存储器装置,其中所述第一区域、所述第二区域、所述体区域及所述第三区域以平面配置来布置。
4.根据权利要求3所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域掺杂有施主杂质。
5.根据权利要求4所述的半导体存储器装置,其中所述第三区域掺杂有受主杂质。
6.根据权利要求3所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域为未掺杂区域。
7.根据权利要求3所述的半导体存储器装置,其中所述体区域耦合到第一掺杂区域,且所述第三区域耦合到第二掺杂区域。
8.根据权利要求7所述的半导体存储器装置,其中所述第二掺杂区域掺杂有受主杂质,所述受主杂质具有高于所述第三区域的浓度。
9.根据权利要求3所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域掺杂有受主杂质。
10.根据权利要求3所述的半导体存储器装置,其中所述第三区域掺杂有施主杂质。
11.根据权利要求10所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域为未掺杂区域。
12.根据权利要求1所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域以垂直配置来布置。
13.根据权利要求12所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域掺杂有施主杂质。
14.根据权利要求13所述的半导体存储器装置,其中所述第三区域掺杂有受主杂质。
15.根据权利要求14所述的半导体存储器装置,其中所述第三区域由P阱区域制成。
16.根据权利要求1所述的半导体存储器装置,其中所述第一区域、所述第二区域以及所述体区域具有各种掺杂浓度。
17.根据权利要求12所述的半导体存储器装置,其中所述源极线及所述位线布置在所述存储器单元的相对侧上。
18.根据权利要求12所述的半导体存储器装置,其中所述第一区域、所述第二区域及所述体区域掺杂有受主杂质。
19.根据权利要求18所述的半导体存储器装置,其中所述第三区域掺杂有施主杂质。
20.根据权利要求19所述的半导体存储器装置,其中所述第三区域由N阱区域制成。
21.一种用于对半导体存储器装置进行偏置的方法,其包含以下步骤:
经由存储器单元阵列的相应源极线将第一电压电位施加到所述阵列的第一存储器单元的第一区域;
经由所述阵列的相应位线将第二电压电位施加到所述第一存储器单元的第二区域;
经由电容性地耦合到所述第一存储器单元的体区域的所述阵列的至少一个相应字线将第三电压电位施加到所述第一存储器单元的所述体区域;及
经由所述阵列的相应载流子注入线将第四电压电位施加到所述第一存储器单元的第三区域,
其中所述第一区域、所述第二区域和所述体区域具有共同的第一掺杂极性。
22.根据权利要求21所述的方法,其进一步包含增加在保持操作期间施加到所述至少一个相应字线的所述第三电压电位,以便执行写入逻辑低操作。
23.根据权利要求21所述的方法,其进一步包含维持在保持操作期间施加的所述第一电压电位、所述第二电压电位及所述第四电压电位,以便执行写入逻辑低操作。
24.根据权利要求21所述的方法,其进一步包含增加在保持操作期间施加的所述第四电压电位,以便执行写入逻辑高操作。
25.根据权利要求21所述的方法,其进一步包含维持在保持操作期间施加的所述第一电压电位、所述第二电压电位及所述第三电压电位,以便执行写入逻辑高操作。
26.根据权利要求21所述的方法,其进一步包含增加在保持操作期间施加的所述第二电压电位,以便执行读取操作。
27.根据权利要求21所述的方法,其进一步包含增加在保持操作期间施加的所述第三电压电位,以便执行读取操作。
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EP2548227A4 (en) | 2014-09-03 |
US9019759B2 (en) | 2015-04-28 |
EP2548227A2 (en) | 2013-01-23 |
WO2011115893A3 (en) | 2011-12-22 |
US20110222356A1 (en) | 2011-09-15 |
US9524971B2 (en) | 2016-12-20 |
WO2011115893A9 (en) | 2012-11-15 |
CN102812552A (zh) | 2012-12-05 |
EP3511982A1 (en) | 2019-07-17 |
US8547738B2 (en) | 2013-10-01 |
US20150155285A1 (en) | 2015-06-04 |
US20140029360A1 (en) | 2014-01-30 |
KR20130007609A (ko) | 2013-01-18 |
WO2011115893A2 (en) | 2011-09-22 |
EP2548227B1 (en) | 2021-07-14 |
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