TWI756234B - 使用材料變性及rf脈衝的選擇性蝕刻 - Google Patents

使用材料變性及rf脈衝的選擇性蝕刻 Download PDF

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TWI756234B
TWI756234B TW106121039A TW106121039A TWI756234B TW I756234 B TWI756234 B TW I756234B TW 106121039 A TW106121039 A TW 106121039A TW 106121039 A TW106121039 A TW 106121039A TW I756234 B TWI756234 B TW I756234B
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plasma
power supply
semiconductor substrate
pulsed
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巴加夫 席特拉
正操 殷
史林尼法斯 奈馬尼
維亞契史拉維 芭芭洋
爾麥克 史托威
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美商應用材料股份有限公司
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Abstract

半導體系統及方法可包括執行選擇性蝕刻的方法，該等方法包括以下步驟：使半導體基板上的材料變性。該半導體基板可在該半導體基板的表面上具有至少兩種受暴材料。該等方法可包括以下步驟：在收容該半導體基板的處理腔室內形成低電力電漿。該低電力電漿可為射頻（「RF」）電漿，該射頻電漿在實施例中可至少部分地由RF偏壓電源所形成，該RF偏壓電源在約10 W及約100 W之間運作。該RF偏壓電源亦可使用低於約5,000 Hz的一頻率發出脈衝。該等方法亦可包括以下步驟：相較於該半導體基板之該表面上之該至少兩種受暴材料中的第二種材料以較高的蝕刻速率蝕刻該半導體基板之該表面上之該至少兩種受暴材料中的一種受暴材料。

Description

使用材料變性及RF脈衝的選擇性蝕刻
本技術關於用於處理半導體材料的系統及方法。更具體而言，本技術關於用於產生低電力電漿的半導體材料變性及硬體變性。
可能藉由在基板表面上產生錯綜複雜地佈局的材料層的製程來製作積體電路。在基板上產生經佈局的材料的步驟需要用於施用及移除材料的受控方法。對於移除而言，化學蝕刻用於各種用途，包括將光阻劑中的圖樣轉移進下層的層、薄化的層或已經存在於表面上的薄化的特徵側向尺度。通常想要擁有較另一材料為快地蝕刻一個材料而例如促進圖樣轉移製程的蝕刻製程。此類蝕刻製程被稱為對於第一材料是有選擇性的。材料、電路及製程的多樣性的結果是，已研發了對於各種材料具有選擇性的蝕刻製程。
可基於製程中所使用的材料而將蝕刻製程稱為是濕的或乾的。濕的HF蝕刻相較於其他介電質及材料而言優先移除氧化矽。然而，濕製程可能在穿透某些受限的溝時有困難，且亦可能有時使其餘材料變形。在基板處理區域內所形成之局部電漿中所產生的乾蝕刻可穿透更加受限的溝且展現了較少的精巧的其餘結構的變形。然而，局部的電漿可能在它們放電時經由產生電弧而損傷基板。此外，電漿溢流可能損傷可能需要替換或處理的腔室元件。
因此，存在著可用以產生高品質設備及結構的改良的系統及方法的需要。本技術解決這些及其他的需要。
半導體系統及方法可包括執行選擇性蝕刻的方法，該等方法包括以下步驟：使一半導體基板上的一材料變性。該基板可在該半導體基板的一表面上具有至少兩種受暴材料。該等方法可包括以下步驟：在收容該半導體基板的一處理腔室內形成一低電力電漿。該低電力電漿可為一射頻（「RF」）電漿，該射頻電漿在實施例中可至少部分地由一RF偏壓電源所形成，該RF偏壓電源在約10 W及約100 W之間運作。該RF偏壓電源亦可使用低於約5,000 Hz的一頻率發出脈衝。該等方法亦可包括以下步驟：相較於該半導體基板之該表面上之該至少兩種受暴材料中的一第二種材料以一較高的蝕刻速率蝕刻該半導體基板之該表面上之該至少兩種受暴材料中的一種受暴材料。
在實施例中，該變性操作可包括以該RF偏壓電源從該處理腔室內的一母材形成一電漿。在實施例中，該母材可選自由以下所組成之群組：氧、氫或氦。此外，該半導體基板之該表面上之該至少兩種受暴材料中的各者可選自由以下所組成之群組：氧化矽、氮化矽、碳化矽及碳氧化矽。
對於蝕刻操作而言，該RF偏壓電源可至少部分地形成該低電力電漿且低於約50%的一工作週期下運作。並且，形成該低電力電漿的步驟可更包括利用低於約100 W的一RF源電源。在實施例中，形成該低電力電漿的步驟亦可包括利用一脈衝式DC電源。該脈衝式DC電源可施用於支撐該半導體基板的一雙極靜電夾具。在實施例中，該脈衝式DC電源可施用於一導電環，該導電環嵌在支撐該半導體基板之一托架的一罩環中或與該處理腔室內的一蓮蓬頭耦合。
本技術亦包括了從一半導體基板移除材料的方法。該等方法可包括以下步驟：使一半導體基板上的一材料變性，該半導體基板在該半導體基板的一表面上具有至少兩種受暴材料。該變性步驟可包括：以一RF偏壓電源從一母材形成一電漿以生成使該材料變性的電漿溢流。該等方法亦可包括以下步驟：在收容該半導體基板的一處理腔室內形成一低電力電漿。該低電力電漿在實施例中可為一射頻（RF）電漿。該低電力電漿可藉由一脈衝式RF偏壓電源來形成，該脈衝式RF偏壓電源在約500 Hz及約2,000 Hz之間的一脈衝頻率下在約20 W及50 W之間下運作。該脈衝式RF偏壓電源亦可在約20%及50%之間的一工作週期下運作。該等方法可包括以下步驟：與該RF偏壓電源脈衝在一交流頻率上操作一DC脈衝式電源。該等方法可更包括以下步驟：相對於該半導體基板之該表面上之該至少兩種受暴材料中的一第二種材料以至少約20:1的一選擇性蝕刻該半導體基板之該表面上之該至少兩種受暴材料中的一種受暴材料。
在該等方法中，該變性操作包括一化學變性，該化學變性對於該半導體基板上的該材料造成一化學變化。該變性步驟亦可包括利用一惰性母材的一物理變性。在實施例中，該物理變性可包括以該惰性母材的離子損傷該半導體基板上之該材料的鍵結。形成該低電力電漿的該操作可更包括利用以最多約100 W運作的一RF源電源。
本技術亦包括了基板處理腔室，該等基板處理腔室包括被配置為支撐一半導體基板的一托架。在實施例中，該等腔室可包括一RF偏壓電源，該RF偏壓電源與該托架電耦合且被配置為以約20 W及約50 W之間的一功率在該處理腔室內生成一電漿。該RF偏壓電源可為被配置為使用低於約5,000 Hz的一頻率發出脈衝的一脈衝電源。該等基板處理腔室可更包括：一DC脈衝電源，與該基板處理腔室電耦合，且被配置為產生用於該RF偏壓電漿的引火粒子。此外，該DC脈衝電源供應器可被配置為在不發展一電漿鞘的情況下以一頻率發出脈衝以產生引火粒子。
在實施例中，該DC脈衝電源供應器可被配置為在小於約50%的一工作週期下啟動脈衝100微秒或更少的一持續時間。此外，在實施例中，該托架可為一雙極靜電夾具，且該DC脈衝電源可施用於該雙極靜電夾具的電接地。在實施例中，該DC脈衝電源可與一導電環電耦合，該導電環與該托架耦合，且該導電環可與該靜電夾具及該RF偏壓電解耦。在實施例中，該DC脈衝電源亦可與一導電環電耦合，該導電環嵌在該基板處理腔室內的一蓮蓬頭中。
此類技術相對於傳統的技術可提供許多益處。例如，該技術可例如由於材料變性而允許改良的蝕刻操作選擇性。此外，本技術的低電力電漿相對於傳統的技術可產生改良的特徵剖面，且允許在使用強化的電漿控制的情況下進行改良的前端及後端處理。與以下說明及隨附圖式結合來更詳細地描述這些及其他實施例以及許多它們的優點及特徵。
在半導體處理中，可基於許多理由而執行蝕刻。在乾式蝕刻中，母材可流過電漿而產生用於蝕刻各種半導體材料的自由基電漿溢流。電漿溢流包括了被導向要蝕刻之基板表面及材料的離子。在某些蝕刻操作中（例如在使用反應性離子蝕刻法的情況下），離子被導向材料表面，且基於所涉及的能量可從基板表面濺散材料。基於較第二材料為快地移除一個材料的目標而設計了其他的蝕刻操作（通常稱為選擇性蝕刻）。為了強化選擇性，一個方法可包括以下步驟：減少蝕刻操作的濺散成分。這可部分地藉由減少電漿電力以減少電子溫度來達成。選擇性可能隨著特徵尺寸減少而變得越來越關鍵。選擇性越高，越少的要維持的材料可形成為用於最終產品之目標尺度的緩衝劑。甚至傳統較高的選擇性可能隨著尺寸持續減少而是不適合的。例如，即使從要維持的材料移除數奈米，設備效能亦可能被負面影響。
可以許多方式產生電漿，例如包括使用電連接至支撐基板之托架的射頻（「RF」）偏壓。此偏壓電源可與跟腔室的部分耦合的RF源結合使用或替代該RF源，或可與電感耦合的電漿源、電容耦合的電漿源、微波源或可額外地用以產生電漿溢流的任何其他電漿源結合工作。藉由替代或附加於源電源而利用偏壓電源，可向離子提供方向性以提供更多的異向性的或取決於定向的蝕刻。然而，隨著離子能量增加，濺散亦可能增加。因為濺散可能是更材料獨立的，這可能減少材料之間的選擇性，在該等材料中只有一個材料是要被移除的。據此，目標可能是減少偏壓方的電漿電力以減少濺散以改良選擇性。
傳統的技術可減少來源或偏壓處的電漿電力，但從使電漿放電的觀點來看以及在產生蝕刻時，該等傳統技術皆在可減少偏壓電力的程度上是受限的。為了使電漿放電，電力必須超過電漿所從以產生之流體的崩潰電壓。對於傳統的濺散及脈衝式蝕刻操作而言，生輝放電通常例如產生在低電流、中電壓工作狀態的500 V周圍及數千瓦特的功率處。然而，這些電力位準將提供增加的離子能量及伴生的材料濺散，這可能導致較低的選擇性。若降低電漿電力以進一步減少濺散，則可能根本難以產生或維持電漿，特別是在使用脈衝式電漿電力的情況下。此外，若偏壓電力被減少太多，則雖然可解決濺散，整體的蝕刻可能被減少至零。
本技術藉由產生脈衝式的低電力RF電漿而克服了許多這些問題。可在高達數百瓦特的源電源下及在百萬赫茲範圍中的脈衝頻率下產生傳統的所謂的低電力電漿。這些電力範圍不能夠產生本技術的選擇性，因為這些電漿的濺散成分仍太明顯。另一方面來說，本技術可在使用低於100瓦特運作之脈衝式RF徧壓的情況下在各種腔室條件下、在低達約20%的工作週期下及在低達約500 Hz的脈衝頻率下產生電漿。在此運作工作狀態下，可減少或實質消除濺散，且可產生可能相較於傳統技術高達一個數量級改良的蝕刻選擇性。本技術可涉及透過材料變性來強化選擇性及執行低電力蝕刻的組合。這些製程可藉由減少要維持的材料量來強化整體選擇性，減少要維持的材料量的步驟是皆藉由減少與其他材料相關的蝕刻量以及減少可能負面地濺散或影響材料的任何電漿效應來進行的。
雖然以下說明將例行地識別蝕刻操作，要瞭解的是，本技術可被更廣泛地應用。該等系統及操作方法可被額外應用於沉積、清潔或可能受益於所述之低電力電漿的任何其他電漿操作。據此，本說明書不是要將應用僅限制在本說明書各處所述的實例。
圖1繪示依據本技術的實施例來蝕刻基板的方法100。可在所指出的方法操作之前執行可選的操作，包括佈局、薄膜形成或各種其他習知的製程操作。該方法可包括以下步驟：在操作110處使半導體基板上的材料變性。基板可在半導體基板的表面上具有至少兩種受暴的材料，且可具有三種、四種、五種、六種或更多種不同的受暴材料。此外，一或更多種材料可在選擇性蝕刻方法100之前一開始被覆蓋，但接著被操作暴露，且因此受暴薄膜中的一或更多者可在實施例中的蝕刻操作期間受暴。在實施例中，可試圖移除這些材料中的一或更多者。
該方法亦可包括以下步驟：在操作120處在收容半導體基板的處理腔室內形成低電力電漿。低電力電漿在實施例中可為射頻（「RF」）電漿，然而亦可類似地包括其他的電漿形成方法。低電力電漿在實施例中可藉由在約10 W及100 W之間下運作的RF偏壓電源來至少部分地形成。在實施例中，RF偏壓電源可為脈衝式的，且可在低於約5,000 Hz的脈衝頻率下運作。該方法可更包括以下步驟：在操作130處蝕刻半導體基板表面上之該至少兩個受暴材料中的一或更多者。在實施例中，蝕刻該至少兩個受暴材料中的一或更多者的步驟相較於半導體基板表面上之該至少兩個受暴材料中的第二種材料可處於較高的速率。
變性操作可基於基板表面上的材料以任何數量的方式調諧，且可基於材料性質的識別及該等材料與基板表面上的其他材料是如何地不同。例如，變性操作一開始可識別密度、化學結構、反應本性上的差異或薄膜之間可利用的任何其他特徵。可執行材料中的一或更多者的變性以強化或產生薄膜之間可在蝕刻操作中利用的差異。可在實施例中藉由將材料暴露於一或更多種母材來執行變性。在實施例中，母材可或可不在與受暴材料交互作用之前被激發。在實施例中，變性步驟可包括從處理腔室內的母材形成電漿。取決於被變性的薄膜，電漿可在約50 W到約300 W之間。例如，展現較高密度的薄膜在實施例中可受益於較高的電漿電力。可在實施例中以源電源或偏壓電源以及以兩者的組合來產生電漿，以產生使受暴材料中的一或更多者變性的電漿溢流。在實施例中，可以RF偏壓電源形成電漿。
操作中所利用的母材可基於所執行之變性的類型而包括一或更多種母材。母材可包括要以一個形式或另一形式與材料反應的一或更多種母材，或可包括要在物理上變更受暴材料中的一或更多者的一或更多種母材。亦可在實施例中利用具有這些效果中的任一者或兩者的母材組合。在實例中，母材可選自包括貴重或惰性元素（例如氦、氖、氬、氪、氙及氡）的元素群組。在實施例中，母材亦可選自鹵素，包括氟、氯、溴、碘及砈。母材亦可選自硫族元素（包括氧）以及各種其他反應性及非反應性的母材（包括氫），舉例而言。
如上所述，變性操作可包括化學變性或物理變性中的任一者或兩者。化學變性可對於半導體基板上之材料中的一或更多者造成化學變化。化學變化可包括反應，例如在實施例中產生材料層的氧化物。化學變化亦可調整材料的鍵結結構，或可在化學上變更材料的原子或分子（例如藉由移除電子）。化學變性亦可涉及密化相對於要移除的額外材料要維持在基板表面上的材料或薄膜。可以不與基板上的受暴材料反應的惰性母材執行物理變性。例如，物理變性可涉及以惰性母材的離子損傷半導體基板上之材料中的一或更多者的鍵結。要瞭解的是，變性可涉及化學及物理變性的組合，且所利用的個別母材可使得一定量的物理變性及化學變性兩者發生。
半導體基板之表面上的材料可包括各種半導體處理中所使用的各種材料。該等材料可包括包含半導體處理中所一般理解之許多元素中的任何元素的金屬、介電質、蝕刻停止層及基板材料。例如，該等材料可包括金屬（例如銅、鎢、鈦或其他金屬）或含金屬的層。該等材料亦可包括含矽的材料（例如氧化矽、氮化矽、多晶矽、碳化矽、碳氧化矽、碳氮化矽）或基於其他半導體基礎的材料的材料（例如鎵）。
在實施例中，蝕刻操作中所利用的低電力電漿可至少部分地產生自與托架電耦合的RF偏壓電源，基板被支撐在該托架上。偏壓電源在實施例中可在從約1 W到約500 W的功率下運作。在實施例中，偏壓電源亦可在從約10瓦特到約250瓦特、從約15瓦特到約200瓦特、從約20瓦特到約150瓦特、從約20瓦特到約100瓦特或從約20瓦特到約50瓦特下運作。偏壓電源可運作在此範圍中，該範圍可提供減少濺散的益處，同時仍使電漿放電及產生蝕刻結果。例如，隨著電力位準增加，濺散亦可能由於增加的離子能量而增加，且因此在實施例中可將電力位準維持在約100瓦特以下。另一方面來說，可在實施例中將電力位準維持在約20瓦特以上，因為此臨限值以下的位準可能減少蝕刻能力或減少用以使電漿放電的能力。這些參數亦可在一定程度上取決於腔室條件（包括壓力及溫度），但仍可在利用下文更詳細討論之技術的脈衝條件下產生穩定的電漿。
RF偏壓電源可在低的工作週期及脈衝頻率下運作，以產生低電力電漿。工作週期在實施例中可低於約75%，且在實施例中可低於約70%、低於約65%、低於約60%、低於約55%、低於約50%、低於約45%、低於約40%、低於約35%、低於約30%、低於約25%、低於約20%、低於約15%或低於約10%。基於維持較低的離子能量同時仍有足夠的導通時間來產生穩定電漿的類似理由，RF偏壓脈衝工作週期在實施例中亦可以約10%及約60%之間或約20%及50%之間的工作週期來運作。
用於RF偏壓的脈衝頻率在實施例中可低於約10 kHz。用於RF偏壓的脈衝頻率在實施例中亦可低於約9,000 Hz、低於約8,000 Hz、低於約7,000 Hz、低於約6,000 Hz、低於約5,000 Hz、低於約4,500 Hz、低於約4,000 Hz、低於約3,500 Hz、低於約3,000 Hz、低於約2,500 Hz、低於約2,000 Hz、低於約1,500 Hz、低於約1,000 Hz、低於約750 Hz或低於約500 Hz。脈衝頻率亦可在實施例中被維持在約500 Hz及約5,000 Hz之間或在實施例中被維持在約500 Hz及約2,000 Hz之間。偏壓脈衝的頻率可影響電漿母材的解離作用，且因此藉由調整頻率，可調整解離作用。
除了RF偏壓電源以外，可在實施例中使用RF源電源。RF源電源可以最多約1,000 W或更少的功率用在蝕刻操作中，且在實施例中可以最多約500 W或最多約100 W的電力運作。RF源電源在實施例中可在低於約100 W下運作，且在實施例中可在約0 W及100 W之間運作。不同的母材可受益於RF源的添加，而其他的母材可受益於RF源電源的缺乏。例如，RF源可增加聚合物的解離作用，因此對於例如包括C4 F8 及C4 F6 的某些母材而言，源電源可解離聚合物且將碳材料沉積在基板上而阻礙了蝕刻操作。據此，使用低的RF源或不使用RF源在某些實施例中可改良蝕刻。在實施例中，可取決於受蝕刻之薄膜的類型而在蝕刻操作中利用各種母材。可使用的示例性母材包括了C4 F8 、C4 F6 、CF4 、Cl2 、CH2 F2 、O2 、N2 以及可提供用以移除目標材料之蝕刻劑特徵的任何其他母材。
先前所討論的RF偏壓條件在實施例中可能帶來控制電漿鞘或維持鞘的均質性的困難。然而，該等條件可在蝕刻製程期間協助最小化濺散。據此，本技術更試圖獲得在可不受磁性元件或相關聯的元件協助的情況下在低電力下運作電漿上的控制。因為針對特定的製程調整了壓力及運作條件，電漿在這些條件下可能更難以放電。電漿生成或氣體放電可能部分取決於引火粒子或產生帶電粒子作為用以崩潰的母材的步驟。這些帶電粒子被產生來加速放電，這可減少所需的點火電壓。在例如先前所討論的脈衝電力運作期間，包括用以產生引火粒子及將電子維持在電漿反饋迴路中的額外能量源可協助在各種處理條件期間在低電力下控制電漿生成。藉由提供額外的能量源，電漿可接著在例如為如上所述的那些電力位準的低的電力位準下或較正常電力位準為低的電力位準下放電。本技術在實施例中提供了額外的能量源以將高能粒子傳回進電漿引火迴路。
各種額外的能量源可用在本技術中，且在一個實例中可包括脈衝式DC電源。脈衝式DC電源可連接至腔室中的各種位置以幫助在以RF偏壓電源使低電力電漿放電之前將電漿引火。然而，此脈衝式DC電源基本上與傳統的DC偏壓是不同的。在某些傳統的處理中，DC偏壓被施用在系統中，包括用作托架上的偏壓。在施用DC脈衝時，電漿將從主體一路形成，且將維持足夠長的時間以供將電流容納在托架處的電漿鞘中。據此，其將向下崩陷至托架的表面而產生具有某個DC電勢量的鞘。此電漿鞘及電勢產生了用於製程的離子能量，且將由於與DC電漿相關聯的高離子能量而在陰極表面處產生材料濺散。然而，本技術可在形成電漿鞘之前循環DC脈衝。
在本技術的實施例中，可起動脈衝式DC電勢以將電漿引火，且接著結束循環以防止在基板表面處形成高電壓DC電漿鞘。因此，傳統的DC偏壓維持脈衝足夠長的時間以發展鞘，這是處於高電壓下的且影響了離子的能量。本技術可利用脈衝式DC電源來產生引火粒子以允許低的RF電力在該低的RF電力每次發動脈衝時點燃電漿。可能在一般崩潰電壓以下的低的RF電力相較於會在高電壓DC電漿鞘中所產生的（例如由傳統的DC偏壓所產生的）離子能量提供了較低的離子能量。儘管RF偏壓的電力是低的，本技術的脈衝式DC電源反而產生了在RF偏壓啟動循環時允許突崩潰及鞘的發展的引火粒子。結果是較低離子能量下的電漿鞘，這可相對於傳統技術減少或實質減少濺散。藉由減少濺散，可如先前所解釋地提供較高的選擇性。
為了產生脈衝式DC電源的機能，脈衝式DC電源的工作週期可為非常低的，且在實施例中可與1微秒到約100微秒的導通時間相關聯。在實施例中，導通時間可小於約75微秒、小於約50 微秒、小於約30 微秒、小於約25 微秒、小於約20 微秒、小於約15 微秒、小於約10 微秒、小於約5微秒或小於約1微秒。
在工作週期的意義上，雖然傳統的DC偏壓可能包括50%以上、75%以上或90%以上的工作週期以產生電漿鞘，本技術在實施例中可利用脈衝式DC電源小於約50%的工作週期。脈衝式DC電源的工作週期在實施例中亦可小於約40%、小於約30%、小於約25%、小於約20%、小於約15%、小於約10%、小於約5%或小於約1%。DC電力亦可在約1%及約50%之間、約1%及約25%之間、約1%及約10%之間或這些值之間或內的任何其他範圍的工作週期下發出脈衝。
脈衝式DC電源亦可與RF偏壓脈衝在交流或半交流的頻率上運作。例如，脈衝式DC電源的頻率可使其在RF偏壓處於關閉循環的同時處於導通循環，反之亦然。取決於兩個電源的工作週期，兩個電源中的任一者可在給定的時間運作，或兩個電源都可不在給定的時間運作。在實施例中，兩者亦皆可在給定的時間運作。藉由利用本技術的減少的工作週期，電漿鞘可在脈衝式DC電源運作的同時不形成於基板表面處。因此，脈衝式DC電源維持了可用於放電崩潰及用以穩定化阻抗以改良系統運作條件的引火粒子，同時不形成鞘或崩潰直到RF電源啟動循環為止。如此，可藉由本技術來適應各種壓力範圍，包括低於約50毫托的壓力工作狀態以及高達數百毫托或以上的壓力工作狀態。換言之，本技術控制用於生輝放電崩潰的阻抗以移除傳統的配置、定向、壓力、化學作用等等的阻抗限制。
脈衝式DC電源可以下文與其他圖式關聯而進一步描述的許多方式與系統耦合。例如，且如下文所詳細描述的，可將脈衝式DC電源施用於支撐半導體基板的雙極靜電夾具。此外，可將脈衝式DC電源施用於嵌在支撐半導體基板之托架的罩環中或與該罩環耦合的導電環。又進一步地，可將脈衝式DC電源施用於嵌在處理腔室內的蓮蓬頭中或與該蓮蓬頭連接的導電環。
參照圖2，圖2圖示一圖解，繪示依據本技術的實施例之材料變性及低電力電漿的累加效應。如所繪示的，示例性製程可包括相對於基板表面上的碳化物薄膜移除氧化物薄膜。如由第一個棒所示，反應性離子蝕刻法或連續的波形製程可針對氧化物材料相對於碳化物材料提供低於10:1的選擇性。這可能部分地是由於由離子製程所造成的濺散，該濺散對於所有材料是更具有攻擊性的而藉此增加了兩者的蝕刻速率。並且，反應性離子蝕刻亦可能在蝕刻剖面中產生圓角，且一旦所需的薄膜已被移除，反應性離子蝕刻亦可能由於離子轟擊而蝕刻到下層的層。據此，反應性離子蝕刻對於選擇性處理及維持基板的特徵而言不是令人滿意的。
如第二個棒中所示，藉由僅利用上述的脈衝式低電力RF偏壓電漿（例如同脈衝式DC電源利用），可相對於傳統的反應性離子蝕刻製程改良選擇性。該製程亦可減少或消除由反應性離子蝕刻法所產生的圓角化及下層的層的蝕刻。然而，第三個棒繪示了在執行低電力脈衝之前執行材料變性的有加成作用的益處。藉由利用兩種薄膜變性以及低電力電漿RF脈衝製程，選擇性相對於反應性離子蝕刻製程增加了幾乎一個數量級。此外，在減少圓角化及下層的層的蝕刻的情況下，蝕刻剖面被更加改良了。
圖3繪示依據本技術的實施例來執行之蝕刻製程的成像。如左方影像中所示，氮化矽區域305安置在碳化矽區域310之間。在執行如先前所討論的材料變性及低電力RF蝕刻操作之後，碳化矽區段被移除了，如右方圖式中所繪示。實質上維持了氮化矽層305，且僅可觀察到最小限度的圓角化。此外，在碳化矽區段310下層的氧化矽層315在蝕刻製程期間受暴，但該薄膜能夠充當製程的蝕刻停止物，與由於氧化矽的轟擊而會蝕刻進溝的反應性離子製程相反。量測到的效果說明的是，本技術能夠在最小限度地圓角化氮化矽的情況下產生超過50:1的碳化矽對氮化矽的蝕刻選擇性。本技術亦能夠產生超過70:1的碳化矽對氧化矽的蝕刻選擇性。
圖4圖示一圖表，繪示在使用及不使用依據本技術的實施例的處理的情況下的各種材料的蝕刻速率。本實例圖示了在電漿中利用氧母材來使基板表面上受暴的碳氧化矽、氧化矽、碳化矽及氮化矽變性的材料變性。在使用及不使用該氧處理的情況下在類似的材料上執行低電力脈衝式RF蝕刻製程。如所繪示，是在不使用材料變性的情況下在低電力蝕刻製程期間以低選擇性蝕刻所有四個薄膜。另一方面來說，在氧處理之後，碳氧化矽及碳化矽持續蝕刻，同時氧化矽及氮化矽薄膜被向那些薄膜提供表面強化的氧處理實質維持住及緩衝了。
圖5圖示一圖表，繪示在使用及不使用依據本技術的實施例的處理的情況下的碳氧化矽及碳化矽的蝕刻速率。雖然在圖4中所繪示之實例中所執行的氧變性相對於氧化矽及氮化矽而言對於含碳的薄膜是成功的，兩個含碳的薄膜相對於彼此並不具高的選擇性。在圖5中，執行了利用碳氧化矽薄膜的較高多孔性的物理變性。碳氧化矽相較於碳化矽而言是更加多孔的薄膜，且化學鍵結亦是較弱的。此示例的物理變性包括了在電漿中利用氦母材，且接著將薄膜暴露於那些電漿溢流。雖然氦離子的衝擊具有充足的損傷碳氧化矽之化學鍵的能力，但因為氦對於兩個薄膜而言是惰性的，其在化學上並不與材料反應。這進一步弱化了薄膜，在這之後執行低電力RF脈衝蝕刻。如由圖式所繪示，在變性之後進行低電力蝕刻移除了碳氧化矽材料同時實質上維持了碳化矽。
由圖4及5所繪示的實例僅為示例性的，且不是要限制本技術。這些實例僅顯示由本技術所包括之材料變性的類型。具技藝者將藉由這些實例輕易瞭解可如何將材料變性及低電力蝕刻操作應用於各種材料來強化選擇性且改良蝕刻剖面。藉由利用本技術，可針對碳氧化矽相對於氧化矽及氮化矽達成大於20:1的選擇性。亦可使用依據本技術的各種材料變性及蝕刻來針對氧化矽相對於碳氧化矽、氮化矽及碳化矽達成大於20:1的選擇性。亦可使用依據本技術的各種材料變性及蝕刻來針對碳化矽相對於氧化矽、氮化矽及碳氧化矽達成大於20:1的選擇性。此外，可使用依據本技術的各種材料變性及蝕刻來針對氮化矽相對於氧化矽、碳氧化矽及碳化矽達成大於20:1的選擇性。在實施例中，任何這些操作的選擇性亦可大於或約為25:1、大於或約為30:1、大於或約為35:1 、大於或約為40:1、大於或約為45:1、大於或約為50:1、大於或約為55:1、大於或約為60:1、大於或約為65:1、大於或約為70:1、大於或約為75:1、大於或約為80:1、大於或約為85:1、大於或約為90:1、大於或約為95:1、或大於或約為100:1。
參照圖6，圖6圖示依據本技術的實施例之向靜電夾具提供DC脈衝之控制器的部分示意說明。該系統可被包括為具有依據本技術的實施例的基板處理腔室。示例性腔室可為由加州聖克拉拉市的應用材料公司所生產的MesaTM 蝕刻系統。元件可包括被配置為支撐半導體基板的托架605。該系統亦可包括與托架電耦合且被配置為如先前所述地產生電漿的脈衝式RF偏壓電源610。脈衝式RF偏壓電源610可被配置為以約20 W及約50 W之間的功率在處理腔室內產生電漿，且脈衝式RF偏壓電源可在低於約5,000 Hz的頻率下發出脈衝。該系統亦可被配置為在先前所述的任何其他的位準下運作。
該系統亦可包括與基板處理腔室電耦合的DC脈衝電源615。DC脈衝電源615可如先前所述的，且被配置為針對RF偏壓電漿產生引火粒子。在實施例中，DC脈衝電源可被配置為以一定頻率發出脈衝以在不發展電漿鞘的情況下產生引火粒子。DC脈衝電源可以先前所述的任何時間點或在先前所述的任何工作週期下運作，且可被配置為在小於約50%的工作週期下以100微秒或更少的持續時間發出脈衝。DC脈衝電源亦可被配置為在小於約20%的工作週期下以小於約50微秒的脈衝持續期間運作。在實施例中，DC脈衝電源亦可被配置為在小於約10%的工作週期下以小於約10微秒的脈衝持續期間運作。
如圖6中所繪示，托架605可為靜電夾具。腔室控制器620可向靜電夾具控制器625（包括用於雙極靜電夾具的輸入/輸出模組630）提供指令。DC脈衝電源615可如圖式中所繪示地與雙極靜電夾具630的電接地電耦合。在許多處理腔室中，電極可被偏壓至DC電壓，且可在DC電源供應器的輸出處包括重濾波（heavy filtering）以阻擋RF電力。從而，在電源如配置中所示地發出脈衝時，波形可開始扭曲及衰減。據此，為了克服此問題，靜電夾具電源可在脈衝式DC的電壓處浮動。因此，靜電夾具電極接著參考了脈衝式DC的高電壓。換言之，靜電夾具電源可接著浮動而在電學上與機器的接地隔離，且靜電夾具的接地實質上可在高電壓處。靜電夾具可接著相對於高電壓輸出正及負極性。
因此，若脈衝式DC關閉循環或接地，則靜電夾具電極會以正或負的方式參考接地。然而，在DC被施用或發出脈衝時，則靜電夾具電極會參考所施用之DC電源的電源。為瞭解釋的目的而非作為特定的製程情境，作為如此配置的非限制性實例，若脈衝式DC電源在1 kV下運作，且靜電夾具在+/- 500伏特下運作，則在DC電源啟動循環以如先前所述地協助電漿生成時，電極會分別處於1500伏特及500伏特。此配置的益處可為，在腔室裡面可能不需要用於脈衝式DC電源的額外導體。此外，在實施例中，DC及RF脈衝可為交替的，且因此DC及RF電源儘管它們各偏壓相同的托架基座亦可彼此解耦。
可與靜電夾具解耦的額外耦合選項繪示於圖7中，圖7圖示依據本技術的實施例之向與托架結構耦合之導體提供DC脈衝之控制器的部分示意說明。如圖式中所繪示，基板處理腔室701被圖示為具有蓮蓬頭703及被配置為支撐基板的托架705。該系統可包括如先前所討論的脈衝式RF徧壓710，以及用於靜電夾持的DC電源715。可包括額外的DC脈衝單元720，該單元提供如先前所討論的脈衝式DC電源以供產生引火以供由RF偏壓點燃電漿。在此實例中，DC脈衝電源與導電環725電耦合，該導電環嵌在托架中或與該托架耦合。此導電環725在實施例中可與靜電夾具解耦及與RF偏壓解耦。例如，導電環725可被包括在托架705的介電罩環（包括石英罩環）中，如圖示。在實施例中，導電環可為任何導電材料，包括金屬或碳化矽。在此情境中，雖然因為導電環與其他電源解耦而在系統中包括了額外的導體，該等元件並不需要相對於彼此在電學上浮動。
可與靜電夾具解耦的另一耦合選項繪示於圖8中，圖8圖示依據本技術的實施例之向處理腔室之蓮蓬頭內的嵌式導體提供DC脈衝之控制器的部分示意說明。如所繪示的，圖示了與針對圖7所討論的那些元件類似的元件，包括基板處理腔室701，該基板處理腔室包括蓮蓬頭703及托架705，舉例而言。該系統類似地包括脈衝式RF徧壓710、用於靜電夾持的DC電源715及DC脈衝單元720。圖式額外包括了導電環825，該導電環可為上文所討論的類似材料，但在實施例中可與蓮蓬頭703耦合。此耦合選項亦將脈衝式DC與其他電源解耦。
亦可在實施例中包括與腔室壁耦合或嵌在該腔室壁中的耦合環，或與腔室系統的其他元件耦合或嵌在該等其他元件中的耦合環。藉由以任何這些選項或如會輕易地瞭解到要類似地包括的替代選項提供脈衝式DC電源，該系統相較於傳統系統可產生較低電力的電漿。藉由提供能量來產生高能粒子而允許低電力的脈衝RF偏壓更容易以較低的離子能量在較低的電壓下使電漿放電，可針對蝕刻、沉積、清潔或可受益於低電力電漿的任何其他製程提供改良的電漿處理。
在上述說明中，為了解釋的目的，已闡述了許多細節以提供本技術之各種實施例的瞭解。然而，本領域中具技藝者將理解的是，可在沒有某些這些細節的情況下或在有額外的細節的情況下實行某些實施例。
在已揭露了若干實施例的情況下，將由本領域中具技藝者所辨識的是，可在不脫離實施例之精神的情況下使用各種變體、替代構造及等效物。此外，未描述許多習知的製程及構件以避免不必要地模糊了本技術。據此，不應將以上說明視為限制了本技術的範圍。
若提供了值的範圍，則瞭解的是，亦具體揭露了該範圍之上限及下限之間的各個中介值（揭露到下限的最小的單位小數），除非上下文另有清楚指定。包括了任何經陳述的值之間的任何較窄範圍或經陳述範圍中的未經陳述的中介值及該經陳述範圍中的任何其他經陳述的或中介的值。可獨立地在範圍中包括或排除那些較小範圍的上限及下限，且在較小範圍中包括任一限值、不包括任何限值或包括兩個限值的各個範圍亦被包括在本技術內，取決於經陳述範圍中的任何被具體排除的限值。若經陳述的範圍包括該等限值中的一者或兩者，則亦包括了排除該等經包括之限值中之任一者或兩者的範圍。若在列表中提供了多個值，則類似地具體揭露了包括任何這些值或基於任何這些值的任何範圍。
如本文中及隨附請求項中所使用的，單數形式「一（a）」、「一「an」」及「該」包括了複數的指稱，除非上下文另有清楚指定。例如，因此，對於「一種材料」的指稱包括了複數種此類材料，且對於「該母材」的指稱包括了對於本領域中具技藝者所習知的一或更多種母材及其等效物的指稱等等。
並且，用字「包括（comprise）」、「包括（comprising）」、「包含（contain）」、「包含（containing）」、「包括（include）」及「包括（including）」在被用在此說明書中及以下請求項中時，是要指定經陳述的特徵、整數、元件或操作的存在，但該等用字並不排除一或更多個其他的特徵、整數、元件、操作、行動或群組的存在或添加。
100‧‧‧方法110-130‧‧‧操作305‧‧‧氮化矽區域310‧‧‧碳化矽區域315‧‧‧氧化矽層605‧‧‧托架610‧‧‧RF偏壓電源615‧‧‧DC脈衝電源620‧‧‧腔室控制器625‧‧‧靜電夾具控制器630‧‧‧雙極靜電夾具701‧‧‧腔室703‧‧‧蓮蓬頭705‧‧‧托架710‧‧‧RF偏壓715‧‧‧DC電源720‧‧‧DC脈衝單元725‧‧‧導電環825‧‧‧導電環
可藉由參照本說明書的其餘部分及繪圖來實現所揭露之實施例之本質及優點的進一步瞭解。
圖1繪示依據本技術的實施例來蝕刻基板的方法。
圖2圖示一圖解，繪示依據本技術的實施例之材料變性及低電力電漿的累加效應。
圖3圖示依據本技術的實施例來執行之蝕刻製程的成像。
圖4圖示一圖表，繪示在使用及不使用依據本技術的實施例的處理的情況下的各種材料的蝕刻速率。
圖5圖示一圖表，繪示在使用及不使用依據本技術的實施例的處理的情況下的碳氧化矽及碳化矽的蝕刻速率。
圖6圖示依據本技術的實施例之向靜電夾具提供DC脈衝之控制器的部分示意說明。
圖7圖示依據本技術的實施例之向導體提供DC脈衝之控制器的部分示意說明，該導體與處理腔室內的托架結構耦合。
圖8圖示依據本技術的實施例之向導體提供DC脈衝之控制器的部分示意說明，該導體與處理腔室的蓮蓬頭耦合。
在隨附的圖式中，類似的元件及/或特徵可具有相同的數字參考標示。進一步地，可藉由在參考標示之後加上一字母來區隔相同類型的各種元件，該字母在類似的元件及/或特徵之中進行區隔。若在本說明書中僅使用第一數字參考標示，則該說明適用於具有相同第一數字參考標示之類似元件及/或特徵中的任何一者而不論字母字尾。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
605‧‧‧托架
610‧‧‧RF偏壓電源
615‧‧‧DC脈衝電源
620‧‧‧腔室控制器
625‧‧‧靜電夾具控制器
630‧‧‧雙極靜電夾具

Claims (20)

  1. 一種執行一選擇性蝕刻的方法，該方法包括以下步驟： 使一半導體基板上的一材料變性，該半導體基板在該半導體基板的一表面上具有至少兩種受暴材料； 在收容該半導體基板的一處理腔室內形成一低電力電漿，其中該低電力電漿為一射頻（RF）電漿，且其中該低電力電漿至少部分地是由一RF偏壓電源所形成，該RF偏壓電源在約10 W及100 W之間下及在低於約5,000 Hz的一脈衝頻率下運作；及 相較於該半導體基板之該表面上之該至少兩種受暴材料中的一第二種材料以一較高的速率蝕刻該半導體基板之該表面上之該至少兩種受暴材料中的一種受暴材料。
  2. 如請求項1所述之方法，其中該變性步驟包括以該RF偏壓電源從該處理腔室內的一母材形成一電漿。
  3. 如請求項2所述之方法，其中該母材是選自由以下所組成之群組：氧、氫或氦。
  4. 如請求項1所述之方法，其中該半導體基板之該表面上之該至少兩種受暴材料中的各者是選自由以下所組成之群組：氧化矽、氮化矽、碳化矽及碳氧化矽。
  5. 如請求項1所述之方法，其中至少部分地形成該低電力電漿的該RF偏壓電源在低於約50%的一工作週期下運作。
  6. 如請求項1所述之方法，其中形成該低電力電漿的步驟更包括利用低於約100W的一RF源電源。
  7. 如請求項1所述之方法，其中形成該低電力電漿的步驟更包括利用一脈衝式DC電源。
  8. 如請求項7所述之方法，其中該脈衝式DC電源施用於支撐該半導體基板的一雙極靜電夾具。
  9. 如請求項7所述之方法，其中該脈衝式DC電源施用於一導電環，該導電環嵌在支撐該半導體基板之一托架的一罩環中或嵌在該處理腔室內的一蓮蓬頭中。
  10. 一種從一半導體基板移除材料的方法，該方法包括以下步驟： 使一半導體基板上的一材料變性，該半導體基板在該半導體基板的一表面上具有至少兩種受暴材料，其中該變性步驟包括以一RF偏壓電源從一母材形成一電漿以產生使該材料變性的電漿溢流； 在收容該半導體基板的一處理腔室內形成一低電力電漿，其中該低電力電漿為一射頻（RF）電漿，且其中該低電力電漿是由一脈衝式RF偏壓電源所形成的，該脈衝式RF偏壓電源在約20%及50%之間的一工作週期下在約500 Hz及約2,000 Hz之間的一脈衝頻率下在約20 W及50 W之間下運作； 與該RF偏壓電源脈衝在一交流頻率上操作一DC脈衝式電源；及 相對於該半導體基板之該表面上之該至少兩種受暴材料中的一第二種材料以至少約20:1的一選擇性蝕刻該半導體基板之該表面上之該至少兩種受暴材料中的一種受暴材料。
  11. 如請求項10所述之方法，其中該變性步驟包括一化學變性，該化學變性對於該半導體基板上的該材料造成一化學變化。
  12. 如請求項10所述之方法，其中該變性步驟包括利用一惰性母材的一物理變性。
  13. 如請求項12所述之方法，其中該物理變性包括以該惰性母材的離子損傷該半導體基板上之該材料的鍵結。
  14. 如請求項10所述之方法，其中形成該低電力電漿的步驟更包括利用以最高約100 W運作的一RF源電源。
  15. 一種基板處理腔室，包括： 一托架，被配置為支撐一半導體基板； 一RF偏壓電源，與該托架電耦合，且被配置為以約20 W及約50 W之間的一功率在該處理腔室內生成一電漿，其中該偏壓電源為被配置為使用低於約5,000 Hz的一頻率發出脈衝的一脈衝電源；及 一DC脈衝電源，與該基板處理腔室電耦合，且被配置為產生用於該RF偏壓電漿的引火粒子。
  16. 如請求項15所述之基板處理腔室，其中該DC脈衝電源供應器被配置為在不發展一電漿鞘的情況下以一頻率發出脈衝以產生引火粒子。
  17. 如請求項16所述之基板處理腔室，其中該DC脈衝電源供應器被配置為在小於約50%的一工作週期下啟動脈衝100微秒或更少的一持續時間。
  18. 如請求項15所述之基板處理腔室，其中該托架包括一雙極靜電夾具，且其中該DC脈衝電源施用於該雙極靜電夾具的電接地。
  19. 如請求項15所述之基板處理腔室，其中該托架包括一靜電夾具，且其中該DC脈衝電源與一導電環電耦合，該導電環與該托架耦合，其中該導電環與該靜電夾具及該RF偏壓電解耦。
  20. 如請求項15所述之基板處理腔室，其中該DC脈衝電源與嵌在該基板處理腔室內之一蓮蓬頭中的一導電環電耦合。
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