CN109417028A - 使用材料改性及rf脉冲的选择性蚀刻 - Google Patents

使用材料改性及rf脉冲的选择性蚀刻 Download PDF

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CN109417028A
CN109417028A CN201780039924.4A CN201780039924A CN109417028A CN 109417028 A CN109417028 A CN 109417028A CN 201780039924 A CN201780039924 A CN 201780039924A CN 109417028 A CN109417028 A CN 109417028A
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semiconductor substrate
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巴尔加夫·西特拉
殷正操
斯里尼瓦斯·内曼尼
维亚斯拉夫·巴比扬
迈克尔·斯托厄尔
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Abstract

半导体系统及方法可包括执行选择性蚀刻的方法，所述方法包括以下步骤：使半导体基板上的材料改性。该半导体基板可在该半导体基板的表面上具有至少两种暴露的材料。所述方法可包括以下步骤：在容纳该半导体基板的处理腔室內形成低功率等离子体。该低功率等离子体可为射频(“RF”)等离子体，该射频等离子体在实施方式中可至少部分地由RF偏压电源所形成，该RF偏压电源在约10W及约100W之间运作。该RF偏压电源亦可用低于约5,000Hz的一频率发出脉冲。这些方法亦可包括以下步骤：相较于该半导体基板的该表面上的所述至少两种暴露的材料中的第二种材料以更高的蚀刻速率蚀刻该半导体基板的该表面上的所述至少两种暴露的材料中的一种暴露的材料。

Description

使用材料改性及RF脉冲的选择性蚀刻
技术领域
本技术涉及用于处理半导体材料的系统及方法。更具体而言，本技术涉及用于产生低功率等离子体的半导体材料改性及硬件改性。
背景技术
可能由在基板表面上产生错综复杂地图案化的材料层的工艺来制作集成电路。在基板上产生经图案化的材料的步骤需要用于施用及移除材料的受控方法。对于移除而言，化学蚀刻用于各种用途，包括将光刻胶中的图样转移进下层的层、使层薄化或已经存在于表面上的的特征侧向尺度薄化。通常想要拥有一种蚀刻一种材料比另一材料蚀刻得更快的蚀刻工艺，例如此举促进图样转移工艺。这类蚀刻工艺被称为对于第一材料是有选择性的。材料、电路及工艺的多样性的结果是，已研发了对于各种材料具有选择性的蚀刻工艺。
可基于工艺中所使用的材料而将蚀刻工艺称为是湿式或干式。湿式HF蚀刻相较于其他介电质及材料而言优先移除氧化硅。然而，湿式工艺可能在穿透某些受限的沟道时有困难，且亦可能有时使其余材料变形。在基板处理区域内所形成的局部等离子体中所产生的干式蚀刻可穿透更加受限的沟道且展现了精巧的其余结构较少的变形。然而，局部的等离子体可能在它们放电时经由产生电弧而损伤基板。此外，等离子体流出物可能损伤可能需要替换或处理的腔室部件。
因此，存在着对于可用以产生高品质设备及结构的改良的系统及方法的需要。本技术解决这些及其他的需要。
发明内容
半导体系统及方法可包括执行选择性蚀刻的方法，所述方法包括以下步骤：使半导体基板上的材料改性。该基板可在该半导体基板的表面上具有至少两种暴露的材料。所述方法可包括以下步骤：在容纳该半导体基板的处理腔室内形成低功率等离子体。该低功率等离子体可为射频(“RF”)等离子体，该射频等离子体在实施方式中可至少部分地由RF偏压电源所形成，该RF偏压电源在约10W及约100W之间运作。该RF偏压电源亦可使用低于约5,000Hz的频率发出脉冲。所述方法亦可包括以下步骤：以高于该半导体基板的该表面上的所述至少两种暴露的材料中的第二种材料的蚀刻速率蚀刻该半导体基板的该表面上的所述至少两种暴露的材料中的一种暴露的材料。
在实施方式中，该改性操作可包括以该RF偏压电源从该处理腔室内的前驱物形成等离子体。在实施方式中，该前驱物可选自由以下所组成的群组：氧、氢或氦。此外，该半导体基板的该表面上的所述至少两种暴露的材料中的各者可选自由以下所组成的群组：氧化硅、氮化硅、碳化硅及碳氧化硅。
对于蚀刻操作而言，该RF偏压电源可至少部分地形成该低功率等离子体且低于约50％的工作周期下运作。并且，形成该低功率等离子体的步骤可进一步包括利用低于约100W的RF源功率。在实施方式中，形成该低功率等离子体的步骤亦可包括利用脉冲式DC功率。该脉冲式DC功率可施用于支撑该半导体基板的双极静电夹具。在实施方式中，该脉冲式DC电源可施用于导电环，该导电环嵌入在支撑该半导体基板的托架的屏蔽环中或与该处理腔室内的喷头耦合。
本技术亦包括了从半导体基板移除材料的方法。所述方法可包括以下步骤：使半导体基板上的材料改性，该半导体基板在该半导体基板的表面上具有至少两种暴露的材料。该改性步骤可包括：用RF偏压电源从前驱物形成等离子体以生成使该材料改性的等离子体流出物。所述方法亦可包括以下步骤：在容纳该半导体基板的处理腔室内形成低功率等离子体。该低功率等离子体在实施方式中可为射频(RF)等离子体。该低功率等离子体可由脉冲式RF偏压电源来形成，该脉冲式RF偏压电源在约500Hz及约2,000Hz之间的脉冲频率下在约20W及50W之间下运作。该脉冲式RF偏压电源亦可在约20％及50％之间的工作周期下运作。所述方法可包括以下步骤：与该RF偏压电源脉冲在交流频率上操作DC脉冲式电源。所述方法可进一步包括以下步骤：相对于该半导体基板的该表面上的所述至少两种暴露的材料中的第二种材料，以至少约20:1的选择性蚀刻该半导体基板的该表面上的所述至少两种暴露的材料中的一种暴露的材料。
在所述方法中，该改性操作包括化学改性，该化学改性对该半导体基板上的该材料造成化学变化。该改性步骤亦可包括利用惰性前驱物的物理改性。在实施方式中，该物理改性可包括以该惰性前驱物的离子损伤该半导体基板上的该材料的键结。形成该低功率等离子体的该操作可进一步包括利用多达约100W运作的RF源功率。
本技术亦包括了基板处理腔室，所述基板处理腔室包括被配置为支撑半导体基板的托架。所述腔室可包括RF偏压电源，该RF偏压电源与该托架电耦合且被配置为在实施方式中以约20W及约50W之间的功率在该处理腔室内生成等离子体。该RF偏压电源可为被配置为使用低于约5,000Hz的频率发出脉冲的脉冲电源。所述基板处理腔室可进一步包括：DC脉冲电源，与该基板处理腔室电耦合，且被配置为产生用于该RF偏压等离子体的引火粒子(priming particles)。此外，该DC脉冲电源供应器可被配置为在不发展等离子体鞘的情况下以一频率发出脉冲以产生引火粒子。
在实施方式中，该DC脉冲电源供应器可被配置为在小于约50％的工作周期下启动脉冲100微秒或更少的持续时间。此外，在实施方式中，该托架可为双极静电夹具，且该DC脉冲电源可施用于该双极静电夹具的电接地。在实施方式中，该DC脉冲电源可与导电环电耦合，该导电环与该托架耦接，且该导电环可与该静电夹具及该RF偏压电解耦。在实施方式中，该DC脉冲电源亦可与导电环电耦合，该导电环嵌入在该基板处理腔室内的喷头中。
此类技术相对于传统的技术可提供许多益处。例如，该技术例如可由于材料改性而允许改良的蚀刻操作选择性。此外，本技术的低功率等离子体相对于传统的技术可产生改良的特征轮廓，且允许在使用强化的等离子体控制的情况下进行改良的前端及后端处理。与以下说明及随附图式结合来更详细地描述这些及其他实施方式以及许多它们的优点及特征。
附图说明
可通过参照本说明书的其余部分及附图来实现所公开的实施方式的本质及优点的进一步了解。
图1图示依据本技术的实施方式来蚀刻基板的方法。
图2示出一图表，该图表图示依据本技术的实施方式的材料改性及低功率等离子体的累加效应。
图3图示依据本技术的实施方式来执行的蚀刻工艺的图像。
图4图示一图表，该图表图示在使用及不使用依据本技术的实施方式的处理的情况下的各种材料的蚀刻速率。
图5图示一图表，该图表图示在使用及不使用依据本技术的实施方式的处理的情况下的碳氧化硅及碳化硅的蚀刻速率。
图6示出依据本技术的实施方式向静电夹具提供DC脉冲的控制器的部分示意说明。
图7示出依据本技术的实施方式向导体提供DC脉冲的控制器的部分示意说明，该导体与处理腔室内的托架结构耦接。
图8图示依据本技术的实施方式之向导体提供DC脉冲之控制器的部分示意说明，该导体与处理腔室的喷头耦接。
在所附的图式中，类似的部件和/或特征可具有相同的数字参考标号。进一步地，可通过在参考标示之后加上字母来区分相同类型的各种元件，该字母在类似的元件和/或特征之中进行区分。若在本说明书中仅使用第一数字参考标号，则该说明适用于具有相同第一数字参考标号的类似部件和/或特征中的任何一者而不论字母字尾。
具体实施方式
在半导体处理中，可基于许多理由而执行蚀刻。在干式蚀刻中，前驱物可流过等离子体而产生用于蚀刻各种半导体材料的自由基等离子体流出物。等离子体流出物包含了被导向待蚀刻的基板表面及材料的离子。在某些蚀刻操作中，例如在使用反应性离子蚀刻法的情况下，离子被导向材料表面，且基于所涉及的能量可从基板表面溅散材料。带有相较于第二材料更快地移除一种材料的目标而设计了其他的蚀刻操作，通常称为选择性蚀刻。为了强化选择性，一个方法可包括以下步骤：减少蚀刻操作的溅散成分。这可部分地通过减少等离子体功率以致减少电子温度来达成。选择性可能随着特征尺寸减少而变得越来越关键。选择性越高，意欲维持的可形成为缓冲剂的材料越少地用于最终产品的目标尺度。甚至随着尺寸持续减少而传统较高的选择性可能是不适合的。例如，即使从意欲维持的材料移除数纳米，设备效能亦可能被负面影响。
可以许多方式产生等离子体，例如包括使用电连接至支撑基板之托架的射频(“RF”)偏压。此偏压电源可与跟腔室的部分耦接的RF源结合使用或替代该RF源，或者可与电感耦合的等离子体源、电容耦合的等离子体源、微波源或可额外地用以产生等离子体流出物的任何其他等离子体源结合工作。藉由替代或附加于源功率而利用偏压电源，可向离子提供方向性以提供更多的各向异性(anisotropic)的或取决于定向的蚀刻。然而，随着离子能量增加，溅散亦可能增加。因为溅散可能是更独立于材料的，这可能减少材料之间的选择性，在这些材料中只有一种材料是要被移除的。据此，目标可能是减少偏压方的等离子体功率以试图改善选择性而减少溅散。
传统的技术可减少来源或偏压处的等离子体功率，但从使等离子体放电的观点来看以及在产生蚀刻时，这些传统技术皆在可减少偏压功率的程度上是受限的。为了使等离子体放电，功率必须超过等离子体所从以产生的流体的击穿电压(breakdown voltage)。对于传统的溅散及脉冲式蚀刻操作而言，辉光放电通常例如产生在低电流、中电压工作状态的500V周围及数千瓦特的功率处。然而，这些功率级(power level)将提供增加的离子能量及伴生的材料溅散，这可能导致较低的选择性。若降低等离子体功率以进一步减少溅散，则可能根本难以产生或维持等离子体，特别是在使用脉冲式等离子体功率的情况下。此外，若偏压功率被减少太多，则虽然可解决溅散，整体的蚀刻可能被减少至零。
本技术通过产生脉冲式的低功率RF等离子体而克服了许多这些问题。可在高达数百瓦特的源功率下及在百万赫兹范围中的脉冲频率下产生传统的所谓的低功率等离子体。这些功率范围不能够产生本技术的选择性，因为这些等离子体的溅散成分仍太明显。另一方面来说，本技术可在使用低于100瓦特运作的脉冲式RF偏压的情况下在各种腔室条件下、在低达约20％的工作周期下及在低达约500Hz的脉冲频率下产生等离子体。在此运作工作状态下，可减少或实质消除溅散，且可产生可能相较于传统技术高达一个数量级改良的蚀刻选择性。本技术可涉及经由材料改性来强化选择性及执行低功率蚀刻的组合。这些工艺可通过以如下两种方式来减少意欲维持的材料的量来强化整体选择性：减少与其他材料相关的蚀刻量以及减少可能负面地溅散或影响材料的任何等离子体效应。
虽然以下说明将例行地识别蚀刻操作，可以理解的是，本技术可被更广泛地应用。这些系统及操作方法可被额外应用于沉积、清洁或可能受益于所述的低功率等离子体的任何其他等离子体操作。据此，本说明书非旨在将应用仅限制在本说明书各处所述的实例。
图1图示依据本技术的实施方式来蚀刻基板的方法100。可在所指出的方法操作之前执行可选的操作，包括图案化、薄膜形成或各种其他已知的工艺操作。该方法可包括以下步骤：在操作110处使半导体基板上的材料改性。基板可在半导体基板的表面上具有至少两种暴露的材料，且可具有三种、四种、五种、六种或更多种不同的暴露的材料。此外，一或多种材料可在选择性蚀刻方法100之前一开始被覆盖，但接着被操作暴露，且因此暴露的薄膜中的一或多者可在实施方式中的蚀刻操作期间被暴露。在实施方式中，可试图移除这些材料中的一或多种。
该方法亦可包括以下步骤：在操作120处在容纳半导体基板的处理腔室内形成低功率等离子体。低功率等离子体在实施方式中可为射频(“RF”)等离子体，然而亦可类似地包括其他的等离子体形成。低功率等离子体在实施方式中可通过在约10W及100W之间下运作的RF偏压电源来至少部分地形成。在实施方式中，RF偏压电源可为脉冲式的，且可在低于约5,000Hz的脉冲频率下运作。该方法可进一步包括以下步骤：在操作130处蚀刻半导体基板表面上的所述至少两个暴露的材料中的一或多种。在实施方式中，蚀刻所述至少两个暴露的材料中的一或多种的步骤可以相较于半导体基板表面上的所述至少两个暴露的材料中的第二种材料处于更高的速率。
改性操作可基于基板表面上的材料以任何数量的方式调谐，且可基于材料性质的识别及这些材料与基板表面上的其他材料是如何地不同。例如，改性操作一开始可识别密度、化学结构、反应本性上的差异或薄膜之间可利用的任何其他特征。可执行一或多种材料的改性以强化或产生薄膜之间可在蚀刻操作中利用的差异。可在实施方式中通过将材料暴露于一或多种前驱物来执行改性。在实施方式中，前驱物可在或可不在与暴露的材料交互作用之前被激发。在实施方式中，改性步骤可包括从处理腔室内的前驱物形成等离子体。取决于被改性的薄膜，等离子体可在约50W到约300W之间。例如，展现较高密度的薄膜在实施方式中可受益于较高的等离子体功率。可在实施方式中用源功率或偏压电源以及两者的组合来产生等离子体，以产生使暴露的材料中的一或多者改性的等离子体流出物。在实施方式中，可以用RF偏压电源形成等离子体。
操作中所利用的前驱物可基于所执行改性的类型而包括一或多种前驱物。前驱物可包括要以一个形式或另一形式与材料反应的一或多种前驱物，或可包括要在物理上变更暴露的材料中的一或多种的一或多种前驱物。亦可在实施方式中利用具有这些效果中的任一者或两者的前驱物组合。在实例中，前驱物可选自包括贵重或惰性元素的元素群组，惰性元素诸如氦、氖、氩、氪、氙及氡。在实施方式中，前驱物亦可选自卤素，包括氟、氯、溴、碘及砹。前驱物亦可选自包括氧的硫族元素，以及包括氢的各种其他反应性及非反应性的前驱物，举例而言。
如上所述，改性操作可包括化学改性或物理改性中的任一者或两者。化学改性可对于半导体基板上的材料中的一或多种造成化学变化。化学变化可包括反应，例如在实施方式中产生材料层的氧化物。化学变化亦可调整材料的键结结构，或可在化学上变更材料的原子或分子，例如，通过移除电子。化学改性亦可涉及致密化相对于待移除的额外材料意欲维持在基板表面上的材料或薄膜。可以用不与基板上的暴露的材料反应的惰性前驱物执行物理改性。例如，物理改性可涉及用惰性前驱物的离子损伤半导体基板上的材料中的一或多种的键结。可以理解的是，改性可涉及化学及物理改性的组合，且所利用的个别前驱物可使得一定量的物理改性及化学改性两者发生。
半导体基板的表面上的材料可包括各种半导体处理中所使用的各种材料。这些材料可包括包含半导体处理中所一般理解的许多元素中的任何元素的金属、介电质、蚀刻停止层及基板材料。例如，这些材料可包括金属，诸如：铜、钨、钛；或其他金属；或含金属的层。这些材料亦可包括含硅的材料，诸如：氧化硅、氮化硅、多晶硅、碳化硅、碳氧化硅、碳氮化硅；或基于其他半导体基体材料的材料，例如镓。
在实施方式中，蚀刻操作中所利用的低功率等离子体可至少部分地产生自与托架电耦合的RF偏压电源，基板被支撑在该托架上。偏压电源在实施方式中可在从约1W到约500W的功率下运作。在实施方式中，偏压电源亦可在从约10瓦特到约250瓦特、从约15瓦特到约200瓦特、从约20瓦特到约150瓦特、从约20瓦特到约100瓦特或从约20瓦特到约50瓦特下运作。偏压电源可运作在此范围中，该范围可提供减少溅散的益处，同时仍使等离子体放电及产生蚀刻结果。例如，随着功率级增加，溅散亦可能由于增加的离子能量而增加，且因此在实施方式中可将功率级维持在约100瓦特以下。另一方面来说，可在实施方式中将功率级维持在约20瓦特以上，因为此临界值以下的功率级可能降低蚀刻能力或减少用以使等离子体放电的能力。这些参数亦可在一定程度上取决于腔室条件，腔室条件包括压力及温度，但仍可在利用下文更详细讨论的技术的脉冲条件下产生稳定的等离子体。
RF偏压电源可在低的工作周期及脉冲频率下运作，以产生低功率等离子体。工作周期在实施方式中可低于约75％，且在实施方式中可低于约70％、低于约65％、低于约60％、低于约55％、低于约50％、低于约45％、低于约40％、低于约35％、低于约30％、低于约25％、低于约20％、低于约15％或低于约10％。基于维持较低的离子能量同时仍有足够的导通时间来产生稳定等离子体的类似理由，RF偏压脉冲工作周期在实施方式中亦可以约10％及约60％之间或约20％及50％之间的工作周期来运作。
用于RF偏压的脉冲频率在实施方式中可低于约10kHz。用于RF偏压的脉冲频率在实施方式中亦可低于约9,000Hz、低于约8,000Hz、低于约7,000Hz、低于约6,000Hz、低于约5,000Hz、低于约4,500Hz、低于约4,000Hz、低于约3,500Hz、低于约3,000Hz、低于约2,500Hz、低于约2,000Hz、低于约1,500Hz、低于约1,000Hz、低于约750Hz或低于约500Hz。脉冲频率亦可在实施方式中被维持在约500Hz及约5,000Hz之间或在实施方式中被维持在约500Hz及约2,000Hz之间。偏压脉冲的频率可影响等离子体前驱物的解离作用，且因此通过调整频率，可调整解离作用。
除了RF偏压电源以外，可在实施方式中使用RF源功率。RF源功率可以最多约1,000W或更少的功率用在蚀刻操作中，且在实施方式中可以最多约500W或最多约100W的功率运作。RF源功率在实施方式中可在低于约100W下运作，且在实施方式中可在约0W及100W之间运作。不同的前驱物可受益于RF源的添加，而其他的前驱物可受益于RF源功率的缺乏。例如，RF源可增加聚合物的解离作用，因此对于例如包括C4F8及C4F6的某些前驱物而言，源功率可解离聚合物且将碳材料沉积在基板上而阻碍了蚀刻操作。据此，使用低的RF源或不使用RF源在某些实施方式中可改良蚀刻。在实施方式中，可取决于受蚀刻的薄膜的类型而在蚀刻操作中利用各种前驱物。可使用的示例性前驱物包括C4F8、C4F6、CF4、Cl2、CH2F2、O2、N2以及可提供用以移除目标材料的蚀刻剂特征的任何其他前驱物。
先前所讨论的RF偏压条件在实施方式中可能带来控制等离子体鞘或维持鞘的均质性的困难。然而，这些条件可在蚀刻工艺期间协助最小化溅散。据此，本技术进一步试图获得在可不受磁性元件或相关联的元件协助的情况下在低功率下运作等离子体上的控制。因为针对特定的工艺调整了压力及运作条件，等离子体在这些条件下可能更难以放电。等离子体生成或气体放电可能部分取决于引火粒子或产生带电粒子作为用以击穿的前驱物的步骤。这些带电粒子被产生来加速放电，这可减少所需的点火电压。在例如先前所讨论的脉冲功率运作期间，包括用以产生引火粒子及将电子维持在等离子体反馈回路中的额外能量源可协助在各种工艺条件期间在低功率下控制等离子体生成。通过提供额外的能量源，等离子体可接着在例如为如上所述的那些功率位准的低的功率级下或较正常功率级更低的功率级下放电。本技术在实施方式中提供了额外的能量源以将高能粒子传回进等离子体引火回路。
各种额外的能量源可用在本技术中，且在一个实例中可包括脉冲式DC电源。脉冲式DC电源可连接至腔室中的各种位置以帮助在用RF偏压电源使低功率等离子体放电之前将等离子体引火。然而，此脉冲式DC电源基本上与传统的DC偏压是不同的。在某些传统的处理中，DC偏压被施用在系统中，包括用作托架上的偏压。在施用DC脉冲时，等离子体将从主体一路形成，且将维持足够长的时间以供将电流容纳在托架处的等离子体鞘中。据此，其将向下崩陷至托架的表面而产生具有某个DC电势量的鞘。此等离子体鞘及电势产生了用于工艺的离子能量，且将由于与DC等离子体相关联的高离子能量而在阴极表面处产生材料溅散。然而，本技术可在形成等离子体鞘之前循环DC脉冲。
在本技术的实施方式中，可起动脉冲式DC电势以将等离子体引火，且接着结束循环以防止在基板表面处形成高电压DC等离子体鞘。因此，传统的DC偏压维持脉冲足够长的时间以发展鞘，这样处于高电压下的且影响了离子的能量。本技术可利用脉冲式DC电源来产生引火粒子以允许低的RF功率在该低的RF功率每次发动脉冲时点燃等离子体。相较于将在高电压DC等离子体鞘中所产生的离子能量，例如由传统的DC偏压所产生的的离子能量，可能在一般击穿电压以下的低的RF功率提供了更低的离子能量。尽管RF偏压的功率是低的，本技术的脉冲式DC电源反而产生了在RF偏压启动循环时允许突增击穿及鞘的发展的引火粒子。结果是较低离子能量下的等离子体鞘，这可相对于传统技术减少或实质减少溅散。通过减少溅散，可如先前所解释地提供较高的选择性。
为了产生脉冲式DC电源的机能，脉冲式DC电源的工作周期可为非常低的，且在实施方式中可与1微秒到约100微秒的导通时间相关联。在实施方式中，导通时间可小于约75微秒、小于约50微秒、小于约30微秒、小于约25微秒、小于约20微秒、小于约15微秒、小于约10微秒、小于约5微秒或小于约1微秒。
在工作周期的意义上，虽然传统的DC偏压可能包括50％以上、75％以上或90％以上的工作周期以产生等离子体鞘，本技术在实施方式中可利用脉冲式DC电源小于约50％的工作周期。脉冲式DC电源的工作周期在实施方式中亦可小于约40％、小于约30％、小于约25％、小于约20％、小于约15％、小于约10％、小于约5％或小于约1％。DC功率亦可在约1％及约50％之间、约1％及约25％之间、约1％及约10％之间或这些值之间或内的任何其他范围的工作周期下发出脉冲。
脉冲式DC电源亦可与RF偏压脉冲在交流或半交流的频率上运作。例如，脉冲式DC电源的频率可使其在RF偏压处于关闭循环的同时处于导通循环，反之亦然。取决于两个电源的工作周期，两个电源中的任一者可在给定的时间运作，或两个电源都可不在给定的时间运作。在实施方式中，两者亦皆可在给定的时间运作。通过利用本技术的减少的工作周期，等离子体鞘可在脉冲式DC电源运作的同时不形成于基板表面处。因此，脉冲式DC电源维持了可用于放电击穿及用以稳定化阻抗以改良系统运作条件的引火粒子，同时不形成鞘或击穿直到RF电源启动循环为止。以此方式，本技术可适应各种压力范围，包括低于约50毫托的压力工作状态以及高达数百毫托或以上的压力工作状态。换言之，本技术控制用于辉光放电击穿的阻抗以移除传统的配置、定向、压力、化学作用等等的阻抗限制。
于下文与其他图式关联而进一步描述的脉冲式DC电源可以许多种方式与系统耦接。例如，且如下文所详细描述的，可将脉冲式DC电源施用于支撑半导体基板的双极静电夹具。此外，可将脉冲式DC电源施用于嵌入在支撑半导体基板的托架的屏蔽环中或与该屏蔽环耦接的导电环。又进一步地，可将脉冲式DC电源施用于嵌入在处理腔室内的喷头中或与该喷头连接的导电环。
参照图2，图2图示一图表，该图表示出依据本技术的实施方式的材料改性及低功率等离子体的累加效应。如所图示的，示例性工艺可包括相对于基板表面上的碳化物薄膜移除氧化物薄膜。如由第一个柱形所示，反应性离子蚀刻法或连续的波形工艺可针对氧化物材料相对于碳化物材料提供低于10:1的选择性。这可能部分地是由于由离子工艺所造成的溅散，该溅散对于所有材料是更具有攻击性的而由此增加了两者的蚀刻速率。并且，反应性离子蚀刻亦可能在蚀刻轮廓中产生圆角，且一旦所需的薄膜已被移除，反应性离子蚀刻亦可能由于离子轰击而蚀刻到下层。据此，反应性离子蚀刻对于选择性处理及维持基板的特征而言不是令人满意的。
如第二个柱形中所示，通过仅利用上述的脉冲式低功率RF偏压等离子体，例如与脉冲式DC电源一起利用，可相对于传统的反应性离子蚀刻工艺改良选择性。该工艺亦可减少或消除由反应性离子蚀刻法所产生的圆角化及下层的层的蚀刻。然而，第三个柱形图示在执行低功率脉冲之前执行材料改性的有协同(synergistic)作用的益处。通过利用两种薄膜改性以及低功率等离子体RF脉冲工艺，选择性相对于反应性离子蚀刻工艺增加了几乎一个数量级。此外，在减少圆角化及下层的层的蚀刻的情况下，蚀刻轮廓被更加改良了。
图3图示依据本技术的实施方式来执行的蚀刻工艺的图像。如左方图像中所示，氮化硅区域305安置在碳化硅区域310之间。在执行如先前所讨论的材料改性及低功率RF蚀刻操作之后，碳化硅区段被移除了，如右方图式中所绘示。实质上维持了氮化硅层305，且仅可观察到最小限度的圆角化。此外，在碳化硅区段310下层的氧化硅层315在蚀刻工艺期间被暴露，但该薄膜能够充当工艺的蚀刻停止物，与由于氧化硅的轰击而会蚀刻进入沟道的反应性离子工艺相反。量测到的效果说明，本技术能够在最小限度地圆角化氮化硅的情况下产生超过50:1的碳化硅对氮化硅的蚀刻选择性。本技术亦能够产生超过70:1的碳化硅对氧化硅的蚀刻选择性。
图4图示一图表，该图表绘示在使用及不使用依据本技术的实施方式的处理的情况下的各种材料的蚀刻速率。本实例图示了在等离子体中利用氧前驱物的材料改性，以使基板表面上暴露的的碳氧化硅、氧化硅、碳化硅及氮化硅改性。在使用及不使用该氧处理的情况下在类似的材料上执行低功率脉冲式RF蚀刻工艺。如所图示的，在不使用材料改性的情况下在低功率蚀刻制程期间以低选择性蚀刻所有四个薄膜。另一方面来说，在氧处理之后，碳氧化硅及碳化硅持续蚀刻，同时氧化硅及氮化硅薄膜被向那些薄膜提供表面强化的氧处理实质维持住及缓冲了。
图5图示一图表，该图表图示在使用及不使用依据本技术的实施方式的处理的情况下的碳氧化硅及碳化硅的蚀刻速率。虽然在图4中所绘示的实例中对含碳的薄膜所执行的氧改性相对于氧化硅及氮化硅而言是成功的，两个含碳的薄膜相对于彼此并不具高的选择性。在图5中，执行了利用碳氧化硅薄膜的较高多孔性的物理改性。碳氧化硅相较于碳化硅而言是更加多孔的薄膜，且化学键结亦是较弱的。此示例的物理改性包括了在等离子体中利用氦前驱物，且接着将薄膜暴露于那些等离子体流出物。虽然氦离子的冲击具有充足的损伤碳氧化硅的化学键的能力，但因为氦对于两个薄膜而言是惰性的，其在化学上并不与材料反应。这进一步弱化了薄膜，在这之后执行低功率RF脉冲蚀刻。如由图式所绘示，在改性之后进行低功率蚀刻移除了碳氧化硅材料同时实质上维持了碳化硅。
由图4及5所图示的实例仅为示例性的，且不是要限制本技术。这些实例仅示出由本技术所包括的材料改性的类型。技术人员将由这些实例容易地理解可如何将材料改性及低功率蚀刻操作应用于各种材料来强化选择性且改良蚀刻轮廓。通过利用本技术，可针对碳氧化硅相对于氧化硅及氮化硅达成大于20:1的选择性。亦可使用依据本技术的各种材料改性及蚀刻来针对氧化硅相对于碳氧化硅、氮化硅及碳化硅达成大于20:1的选择性。亦可使用依据本技术的各种材料改性及蚀刻来针对碳化硅相对于氧化硅、氮化硅及碳氧化硅达成大于20:1的选择性。此外，可使用依据本技术的各种材料改性及蚀刻来针对氮化硅相对于氧化硅、碳氧化硅及碳化硅达成大于20:1的选择性。在实施方式中，任何这些操作的选择性亦可大于或约为25:1、大于或约为30:1、大于或约为35:1、大于或约为40:1、大于或约为45:1、大于或约为50:1、大于或约为55:1、大于或约为60:1、大于或约为65:1、大于或约为70:1、大于或约为75:1、大于或约为80:1、大于或约为85:1、大于或约为90:1、大于或约为95:1、或大于或约为100:1。
参照图6，图6示出依据本技术的实施方式向静电夹具提供DC脉冲的控制器的部分示意说明。该系统可与依据本技术的实施方式的基板处理腔室一起被包括。示例性腔室可为由加州圣克拉拉市的应用材料公司所生产的MesaTM蚀刻系统。部件可包括被配置为支撑半导体基板的托架605。该系统亦可包括与托架电耦合且被配置为如先前所述的产生等离子体的脉冲式RF偏压电源610。脉冲式RF偏压电源610可被配置为以约20W及约50W之间的功率在处理腔室内产生等离子体，且脉冲式RF偏压电源可在低于约5,000Hz的频率下发出脉冲。该系统亦可被配置为在先前所述的任何其他的水平下运作。
该系统亦可包括与基板处理腔室电耦合的DC脉冲电源615。DC脉冲电源615可如先前所述的，且被配置为针对RF偏压等离子体产生引火粒子。在实施方式中，DC脉冲电源可被配置为以一定频率发出脉冲以在不发展等离子体鞘的情况下产生引火粒子。DC脉冲电源可以运作持续先前所述的时间中的任一个时间或用先前所述的工作周期中的任一个工作周期运作，且可被配置为在小于约50％的工作周期下以100微秒或更少的持续时间发出脉冲。DC脉冲电源亦可被配置为在小于约20％的工作周期下以小于约50微秒的脉冲持续期间运作。在实施方式中，DC脉冲电源亦可被配置为在小于约10％的工作周期下以小于约10微秒的脉冲持续期间运作。
如图6中所示，托架605可为静电夹具。腔室控制器620可向静电夹具控制器625提供指令，静电夹具控制器625包括用于双极静电夹具的输入/输出模组630。DC脉冲电源615可如图式中所示的与双极静电夹具630的电接地电耦合。在许多处理腔室中，电极可被偏压至DC电压，且可在DC电源的输出处包括重滤波(heavy filtering)以阻挡RF功率。从而，在电源如配置中所示地发出脉冲时，波形可开始扭曲及衰减。据此，为了克服此问题，静电夹具电源可在脉冲式DC的电压处浮动。因此，静电夹具电极接着参考了脉冲式DC的高电压。换言之，静电夹具电源可接着浮动而在电学上与机器的接地隔离，且静电夹具的接地实质上可在高电压处。静电夹具可接着相对于高电压输出正及负极性。
因此，若脉冲式DC关闭循环或接地，则静电夹具电极会以正或负的方式参考接地。然而，在DC被施用或发出脉冲时，则静电夹具电极会参考所施用的DC电源的功率。为了解释的目的而非作为特定的工艺方案，作为如此配置的非限制性实例，若脉冲式DC电源在1kV下运作，且静电夹具在+/-500伏特下运作，则在DC电源启动循环以如先前所述地协助等离子体生成时，电极会分别处于1500伏特及500伏特。此配置的益处可为，在腔室里面可能不需要用于脉冲式DC电源的额外导体。此外，在实施方式中，DC及RF脉冲可为交替的，且因此尽管DC及RF电源各偏压相同的托架基座它们亦可彼此解耦。
可与静电夹具解耦的额外耦接选项绘示于图7中，图7图示依据本技术的实施方式向与托架结构耦接的导体提供DC脉冲的控制器的部分示意说明。如图式中所图示，基板处理腔室701被图示为具有喷头703及被配置为支撑基板的托架705。该系统可包括如先前所讨论的脉冲式RF偏压710，以及用于静电夹持的DC电源715。可包括额外的DC脉冲单元720，该单元提供如先前所讨论的脉冲式DC电源以提供产生由RF偏压点燃等离子体的引火。在此实例中，DC脉冲电源与导电环725电耦合，该导电环嵌入在托架中或与该托架耦接。此导电环725在实施方式中可与静电夹具解耦及与RF偏压解耦。例如，导电环725可被包括在托架705的介电屏蔽环(包括石英屏蔽环)中，如图示。在实施方式中，导电环可为任何导电材料，包括金属或碳化硅。在此方案中，虽然因为导电环与其他电源解耦而在系统中包括了额外的导体，这些部件并不需要相对于彼此在电学上浮动。
可与静电夹具解耦的另一耦接选项绘示于图8中，图8示出依据本技术的实施方式向处理腔室的喷头内的嵌入式导体提供DC脉冲的控制器的部分示意说明。如所图示的，示出与针对图7所讨论的那些部件类似的部件，包括基板处理腔室701，该基板处理腔室包括喷头703及托架705，举例而言。该系统类似地包括脉冲式RF偏压710、用于静电夹持的DC电源715及DC脉冲单元720。图式额外包括了导电环825，该导电环可为上文所讨论的类似材料，但在实施方式中可与喷头703耦合。此耦合选项亦将脉冲式DC与其他电源解耦。
亦可在实施方式中包括与腔室壁耦接或嵌入在该腔室壁中的耦接环，或与腔室系统的其他元件耦接或嵌入在这些其他部件中的耦接环。通过以任何这些选项或如将容易地理解到类似地包括的替代选项提供脉冲式DC电源，该系统相较于传统系统可产生更低功率的等离子体。通过提供能量来产生高能粒子而允许低功率的脉冲RF偏压更容易以较低的离子能量在较低的电压下使等离子体放电，可针对蚀刻、沉积、清洁或可受益于低功率等离子体的任何其他工艺提供改良的等离子体处理。
在上述说明中，为了解释的目的，已阐述了许多细节以提供本技术的各种实施方式的了解。然而，本领域技术人员将显而易见的是，可在没有某些这些细节的情况下或在有额外的细节的情况下实行某些实施方式。
在已揭露了若干实施方式的情况下，将由本领域技术人员所辨识的是，可在不脱离实施方式的精神的情况下使用各种变型、替代构造及等效物。此外，未描述许多公知的工艺及元件以避免不必要地模糊了本技术。据此，不应将以上说明视为限制本技术的范围。
若提供了值的范围，除非上下文另有清楚指定，可以理解的是，亦具体公开了该范围的上限及下限之间的各个中间值，公开到下限的最小的单位小数。涵盖了任何经陈述的值之间的任何较窄范围或在所陈述范围中的未经陈述的中间值及该所陈述范围中的任何其他经陈述的或中间的值。可独立地在范围中包括或排除那些较小范围的上限及下限，且在较小范围中包括任一限值、不包括任何限值或包括两个限值的各个范围亦被包括在本技术内，取决于经陈述范围中的任何被具体排除的限值。若经陈述的范围包括这些限值中的一个或两个，则亦包括了排除这些所包括的限值中的任一个或两个的范围。若在列表中提供了多个值，则类似地具体公开了涵盖这些值中的任一个或基于这些值中的任一个的任何范围。
如本文中及随附权利要求中所使用的，除非上下文另有清楚指定，单数形式“一(a)”、“一(an)”及“该”包括了多个的指称。例如，因此，对于“一种材料”的指称包括了多种此类材料，且对于“该前驱物”的指称包括了对于本领域技术人员已知的一或多种前驱物及其等效物的指称等等。
并且，用字“包括(comprise)”、“包括(comprising)”、“包含(contain)”、“包含(containing)”、“包括(include)”及“包括(including)”在被用在此说明书中及以下权利要求中时，旨在指定经陈述的特征、整数、元件或操作的存在，但这些用语并不排除一或多个其他的特征、整数、元件、操作、行动或群组的存在或添加。

Claims (15)

1.一种执行选择性蚀刻的方法，所述方法包括以下步骤：
使半导体基板上的材料改性，所述半导体基板在所述半导体基板的表面上具有至少两种暴露的材料；
在容纳所述半导体基板的处理腔室内形成低功率等离子体，其中所述低功率等离子体为射频(RF)等离子体，且其中所述低功率等离子体至少部分地由RF偏压电源所形成，所述RF偏压电源在约10W及100W之间下及在低于约5,000Hz的脉冲频率下运作；及
相较于所述半导体基板的所述表面上的所述至少两种暴露的材料中的第二种材料以更高的速率蚀刻所述半导体基板所述表面上的所述至少两种暴露的材料中的一种暴露的材料。
2.如权利要求1所述的方法，其中所述改性步骤包括用所述RF偏压电源从所述处理腔室内的前驱物形成等离子体。
3.如权利要求2所述的方法，其中该前驱物选自由以下所组成的群组：氧、氢或氦。
4.如权利要求1所述的方法，其中所述半导体基板的所述表面上的所述至少两种暴露的材料中的各者选自由以下所组成的群组：氧化硅、氮化硅、碳化硅及碳氧化硅。
5.如权利要求1所述的方法，其中至少部分地形成所述低功率等离子体的所述RF偏压电源在低于约50％的工作周期下运作。
6.如权利要求1所述的方法，其中形成所述低功率等离子体的步骤进一步包括利用低于约100W的RF源功率。
7.如权利要求1所述的方法，其中形成所述低功率等离子体的步骤进一步包括利用脉冲式DC功率。
8.如权利要求7所述的方法，其中所述脉冲式DC功率施用于支撑所述半导体基板的双极静电夹具。
9.如权利要求7所述的方法，其中所述脉冲式DC电源施用于导电环，所述导电环嵌入在支撑所述半导体基板的托架的屏蔽环中或嵌入在所述处理腔室内的喷头中。
10.一种从半导体基板移除材料的方法，所述方法包括以下步骤：
使半导体基板上的材料改性，所述半导体基板在所述半导体基板的表面上具有至少两种暴露的材料，其中所述改性步骤包括用RF偏压电源从前驱物形成等离子体以产生使所述材料改性的等离子体流出物；
在容纳所述半导体基板的处理腔室内形成低功率等离子体，其中所述低功率等离子体为射频(RF)等离子体，且其中所述低功率等离子体由脉冲式RF偏压电源所形成，所述脉冲式RF偏压电源在约20％及50％之间的工作周期下在约500Hz及约2,000Hz之间的脉冲频率下在约20W及50W之间下运作；
用所述RF偏压电源脉冲在交流频率上操作DC脉冲式功率；及
相对于所述半导体基板的所述表面上的所述至少两种暴露的材料中的第二种材料，以至少约20:1的选择性蚀刻所述半导体基板的所述表面上的所述至少两种暴露的材料中的一种暴露的材料。
11.如权利要求10所述的方法，其中所述改性步骤包括化学改性，所述化学改性对所述半导体基板上的所述材料造成化学变化。
12.如权利要求10所述的方法，其中所述改性步骤包括利用惰性前驱物的物理改性。
13.如权利要求12所述的方法，其中所述物理改性包括以所述惰性前驱物的离子损伤所述半导体基板上的所述材料的键结。
14.如权利要求10所述的方法，其中形成所述低功率等离子体的步骤进一步包括利用以多达约100W运作的RF源功率。
15.一种基板处理腔室，包括：
托架，被配置为支撑半导体基板；
RF偏压电源，与所述托架电耦合，且被配置为以约20W及约50W之间的功率在所述处理腔室内生成等离子体，其中所述偏压电源为被配置为使用低于约5,000Hz的频率发出脉冲的脉冲电源；及
DC脉冲电源，与所述基板处理腔室电耦合，且被配置为产生用于所述RF偏压等离子体的引火粒子，其中所述DC脉冲电源被配置为在小于约50％的工作周期下启动脉冲100微秒或更少的持续时间。
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