JP5678106B2 - 蓄積電荷シンクを用いてmosfetの線形性を改善することに使用される方法及び装置 - Google Patents
蓄積電荷シンクを用いてmosfetの線形性を改善することに使用される方法及び装置 Download PDFInfo
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Description
蓄積電荷はチャネル内のキャリアの極性に対して逆の極性である。上述のようにチャネル内のキャリアの極性はソース及びドレイン内のキャリアの極性と同一であるので、蓄積電荷120の極性はソース及びドレイン内のキャリアの極性とも逆である。例えば、上述の動作条件の下で、オフ状態のNMOSFETでは正孔(“P”極性を有する)が蓄積し、オフ状態のPMOSFETでは電子(“N”極性を有する)が蓄積する。故に、MOSFETデバイスは、ここでは、該MOSFETがオフ状態で動作するようにバイアスされ、且つチャネルキャリアとは逆の極性を有するキャリアがチャネル領域内に存在するとき、“蓄積電荷レジーム”内で動作しているとして定義される。言い換えると、MOSFETは、該MOSFETがオフ状態で動作するようにバイアスされ、且つソース及びドレインのキャリアの極性とは逆の極性を有するキャリアがチャネル領域内に存在するとき、蓄積電荷レジーム内で動作しているとして定義される。
背景技術にて説明されたように、MOSFETが何れの動作モード(すなわち、エンハンスメントモード、又はディプレッションモード)を用いていようとも、或る状況下で、ソース及びドレインに対してゼロでないゲートバイアス電圧が印加されてMOSFETがオフ状態にされると、ゲートの下に蓄積電荷が発生する。この教示によれば、上述のようにMOSFETがオフ状態にあり、且つソース及びドレインのキャリアの極性とは逆の極性を有するキャリアがチャネル領域に存在するとき、MOSFETは蓄積電荷レジームで動作しているとして定義される。
図2Bは、図1を参照して説明されたSOI型NMOSFET100のような従来のMOSFETを用いて実現された典型的なRFスイッチ回路250を簡略化して示している。RFスイッチ回路の動作及び実装の詳細な説明は米国特許第6804502に記載されている。なお、RFスイッチ回路の教示に関してその全体が参照することによりここに組み込まれる。図2Bに示されるように、従来のRFスイッチ回路250は、5つの分流(シャント)MOSFET260a−260eに動作可能に結合された単一の“パス”すなわち“スイッチング”MOSFET254を含んでいる。
より詳細に後述されるように、この開示はSOI型MOSFETにおける半導体デバイスの線形性を改善する(例えば、高調波歪み及びIMDの悪影響を抑制する)方法及び装置を説明するものである。典型的な一実施形態において、この方法及び装置は、MOSFETデバイスのボディ内の蓄積電荷を削減することによって、MOSFETデバイスの線形性を改善し、高調波歪み及びIMDの影響を制御する。一実施形態において、この方法及び装置は、MOSFETボディに動作可能に結合された蓄積電荷シンク(accumulated charge sink;ACS)を用いて、MOSFETボディ内の蓄積電荷を削減、あるいはその他の方法で制御する。一実施形態において、この方法及び装置はMOSFETデバイスのボディから全ての蓄積電荷を完全に除去する。上述の1つの実施形態において、MOSFETは蓄積電荷レジームで動作するようにバイアスされ、蓄積電荷を完全に除去、削減、あるいはその他の方法で制御し、それにより、さもなければ発生することになる高調波歪み及びIMDを抑制するために、ACSが用いられる。一部の実施形態においては、蓄積電荷を除去あるいはその他の方法で制御することによって線形性も改善され、それによりフローティングボディ型MOSFETのBVDSS特性が改善される。
図3A及び3Bは、この開示に従って蓄積電荷120(図1)を制御するように適応された蓄積電荷制御(ACC)型のSOI型NMOSFET300を簡略化して示す上面図である。典型的な実施形態において、ゲートコンタクト301はゲート302の第1の端部に結合されている。ゲート酸化物(図3Aには示されていないが、図1に示されている)及びボディ312(図3Bに示されている)がゲート302の下に位置している。図示された典型的なNMOSFET300において、ソース304及びドレイン306はN+領域から成っている。この典型的な実施形態において、ACC型NMOSFET300は、P−領域から成る蓄積電荷シンク(ACS)308を含んでいる。ACS308は、やはりP−領域から成るボディ312に結合されており、それと電気的に連通している。電気コンタクト領域310はACS308への電気接続を提供している。一部の実施形態において、電気コンタクト領域310はP+領域から成っている。図3Aに示されるように、電気コンタクト領域310はACS308に結合されており、それと電気的に連通している。
この開示に従って、ACC型のSOI型MOSFETを実現するために使用されるACS308は、構造、機能、動作及び設計において、それを従来技術において周知である所謂“ボディコンタクト”(通常、“ボディコンタクト”がソースに直接接続されるときには、“ボディタイ”と呼ばれるときもある)から区別する新規な特徴を含んでいる。
(1)F.Hameau、O.Rozeau、「Radio-Frequency Circuits Integration Using CMOS SOI 0.25μm Technology」、2002 RF IC Design Workshop Europe、2002年3月19−22日、仏国;
(2)J.R.Cricci等、「Silicon on Sapphire MOS Transistor」、米国特許第4053916号明細書、1977年10月11日;
(3)O.Rozeau等、「SOI Technologies Overview for Low-Power Low-Voltage Radio-Frequency Applications」、Analog Integrated Circuits and Signal Processing、第25巻、pp.93-114、米国、Kluwer Academic出版、2000年11月;
(4)C.Tinella等、「A High-Performance CMOS-SOI Antenna Switch for the 2.5-5-GHz Band」IEEE Journal of Solid-State Circuits、第38巻、第7号、2003年7月;
(5)H.Lee等、「Analysis of body bias effect with PD-SOI for analog and RF applications」Solid State Electron.、第46巻、pp.169-1176、2002年;
(6)J.H.Lee等、「Effect of Body Structure on Analog Performance of SOI NMOSFETs」、Proceedings 1998 IEEE International SOI Conference、1998年10月5−8日、pp.61-62;
(7)C.F.Edwards等、「The Effect of Body Contact Series Resistance on SOI CMOS Amplifier Stages」、IEEE Transactions on Electron Devices、第44巻、第12号、1997年12月、pp.2290-2294;
(8)S.Maeda等、「Substrate-bias Effect and Source-drain Breakdown Characteristics in Body-tied Short-channel SOI MOSFET's」、IEEE Transactions on Electron Devices、第46巻、第1号、1999年1月、pp.151-158;
(9)F.Assaderaghi等、「Dynamic Threshold-voltage MOSFET (DTMOS) for Ultra-low Voltage VLSI」、IEEE Transactions on Electron Devices、第44巻、第3号、1997年3月、pp.414-422;
(10)G.O.Workman、J.G.Fossum、「A Comparative Analysis of the Dynamic Behavior of BTG/SOI MOSFETs and Circuits with Distributed Body Resistance」、IEEE Transactions on Electron Devices、第45巻、第10号、1998年10月、pp.2138-2145;及び
(11)T.-S.Chao等、「High-voltage and High-temperature Applications of DTMOS with Reverse Schottky Barrier on Substrate Contacts」、IEEE Electron Device Letters、第25巻、第2号、2004年2月、pp.86-88;
がある。
図3A及び3BのSOI型NMOSFET300は、図4Aに概略的に示されるように、四端子デバイスとして実現され得る。図4Aの改善されたACC型のSOI型NMOSFET300に示されるように、ゲート端子402は、図3Cに示されたゲート端子302’と同様のものであり、ゲートコンタクト301(例えば、図3A)に電気的に結合されている。ゲートコンタクト301はゲート302(例えば、図3A及び3C)に電気的に結合されている。同様に、ソース端子404は、図3Cのソース端子304’と同様のものであり、ソース304(例えば、図3A−3C)に電気的に結合されている。同様に、ドレイン端子406は、図3Cのソース端子306’と同様のものであり、ドレイン306(例えば、図3A−3C)に電気的に結合されている。最後に、ACC型NMOSFET300は、領域310を介してACS308(例えば、図3A−3B、3D及び3J−3Kを参照)に電気的に結合されたACS端子408を含んでいる。電子デバイス設計及び製造技術の当業者に理解されるように、領域310は一部の実施形態においてACS308への電気的な結合を容易にするために使用され得るものである。何故なら、一部の実施形態において、低濃度にドープされた領域(すなわち、ACS308)に直接的なコンタクトを形成することは困難だからである。ACS端子408は、図3Cに示されたACS端子308’と同様のものである。
図4Hは、AC信号がMOSFETに印加されたときの、SOI型MOSFETのドレイン−ソース間印加電圧に対するオフ状態キャパシタンス(Coff)を示すグラフ460である(プロット460は典型的な1mm幅のMOSFETに関するものであるが、より広いデバイスやより狭いデバイスを用いても同様のプロットが得られる)。一実施形態において、ゲート電圧は−2.5V+Vd/2であり、Vs=0である。第1のプロット462は、蓄積電荷レジーム内で動作し、図1を参照して説明されたように蓄積電荷を有する典型的な従来のNMOSFETのオフ状態キャパシタンスCoffを示している。図4Hに示されているように、従来FETのプロット462に示されたオフ状態キャパシタンスCoffは電圧に依存しており(すなわち、非線形であり)、Vd=0Vでピークを有している。第2のプロット464は、この教示に従って製造され、蓄積電荷がACC型MOSFETから運び出され、それによりACC型MOSFETボディから蓄積電荷が削減、制御且つ/或いは除去される改善されたACC型のSOI型MOSFETのオフ状態キャパシタンスCoffを例示している。図4Hに示されているように、ACC型のSOI型MOSFETのプロット464に示されたオフ状態キャパシタンスCoffは電圧に依存していない(すなわち、非線形である)。
図5Aは、従来技術に従った単極単投(SPST)RFスイッチ回路500の回路図を示している。RFスイッチ回路500は一般的なクラスの周知のRFスイッチ回路の一例である。同様のRFスイッチ回路が以下の同時継続中の米国特許出願及び特許の明細書に記載されている:仮出願番号60/651,736、出願日2005年2月9日、発明名称「UNPOWERED SWITCH AND BLEEDER CIRCUIT」;米国特許第6,804,502号として2004年10月12日に発行され、また仮出願番号60/328,35、出願日2001年10月10日に基づく出願番号10/267,531、出願日2002年10月8日、発明名称「SWITCH CIRCUIT AND METHOD OF SWITCHING RADIO FREQENCY SIGNALS」の継続出願である出願番号10/922,135、出願日2004年8月18日。なお、これらの特許出願及び特許は参照することによりここに組み込まれる。
上述の典型的なRFスイッチ回路の実施形態においては、スイッチ回路は、RF出力へのRF入力信号の選択的な結合又は遮断(すなわち、回路接続を電気的に開くこと)を行う単一のSOI型NMOSFET(例えば、図5Aの単一のSOI型NMOSFET506、及び図5B−5Dの単一のSOI型NMOSFET526)を用いて実現されている。同様に、図5A−5Dを参照して説明された典型的な実施形態においては、単一のSOI型NMOSFET(例えば、図5Aの単一のSOI型NMOSFET508、及び図5B−5Dの単一のACC型のSOI型NMOSFET528)が使用されて、グランドへのRF入力信号のシャント(FETがオン状態)又は遮断(FETがオフ状態)が行われている。米国特許第6804502号(発行日:2004年8月12日、発明名称「SWITCH CIRCUIT AND METHOD OF SWITCHING RADIO FREQUENCY SIGNALS」)には、RF信号の選択的な結合及び遮断を行う積層化されたトランジスタ群を用いて実現された、SOI型NMOSFETを用いたRFスイッチ回路が記載されている。
図7は、この開示に従って蓄積電荷シンク(ACS)を用いてSOI型MOSFETの線形性を向上させる典型的な一方法700を例示している。方法700は段階702で開始し、ACS端子を有するACC型のSOI型MOSFETが、回路内で動作するように構成される。ACS端子は、(図4B、4C、5B及び5Cを参照して説明されたように)SOI型MOSFETのゲート、又は(図4D及び5Dを参照して説明されたように)制御回路に動作可能に結合され得る。他の実施形態においては、ACS端子は、回路又はシステムの設計者に都合の良い如何なる好適な蓄積電荷シンク機構、回路、又はデバイスに動作可能に結合されてもよい。そして、この方法は段階704へと進む。
図8は、この開示に従って製造されるRFスイッチ回路の典型的な一実施形態800を示している。図8に示されているように、この開示に従って製造されるRFスイッチの一部の実施形態は、ACC型MOSFET群それぞれのソースとドレインとに電気的に接続されたドレイン−ソース間抵抗(Rds)を含んでいてもよい。例えば、図8の典型的なスイッチ800は、分流用のACC型のSOI型NMOSFET620、622及び624それぞれのソースとドレインとに電気的に接続されたドレイン−ソース間抵抗(Rds)802、804及び806を含んでいる。続いて、ドレイン−ソース間抵抗Rdsを使用する動機を説明する。
上述のように、SOI型MOSFETのボディ内の蓄積電荷の存在は、フローティングボディ型MOSFETのドレイン−ソース間破壊電圧(BVDSS)特性に悪影響を及ぼし得る。これはまた、例えばRFスイッチング回路などの或る一定の回路で使用されるときにオフ状態のMOSFETの線形性を悪化させるという望ましくない影響を有する。例えば、図9に示された分流SOI型NMOSFET528を考察する。さらに、分流NMOSFET528は、この教示に従って製造されたACC型NMOSFETではなく従来のSOI型NMOSFETで実現されている場合を考える。また、RF伝送配線は50Ω系を使用していると仮定する。信号入力が小さく、且つNMOSFET528がオフ状態で動作しているとき、従来のオフ状態の分流NMOSFET528は、複数のRF信号の存在下で高調波歪み及び/又は相互変調歪みをもたらし得る。これはまた、目に付くほどの信号電力の損失をもたらす。
この開示に係る一実施形態において、上述の典型的なRFスイッチは、完全に絶縁性の基板の半導体・オン・インシュレータ(SOI)技術を用いて実現されてもよい。また、上述のように、広く使用されているシリコン系に加え、この教示に係る一部の実施形態は、シリコンに代えてシリコンゲルマニウム(SiGe)を同等に用いて実現されてもよい。
MOSFETの線形性を改善することに使用される開示された方法及び装置を用いて得られ得る典型的な結果が図10−19に示されている。測定結果は単極六投(SP6T)RFスイッチに関して提示される。RFスイッチ回路設計の当業者に理解されるように、これらの結果は如何なる実用的なRFスイッチ構成にも拡張され得るものであり、故に、結果を示される例示的なSP6Tスイッチに限定されるものではない。
Claims (25)
- 蓄積電荷制御型のフローティングボディ型MOSFET(ACC型MOSFET)という、当該MOSFETが蓄積電荷レジームで動作しているときの当該MOSFETの非線形応答を制御するように適応されたACC型MOSFETであって:
a)フローティングのボディを有するMOSFETであり、選択的に前記蓄積電荷レジームで動作し、前記蓄積電荷レジームで動作するときに前記ボディ内に蓄積電荷が存在するMOSFET;及び
b)前記MOSFETの前記ボディに動作可能に結合された蓄積電荷シンク(ACS)であり、前記MOSFETが前記蓄積電荷レジームで動作するときに前記ボディ内の前記蓄積電荷を制御する蓄積電荷シンク;
を有し、
前記MOSFETはゲート、ドレイン、ソース、及び前記ゲートと前記ボディとの間に配置されたゲート酸化物層を含み、前記ACSは前記MOSFETの前記ソースとは独立に動作され、且つ前記MOSFETは、オフ状態で動作させられ且つ前記ゲート酸化物層に近接する領域で前記ボディ内に電荷が蓄積するとき、前記蓄積電荷レジームで動作する、
ACC型MOSFET。 - 前記MOSFETの前記ボディは、前記ソースと前記ドレインとの間に、ゲート変調される導電性チャネルを含むチャネル領域を有し、前記のソース、ドレイン及びチャネルは、前記MOSFETがオン状態で動作するとき同一極性のキャリアを有し、且つ前記MOSFETは、該MOSFETがオフ状態で動作するようにバイアスされ且つ前記蓄積電荷が前記のソース、ドレイン及びチャネルの前記キャリアの極性と反対の極性を有するとき、前記蓄積電荷レジームで動作する、請求項1に記載のACC型MOSFET。
- 前記蓄積電荷シンクは、前記MOSFETの前記ボディから前記蓄積電荷を除去することによって、前記MOSFETの前記ボディ内の前記蓄積電荷を制御する、請求項1に記載のACC型MOSFET。
- 前記MOSFETは、ベース絶縁基板上に単結晶シリコン膜を接合し且つ電気的に貼り付けることによる直接シリコン接合基板上に製造されている、請求項1に記載のACC型MOSFET。
- 前記蓄積電荷シンクは、およそ1MΩより高いインピーダンスを有する、請求項1乃至4の何れか一項に記載のACC型MOSFET。
- 蓄積電荷制御型のフローティングボディ型MOSFET(ACC型MOSFET)という、当該MOSFETが蓄積電荷レジームで動作しているときに当該MOSFETのボディ内に蓄積される蓄積電荷を制御するように適応されたACC型MOSFETであって:
a)ゲート、ドレイン、ソース、フローティングボディ、及び前記ゲートと前記フローティングボディとの間に配置されたゲート酸化物層を有し、当該ACC型MOSFETは、オフ状態で動作させられ且つ前記ゲート酸化物層の近傍且つ下の領域で前記ボディ内に電荷が蓄積するとき、前記蓄積電荷レジームで動作し、且つ
b)前記フローティングボディの第1の末端部に近接して配置された第1の蓄積電荷シンク(ACS)であり、該ACSは前記フローティングボディと電気的に連通し、該ACSは当該ACC型MOSFETの前記ソースとは独立に動作され、且つ該ACSは当該ACC型MOSFETの前記ボディ内の前記蓄積電荷を制御する、第1の蓄積電荷シンクを有する;
ACC型MOSFET。 - 当該ACC型MOSFETは、NMOSFETであり、且つ前記第1の蓄積電荷シンクに近接して配置され且つそれと電気的に連通した電気コンタクト領域であり、前記第1の蓄積電荷シンクへの電気的な結合を容易にする電気コンタクト領域、を更に有し、前記ソース及び前記ドレインはN+型ドープト領域から成り、前記フローティングボディ及び前記第1の蓄積電荷シンクはP−型ドープト領域から成り、前記電気コンタクト領域は、前記第1の蓄積電荷シンクへのダイオード接続として作用するN+型ドープト領域から成り、それにより所定のバイアス電圧条件の下で前記第1の蓄積電荷シンク及び前記フローティングボディに正の電流が流入することを阻止する、請求項6に記載のACC型MOSFET。
- 前記蓄積電荷シンクは、前記MOSFETの前記ボディから前記蓄積電荷を除去することによって、前記MOSFETの前記ボディ内の前記蓄積電荷を制御する、請求項6に記載のACC型MOSFET。
- 前記蓄積電荷シンクは、およそ1MΩより高いインピーダンスを有する、請求項6に記載のACC型MOSFET。
- 前記蓄積電荷は、当該ACC型MOSFETが前記蓄積電荷レジームで動作しているとき、前記ACS端子にACSバイアス電圧を印加することによって制御され、当該ACC型MOSFETはディプレッションモード型のNMOSFETデバイスから成り、前記ACSバイアス電圧は、ソースバイアス電圧及びドレインバイアス電圧の小さい方に等しく、あるいはそれより負側になるように選択される、請求項6又は7に記載のACC型MOSFET。
- 前記ボディの前記チャネル領域及び前記ゲート酸化物層の上の前記ゲートの末端部に近接して配置されたコンタクト領域重なり領域を更に含み、該重なり領域は、前記ゲート酸化物層の全てが、前記電気コンタクト領域を形成するために使用されるドーパント材料と同一のドーパント材料で完全に覆われることを確実にする、請求項6又は7に記載のACC型MOSFET。
- 当該ACC型MOSFETはT型ゲート構成のACC型MOSFETから成り、前記フローティングボディが、このT型ゲート構成MOSFETの支持部材を形成し、且つ前記第1の蓄積電荷シンクが、このT型ゲート構成MOSFETの被支持部材を形成ており、前記第1の蓄積電荷シンクは、前記フローティングボディの前記第1の末端部に沿って配置され、且つ前記フローティングボディの少なくとも一部に接触している、請求項6に記載のACC型MOSFET。
- 前記蓄積電荷シンクは、およそ1MΩより高いインピーダンスを有する、請求項6に記載のACC型MOSFET。
- 四端子の蓄積電荷制御型のフローティングボディ型MOSFET(四端子ACC型MOSFET)という、当該MOSFETが蓄積電荷レジームで動作するときに当該MOSFETのボディ内に蓄積される蓄積電荷を制御するように適応された四端子ACC型MOSFETであって:
a)ゲート、ドレイン、ソース、フローティングボディ、及び前記ゲートと前記フローティングボディとの間に配置されたゲート酸化物層を有し、当該ACC型MOSFETは、オフ状態で動作させられ且つ前記ゲート酸化物層の近傍且つ下の領域で前記ボディ内に電荷が蓄積するとき、前記蓄積電荷レジームで動作し、且つ
b)前記フローティングボディの末端部に近接して配置され、且つ前記フローティングボディと電気的に連通した蓄積電荷シンク(ACS)を有し;
c)前記ゲートに電気的に結合されたゲート端子、前記ドレインに電気的に結合されたドレイン端子、前記ソースに電気的に結合されたソース端子、及び前記ACSに電気的に結合されたACS端子を有し、前記ACSは当該ACC型MOSFETの前記ソースとは独立に動作され;
前記ボディ内に蓄積される前記蓄積電荷は、当該MOSFETが前記蓄積電荷レジームで動作しているときに、前記ACS端子によって制御される;
四端子ACC型MOSFET。 - 前記のゲート端子及びACS端子は互いに電気的に結合される、請求項14に記載の四端子ACC型MOSFET。
- 前記蓄積電荷は、前記ボディから前記蓄積電荷を除去することによって制御される、請求項15に記載の四端子ACC型MOSFET。
- 前記ゲート端子と前記ACS端子との間にダイオードが結合され、該ダイオードは、当該ACC型MOSFETがオン状態で動作し且つ該ダイオードが逆バイアスされるとき、正の電流が当該ACC型MOSFETの前記ボディに流入するのを阻止する、請求項15に記載の四端子ACC型MOSFET。
- 前記ACS端子は蓄積電荷シンク機構に結合され、前記蓄積電荷シンク機構は、当該ACC型MOSFETが蓄積電荷レジームで動作しているときに、前記蓄積電荷を制御するように選択される選択可能な蓄積電荷シンク(ACS)バイアス電圧を生成する、請求項14に記載の四端子ACC型MOSFET。
- 前記ACSバイアス電圧は、およそ1MΩより高いインピーダンスを有するバイアス源によって供給される、請求項14又は17に記載の四端子ACC型MOSFET。
- 前記のゲート、ドレイン及びソースはそれぞれゲートバイアス電圧、ドレインバイアス電圧及びソースバイアス電圧を有し、前記ACSバイアス電圧は、前記のソースバイアス電圧及びドレインバイアス電圧のうちの小さい方に等しく、あるいはそれより負側になるように選択される、請求項14又は19に記載の四端子ACC型MOSFET。
- 前記のゲート端子及びACS端子は、該ゲート端子と該ACS端子との間に直列に配置されるクランプ回路を介して、互いに電気的に結合される、請求項14又は18に記載の四端子ACC型MOSFET。
- 前記クランプ回路は、ディプレッションモード型のMOSFETに直列に配置されたダイオードと、前記ダイオードに並列接続された交流短絡用キャパシタとを有し、該交流短絡用キャパシタは、前記ダイオードに交流信号が加えられるときに該ダイオードの非線形性が誘起されないことを確実にする、請求項21に記載の四端子ACC型MOSFET。
- フローティングボディ型MOSFETの線形性を制御する方法であって、前記フローティングボディ型MOSFETは、該MOSFETのボディに動作可能に結合された蓄積電荷シンク(ACS)であって該MOSFETがオフ状態で動作しているときに該MOSFETの前記ボディに蓄積する蓄積電荷を制御するように適応された蓄積電荷シンクを含み、当該方法は:
a)所定の回路内で動作するように前記フローティングボディ型MOSFETを構成する段階;
b)蓄積電荷レジームで動作するように前記フローティングボディ型MOSFETをオフにバイアスする段階;及び
c)前記フローティングボディ型MOSFETのソースとは独立に前記ACSを動作させることによって前記蓄積電荷を制御する段階;
を有する、方法。 - 前記のc)前記蓄積電荷を制御する段階は、前記蓄積電荷を除去することを有する、請求項23に記載の方法。
- 前記蓄積電荷シンクは、およそ1MΩより高いインピーダンスを有する、請求項23又は24に記載の方法。
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US11/484,370 US7910993B2 (en) | 2005-07-11 | 2006-07-10 | Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink |
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