TWI669808B - 淺溝槽紋理化區域及相關方法 - Google Patents
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/352—Working by laser beam, e.g. welding, cutting or boring for surface treatment
- B23K26/355—Texturing
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H01L27/144—Devices controlled by radiation
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- H01L27/14625—Optical elements or arrangements associated with the device
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- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
Abstract
本發明提供了光敏裝置及相關聯的方法。例如,在一觀點中,一光敏成像器裝置可包含:一半導體層,該半導體層具有形成至少一接面之多個摻雜區;以及被耦合到該半導體層之一紋理化區,該紋理化區定位成與電磁輻射交互作用。自一系列的淺溝槽隔離特徵形成該紋理化區。
Description
本申請案主張擁有於2013年6月29日提出申請的美國臨時專利申請案序號60/841,326的優先權之權益,本申請案特此引用該專利申請案之完整內容以供參照。
本發明關於淺溝槽紋理化區域及相關方法。
光與半導體材料之交互作用已成為一種重要的創新。矽成像裝置被用於諸如數位相機、光學式滑鼠、視訊攝影機、及細胞式電話等的各種技術。電荷耦合裝置(Charge-Coupled Device;簡稱CCD)被廣泛用於數位成像,且後來被有較佳性能的互補金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor;簡稱CMOS)成像器加以改進。許多傳統的CMOS成像器利用前面照射(Front Side Illumination;簡稱FSI)。在這些例子中,電磁輻射入射到含有CMOS裝置及電路之半導體面。也 使用了背面照射(Back Side Illumination;簡稱BSI)CMOS成像器,且在許多設計中,電磁輻射入射到在CMOS裝置及電路對向之半導體面。通常利用矽製造CMOS感測器,且該等CMOS感測器可將入射的可見光轉換為光電流,且最終轉換為數位影像。然而,用於偵測入射的紅外線電磁輻射之矽基技術是有一些問題的,這是因為矽是一種具有大約1.1電子伏特(eV)的能隙之間接能隙(indirect bandgap)半導體。因此,矽對波長大於大約1100奈米的電磁輻射之吸收是非常低的。
本發明之揭示提供了具有增強光吸收特性之光電裝置,其中包括納入此類裝置及各種相關聯的方法之系統。例如,在一觀點中,提供了一種具有增強電磁輻射吸收之光電裝置。該裝置可包含被耦合到一支承基材之一半導體層、以及被定位在該半導體層與該支承基材之間的一陣列之淺溝槽隔離面特徵,該等面特徵被定位成與通過該半導體層之電磁輻射交互作用。在一觀點中,該半導體層是單晶矽。在另一觀點中,一裝置層可被耦合到該等面特徵的對向面上之該半導體層。
在一觀點中,一第一接合層可被耦合於該半導體層與該支承基材之間。雖然考慮到各種組態,但是在一特定觀點中,第一接合層可被耦合於該支承基材與該等面特徵之間。在另一觀點中,一第二接合層可被定位於該第一接合 層與該支承基材之間。在又一觀點中,一反射層可被配置於該第一接合層與該第二接合層之間。
該等面特徵可具有各種組態,且可在該半導體層與該半導體支承間之各種位置中形成該等面特徵。例如,在一觀點中,可在該支承基材中形成該等面特徵。在另一觀點中,可在該半導體層中形成該等面特徵。此外,在一觀點中,可根據一預定圖案而配置該等面特徵。在一特定觀點中,該預定圖案可以是一至少實質上均勻的網格。在特定觀點中,該預定圖案可以是一不均勻的配置。此外,在一觀點中,該等面特徵可具有一至少實質上一致的高度。在另一觀點中,該等面特徵的高度是不一致的。
此外,考慮到各種架構組態。例如,在一觀點中,可將該裝置在架構上配置成一前面照射光電裝置。在另一觀點中,可將該裝置在架構上配置成一背面照射光電裝置。
在另一觀點中,提供了一種製造光電裝置之方法。該方法可包含下列步驟:使用淺溝槽隔離蝕刻產生一陣列的面特徵;以及將該陣列的面特徵接合於一支承基材與一半導體層之間。在另一觀點中,產生該陣列的面特徵之該步驟可進一步包含下列步驟:在該半導體層的一面的至少一部分上產生該陣列的面特徵。在又一觀點中,產生該陣列的面特徵之該步驟進一步包含下列步驟:在該支承基材的一面的至少一部分上產生該陣列的面特徵。此外,在一觀點中,將該陣列的面特徵接合於該支承基材與該半導體層之間之該步驟可進一步包含下列步驟:將一第一接合層沉 積到該半導體層上;以及將該第一接合層接合到被配置在該支承基材上之一第二接合層。在某些觀點中,在將該半導體層接合到該支承基材之前,可先在該第一接合層及該第二接合層中之至少一接合層上沉積一反射層。在一進一步的觀點中,該方法可包含下列步驟:使該支承基材對向的一面上之該半導體層變薄到自大約1微米至大約10微米的厚度,而產生一初始薄化面,且在該薄化面上形成一裝置層。然後可視需要而進一步處理該半導體,而形成該光電裝置。
200‧‧‧前面照射裝置
202、302‧‧‧半導體層
204、304‧‧‧支承基材
206、208、306、308‧‧‧摻雜區
210、310‧‧‧紋理化層
212‧‧‧電路層
214、312‧‧‧光
300‧‧‧背面照射裝置裝置
402‧‧‧面特徵
404、504‧‧‧材料層
406、506、606‧‧‧空間
408、508、608‧‧‧線
若要進一步了解本發明揭示之本質及優點,請以與各圖式有關之方式參閱前文中對各實施例之詳細說明,在該等圖式中:第1圖根據本發明揭示的一實施例而提供了示出係為波長的函數的紋理化矽與標準矽比較之光吸收資料;第2圖是根據本發明揭示的另一實施例的一影像感測器之一橫斷面圖;第3圖是根據本發明揭示的另一實施例的一影像感測器之一橫斷面圖;第4圖是根據本發明揭示的另一實施例的與一基材相關聯的一紋理化層之一橫斷面圖;第5圖是根據本發明揭示的另一實施例的與該基材相關聯的一紋理化層之一橫斷面圖;以及 第6圖是根據本發明揭示的另一實施例的與該基材相關聯的一紋理化區之一橫斷面圖。
在本說明書中說明本發明的揭示之前,我們先要了解:該揭示不限於本說明書中揭示的特定結構、製程步驟、或材料,而是將延伸到對相關技術具有一般知識者所將認知的該等特定結構、製程步驟、或材料之等效物。我們亦應可了解:只是為了說明特定實施例而使用本說明書中採用的術語,且此種術語之意圖不在於限制。
將根據下文所述之定義而使用下列術語。
請注意,在本說明書及最後的申請專利範圍之用法中,除非前後文中另有清楚的指示,否則單數形式“一”(“a”)及“該”(“the”)包括複數指示對象。因此,提及“一摻雜劑”時,包括一或多種此類摻雜劑,且提及“該層”時,包括意指一或多個此種層。
在本說明書的用法中,可互換地使用使用術語“光”及“電磁輻射”,且術語“光”及“電磁輻射”可意指在紫外線、可見光、近紅外線、及紅外線光譜中之電磁輻射。該等術語可進一步更廣泛地包括諸如無線電波、微波、X射線、及伽瑪射線等的電磁輻射。因此,術語“光”不限於可見光譜中之電磁輻射。本發明所述的光之許多例子特別意指可 見光及紅外線(及/或近紅外線)光譜中之電磁輻射。對於本發明之揭示而言,可見光範圍的波長被視為自大約350奈米至800奈米,且非可見光波長被視為長於大約800奈米或短於大約350奈米。此外,紅外線光譜被視為包括:該光譜的近紅外線部分(其中包括大約800奈米至1100奈米的波長)、該光譜的短波紅外線(“short wave infrared”)部分(其中包括大約1100奈米至3微米的波長)、以及該光譜的中波長至長波長紅外線(mid-to-long wavelength infrared)(或熱紅外線(thermal infrared))部分(其中包括大於大約3微米且可長達大約30微米的波長)。除非另有提到,否則本說明書中將這些紅外線部分一般被統稱為電磁頻譜的“紅外線”部分。
在本說明書的用法中,術語“偵測”意指對電磁輻射的感測、吸收、及/或收集。
在本說明書的用法中,術語“背面照射”意指一種電磁輻射入射到含有裝置電路的一面對向的半導體材料的一面上之裝置架構設計。換言之,電磁輻射在接觸該裝置電路之前,先入射到一半導體材料上,且通過該半導體材料。
在本說明書的用法中,術語“前面照射”意指一種電磁輻射入射到含有裝置電路的半導體材料的一面上之裝置架構設計。換言之,電磁輻射在接觸該半導體材料之前,先入射到該裝置電路上,且通過該裝置電路。
在本說明書的用法中,術語“吸收率”(“absorptance”)意指入射電磁輻射被一材料或裝置吸收的分數。
在本說明書的用法中,術語“紋理化層”及“紋理化面”可被互換使用,且意指一種具有奈米至微米尺寸的面變化的構形之面。可以各種已知的淺溝槽隔離(STI)技術形成此種面構形。請注意,至少在一觀點中特別放棄雷射消熔(laser ablation)技術。雖然該面的特性可根據所採用的材料及技術而是可變的,但是該面可包括微米尺寸的結構(例如,大約1微米至大約10微米。在又一觀點中,該面可包括自大約5奈米及大約10微米之奈米尺寸及/或微米尺寸的結構。在另一觀點中,面結構可自大約100奈米至大約1微米。可將各種準則用來量測此種結構的尺寸。例如,對於像圓錐體的結構而言,將自一結構的峰至該結構與一鄰接結構之間形成的谷量測該等上述的範圍。對於諸如奈米孔(nanopore)等的結構而言,該等上述範圍將是大約的直徑。此外,該等面結構可相互間隔各種平均距離。在一觀點中,各鄰近結構可間隔自大約50奈米至大約2微米的距離。該間隔將自結構的中心點至一鄰近結構的中心點。
在本說明書的用法中,術語“實質上”意指一行動、特徵、特性、狀態、結構、項目、或結果之完全或幾乎完全的程度或等級。本發明被“實質上”包封的一物體意指該物體被完全包封或被幾乎完全包封。在某些情形中,偏離絕對完全的確切容許程度係取決於特定的情境。然而,一般而言,接近完全時將有達到絕對的全面完成時相同的整體結果。“實質上”被用於負面含義而提及一行動、特徵、特 性、狀態、結構、項目、或結果之完全或幾乎完全的缺少時,同樣可使用“實質上”。例如,“實質上沒有”粒子之一成分將完全缺少粒子,或幾乎完全缺少粒子而使效果與完全缺少粒子時的效果相同。換言之,“實質上沒有”一要素或元素的一成分仍然可能實際上含有該項目,只要沒有該項目的可量測效果即可。
在本說明書的用法中,術語“大約”被用來而提供數值域終點的彈性,其方方式為提供某一值可“稍微高於”或“稍微低於”該終點。
在本說明書的用法中,為了便利,可在一共同列表中出現複數個項目、結構元件、成分元件、及/或材料。然而,應將這些列表詮釋為猶如該列表之每一成員被識別為一獨立的及唯一的成員。因此,不應在沒有相反指示下只根據該列表的任何個別成員及相同列表的任何其他成員出現在一共同組中,就將該個別成員視為該任何其他成員之事實上的等效物。
本說明書中可以一範圍格式表示或呈現濃度、量、及其他數值資料。我們應可了解:只是為了便利及簡潔而使用該範圍格式,且因而應彈性地詮釋為不只是包括被明確地陳述為該範圍的界限之數值,而且也包括該範圍內包含的所有個別數值或子範圍,猶如每一數值及子範圍被明確陳述一般。舉例而言,應將“大約1至大約5”的數值範圍詮釋為:不只是包括大約1至大約5之被明確陳述的值,而且也包括該所示範圍內之個別數值及子範圍。因此,該 數值範圍中包括諸如2、3、及4等的個別值、以及諸如自1至3、自2至4、及自3至5等的子範圍,且個別地包括1、2、3、4、及5。
該相同的原則適用於只以最小值或最大值之方式陳述數值的範圍。此外,不論所述特性的範圍之幅度有多大,都應適用此種詮釋。
傳統的矽光偵測成像器有有限的光吸收/偵測特性。例如,此類矽基偵測器對紅外光可能是大部分透明的,且薄矽層尤其是如此。在某些例子中,可將諸如砷化銦鎵(InGaAs)等的其他材料用於偵測波長大於大約1000奈米的紅外光,而矽通常仍然被用於偵測可見光譜(亦即,350奈米至800奈米波長的可見光)中之波長。傳統的矽材料需要用於偵測來自波長大於大約700奈米的電磁輻射的光子之相當長的光程長度。因此,可能在矽中之較淺的深度上吸收了可見光,且在標準晶圓深度(例如,大約為750微米)的矽中對較長波長(例如,900奈米)的吸收是很差的。為了可吸收較長的波長而增加矽層的厚度時,將因而大幅增加光偵測成像器的厚度。
根據本發明揭示的觀點之光電裝置由於較長光波長的有效光程長度比傳統裝置增加了,因而呈現增加的光吸收。傳統矽偵測器中之吸收深度是輻射強度減少到半導體面上的輻射強度值的大約36%之矽深度。採用本發明的矽 材料時之光子的增加之光程長度導致吸收深度的明顯減少、或減少之表觀或有效吸收深度。例如,矽的有效吸收深度可被減少到使這些較長的波長可在厚度小於850微米的矽層中被吸收。換言之,藉由增加光程長度,這些裝置能夠在較薄的矽材料內吸收較長的波長(例如,矽可吸收大於1000奈米的波長)。除了在薄矽材料(與700微米厚度比較下之小於30微米厚度之矽材料)中吸收較長波長的光之外,亦可利用此種薄材料增加響應速率(response rate)或響應速度(response speed)。
本發明揭示之光電裝置可以是前面照射(FSI)或背面照射(BSI)裝置。在一典型的FSI成像器中,入射光先經過電晶體及金屬電路,而進入半導體裝置。然而,光在進入成像器的光感測部分之前,可能先自該等電晶體及電路散射,因而導致光損耗(optical loss)及雜訊。因而可將一透鏡配置在FSI像素的上面,以便將該入射光導引且聚焦到該裝置的光感測有效區,因而至少部分地避開該電路。可考慮各種透鏡及透鏡組態,然而,在一觀點中,該透鏡可以是一微透鏡(micro-lens)。
另一方面,BSI成像器被配置成使入射光經由該電路對向的該光敏區而進入該裝置,且使紅外光先被大部分地吸收,然後才抵達該電路,因而大幅減少散射及/或雜訊。BSI設計亦可使成像器具有較大的靈敏度、較小的像素架構、及高填充係數(fill factor)。此外,我們亦應可了解:根據本發明揭示的觀點之裝置不論其為FSI或 BSI,都可被包含到互補金屬氧化物半導體(CMOS)成像器架構或電荷耦合裝置(CCD)成像器架構。
一般而言,且在沒有限制的情形下,本發明之揭示提供了諸如寬頻光敏二極體、像素、以及能夠偵測可見光及紅外線電磁輻射之成像器等的各種光電裝置,且包括提供了製造此種裝置之相關方法。例如,在一特定觀點中,提供了一種可加強吸收的電磁輻射光電裝置。該裝置可包含被耦合到一支承基材之一半導體層、以及被定位在該半導體層與該支承基材之間的一陣列之淺溝槽隔離面特徵,該等面特徵被定位成與通過該半導體層之電磁輻射交互作用。
因而已發現以一種在架構上適當之方式定位的該陣列之淺溝槽隔離面特徵可大幅增加矽材料的光吸收。例如,如第1圖所示,與無紋理化矽比較時,該紋理化區域可在至少大約700奈米至大約1100奈米的電磁頻譜範圍中增加矽的光吸收。
如第2圖所示,圖中示出一FSI裝置200,該FSI裝置200具有被耦合到一支承基材204之一半導體層202,其中該半導體層可包含用來形成至少一接面之一或多個摻雜區206、208。包含一陣列或複數個STI面特徵之一紋理化層210被定位在半導體層202與支承基材204之間。一電路層212被耦合到支承基材204的一對向面上之半導體層202。圖中示出光214照射在裝置200上,且先通過電路層212,然後才接觸半導體層202。並未被吸收且然 後通過半導體層202之光214接觸紋理化層210,而且被改向回到半導體層202,因而可讓光在後續的過程中被吸收。因此,當光214通過該裝置時,紋理化層210增加了光214的有效光程長度。在一觀點中,該半導體層可以是單晶矽。
請參閱第3圖,圖中示出一BSI裝置300,該BSI裝置300具有被耦合到一支承基材304之一半導體層302,其中該半導體層可包含用來形成至少一接面之一或多個摻雜區306、308。在此種情形中,支承基材304可以是一電路層、或包含一電路層之一基體基材。包含一陣列或複數個面特徵之一紋理化層310被定位在半導體層302與支承基材304之間。圖中示出光312照射在裝置300上,且在不接觸可被定位在支承基材304中或上的任何電路元件之情形下通過半導體層302。並未被吸收且然後通過半導體層302之光312接觸紋理化層310,而且被改向回到半導體層302。如同第2圖所示之FSI裝置,當光312通過該裝置時,紋理化層310增加了光312的有效光程長度。在一觀點中,該半導體層可以是單晶矽。
該FSI及BSI例子中之該等多個摻雜區可根據該裝置而具有相同的摻雜分佈(doping profile)或不同的摻雜分佈。此外,任何數目或任何組態的摻雜區被視為在本發明的範圍內。在某些觀點中,該半導體層可被摻雜,因而可被視為一摻雜區。
此外,該裝置可包含深溝槽隔離(Deep Trench Isolation;簡稱DTI),用以隔離該成像器,且提供光補捉(light trapping)功能。在某些觀點中,該裝置除了該支承基材之外可包含一矽操作晶圓(handle wafer),用以協助對該裝置的操縱。在某些觀點中,該支承基材可以是一矽操作晶圓。將一矽操作晶圓耦合到該半導體層的一種技術包括氧化物接合(oxide bonding)。可在美國專利申請案序號13/069,135中找到與基材、接合、及各種成像器細節有關之進一步細節,且本發明特此引用該專利申請案以供參照。
根據本發明揭示的觀點之光電裝置可包含能夠吸收特定波長範圍內的電磁輻射光電二極體或像素。此類成像器可以是被動式像素感測器(Passive Pixel Sensor;簡稱PPS)、主動式像素感測器(Active Pixel Sensor;簡稱APS)、或數位像素感測成像器(Digital Pixel Sensor Imager;簡稱DPS)等的成像器。此類裝置亦可在架構上被配置成三或四電晶體主動式像素感測器(3T APS或4T APS)。此外,具有4個以上的電晶體之裝置也是在本發明的範圍內。此類裝置亦可包含被用於CMOS成像器之針扎光電二極體(pinned photodiode)架構。此外,此類光電裝置亦可被用於飛行時間(Time-Of-Flight;簡稱TOF)應用、以及各種結構化燈光(structured light)應用。也考慮到可將此類裝置配置為滾動快門(rolling shutter)或全域快門(global shutter)讀出裝置。
在某些觀點中,一裝置可包含被定位在該紋理化層與 該等摻雜區間之一鈍化層(passivation layer)。在某些觀點中,如將於下文中更完整地說明的,可摻雜該鈍化層而產生一表面場(surface field)。請注意,不論是否設有該鈍化區,都可將該紋理化區設置在該半導體材料的光入射面、該半導體材料的該光入射面對向之一面、或該光入射面及該光入射面之對向面。此外,該裝置亦可包含被耦合到半導體層且可操作而自該等摻雜區傳輸電信號之一電傳輸元件。此外,一電傳輸元件可包括各種裝置,其中包括(但不限於)電晶體、感測節點、傳輸閘(transfer gate)、及傳輸電極(transfer electrode)等的裝置。
如前文所述,係由複數個面特徵構成該紋理化層,其中已在該半導體層與該支承基材間之一界面上以一陣列或其他群組之方式形成了這些面特徵。在某些觀點中,該紋理化區可覆蓋該半導體層與該支承基材間之整個界面,而在其他觀點中,該紋理化區可以只覆蓋該半導體層與該支承基材間之界面的一部分。例如,在一觀點中,該紋理化層可覆蓋至少在通過該半導體層的光將接觸該界面的區域中之材料間之界面。在另一觀點中,該紋理化層可覆蓋只有在通過該半導體層的光將接觸該界面的區域中之材料間之界面。因此,我們應可了解:該紋理化層之覆蓋區可取決於該裝置的設計、以及所需光補捉及/或光改向的預期圖案。本發明揭示之範圍將不必然受限於該界面包括紋理化層的程度。
此外,在某些觀點中,該半導體層與該支承基材之間 可設有一或多個中間層。這些層可被用於促進接合,被用於反射光,或用於各種其他用途。例如,在一觀點中,一或多個接合層可被用於促進將該支承基材接合到該半導體層。在此類情形中,將一第一接合層施加到該半導體層且將一第二接合層施加到該支承基材作為接合機構,可能是有利的。該接合層可包括能夠促進該支承基材與該半導體層間之接合的材料。非限制性例子可包括二氧化矽、氮化矽、及非晶矽(amorphous silicon)等的材料。特定接合層之厚度又可根據所利用的製造技術及設計者的偏好而改變。然而,在一觀點中,接合層可厚到足以促進接合,且薄到足以將該裝置內之波導效應(waveguide effect)最小化。在另一觀點中,接合層可具有自大約30奈米至大約3微米的厚度。在又一觀點中,接合層可具有自大約40奈米至大約2微米的厚度。
該紋理化層之位置可因而受到該支承基材與該半導體層耦合的本質以及該紋理化層的形成位置之影響。在一觀點中,可在該半導體層中或上形成該紋理化層。在另一觀點中,可在該支承基材中或上形成該紋理化層。對於在該半導體層中或上形成該紋理化層之情況而言,可將一或多個接合層耦合在該支承基材與該紋理化層之間。如果利用兩個或更多個接合層,則可在該紋理化層上形成一第一接合層,可在該支承基材上形成一第二接合層,然後可將該第一及第二接合層接合在一起。
對於在該支承基材中或上形成該紋理化層之情況而 言,可將一或多個接合層耦合在該半導體層與該紋理化層之間。例如,在一觀點中,可將一或多個接合層耦合於該支承基材與該等面特徵之間。如果利用兩個或更多個接合層,則可在該紋理化層上形成一第一接合層,可在該半導體層上形成一第二接合層,然後可將該第一及第二接合層接合在一起。
如前文所述,可在任何兩個上文中提及的層或材料之間額外地配置一光反射層。例如,在一觀點中,可將一反射層施加到該紋理化層的一面。在另一觀點中,可將一反射層施加到一接合層的任一面。在一特定觀點中,可使一反射層定位在一第一與第二接合層之間。該反射層可包含能夠將光反射回到該半導體層的任何材料。非限制性例子可包括金屬、陶瓷、氧化物、玻璃、及分散式布瑞格反射器(distributed Bragg reflector)堆疊等的材料,其中包括該等材料的合金及組合。
可以能夠以一種可重複且可預設的方式蝕刻之製程製造該紋理化層之該等面特徵。然而,在一觀點中,可以任何數目的淺溝槽隔離(STI)技術形成該等面特徵。雖然此類製造技術是已知的,但是先前並未將該等製造技術用於產生各電路元件間之電絕緣區。因此,已將此種實施方式用於電路元件的周圍。然而,本發明之範圍係有關在與光交互作用的位置上的面特徵陣列之產生。利用該交互作用,光可被該面特徵陣列改向、擴散、聚焦、或其以其他方式操縱。
此外,STI技術可被用於形成有各種形狀及圖案等的特性之此類面特徵。例如,在一觀點中,可根據一預定圖案而將該等面特徵配置到一陣列中。在一特定觀點中,該預定圖案可以是一均勻的或實質上均勻的網格。此外,預定圖案可以是一有組織的、整齊的、或週期性的圖案。在另一觀點中,該預定圖案可以是一不均勻的或實質上不均勻的圖案。面特徵陣列之圖案也可以是雜亂的、準週期性的(quasi-periodic)、或隨機的等的圖案。
如前文所述,該紋理化層可被用於擴散光,使光改向,且因而增加該裝置的量子效率(quantum efficiency)。在某些例子中,一部分的光通過該半導體層而接觸該紋理化層。該紋理化層之該等面特徵因而有助於增加該半導體層之有效光程長度。這些面特徵可以是微米尺寸的及/或奈米尺寸的,且可以是可經由STI技術而形成的任何形狀或組態。這些形狀及組態之非限制性例子包括圓錐形、柱形、角錐形、倒轉的特徵、溝槽、及突出構造等的形狀及組態,其中包括該等形狀及組態之組合。此外,諸如特徵尺寸、維度、材料類型、摻雜分佈、紋理位置等的因素之操縱可讓特定波長或特定範圍的波長穿隧通過該紋理化層。在一觀點中,調整該裝置時,可讓特定波長或特定範圍的波長被吸收。在另一觀點中,調整該裝置時,可讓特定波長或特定範圍的波長經由濾波而被減少或消除。
根據本發明揭示的觀點之紋理化層可讓該裝置內之半導體層經歷多次光(尤其是較長波長的光(亦即,紅外 線))通過。此種內反射(internal reflection)可增加有效光程長度,因而可是諸如矽等的材料在小於標準矽的厚度下吸收光。如前文所述,以此種方式增加矽中之電磁輻射的有效光程長度時,將增加該裝置的量子效率,因而導致較佳的信號雜訊比。
可根據該裝置之設計及所需特性而改變被用於製造該紋理化層的材料。因此,將可被用於建構紋理化區的任何材料視為在本發明之範圍內。在一觀點中,可在該半導體層(例如,一矽磊晶層)上直接形成該紋理化區。在另一觀點中,可在該半導體層之上沉積一額外的材料,用以支持該紋理化層的形成。此類材料之非限制性例子包括半導體材料、介電材料、矽、多晶矽、非晶矽、及透明導電氧化物等的材料,其中包括該等材料之複合物及組合。在一特定觀點中,該紋理化層可以是一紋理化多晶矽層。因此,可將一多晶矽層沉積到該半導體層之上,且可直接沉積到該半導體層之上或沉積到一中間鈍化層之上,然後使該鈍化層產生紋理,而形成該紋理化區。在另一觀點中,該紋理化層可以是一紋理化介電層。在此種情形中,該紋理化層可以是構成被配置在該半導體層上的一鈍化區的一介電層之一部分。在又一觀點中,該紋理化層可以是一透明導電氧化物或另一半導體材料。在介電層之情形中,該紋理化層可以是一鈍化層的一紋理化部分,或可自被沉積在一鈍化層之上的其他介電材料形成該紋理化層。
可將各種方法用於形成STI特徵,且任何此類淺溝槽 形成技術被視為在本發明的範圍內。請注意,在一觀點中,特別自本發明的範圍中放棄涉及雷射消熔技術之紋理化技術。
在某些情形中,可使用被圖案化的光罩且利用微影技術,然後蝕刻而形成特定結構或圖案,而形成該紋理化層。在一觀點中,STI技術可被用於形成該紋理化區。考慮到了各種STI技術,且任何此類技術被視為在本發明的範圍內。在一非限制性例子中,在將利用淺溝槽蝕刻的材料上沉積一氧化物材料。在該氧化物材料上沉積一氮化物材料的均勻塗層,然後將一光阻材料的一有圖案之塗層用來作為一光罩。因此,該光罩之圖案將界定該紋理化區之未來圖案。然後可將一些蝕刻製程中之任何蝕刻製程施加到該分層材料。因此,在該光阻之下的該分層材料之各區域被保護而不被蝕刻,而並非位於該光阻之下的該分層材料之各區域利用該製程而被蝕刻。該製程持續被執行,而在該光阻材料間之該等未被保護的區域中產生被蝕刻通過該氮化物材料、該氧化物材料且進入該基材的淺溝槽(或洞)。在蝕刻了該淺溝槽之後,可以任何適當的製程去除該光阻材料。請注意,雖然術語“淺溝槽”被用來描述該蝕刻製程,但是所形成的蝕刻圖案不限於溝槽,而是亦可包括洞、坑、及圓錐體等的圖案。
在某些觀點中,可以開放空間之方式留下該等被蝕刻區。在其他觀點中,可執行額外的處理,而填補該等被蝕刻區。例如,可沿著該等溝槽之側面及底部沉積類似於氧 化物襯墊之一氧化物材料。可利用一熱氧化製程、一直接氧化物沉積、或任何其他適用之製程沉積該氧化物材料。一旦該等被蝕刻區被充分地填補之後,可以諸如化學機械研磨(CMP)處理等的技術進一步處理所形成的表面,然後一旦露出該表面之後,可去除該氮化物層。
在另一觀點中,可沿著側壁及/或底部而在一摻雜分佈下以高濃度摻雜該等被蝕刻區,而產生一表面場。背表面場(back surface field)可被用來阻止光生載子(photo-generated carrier)自接面朝向該紋理化層移動,且因而應相應地設計該摻雜分佈。該等電磁輻射中之該背表面場的使用因而可被用於在電氣上鈍化該紋理化層周圍的區域。
該等面特徵可根據所形成的裝置之所需特性而具有各種組態、結構、及尺寸。在一觀點中,例如,如第4圖所示,圖中示出在諸如該半導體層等的一材料層404中形成形成一些面特徵402。該例子中之該等面特徵被均勻地配置成由一系列的空間或洞406以及線408或柱構成之一均勻的網格圖案。考慮到各種均勻的網格圖案,且在一觀點中,根據自該被蝕刻材料的上面或下面檢視,該圖案可包括被一些空間圍繞的一系列被均勻間隔開之柱,或被一些柱圍繞的一系列被均勻間隔開之空間。在另一觀點中,該均勻的網格圖案可包括被一系列均勻間隔的空間或洞圍繞的一系列之線(且係在該等線之間切割出該系列的空間或洞),或被一系列均勻間隔的線圍繞的一系列之空間或洞 (且係在該等線之間切割出該系列的空間或洞)。
此外,如前文所述,面特徵的蝕刻圖案可以是預定的不均勻圖案。例如,如第5圖所示,被蝕刻到材料層504內之空間506是大約相同的尺寸及形狀,且線或柱508的寬度有變化。第6圖示出空間606及線或柱608都有變化之一蝕刻圖案。請注意,考慮到各種蝕刻圖案,且本發明之範圍不應受此限制。關於不均勻圖案,在某些觀點中,該等圖案可以是隨機的,線或柱、空間、或以上兩者都可以是隨機的。
除了STI製程形成的圖案之外,蝕刻的深度也可能影響到光吸收。例如,在一觀點中,該等面特徵可具有均勻的或實質上均勻的深度或高度。雖然該深度或高度可根據該裝置的預期用途及設計而改變,但是在一觀點中,該高度或深度可自大約50奈米至大約2微米。請注意,在標準STI製程中,處理深度是大約0.35微米,且該處理深度也被視為在本發明的範圍內。在另一觀點中,該等面特徵可具有不均勻的深度或高度,且因而深度或高度可在該紋理化層的面上改變。根據該裝置的所需設計,此類變化在某些例子中可以是隨機的,且在其他例子中可以是不隨機的。在一觀點中,該深度或高度可自大約50奈米至大約2微米。在某些觀點中,可使用分離的深度級別。例如,在一觀點中,一級別可具有0.35微米的深度,而另一級別可具有0.7微米的深度。藉由使用不同的光罩,可實現不同的深度級別。同樣地,可蝕刻後續的級別,而產 生一第三級別、一第四級別、或更多的級別。請注意,在某些觀點中,每一級別可具有自大約50奈米至大約2微米的深度。
如前文所述,根據本發明揭示的觀點之各種裝置可呈現比傳統的光敏裝置更多的吸收。例如,對於厚度自大約1微米至大約10微米的根據本發明揭示的觀點之主動半導體層而言,該吸收特性可如下所述:在一觀點中,該半導體層可吸收入射的700奈米光之自大約60%至大約80%;在另一觀點中,該半導體層可吸收入射的850奈米光之自大約40%至大約60%;在又一觀點中,該半導體層可吸收入射的940奈米光之自大約25%至大約40%;在一進一步的觀點中,該半導體層可吸收入射的1000奈米光之自大約15%至大約30%;以及在又一進一步的觀點中,該半導體層可吸收入射的1064奈米光之自大約5%至大約10%。此外,視架構而定,根據本發明揭示的觀點之裝置可呈現對特定波長的光之小於上述吸收值之自大約1%至大約5%之外部量子效率(External Quantum Efficiency)。此外,又請注意,本發明揭示之裝置具有與不具有紋理化區的標準磊晶裝置至少實質上相同之暗電流(dark current)。
雖然本發明之揭示將重點放在矽材料,但是我們應可了解:也考慮使用各種半導體材料,且該等半導體材料應被視為在本發明揭示之範圍內。此類半導體材料之非限制性例子包括四族材料、由二族及六族材料構成之化合物及合金、由三族及五族材料構成之化合物及合金、以及上述 半導體材料之組合。更具體而言,例示之四族材料可包括矽、碳(例如,鑽石)、鍺、以及上述材料之組合。四族材料之各種例示組合可包括碳化矽(SiC)及矽鍺(SiGe)。在一特定觀點中,該半導體材料可以是或可包括矽。例示之矽材料可包括非晶矽(a-Si)、微晶矽(microcrystalline silicon)、多晶矽、及單晶矽、以及其他晶體類型。在另一觀點中,該半導體材料可包括矽、碳、鍺、氮化鋁、氮化鎵、砷化銦鎵、砷化鋁鎵、以及上述半導體材料之組合中之至少一者。在又一觀點中,該半導體材料可包括使用於製造成像器之任何材料,其中包括矽、矽鍺、及砷化銦鎵等的材料,且包括上述材料之組合。
矽半導體層之厚度可以是可進行電磁輻射偵測及轉換功能之任何厚度,且因而矽材料之任何此類厚度被視為在本發明揭示之範圍內。在某些觀點中,該紋理化層增加了該裝置的效率,使該矽材料可以比先前所能達到的厚度更薄。減少該矽材料之厚度時,將減少製造此種裝置所需的矽之量。例如,在一觀點中,該矽材料具有自大約500奈米至大約50微米的厚度。在另一觀點中,該矽材料具有小於或等於大約100微米的厚度。在又一觀點中,該矽材料具有自大約1微米至大約10微米的厚度。在一進一步的觀點中,該矽材料可具有自大約5微米至大約50微米的厚度。在又一進一步的觀點中,該矽材料可具有自大約5微米至大約10微米的厚度。
考慮到將各種摻雜劑材料用於形成該等多個摻雜區且在該等淺溝槽區上產生一表面場,且可被用於該等製程之此類摻雜劑被視為在本發明之範圍內。請注意,可根據被摻雜的材料以及所形成的材料之預期用途而改變所採用之特定摻雜劑。
摻雜劑可以是電荷提供(charge donating)或接受摻雜劑物種。更具體而言,電子提供或電洞提供物種可使一區域的極性變為比該半導體層更正或更負。例如,在一觀點中,該摻雜區可以是p型摻雜。在另一觀點中,該摻雜區可以是n型摻雜。可在該摻雜區上或該摻雜區附近形成一高濃度摻雜區,而產生一針扎二極體。在一非限制性例子中,該半導體層之極性可以是負的,且可分別以p+及n型摻雜劑摻雜一摻雜區及一高濃度摻雜區。在某些觀點中,可使用該等區域的n(--)、n(-)、n(+)、n(++)、p(--)、p(-)、p(+)、p(++)型摻雜。在一觀點中,摻雜劑材料之非限制性例子可包括硫(S)、氟(F)、硼(B)、磷(P)、氮(N)、砷(As)、硒(Se)、碲(Te)、鍺(Ge)、氬(Ar)、鎵(Ga)、銦(In)、銻(Sb)、以及上述材料之組合。
Claims (29)
- 一種具有增強電磁輻射吸收之光電裝置,包含:半導體層,具有光入射面及對向面,該半導體層具有形成至少一個接面之多個摻雜區;紋理化區域,包含複數個淺溝槽隔離面特徵,該複數個淺溝槽隔離面特徵被定位在該半導體層的該光入射面上且組構成與入射的電磁輻射交互作用;支承基材,耦合到該半導體層;以及第一接合層,設置在該半導體層與該支承基材之間。
- 如申請專利範圍第1項之裝置,其中該半導體層是單晶矽。
- 如申請專利範圍第1項之裝置,進一步包含被定位在該第一接合層與該支承基材之間的第二接合層。
- 如申請專利範圍第3項之裝置,進一步包含被設置在該第一接合層與該第二接合層之間的反射層。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵是形成在該半導體層中。
- 如申請專利範圍第1項之裝置,其中根據圖案而配置該複數個淺溝槽隔離面特徵。
- 如申請專利範圍第6項之裝置,其中該圖案是至少實質上均勻的網格。
- 如申請專利範圍第6項之裝置,其中該圖案是不均勻的配置。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵具有至少實質上一致的高度。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵的高度是不一致的。
- 如申請專利範圍第1項之裝置,進一步包含裝置層,該裝置層是在該光入射面對向的該對向面上被耦合到該半導體層。
- 如申請專利範圍第1項之裝置,進一步包含深溝槽隔離,用於隔離該裝置。
- 如申請專利範圍第12項之裝置,其中該深溝槽隔離提供光補捉功能。
- 如申請專利範圍第1項之裝置,其中該第一接合層包括氧化矽、氮化矽及非晶矽其中任何一種。
- 如申請專利範圍第1項之裝置,其中該半導體層具有大約1微米至大約10微米之範圍的厚度。
- 如申請專利範圍第1項之裝置,其中該第一接合層具有大約30奈米至大約3微米之範圍的厚度。
- 如申請專利範圍第1項之裝置,其中該第一接合層具有大約40奈米至大約2微米之範圍的厚度。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵具有大約50奈米至大約20微米之範圍的高度。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵包含角錐形。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵是使用被圖案化的光罩且利用微影技術,然後蝕刻而形成的。
- 如申請專利範圍第1項之裝置,其中該複數個淺溝槽隔離面特徵包含多個蝕刻高度。
- 如申請專利範圍第1項之裝置,其中該光電裝置是感光成像裝置。
- 如申請專利範圍第22項之裝置,其中該感光成像裝置能偵測可見及紅外電磁輻射。
- 如申請專利範圍第1項之裝置,其中該紋理化區域增強該半導體層內的電磁輻射之吸收。
- 如申請專利範圍第1項之裝置,其中該紋理化區域在至少大約700奈米至大約1100奈米的電磁頻譜範圍中增加該半導體層內的光吸收。
- 如申請專利範圍第1項之裝置,其中當光線通過該半導體層時,該紋理化區域增加了光線的有效光程長度。
- 如申請專利範圍第1項之裝置,其中該紋理化區域允許該半導體層經歷多次的光線通過。
- 一種製造光電裝置之方法,包含:將半導體層接合於支承基材;以及在該半導體層的光入射面上產生複數個淺溝槽隔離面特徵,其中將該半導體層接合於該支承基材包含:將第一接合層沉積到該半導體層上;以及將該第一接合層接合到被配置在該支承基材上之第二接合層。
- 如申請專利範圍第28項之方法,其中該產生複數個淺溝槽隔離面特徵的步驟包含使用淺溝槽隔離蝕刻來產生面特徵的陣列。
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