TW201822275A - 氮化物間隔物之基腳移除 - Google Patents

氮化物間隔物之基腳移除 Download PDF

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TW201822275A
TW201822275A TW106130805A TW106130805A TW201822275A TW 201822275 A TW201822275 A TW 201822275A TW 106130805 A TW106130805 A TW 106130805A TW 106130805 A TW106130805 A TW 106130805A TW 201822275 A TW201822275 A TW 201822275A
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plasma
processing chamber
semiconductor
etching method
semiconductor processing
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定民 高
湯姆 崔
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美商應用材料股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357—Generation remote from the workpiece, e.g. down-stream
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

可執行處理方法以自基板移除不想要的材料，例如氧化物基腳。方法可包括形成惰性電漿於處理腔室的處理區域中。惰性電漿的流出物可被用來修飾半導體腔室的處理區域中的半導體基板上暴露材料的表面。可自含氟前驅物形成遠端電漿以產生電漿流出物。方法可包括將電漿流出物流至半導體處理腔室的處理區域。方法亦可包括自半導體基板移除暴露材料的經修飾後表面。

Description

氮化物間隔物之基腳移除
本技術關於半導體系統、製程與裝置。更特定言之，本技術關於移除晶圓表面上的氧化物或氮化物材料的系統與方法。
藉由在基板表面上產生複雜圖案材料層的製程而使得積體電路變為可能。在基板上產生圖案化材料需要用於移除暴露材料的受控制方法。化學蝕刻用於多種目的，包括轉移光阻劑中的圖案進入下層、薄化層或薄化已經存在於表面上的特徵的橫向尺寸。通常樂見具有蝕刻一種材料快於另一種材料的蝕刻製程以促進例如圖案轉移製程。上述蝕刻製程被稱為對第一材料具有選擇性。由於材料、線路與製程的多樣性，已經發展出具有針對多種材料的選擇性的蝕刻製程。
可根據製程中所用的材料將蝕刻製程稱為濕式或乾式。濕式HF蝕刻比起其他介電質與材料優先地移除氧化矽。然而，濕式製程可能難以穿透某些受限制的溝槽並亦可能有時會使殘餘材料變形。形成在基板處理區域中的局部電漿中產生的乾蝕刻可穿透更受限的溝槽並呈現出精細殘餘結構的較少變形。然而，當局部電漿放電時可能會透過電弧的產生而傷害基板。
因此，需要可用於產生高品質元件與結構的改良系統與方法。而本技術可解決這些需求與其它的需求。
可執行處理方法以自基板移除不想要的材料，例如氧化物基腳。方法可包括形成惰性電漿於處理腔室的處理區域中。惰性電漿的流出物可被用來修飾半導體腔室的處理區域中的半導體基板上暴露材料的表面。可自含氟前驅物形成遠端電漿以產生電漿流出物。方法可包括將電漿流出物流至半導體處理腔室的處理區域。方法亦可包括自半導體基板移除暴露材料的經修飾後表面。
在修飾操作過程中，惰性電漿可包括氫電漿或由氫電漿所組成。惰性電漿可由低於約100 W的偏壓功率所形成。在實施例中，半導體基板上的暴露材料的表面可經修飾至由半導體基板中之暴露表面起小於約4 nm的深度。在形成惰性電漿時與修飾過程中半導體處理腔室中的壓力可維持低於約50 mTorr。
遠端電漿可在與半導體處理腔室的處理區域流體隔離的半導體處理腔室的區域中形成，或可在流體耦接於半導體處理腔室的遠端電漿單元中形成。在移除暴露材料的經修飾表面過程中，半導體基板可維持在高於或約為80℃的溫度下。移除暴露材料的經修飾表面會暴露材料的未經修飾部分，而材料的經修飾部分比上材料的未經修飾部分的蝕刻選擇性可大於或約為100：1、大於或約為1,000：1或更高。半導體基板上的暴露材料可包括位於沿著半導體基板配置的氮化物間隔物附近的氧化物基腳。在實施例中，可額外地自含氫前驅物形成遠端電漿。再者，在實施例中，可在至少一個額外循環中重複蝕刻方法的各個操作，而所有循環後的總移除可能小於10 nm。
本技術亦可包括用於移除氧化矽材料的蝕刻方法。方法可包括形成惰性電漿於半導體處理腔室的處理區域中。方法可包括以惰性電漿的流出物修飾半導體處理腔室的處理區域中的半導體基板上的氧化矽的暴露區域。方法可包括以含氟前驅物的電漿流出物接觸經修飾的氧化矽。方法可進一步包括蝕刻經修飾的氧化矽。在實施例中，可在單一半導體處理腔室中執行修飾、接觸與蝕刻的全部步驟。
在實施例中，可在約100℃的溫度下執行蝕刻。可在與半導體處理腔室的處理區域流體耦接且實體上隔離的半導體處理腔室的遠端區域中形成含氟前驅物的電漿流出物。可藉由約300 W的功率水平下的電容耦合電漿產生含氟前驅物的電漿流出物。在實施例中，可額外地以含氫前驅物接觸經修飾的氧化矽。含氫前驅物可跳過半導體處理腔室的遠端區域。含氟前驅物的電漿流出物離開半導體處理腔室的遠端區域後，含氫前驅物可與含氟前驅物的電漿流出物交互作用。
本技術亦包括蝕刻沿著氮化物間隔物的基腳的方法。方法可包括形成惰性電漿於半導體處理腔室的處理區域中。惰性電漿可包括藉由小於100 W的偏壓功率所形成的氫電漿。方法亦可包括以惰性電漿的流出物修飾半導體處理腔室的處理區域中的半導體基板上的氧化矽的暴露區域。氧化矽的暴露區域可為或包括配置在氮化物間隔物與氧化矽表面(氮化物間隔物自此延伸)相交處附近的基腳。再者，在修飾操作過程中，半導體處理腔室中的壓力可維持低於約100 mTorr。
方法亦可包括形成含氟前驅物的電漿於與半導體處理腔室的處理區域藉由噴頭分隔的半導體處理腔室的遠端區域中。方法可包括以含氟前驅物的電漿流出物接觸經修飾的氧化矽。額外地，方法可包括在約100℃的溫度下蝕刻經修飾的氧化矽基腳。在實施例中，可在相同的半導體處理腔室中執行修飾、接觸與蝕刻所有步驟。在某些實施例中，在蝕刻過程中沒有產生固態副產物。在實施例中，半導體處理腔室的遠端區域可為界定在半導體處理腔室中的區域。額外地，半導體處理腔室的遠端區域可為半導體處理腔室外部但流體耦接於至半導體處理腔室的入口的區域。
比起傳統系統與技術，上述技術可提供多種優點。舉例而言，完整移除基腳可避免或減少後續製程過程中的間距擺動(pitch walking)。此外，相對於氧化物地實際上無限的選擇性可允許在減少厚度的材料上執行處理。搭配下方描述與附圖更詳細地描述這些與其他實施例以及多個上述實施例的優點與特徵。
本技術包括用於小間距特徵半導體處理的系統與部件。隨著接線間距降低，標準微影術製程可能受到限制，而可利用替代機制於圖案化。在一個上述圖案化操作過程中，可在氧化物表面上形成氮化物間隔物。在一個形成方案中，在虛設多晶矽接線與墊氧化物上沉積氮化物層。為了形成氮化物間隔物，執行可移除氮化物層以及多晶矽的連續性的蝕刻製程。為了確保已經完全移除間隔物之間的氮化物，通常執行過度蝕刻。然而，上述製程可能會濺射下方的墊氧化物使其沿著氮化物間隔物的側壁重新沉積為基腳。若不移除基腳，核心與間隙之間的接線厚度可能有所變化，這可能會造成後續製程中的間距擺動。
傳統技術努力在解決此基腳移除問題，因為過度蝕刻製程通常高度選擇其他材料遠勝氧化物。因此，用於蝕刻的材料很可能以比氮化物慢的速率移除氧化物材料，這會傷害形成的氮化物間隔物。此外，由於墊氧化物可為薄、高品質氧化物(例如，熱氧化物)，更難以達成受控制但又受限的移除。然而，本技術利用能夠進行表面改性以及蝕刻能力兩者的單一腔室來影響材料品質、蝕刻速率與選擇性。藉由修飾或傷害基腳，可在較不適合於標準膜移除的蝕刻條件下執行移除。這些技術不僅移除不想要的材料，亦可用限制整體材料效應的受控制之方式執行移除。因此，所解釋的技術可藉由允許在高度選擇性速率下的限制性移除而適用於橫跨產業的多種半導體製程。舉例而言，除了基腳移除以外，這些技術可用於虛設多晶矽拔除、應變的源極汲極與多種其他修飾與移除製程。
雖然剩餘的揭露內容將常規地確定利用揭露技術的特定蝕刻製程，將可輕易地理解系統與方法因為可能發生在期望腔室中而相等地適用沉積與清洗製程。因此，技術不應視為僅用於蝕刻製程般如此受限。
第 1 圖 顯示根據實施例沉積、蝕刻、烘烤與固化腔室的處理系統100的一個實施例的俯視平面圖。描繪於第1圖中的處理工具100可包括複數個製程腔室114A-D、移送腔室110、檢修腔室116、整合式量測腔室117與一組裝載閘腔室106A-B。製程腔室可包括相似於針對第2圖描述的那些結構或部件的結構或部件以及額外的處理腔室。
為了在腔室之間移送基板，移送腔室110可包含機器人傳送機構113。傳送機構113可具有一對分別附接至可延伸臂113B的末端的基板傳送葉片113A。葉片113A可用於攜帶個別的基板到達與離開製程腔室。在操作中，基板傳送葉片的一者(例如，傳送機構113的葉片113A)可自裝載閘腔室的一者(例如，腔室106A-B) 取回基板W並攜帶基板W至處理的第一階段(例如，下方描述於腔室114A-D中的蝕刻製程)。若腔室被佔據，機器人會等待直到處理完成，並接著以一個葉片113A自腔室移除經處理後的基板並以第二葉片(未圖示)插入新的基板。一但基板經受處理後，其可能接著被移動至處理的第二階段。針對每次移動，傳送機構113大體可具有一個葉片攜帶基板與一個空葉片以完成基板交換。傳送機構113可在各個腔室處等待直到完成交換為止。
一旦製程腔室中的製程完成後，傳送機構113可自最後的製程腔室移動基板W並傳送基板W至裝載閘腔室106A-B中的匣。自裝載閘腔室106A-B，基板可移動進入工廠介面104。工廠介面104大體可操作用來在處於大氣壓力清潔環境中的艙裝載器105A-D與裝載閘腔室106A-B之間傳送基板。舉例而言，大體可透過空氣過濾過程(例如，HEPA過濾)來提供工廠介面104中的清潔環境。工廠介面104亦可包括基板定向器/對齊器(未圖示)，基板定向器/對齊器可用來在處理前適當地對齊基板。至少一個基板機器人(例如，機器人108A-B)可配置在工廠介面104中以在工廠介面104中的多個位置/地點之間傳送基板並傳送基板至其他與工廠介面連通的地點。機器人108A-B可設以沿著封圍件104中的軌道系統自工廠介面104的第一端移動至第二端。
處理系統100可進一步包括整合式量測腔室117以提供控制訊號，整合式量測腔室117可對處理腔室中執行的任何製程提供適應性控制。整合式量測腔室117可包括多種量測裝置的任一者以量測多種膜性質，諸如厚度、粗糙度、組成，且量測裝置可進一步能夠以自動方式取得光柵參數(諸如，真空下的臨界尺寸、側壁角度與特徵高度)的特徵。
現轉向第 2 圖 ，第2圖係根據本技術的示範性處理腔室系統200的橫剖面圖。舉例而言，腔室200可用於先前討論的系統100的處理腔室部分114的一者或多者。一般而言，蝕刻腔室200可包括第一電容耦合電漿源與第二電容耦合電漿源，第一電容耦合電漿源用以實施離子研磨操作，而第二電容耦合電漿源用以實施蝕刻操作並實施選擇性的沉積操作。腔室200可包括圍繞夾盤250的接地腔室壁240。在實施例中，夾盤250可為在處理過程中夾持基板202至夾盤250的頂面的靜電夾盤，然則亦可利用其他習知的夾持機構。夾盤250可包括嵌入式熱交換線圈217。在示範性實施例中，熱交換線圈217包括一個或多個熱傳送流體通道，熱傳送流體(例如，乙二醇/水混合)可通過熱傳送流體通道以控制夾盤250的溫度與最終控制基板202的溫度。
夾盤250可包括耦接至高電壓DC供應器248的網格249，以致網格249可攜帶DC偏壓電位以實施基板202的靜電夾持。夾盤250可耦接於第一RF功率源，且在一個上述實施例中，網格249可耦接於第一RF功率源以致DC電壓偏移與RF電壓電位兩者耦接橫跨夾盤250的頂面上的薄介電層。在描述性實施例中，第一RF功率源可包括第一與第二RF產生器252、253。RF產生器252、253可在任何工業上利用頻率下運作，然而在示範性實施例中，RF產生器252可在60 MHz下運作以提供有利的定向性。當亦提供第二RF產生器253時，示範性頻率可為2 MHz。
當夾盤250為RF供能的，可藉由第一噴頭225提供RF回程。第一噴頭225可配置於夾盤上方以分配第一原料氣體進入第一腔室區域284，第一腔室區域284由第一噴頭225與腔室壁240所界定。因此，夾盤250與第一噴頭225形成第一RF耦合電極對以電容性激發第一腔室區域284中第一原料氣體的第一電漿270。源自RF供能夾盤的電容性耦合的DC電漿偏壓或RF偏壓會產生自第一電漿270至基板202的離子(例如，當第一原料氣體係Ar時產生Ar離子)流量以提供離子研磨電漿。第一噴頭225可為接地的或者耦接於RF源228，RF源228具有一個或多個可在夾盤250的頻率以外的頻率(例如，13.56 MHz或60 MHz)下運作的產生器。在描述性實施例中，第一噴頭225可透過繼電器227選擇性耦接至地面或RF源228，可在蝕刻製程過程中例如藉由控制器(未圖示)自動地控制繼電器227。在揭露實施例中，腔室200可不包括噴頭225或介電性間隔物220，反之可僅包括進一步描述於下的擋板215與噴頭210。
如進一步描述於圖式中，蝕刻腔室200可包括能夠在低製程壓力下有高產量的幫浦堆疊。在實施例中，至少一個渦輪分子幫浦265、266可透過一個或多個閘閥260耦接於第一腔室區域284，並配置於夾盤250下，與第一噴頭225相對。渦輪分子幫浦265、266可為具有適當產量的任何商業上可取得幫浦，且更明確地，可經適當地調整尺寸以在第一原料氣體的期望流動速率(例如，當第一原料氣體係氬時50至500 sccm的Ar)下維持製程壓力低於或約為10 mTorr或者低於或約為5 mTorr。在描繪實施例中，夾盤250可形成為兩個渦輪幫浦265與266之間中央的基座的部分，然而在替代配置中，夾盤250可在自腔室壁240懸臂而出的基座上，且有單一渦輪分子幫浦的中心對齊於夾盤250的中心。
配置在第一噴頭225上方的可為第二噴頭210。在一個實施例中，處理過程中，第一原料氣體源(例如，自氣體分配系統290輸送的氬)可耦接於氣體入口276，而第一原料氣體流動通過複數個延伸通過第二噴頭210的孔280進入第二腔室區域281，並通過複數個延伸通過第一噴頭225的孔282進入第一腔室區域284。具有孔278的額外流動分配器或擋板215可透過分配區域218進一步分配第一原料氣體流動216橫跨蝕刻腔室200的直徑。在替代實施例中，第一原料氣體可透過孔283直接流入第一腔室區域284，如虛線223所示，孔283與第二腔室區域281隔開。
腔室200可額外地自描述用來執行蝕刻操作的狀態重新設置。輔助電極205可配置於第一噴頭225上並在輔助電極205與第一噴頭225之間有第二腔室區域281。輔助電極205可進一步形成蝕刻腔室200的蓋或頂板。輔助電極205與第一噴頭225可藉由介電環220電絕緣，並形成第二RF耦合電極對以電容性放電第二腔室區域281中第二原料氣體的第二電漿292。有利地，第二電漿292無法提供較大的RF偏壓電位於夾盤250上。第二RF耦合電極對的至少一個電極可耦接於RF源以激發蝕刻電漿。輔助電極205可電耦接於第二噴頭210。在示範性實施例中，第一噴頭225可耦接於地面平面或漂浮，並可透過繼電器227耦接至地面，允許第一噴頭225在操作的離子研磨模式過程中亦由RF功率源228所供能。當第一噴頭225係接地時，RF功率源208(具有一個或多個在例如13.56 MHz或60 MHz下運作的RF產生器)可透過繼電器207耦接於輔助電極205，繼電器207可在其他運作模式過程(例如，離子研磨操作過程)中允許輔助電極205亦接地，然則若第一噴頭225被供能輔助電極205亦可保持漂浮。
第二原料氣體源(例如，三氟化氮)與氫源(例如，氨)可由氣體分配系統290輸送並例如透過虛線224耦接於氣體入口276。在此模式中，第二原料氣體可流動通過第二噴頭210並在第二腔室區域281中通電。活性物種可接著通過進入第一腔室區域284以與基板202反應。如進一步所描繪般，對於第一噴頭225係多通道噴頭的實施例，可提供一個或多種原料氣體以與第二電漿292所產生的活性物種反應。在一個上述實施例中，水源可耦接於複數個孔283。額外的配置亦可基於提供的一般描述，但具有多個部件重新配置。舉例而言，流動分配器或擋板215可為相似於第二噴頭210的平板，且可配置於輔助電極205與第二噴頭210之間。由於任何這些板可在多個產生電漿的配置中運作為電極，相似於介電環220的一個或多個環狀或其他形狀的間隔物可配置於這些部件的一個或多個之間。在實施例中，第二噴頭210亦可運作為離子抑制板，並亦可設以降低、限制或抑制離子性物種流動通過第二噴頭210，同時仍允許中性與自由基物種的流動。可在腔室中第一噴頭225與夾盤250之間包括一個或多個額外的噴頭或分配器。上述噴頭可具有先前所述的分配板或構造的形狀或構造。再者，在實施例中，遠端電漿單元(未圖示)可耦接於氣體入口以提供電漿流出物至腔室以用於多種製程中。
在實施例中，夾盤250可在正交於第一噴頭225的方向中沿著距離H2移動。夾盤250可位在波紋管255等等所圍繞的致動機構上以允許夾盤250移動靠近或遠離第一噴頭225，做為控制夾盤250與第一噴頭225(第一噴頭225可在80°C – 150°C或更高的高溫下)之間熱傳送的手段。因此，可藉由在相對於第一噴頭225的第一與第二預定位置之間移動夾盤250來實施蝕刻製程。或者，夾盤250可包括升降器251以提高基板202離開夾盤250的頂面達距離H1以在蝕刻製程過程中控制藉由第一噴頭225的加熱。在其他實施例中，舉例而言，當在例如約90-110°C的固定溫度下執行蝕刻製程時，可避免夾盤位移機制。系統控制器(未圖示)可在蝕刻製程過程中藉由自動地交替供能第一與第二RF耦合電極組而交替地通電第一與第二電漿270與292。
腔室200亦可設以執行沉積操作。可藉由RF放電在第二腔室區域281中產生電漿292，並可用任何描述用於第二電漿292的方式實施RF放電。當第一噴頭225被供能以在沉積過程中產生電漿292時，第一噴頭225可藉由介電性間隔物230與接地腔室壁240隔離以相對於腔室壁為電漂浮。在示範性實施例中，可自氣體分配系統290輸送氧化劑原料氣體源(例如，氧分子)且氧化劑原料氣體源耦接於氣體入口276。在第一噴頭225係多通道噴頭的實施例中，可自氣體分配系統290輸送任何含矽前驅物(舉例而言，OMCTS)並將含矽前驅物引導進入第一腔室區域284，以與自電漿292通過第一噴頭225的活性物種反應。或者，含矽前驅物亦可與氧化劑一起流動通過氣體入口276。腔室200包括可用於參照本技術所討論的多種操作的通用腔室配置。腔室並不視為限制本技術，反之是用來幫助了解所述的製程。多種技術中習知的其他腔室或正在開發的腔室可與本技術一起應用，這些腔室包括應用材料股份有限公司(Santa Clara, California)所生產的任何腔室或可執行下方詳細描述技術的任何腔室。
第 3 圖 描繪可執行於例如先前所述的腔室200中之蝕刻方法300。方法300可包括方法開始前的一個或多個操作，包括前端處理、沉積、蝕刻、研磨、清洗或可在所述操作前執行的任何其他操作。經處理基板(可為任何尺寸的半導體晶圓)可被定位於腔室中以進行方法300。在實施例中，可取決於執行的操作而在多個腔室中執行方法300的操作。此外，在實施例中，可在單一腔室中執行整個方法300以減少等待時間、污染物問題與真空破壞。熟悉技術者能輕易理解亦可在相同腔室或不同腔室中執行參照方法300所述的那些操作的後續操作。
方法300可包括在操作305形成惰性電漿於半導體處理腔室的處理區域中。可在操作305前已經將基板定位於腔室中。參照僅作描述用途之腔室200，電漿可被形成或產生在區域270中、或在至少部分由基板支撐基座界定的區域中。上述電漿同樣被理解為晶圓水平電漿。惰性電漿的流出物可被用於方法300中以在操作310修飾半導體基板上暴露材料的表面。基板可位於或安置在半導體處理腔室的處理區域中。
可在操作315形成遠端電漿以產生電漿流出物，而遠端電漿可包括含氟前驅物或由含氟前驅物所組成。在實施例中，操作315中應用的電漿亦可形成在晶圓水平處，但遠端電漿可降低在晶圓處與自腔室部件處濺射成分。在操作320可將電漿流出物流動通過處理腔室而到達安置基板的半導體處理腔室的處理區域。一旦接觸經修飾的表面，電漿流出物可在操作325自半導體基板移除暴露材料的經修飾表面。
方法300的修飾與移除操作可允許不想要的材料(例如，先前描述的基腳)的受控制移除。操作亦可良好地適用於任何尺寸的特徵，包括具有諸如下列的小間距特徵或連續間隔物之間的寬度，小於或約為50 nm、小於或約為25 nm、小於或約為20 nm、小於或約為15 nm、小於或約為12 nm、小於或約為10 nm、小於或約為9 nm、小於或約為8 nm、小於或約為7 nm、小於或約為6 nm、小於或約為5 nm、小於或約為4 nm、小於或約為3 nm、小於或約為2 nm、小於或約為1 nm或更小。可在多個腔室或單一腔室(舉例而言，腔室200)連續地執行修飾與移除操作，其可在腔室中或腔室連結處中產生晶圓水平電漿與遠端電漿兩者。
修飾操作310可包含一個或多種材料的惰性電漿。用於產生電漿的材料可為一個或多種稀有材料，包括氦、氖、氬、氪、氙或氡。用於產生電漿的材料亦可為與接受修飾的半導體表面上暴露材料具有有限的化學活性或非反應性的額外材料。舉例而言，氫可用於操作310中，且在實施例中，惰性電漿可包括氫電漿或由氫電漿所組成。氫電漿可由任何數目的含氫材料或混合物所產生，且在實施例中，氫電漿可專門地由氫(H2 )所形成。修飾操作可包含待移除材料的轟擊形式。由於氫為小且輕的材料，比起較重材料(舉例而言，氦)而言，氫較不可能在其被引導處濺射材料。
自惰性前驅物形成的電漿可為提供電漿流出物至基板的方向性流動的偏壓電漿。電漿可為低水平電漿以限制轟擊、濺射與表面修飾的量。在實施例中，電漿功率可小於或約為300 W、小於或約為250 W、小於或約為200 W、小於或約為150 W、小於或約為100 W、小於或約為75 W、小於或約為50 W或者小於或約為25 W。藉由利用例如約50 W的電漿功率，可限制電漿流出物的穿透深度。舉例而言，所述的修飾操作可允許半導體基板上暴露材料的表面經修飾到自半導體基板中的暴露表面起小於或約為4 nm的深度，並可允許材料的表面的修飾至小於或約為3 nm、小於或約為2 nm或者小於或約為1 nm的深度。舉例而言，在實施例中，藉由利用低水平電漿(例如，約50 W)與相對輕前驅物(例如，氫)，穿透的飽和深度可約為1 nm。修飾操作可對溫度與材料為相對地或完全地不敏感，並可基本上相同地修飾或傷害氮化物、氧化物或多晶矽的暴露區域。
亦可在修飾操作310過程中控制處理腔室中的壓力。舉例而言，在形成惰性電漿與執行修飾操作時，處理腔室中的壓力可維持在低於或約為1 Torr。此外，在實施例中，處理腔室中的壓力可維持在低於或約為500 mTorr、低於或約為250 mTorr、低於或約為200 mTorr、低於或約為150 mTorr、低於或約為100 mTorr、低於或約為80 mTorr、低於或約為60 mTorr、低於或約為50 mTorr、低於或約為40 mTorr、低於或約為30 mTorr、低於或約為20 mTorr、低於或約為10 mTorr或更低。腔室中的壓力可影響修飾操作310的方向性。舉例而言，隨著壓力提高，修飾製程可變成更各向同性，而隨著壓力降低，修飾製程可變成更各向異性。因此，隨著壓力提高，氮化物間隔物側壁亦開始接受處理，這在移除後會移除超過原本期望在某些操作中的材料。因此，在實施例中，壓力可維持在例如約20 mTorr以維持修飾操作的相對或實質上各向異性分佈。
可在半導體處理腔室的處理區域遠端形成用於移除操作中的電漿。舉例而言，可在與半導體處理腔室的處理區域流體隔離的半導體處理腔室的區域中形成電漿。因此，區域可實體上隔離於處理區域，同時流體耦接於處理區域。舉例而言，在第2圖的示範性腔室中，遠端電漿可產生於區域292中，區域292藉由噴頭225而隔離於處理區域。此外，遠端電漿可形成於遠端電漿單元(例如，RPS單元)中，遠端電漿單元隔離於腔室但流體耦接於腔室以例如透過蓋、頂板或噴頭而輸送電漿流出物進入腔室。
可自包括含氟前驅物的一個或多個前驅物形成遠端電漿。含氟前驅物可包括一個或多個下列材料，包括NF3 、HF、F2 、CF4 、CHF3 、C2 F6 、C3 F6 、BrF3 、ClF3 、SF6 、額外的氟取代烴或含氟材料。含氟前驅物可被流入遠端電漿區域中以產生電漿流出物，例如含氟電漿流出物。亦可併入氫源作為蝕刻劑前驅物，且氫源可包括氫、氨或任何其他不完全取代的烴或其他含氫材料。氫源(舉例而言，氨)可在電漿形成過程中與含氟前驅物一起輸送進入遠端電漿區域中，因此電漿流出物亦可包括含氫電漿流出物。氫源亦可跳過遠端電漿區域並輸送進入氫源與含氟電漿流出物反應所在之處理區域。在任一方案中，電漿流出物可被輸送至電漿流出物可接觸半導體基板上的經修飾材料或與半導體基板上的經修飾材料交互作用所在之半導體處理腔室的處理區域。
如先前所討論般，在實施例中，暴露材料可包括位於氮化物間隔物附近或沿著氮化物間隔物的氧化物基腳，氮化物間隔物可沿著半導體基板配置。前驅物與電漿流出物可在多種半導體製程中有效地移除氧化物與/或氮化物。然而，選擇性移除可受到處理溫度的影響。較低腔室溫度可允許一個或多種材料的蝕刻提高。在利用含氟前驅物並亦利用含氫前驅物以蝕刻氧化物材料的製程中，製程可包含在低溫(例如，低於約50℃或更低)下以電漿流出物或以替代前驅物(例如，HF)執行蝕刻，以在被移除的材料的表面上形成固態副產物。過程可接著包含加熱材料高於約100℃以昇華固態副產物，舉例而言固態副產物可包括氟矽酸銨。
然而，本技術可在下列半導體基板或半導體腔室溫度下執行移除製程，高於或約為50℃、高於或約為60℃、高於或約為70℃、高於或約為80℃、高於或約為90℃、高於或約為100℃、高於或約為110℃、高於或約為120℃、高於或約為130℃、高於或約為140℃或者高於或約為150℃。利用上方討論的前驅物的蝕刻製程可能具有受限的能力，或者可能無法在例如約100℃的溫度下蝕刻某些材料。雖然傳統技術會因為這些溫度會阻礙期望移除進而避免上述溫度，但本技術可利用此優點來提供蝕刻操作上的自我限制停止點。雖然無法在100℃的溫度下以所述的移除製程蝕刻未經修飾的氧化物與氮化物材料，所產生的經修飾材料可在足夠速率下蝕刻以移除不想要的材料(例如，先前討論的氧化物基腳)。
因此，一旦已經移除暴露材料的經修飾部分，下方的未經修飾材料可能不會進行蝕刻或可能具有有限的蝕刻，並可有效地停止蝕刻製程。以此方式，可在不過度攻擊薄半導體層或小間距特徵的情況下移除些微數量的材料。因此，在實施例中，移除暴露材料的經修飾表面會暴露材料的未經修飾部分。材料的經修飾部分與材料的未經修飾部分的蝕刻選擇性可大於或約為10：1。取決於接受蝕刻的材料，材料的經修飾部分與材料的未經修飾部分的蝕刻選擇性可大於或約為約20：1、40：1、100：1、1,000：1、10,000：1、高達約1：0(在此點上，材料的經修飾部分進行蝕刻，但材料的未經修飾部分不進行蝕刻)。修飾操作可產生一定數量的懸垂鍵結與活性位置給經修飾的材料，這可允許移除操作在移除原本不會發生或者對未經修飾的材料實質上降低速率與選擇性的條件下進行。
如先前所討論，可在相對低的電漿功率水平下執行修飾操作以產生暴露材料表面中少許奈米或更低(例如，約1 nm至約2 nm)的穿透深度。由於移除操作可經限制以基本上僅移除經修飾的表面或者對未經修飾的表面具有有限的影響，移除操作可限制於經修飾的區域，並因此移除約1 nm、約2 nm、約3 nm或約4 nm的材料。在實施例中，修飾操作可具有約1 nm的飽和深度， 在實施例中，但修飾或穿透量可發生在高達2 nm、高達3 nm或高達4 nm，雖然飽和深度可遠小於上述。然而，移除操作可繼續部分蝕刻材料的經修飾區域，因此移除操作可些微移除比修飾的飽和深度更多的材料。
為了確保自基板移除所有的基腳或不樂見材料，可執行修飾與移除操作多個循環以讓移除到達超過修飾操作的典型飽和深度的深度。因此，在實施例中，方法300可執行1個循環、2個循環、3個循環、4個循環、5個循環或更多以自基板完全地移除材料。針對基腳移除而言，基於修飾操作的飽和深度在材料移除上的細微調整控制可允許每個循環移除約1 nm、約2 nm、約3 nm或約4 nm。
以此方式，基腳可在1個循環、2個循環、3個循環或4個循環內自基板移除，在所有循環後的總移除係小於或約為20 nm、小於或約為15 nm、小於或約為12 nm、小於或約為11 nm、小於或約為10 nm、小於或約為9 nm、小於或約為8 nm、小於或約為7 nm、小於或約為6 nm、小於或約為5 nm、小於或約為4 nm、小於或約為3 nm、小於或約為2 nm或者小於或約為1 nm。參照有限移除數量來討論操作，但技術亦可藉由諸如下列方式來移除額外材料，使修飾發生在較低深度、提高循環數目或調整蝕刻參數(包括溫度)。然而，為了限制多個半導體處理操作中的移除量，低功率偏壓電漿以及先前討論的前驅物可允許每個循環移除受限的材料。
轉向第 4A-4D 圖 ，第4A-4D圖描繪上方執行本技術的操作的半導體基板的橫剖面圖。第4A圖描繪形成製程，形成製程可包括多晶矽接線415已經形成於墊氧化物405上的墊氧化物405。氮化物(例如，氮化矽)層410可被沉積在結構的表面上。在第4B圖中，已經執行一個或多個移除操作以移除氮化矽層410的連接部分以及多晶矽接線415。氮化物間隔物412遺留在墊氧化物405上。移除氮化物的製程可能非為完美地均勻，因此諸如邊緣區域或縫隙區域的區域會比其他區域更加緩慢地進行蝕刻。因此，製程可包含過度蝕刻執行用來確保在變為氮化物間隔物412的區域之間完全地移除氮化物層410。
此過度蝕刻製程可相比氧化矽或構成墊氧化物405的材料對氮化物、矽或其他材料具有選擇性。當執行時，舉例而言若為電漿製程或活性製程，過度蝕刻操作可產生墊氧化物405的濺射。濺射部分可沿著氮化物間隔物的側壁重新沉積於先前為多晶矽接線之間間隙的區域以及已經移除多晶矽或其他虛設材料後的核心區域中。重新沉積的濺射材料可沿著氮化物間隔物的側壁或角落產生基腳407，或者在氮化物間隔物與墊氧化物表面 (氮化物間隔物自此延伸)相交處附近產生的基腳。此重新沉積在間隔物之間可能為不一致，若不在形成時移除的話，這會造成後續處理中的複雜度。舉例而言，這會造成不一致處理，以致後續操作會在核心區域與縫隙區域之間產生不同寬度，這可能接著由後續操作所顛倒。此現象通常習知為間距擺動並對整體積體電路為有害的。然而，傳統上難以在不具有可進一步減少或傷害間隔物、墊氧化物或其他結構的額外遮罩或蝕刻操作進行基腳移除。
第4C圖描繪根據本技術的蝕刻方法的態樣。舉例而言，可在半導體處理腔室的處理區域中形成惰性電漿。惰性電漿可產生流出物420，將流出物420引導至半導體基板的表面以及其上的暴露材料。惰性電漿420的這些流出物可被用來修飾半導體處理腔室的處理區域中半導體基板上氧化矽(例如，基腳407)的暴露部分。電漿可為自氫(H2 )或前述的一個或多個其他惰性前驅物形成的偏壓電漿。偏壓電漿的功率水平可小於或約為100 W，並在實施例中可約為50 W。
取決於尋求的穿透深度與修飾的參數，修飾操作可執行約10秒或更低、高至數分鐘或更高。舉例而言，可在處理腔室中維持例如約20 mTorr的低壓，以產生如所述般相對各向異性的電漿流出物420輸送。電漿流出物可修飾基腳407、墊氧化物405與氮化物間隔物412的暴露部分。在實施例中，穿透深度可限制為約1 nm，但可延伸至約2 nm、約3 nm、約4 nm、約5 nm或更大的深度。
操作可包括在半導體處理腔室的遠端區域中形成含氟前驅物的電漿，其中遠端區域可藉由噴頭隔離於半導體處理腔室的處理區域。可用含氟前驅物的電漿流出物接觸墊氧化物405、基腳407與氮化物間隔物412的經修飾區域。可在經修飾的氧化矽上執行以電漿流出物蝕刻，且蝕刻過程中基板或腔室的溫度可約為100℃，這可允許蝕刻經修飾的層同時限制或阻礙蝕刻經修飾部分下方各個材料的未經修飾區域。此外，由於在約100℃下執行蝕刻操作，在蝕刻操作過程中可產生有限的固態副產物或沒有產生固態副產物。如第4D圖中所示，這些操作可完全地移除氮化物間隔物附近的基腳以及移除氮化物間隔物412與墊氧化物405a的經修飾區域。將可理解第4D圖僅試圖作為描述製程，不一定準確顯示蝕刻的深度。為了描述根據本技術的方法，第4D圖可能顯示出墊氧化物的誇大分佈。
可在與半導體處理腔室的處理區域流體耦接且實體隔離的半導體處理腔室的遠端區域中形成用於蝕刻操作的電漿流出物。因此，半導體處理腔室的遠端區域可為半導體處理腔室中界定的區域。此外，半導體處理腔室的遠端區域可為半導體處理腔室外部的區域，但流體耦接於至半導體處理腔室的入口。舉例而言，可在耦接於半導體處理腔室的遠端電漿單元中產生含氟電漿流出物。這些配置的任一者可避免或降低蝕刻過程中晶圓水平處的濺射，並降低處理區域中的汙染沉積或產生。
在實施例中，可藉由電容耦合電漿或電感耦合電漿或其他電漿產生製程來產生含氟前驅物的電漿流出物。在實施例中，電漿的功率水平可小於或約為1000 W，並可小於或約為900 W、小於或約為800 W、小於或約為700 W、小於或約為600 W、小於或約為500 W、小於或約為400 W、小於或約為300 W、小於或約為200 W或者小於或約為100 W。舉例而言，功率水平可為約300 W以控制材料的電漿解離作用，這可提供對蝕刻特徵之額外控制，例如未完全解離用於操作的所有含氟前驅物。然而，在實施例中，完全解離可為期望的，且可應用較高的電漿功率水平。
用於經修飾氧化矽的蝕刻操作的前驅物可額外地包括含氫前驅物，含氫前驅物亦可接觸經修飾材料。含氫前驅物可與含氟前驅物一起包括來產生所有前驅物的電漿流出物。在實施例中，含氫前驅物亦可跳過半導體處理腔室的遠端區域。舉例而言，含氫前驅物可在遠端電漿產生下游的埠或通道輸送至處理腔室。在實施例中，在含氟前驅物的電漿流出物離開半導體處理腔室的遠端區域後，含氫前驅物可與含氟前驅物的電漿流出物交互作用。
可在限制移除經修飾材料下方的未經修飾材料或與不想要材料(例如，基腳)分隔的方式在半導體基板的經修飾部分上執行蝕刻。如先前所討論般，執行蝕刻的溫度會影響未經修飾材料一旦暴露後是否蝕刻或者蝕刻的程度。在第 5 圖 中顯示描繪根據本技術的實施例已經經修飾與未經修飾的多個材料的比較蝕刻速率。如圖中所示，顯示出多晶矽、氧化矽與氮化矽的蝕刻深度。沿著X-軸顯示自含氟前驅物的遠端電漿的蝕刻劑產生時間。執行的操作包括先前所述自氫電漿的膜修飾操作，接著為利用三氟化氮與氨的電漿流出物的移除操作，在半導體處理腔室的處理區域的電漿遠端中產生三氟化氮與氨的電漿流出物。
如圖所示，蝕刻操作開始於時間0，此時電漿被形成且蝕刻劑前驅物被輸送至電漿區域。在約5秒時，已經完全移除氧化矽、氮化矽與多晶矽的經修飾區域。在此時間後，未發生氧化矽的進一步蝕刻，並發生氮化矽的極少移除。持續輸送電漿流出物的話，多晶矽持續進行蝕刻。因此，本揭露通篇討論的材料修飾與移除操作能夠執行自第4A圖至氮化物間隔物形成所述的材料整個移除。本技術測定的經修飾與未經修飾材料選擇性針對多晶矽為19.8：1，針對氮化矽為 42.7：1，且針對氧化矽為 100：0。因此，在所討論的方法中產生針對經修飾的氧化矽的無限選擇性，而經修飾的氧化矽比上未經修飾的氧化矽的實際上無限或無限選擇性可允許自基板表面移除氧化矽的離散區域（例如，基腳）。移除操作過程中的溫度維持在100℃下，這有助於蝕刻操作不移除或極少移除未經修飾的材料。隨著處理溫度降低而低於約100℃且如此降低而低於約50℃，下方未經修飾的部分亦進行蝕刻，這降低處理的效率並可能阻礙材料移除的適當結果。
在先前描述內容中，為了解釋目的，已經提出多個細節以提供本技術的多個實施例的理解。然而，本領域熟悉技術人士可理解可在不具有這些細節的某些細節或具有額外細節的情況下執行某些實施例。
已經揭露多種實施例，熟習此項技術者將可理解可在不悖離實施例的精神下使用多個修飾、替代構造與等效物。此外，已經未描述多個習知製程與元件以避免不必要地模糊本技術。因此，上方描述內容不應被視為限制本技術的範圍。
當提供數值範圍時，除非內文清楚地另有要求，將可理解此亦明確地揭露範圍的上限與下限之間的各個中間數值至下限單位的最小分數。包含了標明範圍中任何標明數值或未標明中間數值與標明範圍中任何其他標明或中間數值之間的任何較窄範圍。這些較小範圍的上限與下限可獨立地包含或排除於範圍中，且較小範圍中包含任一限值或兩者限值或不包含任一限值的各個範圍亦包含於本技術中，受限於標明範圍中的任何明確排除限值。當標明範圍包括一個或兩個限值，亦包含了排除那些包含限值的任一者或兩者的範圍。
除非內文清楚地另有要求，否則本文與隨附申請專利範圍中所用的單數形式「一」與「該」包括複數個參照物。因此，舉例而言，提及「一層」包括複數個上述層，而提及「該前驅物」包括提及一個或多個前驅物及熟悉技術人士習知的等效物等等。
再者，詞彙「包括」與「包含」當用於本說明書與後續申請專利範圍中時意圖詳述所稱特徵、整數、部件或操作的存在，但並不妨礙一個或更多個其他特徵、整數、部件、操作、行為或群組的存在或添加。
100‧‧‧處理系統
104‧‧‧工廠介面
105A、105B、105C‧‧‧艙裝載器
106A、106B‧‧‧裝載閘腔室
108A、108B‧‧‧機器人
110‧‧‧移送腔室
113‧‧‧傳送機構
113A‧‧‧葉片
113B‧‧‧可延伸臂
114A、114B、114C、114D‧‧‧製程腔室
116‧‧‧檢修腔室
117‧‧‧整合式量測腔室
200‧‧‧蝕刻腔室
202‧‧‧基板
205‧‧‧輔助電極
207、227‧‧‧繼電器
208‧‧‧RF功率源
210‧‧‧噴頭
215‧‧‧擋板
216‧‧‧流動
217‧‧‧熱交換線圈
218‧‧‧分配區域
220‧‧‧介電環
223、224‧‧‧虛線
225‧‧‧第一噴頭
228‧‧‧RF源
230‧‧‧介電性間隔物
240‧‧‧腔室壁
248‧‧‧高電壓DC供應器
249‧‧‧網格
250‧‧‧夾盤
251‧‧‧升降器
252‧‧‧第一RF產生器
253‧‧‧第二RF產生器
255‧‧‧波紋管
260‧‧‧閘閥
265、266‧‧‧渦輪分子幫浦
270‧‧‧第一電漿
276‧‧‧氣體入口
278、280、282、283‧‧‧孔
281‧‧‧第二腔室區域
284‧‧‧第一腔室區域
290‧‧‧氣體分配系統
292‧‧‧第二電漿
300‧‧‧方法
305、310、315、320、325‧‧‧操作
405‧‧‧墊氧化物
407‧‧‧基腳
410‧‧‧氮化物層
412‧‧‧氮化物間隔物
415‧‧‧多晶矽接線
420‧‧‧流出物
W‧‧‧晶圓
可藉由參照說明書的剩餘部分與圖式來實現揭露技術的性質與優點的進一步理解。
第1圖顯示根據本技術的示範性處理系統的平面俯視圖。
第2圖顯示根據本技術的示範性處理腔室的示意橫剖面圖。
第3圖顯示根據本技術的實施例的蝕刻方法中經選擇的操作。
第4A-D圖描繪根據本技術的實施例執行經選擇操作於其上的基板材料的橫剖面圖。
第5圖顯示描繪根據本技術的實施例經修飾與未經修飾的多個材料的比較性蝕刻速率的圖式。
多個圖式以示意圖的方式包含於圖式中。可理解圖式係用於描述用途，除非明確地標示為按照比例否則不應視為按照比例繪製。此外，作為示意圖，圖式被提供用來幫助理解，且相較於現實表現物可能不包括所有態樣或資訊，並可包括過多或誇大的材料以用於描述目的。
在附圖中，相似的部件與/或特徵可具有相同的元件符號。再者，可藉由在元件符號後標示在相似部件中做為區別的字母來區別相同類型的多個部件。若在說明書中僅使用第一個元件符號，描述內容適用於具有相同第一個元件符號(不論字母)的相似部件的任何一個。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無

Claims (20)

  1. 一種蝕刻方法，包括： 形成一惰性電漿於一半導體處理腔室的一處理區域中； 以該惰性電漿的流出物修飾該半導體處理腔室的該處理區域中的一半導體基板上之一暴露材料的一表面； 自一含氟前驅物形成一遠端電漿以產生電漿流出物； 流動該等電漿流出物至該半導體處理腔室的該處理區域；及 自該半導體基板移除該暴露材料的該經修飾表面。
  2. 如請求項1所述之蝕刻方法，其中該惰性電漿包括一氫電漿。
  3. 如請求項1所述之蝕刻方法，其中該惰性電漿係由一低於約100 W的偏壓功率所形成。
  4. 如請求項1所述之蝕刻方法，其中該半導體基板上的該暴露材料的該表面係經修飾至一由該半導體基板中之該暴露表面起小於約4 nm的深度。
  5. 如請求項1所述之蝕刻方法，其中在形成該惰性電漿時與該修飾過程中將該半導體處理腔室中的一壓力維持低於約50 mTorr。
  6. 如請求項1所述之蝕刻方法，其中該遠端電漿係形成於與該半導體處理腔室的該處理區域流體隔離的該半導體處理腔室的一區域中，或者該遠端電漿係形成於流體耦接於該半導體處理腔室的一遠端電漿單元中。
  7. 如請求項1所述之蝕刻方法，其中在該暴露材料的該經修飾表面的移除過程中將該半導體基板維持在一高於或約為80℃的溫度下。
  8. 如請求項7所述之蝕刻方法，其中移除該暴露材料的該經修飾表面暴露該材料的一未經修飾部分，且其中該材料的一經修飾部分比上該材料的該未經修飾部分的一蝕刻選擇性係大於或約為100：1。
  9. 如請求項1所述之蝕刻方法，其中該半導體基板上的該暴露材料包括一位於鄰近氮化物間隔物的氧化物基腳，該氮化物間隔物沿著該半導體基板定位。
  10. 如請求項1所述之蝕刻方法，其中該遠端電漿係額外地由一含氫前驅物形成。
  11. 如請求項1所述之蝕刻方法，其中該蝕刻方法的各個操作重複至少一額外循環，且其中所有循環後的一總移除係小於10 nm。
  12. 一種蝕刻方法，包括： 形成一惰性電漿於一半導體處理腔室的一處理區域中； 以該惰性電漿的流出物修飾該半導體處理腔室的該處理區域中的一半導體基板上之氧化矽的一暴露區域； 以一含氟前驅物的電漿流出物接觸該經修飾的氧化矽；及 蝕刻該經修飾的氧化矽，其中該修飾、接觸與蝕刻步驟皆執行於該半導體處理腔室中。
  13. 如請求項12所述之蝕刻方法，其中該蝕刻步驟係執行於一約100℃的溫度下。
  14. 如請求項12所述之蝕刻方法，其中該含氟前驅物的該電漿流出物係形成於該半導體處理腔室的一遠端區域中，該遠端區域流體耦接且實體隔離於該半導體處理腔室的該處理區域。
  15. 如請求項14所述之蝕刻方法，其中該含氟前驅物的該電漿流出物係藉由一約300 W的功率水平下的一電容耦合電漿所產生。
  16. 如請求項14所述之蝕刻方法，其中以一含氫前驅物額外地接觸該經修飾的氧化矽。
  17. 如請求項16所述之蝕刻方法，其中該含氫前驅物跳過該半導體處理腔室的該遠端區域，且其中在該含氟前驅物的該電漿流出物離開該半導體處理腔室的該遠端區域後，該含氫前驅物與該含氟前驅物的該電漿流出物交互作用。
  18. 一種蝕刻方法，包括： 形成一惰性電漿於一半導體處理腔室的一處理區域中，其中該惰性電漿包括一藉由一低於100 W的偏壓功率形成的氫電漿； 以該惰性電漿的流出物修飾該半導體處理腔室的該處理區域中的一半導體基板上之氧化矽的一暴露區域，其中氧化矽的該暴露區域包括一基腳，該基腳配置在氮化物間隔物與氧化矽的一表面的一相交處附近，該氮化物間隔物自氧化矽的該表面延伸，其中在該修飾步驟過程中該半導體處理腔室中的一壓力係維持低於約100 mTorr； 形成一含氟前驅物的一電漿於該半導體處理腔室的一遠端區域中，該遠端區域藉由一噴頭隔離於該半導體處理腔室的該處理區域； 以該含氟前驅物的電漿流出物接觸該經修飾的氧化矽；及 在一約100℃的溫度下蝕刻該經修飾的氧化矽基腳，其中該修飾、接觸與蝕刻步驟皆執行於該半導體處理腔室中，且其中在該蝕刻步驟過程中沒有產生固態副產物。
  19. 如請求項18所述之蝕刻方法，其中該半導體處理腔室的該遠端區域係一界定於該半導體處理腔室的區域。
  20. 如請求項18所述之蝕刻方法，其中該半導體處理腔室的該遠端區域係該半導體處理腔室外部但流體耦接於該半導體處理腔室的一入口的一區域。
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