JP2013081463A - 大規模fetアレイを用いた分析物測定のための方法および装置 - Google Patents
大規模fetアレイを用いた分析物測定のための方法および装置 Download PDFInfo
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- JP2013081463A JP2013081463A JP2012246413A JP2012246413A JP2013081463A JP 2013081463 A JP2013081463 A JP 2013081463A JP 2012246413 A JP2012246413 A JP 2012246413A JP 2012246413 A JP2012246413 A JP 2012246413A JP 2013081463 A JP2013081463 A JP 2013081463A
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Abstract
【解決手段】ChemFETアレイは、改良されたFETピクセル、ならびに測定感度および精度を向上させ、同時に顕著に小さいピクセルサイズおよび高密度アレイを従来のCMOSプロセス技術により製造する。複数のテンプレート核酸を複数の反応チャンバ内に配置する(ここで、ここで複数の反応チャンバは、chemFETアレイに接触しており、)、1または2以上の既知のヌクレオチド三リン酸を、順番にシークエンシングプライマーの3’末端に取り込むことにより、新しい核酸鎖を合成する、アレイ内の少なくとも1つのchemFETにおける電流の変化により、1または2以上の既知のヌクレオチド三リン酸の取り込みを検出する。
【選択図】なし
Description
1つの化学感応性電界効果トランジスタを含む複数の電界効果トランジスタ(FET)および複数のFETに電気的に接続した複数の電気伝導体を含み、ここで複数のFETは、複数の電気伝導体が、各センサによって占有されたエリアを横断し、アレイの多数のセンサと相互接続する4つ以下の導体を含むように配置される装置に関する。
多くの使用に対して、上で説明した高密度電子アレイを用いて化学反応または化学剤を感知するシステムを完成させるために、アレイ素子(「ピクセル」と呼ばれる)に、感知のための化学的または生化学的要素を含有する流体を送達するための、技法および装置が必要である。この節では、例示の技法および方法が説明され、これらは所望の特徴を有しており、かかる目的に有用である。
他の場所で検討したように、例えばDNAシークエンシングなどの多くの使用について、半導体センサアレイの上に、対応するマイクロウェルのアレイを提供するのが望ましく、ここで各マイクロウェルは、好ましくは1つのみのDNA負荷ビーズ(DNA-loaded bead)を受け取るのに十分小さく、これに関連して、アレイの下にあるピクセルは、対応する出力信号を提供する。
マイクロウェルの製造は、多くの方法により行ってよい。製造の実際の詳細にはいくつかの実験が必要となることもあり、利用可能な加工能力により変化する。
接触リソグラフィには制限があり、最高密度のウェルを製造するために選択される製造方法ではない可能性があり、すなわち、横方向に、望ましい最小ピッチ限界よりも大きい値をもたらす可能性がある。
チップ上のセンサのアレイのアセンブリをマイクロウェルのアレイと組み合わせて用いて、試料中のDNAのシークエンシングを行うプロセスを、「実験」と呼ぶ。実験の実施には、ウェルにDNA結合ビーズを装填し、ウェル全体に数種類の異なる溶液(すなわち、試薬および洗浄液)を流すことが必要である。流体インターフェイスと結合した液体送達システムが必要であり、これは、種々の溶液をウェル全体に、制御された層流で許容し得る程度の小さい死容積および、順次の溶液間での少ない二次汚染を有して流す。流体インターフェイスは「フローセル」と呼ばれることもある。
・ 流体送達システムとの好適な相互接続−例えば、適当な寸法の配管を介して。
・ ウェルの上の適当なヘッドスペース(dnaシークエンシング用には、約300μm)。
・ フローチャンバ内に入る前に、流体が遭遇する死容積(すなわち、マイクロウェルアレイの上に包含されるスペース)の最小化。
・ 液体と接触する小さなスペースの除去、しかし、フローセルを通って除去するのではない(二次汚染を最小化するため)。
・ 層流特性が、これが入り口側から出口側までチップ全体を横切る間、広い/平らなフロントのプロファイルを維持するようなものであること。
・ 取り外し可能な参照電極の、フローチャンバ内部またはこれにできるだけ近くへの配置に対して、適合性があること。
・ ビーズの装填の容易さ。
・ 許容できるコストで製造可能であること。
・ フローセルの組み立てとチップパッケージへの取り付けの容易さ。
記載を容易にするため、図38から開始される製造についての検討において、これからはグラススライド3422を、図34〜37における配置と比較して上下を逆にして考える。
第2の層は好ましくは約150μmの深さであり、これは流体輸送チャネルを覆っているが、ただし、スリット形成領域4014と4016の下にある、センサアレイチップのそれぞれの端における約150μmの長さのスリットは除く。
図34〜36には図示されていないが、参照電極は、図37に示すように、フローチャンバの天井におけるメタライゼーション3710であることが理解される。
中央ボア5550は、参照電極5560を受けるように、ガラス層を通してエッチングすることができる。電極は、シリコーンカラー5570または同様の構造により、位置に固定および密封することができる。または、電極は好適なワッシャーと一体的に構成して、同様の目的を有効にすることができる。
市販のフロー型流体電極、例えば塩化銀プロトン透過性電極を、直列で流体系に挿入することができ、これらの電極は一般に、種々の電気化学的目的のために、流体系に沿って安定な電位を提供するよう設計されている。しかし上記のシステムおいては、かかる電位はマイクロウェルISFETチップと接触している流体容積において維持されなければならない。従来の塩化銀電極では、チップ表面と電極との間の(フローセル内の小さなチャネルを通る)電気的に長い流体路のために、安定な電位の実現は困難であることが見出された。これは、チップの電子機器においてノイズの受信をもたらす。さらに、電極の流れの空洞(flow cavity)内の大きな容積は、流体との電気的接続を劣化させる気泡を閉じ込めて蓄積しがちである。
センサアレイを用いるための完全なシステムは、好適な流体源、バルブ操作および、用途に依存して、マイクロアレイまたはセンサアレイ上の低い試薬および洗浄液のためのバルブ操作用のコントローラを含むであろう。これらの素子は既製の要素から容易に組み立てることができ、コントローラは容易にプログラムして、所望の実験を実施することができる。
以下は、一本鎖オリゴヌクレオチドの、ISFETアレイを用いた迅速シークエンシングのための原理の証明例である。
5’デュアルビオチンタグ(HPLC精製)付き一本鎖DNAオリゴヌクレオチドテンプレートおよび20塩基汎用プライマーは、IDT(Integrated DNA Technologies, Coralville, IN)から注文した。
5’末端において5.91μmの磁気ビーズに結合した不動化テンプレートを、次にテンプレートの3’末端に相補的な20塩基プライマーにアニーリングした(表1)。400μMのプライマー原液の、不動化テンプレートに対してプライマーの20倍過剰量である1.0μlのアリコートを加え、次にビーズとテンプレートとを、プライマーを用いて15分間95℃でインキュベーションし、次に温度をゆっくりと室温に下げた。次にビーズを、上述のようにMPC−sを用いて、120μlの25mMトリシン緩衝液(25mMトリシン、0.4mg/mlのPVP、0.1%のTween 20、8.8mMの酢酸マグネシウム、pH7.8)で3回洗浄した。ビーズを25mMのトリシン緩衝液中に再懸濁させた。
テンプレートとプライマーのハイブリッドを、基本的にMargulies et al. Nature 2005 437(15):376-380および添付の補足資料に記載のようにしてポリメラーゼと共にインキュベーションした。
ISFETアレイおよびその上のマイクロ流体の寸法および密度は、用途に応じて変えてよい。非限定的な例は、512×512アレイである。かかるアレイの各グリッド(262144個となる)は、単一のISFETを有する。各グリッドはまた、その上に位置するウェル(またはこれは本明細書では「マイクロウェル」と同義で用いられる)を有する。
テンプレート1〜4を有するビーズを、チップ上に負荷した(各テンプレートを10μl)。簡略に述べると、各テンプレートのアリコートを、エッペンドルフピペットを用いてチップ上に加えた。次に磁石を用いてビーズをウェル内に引き入れた。
捕捉ビーズとパッキングビーズの両方を、流れを用いて負荷する。ビーズ溶液の容積に対するマイクロリットル単位の精度、およびビーズ溶液の流体接続を通した配置は、図62に示すように、ビーズ負荷取付け部品(bead loading fitting)を用いて実現する。該ビーズ負荷取付け部品は、大リザーバ(容積約1ml)、小リザーバ(容積約10μl)、および小容積のビーズ溶液を操作するためのマイクロ流体チャネルを含む。この方法はまた、精密なピペットにより可能となる、流体適用のマイクロリットル単位の精度も利用する。
3.1 「オープン」システムでのDNAシークエンシング
提示する結果は、「オープン」システムにおいて行われた実験の代表的なものである(すなわち、この実験は、ISFETチップをISFET装置のプラットフォーム上に配置し、次に各ヌクレオチド(5μl、その結果それぞれ6.5μM)を手動で次の順序:dATP、dCTP、dGTPおよびdTTP(100mM原液、Pierce, Milwaukee, WI)により、与えられたヌクレオチドをチップ表面上に既にある液体中にピペットで加えて、チップから2.5mHzの速度でデータを収集した)。これにより、データ収集は、7.5秒間で約18フレーム/秒となった。次にデータをLab Viewを用いて解析した。
流動様式におけるシークエンシングは、ヌクレオチド試薬のDNAへの取り込みへの、開かれた適用の拡張である。試薬をISFETチップのバルクの溶液中に加えるのでなく、試薬を連続的な様式でチップ表面全体に流し、1回に単一DNA塩基(単数または複数)を伸長させる。dNTPを、dTTPから初めて、次にdATP、dCTPおよびdGTPと連続して流す。チップ上の流体の動きの層流の性質による、ヌクレオチドのマイクロウェルへの、および最終的には核酸負荷ビーズの周りへの拡散が、送達の主要な機構である。
ISFETチップは、ヌクレオチド流の最中に、DNA伸長の化学的生成物を感知するために活性化される。
Claims (106)
- 装置であって、CMOSセンサ(105)のアレイ(100)を含み、各センサが、化学感応性電界効果トランジスタ(chemFET)(150)を含み、かつアレイ表面上の約10マイクロメーター×10マイクロメーター以下の面積を占める、前記装置。
- 各センサが占める面積が約9マイクロメーター×9マイクロメーター以下である、請求項1に記載の装置。
- 各センサが占める面積が約5マイクロメーター×5マイクロメーター以下である、請求項2に記載の装置。
- 各センサが占める面積が約3マイクロメーター×3マイクロメーター以下である、請求項3に記載の装置。
- 複数のCMOSセンサが256を超えるセンサを含む、請求項1〜4のいずれかに記載の装置。
- アレイが少なくとも512行および少なくとも512列のCMOSセンサの2次元アレイを含む、請求項5に記載の装置。
- 2次元アレイが少なくとも2048行および少なくとも2048列のCMOSセンサを含む、請求項6に記載の装置。
- 2次元アレイが少なくとも7400行および少なくとも7400列のCMOSセンサを含む、請求項6に記載の装置。
- アレイの全てのchemFETからのchemFET出力信号の集合がデータフレームを構築し、装置が、アレイに接続され、少なくとも1つのアレイ出力信号(Vout)を生成し、少なくとも10フレーム/秒のフレームレートでアレイから多数のデータフレームを提供するように構成された制御回路(110、192、194、198)をさらに含む、請求項5〜8のいずれかに記載の装置。
- フレームレートが少なくとも20フレーム/秒となるように制御回路が構成される、請求項9に記載の装置。
- フレームレートが少なくとも30フレーム/秒となるように制御回路が構成される、請求項10に記載の装置。
- フレームレートが少なくとも40フレーム/秒となるように制御回路が構成される、請求項11に記載の装置。
- 各センサのchemFETが:
フローティングゲート構造(170)、および、
第2の半導体型を有する領域に設けられた第1の半導体型を有するソース(156)およびドレイン(158)(ここで、第2の半導体型を有する領域とソースまたはドレインとを電気的に接続する電気伝導体が存在しない)
を含む、請求項1〜12のいずれかに記載の装置。 - アレイ内全てのchemFETの第2の半導体型を有する全ての領域を電気的に接続するための少なくとも1つの第1の電気伝導体をさらに含む、請求項13に記載の装置。
- 各センサが:
chemFETを含む複数の電界効果トランジスタ(FET)、および
複数のFETに電気的に接続した複数の第2の電気伝導体を含み、
前記複数のFETが、各センサによって占有されたエリアを横断し、アレイの多数のセンサを相互接続する4つ以下の導体を含むように配置される、請求項1〜14のいずれかに記載の装置。 - 各センサがchemFETを含む3つ以下の電界効果トランジスタ(FET)を含む、請求項1〜15のいずれかに記載の装置。
- 各センサの全てのFETが同じチャンネル型であり、第2の半導体型を有する領域に実装される、請求項15または16に記載の装置。
- 各センサのchemFETがイオン感応性電界効果型トランジスタ(ISFET)である、請求項1〜17のいずれかに記載の装置。
- アレイの少なくとも1つの第1のセンサが、少なくとも1つの第1の分析物に化学感応性があるよう構成された第1のchemFETを含み、かつ
アレイの少なくとも1つの第2のセンサが、前記少なくとも1つの第1の分析物とは異なる少なくとも1つの第2の分析物に化学感応性があるよう構成された第2のchemFETを含む、請求項1〜17のいずれかに記載の装置。 - 少なくとも1つの第1の分析物が少なくとも1つの核酸シークエンシングに関連した結合事象を示し、かつ少なくとも1つの第2の分析物が核酸シークエンシングに関連した少なくとも1つの第2の結合事象を示す、請求項19に記載の装置。
- 少なくとも512行および少なくとも512列の電子センサを含み、各センサが2次元アレイ表面に近接する分析物の存在および/または濃度を示す出力信号を提供するように構成された化学感応性電界効果トランジスタ(chemFET)(150)を含む、電子センサの2次元アレイ(105)を含む、センサアレイ(100)。
- 約7mm×7mmのサイズを有する半導体ダイ上に構成されたアレイである、請求項21に記載のアレイ。
- アレイが少なくとも2048行および少なくとも2048列の電子センサを含む、請求項21に記載のアレイ。
- 半導体ダイ上に構成されたアレイが、約20mm×20mmのサイズを有する、請求項23に記載のアレイ。
- アレイが少なくとも7400行および少なくとも7400列の電子センサを含む、請求項21に記載のアレイ。
- 半導体ダイ上に設けられたアレイが、約20mm×20mmのサイズを有する、請求項25に記載のアレイ。
- アレイが、特定用途集積回路(ASIC)として構成され、複数列の各列に対し、ASICが、列内の各chemFETに、一定のドレイン電流および一定のドレイン−ソース電圧を提供するように構成された列回路(110)を含む、請求項項21〜26のいずれかに記載のアレイ。
- 列回路が、2つの演算増幅器(107A、B)、および、一定のドレイン−ソース電圧を提供するための、各chemFETとケルビンブリッジ形態に配置されたダイオード接続FETを含む、請求項27に記載のアレイ。
- ASICがさらに:
複数行の各行を有効にする少なくとも1つの行選択シフトレジスタ(192)、および
複数列の各列からの出力信号を取得する少なくとも1つの列選択シフトレジスタ(194)を含む、請求項27または28に記載のアレイ。 - 少なくとも1つの列選択シフトレジスタが、複数列のうち多数の列からchemFET出力信号を同時に取得するための、複数の列選択シフトレジスタ(1941、1942)を含む、請求項29に記載のアレイ。
- 少なくとも1つの行選択シフトレジスタが、複数行のうち多数の行を同時に有効にするための、複数の行選択シフトレジスタを含む、請求項29または30に記載のアレイ。
- ASICが少なくとも1つの出力ドライバ(198)をさらに含み、該少なくとも1つの出力ドライバが:
少なくとも1つのバッファ増幅器(199)、および
多数のchemFET出力信号に基づく少なくとも1つのアレイ出力信号(Vout)を提供するために、複数列の少なくともいくつかの列を、少なくとも1つのバッファ増幅器に接続するための少なくとも1つのスイッチ(191)
を含む、請求項27〜31のいずれかに記載のアレイ。 - アレイの全てのchemFETからのchemFET出力信号の集合がデータフレームを構築し、かつ、少なくとも1つの行選択シフトレジスタ、少なくとも1つの列選択シフトレジスタおよび/または少なくとも1つの出力ドライバが、少なくとも10フレーム/秒のフレームレートでアレイから多数のデータフレームを提供するために、少なくとも1つのアレイ出力信号を生成するように構成されている、請求項32に記載のアレイ。
- フレームレートが少なくとも20フレーム/秒である、請求項33に記載のアレイ。
- フレームレートが少なくとも30フレーム/秒である、請求項34に記載のアレイ。
- フレームレートが少なくとも40フレーム/秒である、請求項35に記載のアレイ。
- 少なくとも1つのスイッチが、異なるサイズのFETを有するCMOSペアトランスミッションゲートを含む少なくとも1つの非対称スイッチを含む、請求項32〜36のいずれかに記載の装置。
- 各センサのchemFETがイオン感応性電界効果型トランジスタ(ISFET)である、請求項21〜37のいずれかに記載のアレイ。
- アレイの少なくとも1つの第1のセンサが、少なくとも1つの第1の分析物に化学感応性があるように構成された第1のchemFETを含み、かつ
アレイの少なくとも1つの第2のセンサが、少なくとも1つの第1の分析物とは異なる少なくとも1つの第2の分析物に、化学感応性があるように構成された第2のchemFETを含む、
請求項項21〜30のいずれかに記載のアレイ。 - 少なくとも1つの第1の分析物が核酸シークエンシングプロセスに関連した少なくとも1つの第1の結合事象を示し、かつ、少なくとも1つの第2の分析物が核酸シークエンシングプロセスに関連した少なくとも1つの第2の結合事象を示す、請求項39に記載のアレイ。
- 装置であって、
CMOSセンサ(105)のアレイ(100)を含み、各センサが1つの化学感応性電界効果トランジスタ(chemFET)(150)を含み、
CMOSセンサのアレイは256を超えるセンサを含み、アレイの全てのchemFETからのchemFET出力シグナルの集合がデータフレームを構築し、かつ、該装置が:
アレイに接続され、少なくとも1フレーム/秒のフレームレートでアレイから多数のデータフレームを提供するために、少なくとも1つのアレイ出力信号(Vout)を生成するように構成されている制御回路(110、192、194、198)をさらに含む、前記装置。 - フレームレートが、少なくとも10フレーム/秒のフレームレートになるように制御回路が構成されている、請求項41に記載の装置。
- フレームレートが、少なくとも20フレーム/秒のフレームレートになるように制御回路が構成されている、請求項42に記載の装置。
- フレームレートが、少なくとも30フレーム/秒のフレームレートになるように制御回路が構成されている、請求項43に記載の装置。
- フレームレートが、少なくとも40フレーム/秒のフレームレートになるように制御回路が構成されている、請求項44に記載の装置。
- フレームレートが、少なくとも50フレーム/秒のフレームレートになるように制御回路が構成されている、請求項45に記載の装置。
- フレームレートが、少なくとも100フレーム/秒のフレームレートになるように制御回路が構成されている、請求項46に記載の装置。
- アレイが少なくとも512行および少なくとも512列のCMOSセンサの2次元アレイを含む、請求項41〜47のいずれかに記載の装置。
- 2次元アレイが少なくとも2048行および少なくとも2048列のCMOSセンサを含む、請求項48に記載の装置。
- 2次元アレイが少なくとも7400行および少なくとも7400列のCMOSセンサを含む、請求項49に記載の装置。
- 装置であって、
CMOSセンサ(105)アレイ(100)を含み、各センサが化学感応性電界効果トランジスタ(chemFET)(150)を含み、該chemFETが:
フローティングゲート構造(170)、および
第2の半導体型を有する領域に設けられた第1の半導体型を有するソースおよびドレイン(ここで、第2の半導体型を有する領域とソースまたはドレインに電気的に接続する電気伝導体が存在しない)
を含む、前記装置。 - アレイ内全てのchemFETの第2の半導体型を有する全ての領域を一緒に接続する少なくとも1つの第1の電気伝導体をさらに含む、請求項51に記載の装置。
- chemFETがp−チャンネルchemFETであり、第2の半導体型を有する領域が、アレイのp型基板(152)内にn型ウェルとして形成される、請求項51または52に記載の装置。
- 各センサが:
chemFETを含む複数の電界効果トランジスタ(FET)、および
複数のFETに電気的に接続した複数の第2の電気伝導体を含み、
複数のFETが、複数の第2の電気伝導体が、各センサによって占有された部分を横断しかつアレイの多数のセンサを相互接続する4つ以下の導体を含むように配置されている、請求項51〜53のいずれかに記載の装置。 - 各センサがchemFETを含む3つ以下の電界効果トランジスタ(FET)を含む、請求項51〜54のいずれかに記載の装置。
- 各センサがchemFETを含む3つのFETからなる、請求項55に記載の装置。
- 各センサの全てのFETが同じチャンネル型であり、かつ第2の半導体型を有する領域に実装されている、請求項54〜56のいずれかに記載の装置。
- 各センサ内の全てのFETがp−チャンネルFETであり、第2の半導体型を有する領域が、アレイのp型基板(152)内にn型ウェルとして形成される、請求項57に記載の装置。
- 各センサがアレイ表面上の10マイクロメーター×10マイクロメーター以下の面積を占める、請求項51〜58のいずれかに記載の装置。
- 各センサが占める面積が約5マイクロメーター×5マイクロメーター以下である、請求項59に記載の装置。
- 各センサが占める面積が約3マイクロメーター×3マイクロメーター以下である、請求項60に記載の装置。
- アレイが、複数行および複数列に配置されたCMOSセンサの2次元アレイを含む、請求項51〜61のいずれかに記載の装置。
- アレイが少なくとも512行および少なくとも512列のCMOSセンサを含む、請求項62に記載の装置。
- 複数列の各列に関して、アレイが:
一定のドレイン電流および一定のドレイン−ソース電圧を列内の各chemFETに提供するよう構成された列回路(110)をさらに含む、請求項62または63に記載の装置。 - 列回路が、2つの演算増幅器(107A、B)、および、一定のドレイン−ソース電圧を提供するための、各chemFETとケルビンブリッジ形態に配置されたダイオード接続FETを含む、請求項64に記載の装置。
- アレイが、
複数行の各行を有効にする少なくとも1つの行選択シフトレジスタ(192)、および
複数列の各列からchemFET出力信号を取得する列選択シフトレジスタ(194)をさらに含む、請求項62〜65のいずれかに記載のアレイ。 - 少なくとも1つの列選択シフトレジスタが、複数列のうち多数の列からchemFET出力信号を同時に取得するための、複数の列選択シフトレジスタ(1941、1942)を含む、請求項66に記載の装置。
- 少なくとも1つの行選択シフトレジスタが、複数行のうち多数の行を同時に有効にするための、複数の行選択シフトレジスタを含む、請求項66または67に記載の装置。
- 少なくとも1つの出力ドライバ(198)をさらに含み、該少なくとも1つの出力ドライバが:
少なくとも1つのバッファ増幅器(199)、および
少なくとも1つのアレイ出力信号(Vout)を提供するための、複数列の少なくともいくつかの列と少なくとも1つのバッファ増幅器とを接続する少なくとも1つの非対称なスイッチ(191)を含み、
該少なくとも1つの非対称なスイッチが、サイズが異なるFETを有するCMOSペアトランスミッションゲートを含む、請求項62〜68のいずれかに記載の装置。 - アレイの全てのchemFETからのchemFET出力信号の集合がデータフレームを構築し、かつ、少なくとも1つの行選択シフトレジスタ、少なくとも1つの列選択シフトレジスタおよび/または少なくとも1つの出力ドライバが、少なくとも20フレーム/秒のフレームレートでアレイから多数のデータフレームを提供するために、少なくとも1つのアレイ出力信号を生成するように構成されている、請求項69に記載のアレイ。
- 各センサのchemFETがイオン感応性電界効果型トランジスタ(ISFET)である、請求項51〜70のいずれかに記載の装置。
- アレイの少なくとも1つの第1のセンサが、少なくとも1つの第1の分析物に化学感応性があるように構成された第1のchemFETを含み、かつ
アレイの少なくとも1つの第2のセンサが、少なくとも1つの第1の分析物とは異なる少なくとも1つの第2の分析物に、化学的に感応するように構成された第2のchemFETを含む、請求項項51〜70のいずれかに記載の装置。 - 少なくとも1つの第1の分析物が核酸シークエンシングに関連した少なくとも1つの第1の結合事象を示し、また少なくとも1つの第2の分析物が核酸シークエンシングに関連した少なくとも1つの第2の結合事象を示す、請求項72に記載の装置。
- 装置であって、
電子センサ(105)のアレイ(100)を含み、各センサが1つの化学感応性電界効果トランジスタ(chemFET)(150)を含む3つの電界効果トランジスタ(FET)からなる、前記装置。 - chemFETが、
フローティングゲート構造(170)、および、
第2の半導体型を有する領域に設けられた第1の半導体型を有するソース(156)およびドレイン(158)(ここで、第2の半導体型を有する領域とソースまたはドレインとを電気的に接続する電気伝導体が存在しない)
を含む、請求項74に記載の装置。 - 装置であって、
電子センサ(105)のアレイ(100)を含み、各センサが3つ以下の電界効果トランジスタ(FET)を含み、3つ以下のFETが1つの化学感応性電界効果トランジスタ(chemFET)を含む、前記装置。 - 装置であって、
電子センサ(105)のアレイ(100)を含み、各センサが、
1つの化学感応性電界効果トランジスタ(chemFET)(150)を含む複数の電界効果トランジスタ(FET)および
前記複数のFETに電気的に接続した複数の導体
を含み、
前記複数のFETが、各センサによって占有された部分を横断し、かつ、アレイの多数のセンサを相互接続する4つ以下の導体を含むように配置される、前記装置。 - 装置であって、
CMOSセンサ(105)のアレイ(100)を含み、各センサが1つの化学感応性電界効果トランジスタ(chemFET)(150)を含む複数の電界効果トランジスタ(FET)を含み、各センサの全てのFETが同じチャンネル型であり、かつアレイ基板の単一の半導体領域に実装されている、前記装置。 - 各センサ内の全てのFETがp−チャンネルFETであり、アレイ基板がp型基板(152)であり、単一の半導体領域がp型基板内にn型ウェル(154)として形成される、請求項78に記載の装置。
- センサアレイ(100)であって、
複数行および複数列に配置された複数の電子センサ(105)含み、各センサが、アレイ表面に近接する分析物の存在および/または濃度を示す出力信号を提供するように構成された化学感応性電界効果トランジスタ(chemFET)(150)を含み、
複数列の各列について、各アレイが、
列内の各chemFETに、一定のドレイン電流および一定のドレイン−ソース電圧を提供するよう構成された列回路(110)をさらに含み、列回路が、2つの演算増幅器、および、一定のドレイン−ソース電圧を提供するための、各chemFETとケルビンブリッジ形態に配置されたダイオード接続FETを含む、前記センサアレイ。 - センサアレイ(100)であって、
複数行および複数列に配置された複数の電子センサ(105)(各センサは、アレイ表面に近接する分析物の存在および/または濃度を示す出力信号を提供するように構成された化学感応性電界効果トランジスタ(chemFET)(150)である)、
複数行の各行を有効にする少なくとも1つの行選択シフトレジスタ(192)、および
複数列の各列から出力信号を取得する少なくとも1つの列シフトレジスタ(194)
を含む、前記センサアレイ。 - 少なくとも1つの列選択シフトレジスタが、複数列のうち多数の列からchemFET出力信号を同時に取得するための、複数の列選択シフトレジスタを含む、請求項81に記載のアレイ。
- 少なくとも1つの行選択シフトレジスタが、複数行のうち多数の行を同時に有効にするための、複数の行選択シフトレジスタを含む、請求項81または82に記載のアレイ。
- 少なくとも1つの出力ドライバ(198)をさらに含み、該少なくとも1つの出力ドライバが、
少なくとも1つのバッファ増幅器(199)、および
少なくとも1つのアレイ出力信号(Vout)を提供するために、複数列の少なくともいくつかの列を少なくとも1つのバッファ増幅器に接続するための少なくとも1つの非対称なスイッチ(191)を含み、
該少なくとも1つの非対称なスイッチが、サイズが異なるFETを有するCMOSペアトランスミッションゲートを含む、請求項81〜83のいずれかに記載の装置。 - アレイの全てのchemFETからのchemFET出力信号の集合がデータフレームを構築し、かつ、少なくとも1つの行選択シフトレジスタ、少なくとも1つの列選択シフトレジスタ、および/または少なくとも1つの出力ドライバが、少なくとも20フレーム/秒のフレームレートでアレイから多数のデータフレームを提供するために、少なくとも1つのアレイ出力信号を生成するように構成されている、請求項84に記載の装置。
- 装置であって、
CMOSセンサ(105)のアレイ(100)を含み、各センサが化学感応性電界効果トランジスタ(chemFET)(150)を含み、chemFETが、
フローティングゲート構造(170)、および
第2の半導体型を有する領域に設けられた第1の半導体型を有するソース(156)およびドレイン(158)(ここで、第2の半導体型を有する領域とソースまたはドレインとを電気的に接続する電気伝導体が存在しない)
を含み、
ここで、
前記アレイが、少なくとも512行および少なくとも512列のCMOSセンサの2次元アレイを含み、
各センサが、chemFETを含む3つの電界効果トランジスタ(FET)からなり、
各センサが、前記3つのFETに電気的に接続した複数の導体を含み、
前記3つのFETは、複数の導体が、各センサによって占有されたエリアを横断し、かつアレイの多数のセンサを相互接続する4つ以下の導体を含むように配置され、
各センサの全てのFETは同じチャンネル型であり、かつアレイ基板の単一の半導体領域に実装され、かつ
アレイの全てのchemFETからのchemFET出力シグナルの集合がデータフレームを構築し、
かつ、該装置が、
少なくとも20フレーム/秒のフレームレートでアレイから多数のデータフレームを与えるために少なくとも1つのアレイ出力シグナル(Vout)を生成するよう構成され、前記アレイに接続された制御回路(110、192、194、198)をさらに含む、前記装置。 - CMOSセンサ(105)のアレイ(100)の製造方法であって、各センサが化学感応性電界効果トランジスタ(chemFET)(150)を含み、該方法が、
A)アレイを含む少なくとも1つのダイシングされた部分を形成するためにアレイを含む半導体ウェハをダイシングすること、および
B)前記少なくとも1つのダイシングされた部分上をフォーミングガスアニールすること
を含む、前記方法。 - B)が、
C)少なくとも1つのダイシングされた部分を水素および窒素の混合ガス中で加熱すること
を含む、請求項87に記載の方法。 - 混合ガスが約10%〜15%の水素を含むことを特徴とする、請求項88に記載の方法。
- C)が、
D)少なくとも1つのダイシングされた部分を約30〜60分間加熱すること
をさらに含む、請求項88または89に記載の方法。 - C)が、
少なくとも1つのダイシングされた部分を約400セ氏度から約425セ氏度の温度範囲で加熱すること
をさらに含む、請求項88〜89のいずれかに記載の方法。 - 混合ガスが10%の水素を含み、C)が、
少なくとも1つのダイシングされた部分をセ氏約425度の温度で約30分間加熱すること
を含む、請求項88に記載の方法。 - A)の前に半導体ウェハ上の事前フォーミングガスアニールを行うことをさらに含む、請求項91または92に記載の方法。
- CMOSセンサ(105)のアレイ(100)の製造方法であって、各センサが、
プラズマ化学気相成長法(PECVD)で蒸着された窒化シリコンおよび/または酸窒化シリコンの化学感応性パシベーション層を有する化学感応性電界効果トランジスタ(chemFET)(150)を含み、該方法が、
A)パシベーション層のポロシティーを減少させ、および/または密度を増加させるために化学感応性パシベーション層上に、少なくとも1つの追加パシベーション物質を蒸着することを含む、前記方法。 - 少なくとも1つの追加パシベーション物質が、窒化シリコン、酸窒化シリコン、酸化アルミニウム、酸化タンタル、酸化スズおよび二酸化ケイ素からなる群から選択される、請求項94に記載の方法。
- A)が、RFスパッタリング、DCマグネトロンスパッタリング、熱または電子ビーム蒸着、または少なくとも1つの追加パシベーション物質のイオンアシスト蒸着を含む、請求項94または95に記載の方法。
- A)が、少なくとも1つの追加パシベーション物質を400〜600オングストロームの厚さで蒸着することを含む、請求項94〜96のいずれかに記載の方法。
- 核酸をシークエンシングする方法であって、
複数のテンプレート核酸を複数の反応チャンバ内に配置すること(ここで、複数の反応チャンバは、各反応チャンバに対して少なくとも1つの化学感応性電界効果トランジスタ(chemFET)を含んでいるchemFETアレイに接触しており、各テンプレート核酸は、シークエンシングプライマーとハイブリダイズし、かつポリメラーゼと結合している)、
1または2以上の既知のヌクレオチド三リン酸を、順番にシークエンシングプライマーの3’末端に取り込むことにより、新しい核酸鎖を合成すること、
アレイ内の少なくとも1つのchemFETでの電流の変化によって、前記1または2以上の既知のヌクレオチド三リン酸の取り込みを検出すること、
を含む、前記方法。 - chemFETアレイが256を超えるセンサを含む、請求項98に記載の方法。
- 核酸をシークエンシングする方法であって、
複数のテンプレート核酸を複数の反応チャンバ内に配置すること(ここで、複数の反応チャンバは、各反応チャンバに対して少なくとも1つの化学感応性電界効果トランジスタ(chemFET)を含んでいるchemFETアレイに接触しており、各テンプレート核酸は、シークエンシングプライマーとハイブリダイズし、かつポリメラーゼと結合している)、
1または2以上の既知のヌクレオチド三リン酸を、順番にシークエンシングプライマーの3’末端に取り込むことにより、新しい核酸鎖を合成すること、
シークエンシング反応副生成物の生成によって、前記1または2以上の既知のヌクレオチド三リン酸の取り込みを検出すること、
を含み、ここで、隣接するチャンバ間の中心間距離が1〜10μmである、
前記方法。 - 核酸をシークエンシングする方法であって、
複数のテンプレート核酸を複数の反応チャンバ内に配置すること(ここで、複数の反応チャンバは、各反応チャンバに対して少なくとも1つの化学感応性電界効果トランジスタ(chemFET)を含んでいるchemFETアレイに接触しており、各テンプレート核酸は、シークエンシングプライマーとハイブリダイズし、かつポリメラーゼと結合している)、
1または2以上の既知のヌクレオチド三リン酸を、順番にシークエンシングプライマーの3’末端に取り込むことにより、新しい核酸鎖を合成すること、
前記1または2以上の既知のヌクレオチド三リン酸の取り込みの指標としての無機ピロリン酸(PPi)の放出を直接検出すること、
を含む、前記方法。 - 表面にPPi受容体が配置された化学感応性電界効果トランジスタ(chemFET)を含む、装置。
- 保護層で被覆された能動半導体素子上でセンサのアレイとともに用いるための流体アセンブリであって、
センサアレイに嵌合するための開口部を有する第1の要素、および
流体密封状態で第1の要素に固定されており、かつ、流体経路を支持するための、第1のおよび第2のポートを有する、第2の要素を含み、前記第1のおよび第2の要素およびセンサアレイは、フローチャンバを規定し、
これにより、前記ポートの一方に導入された流体は、前記ポートのもう一方を介して流出する前に、前記アレイの上を流れる、前記流体アセンブリ。 - 保護層で被覆された能動半導体素子上でセンサのアレイとともに用いるための流体アセンブリであって、
前記保護層への流体アクセスを提供するように構成され配置された、マイクロウェルアレイ、
マイクロウェルアレイの周囲のセンサアレイに嵌合するための開口部を有する、第1の要素、および
流体密封状態で第1の要素に固定されており、かつ、流体経路を支持するための、第1のおよび第2のポートを有する、第2の要素を含み、前記第1のおよび第2の要素およびマイクロウェルアレイは、センサアレイに嵌合した場合に半導体素子の保護層の上のフローチャンバを規定し、
これにより、前記ポートの一方に導入された流体は、前記ポートのもう一方を介して流出する前に、マイクロウェルアレイの上を流れ、能動半導体素子は、マイクロウェルアレイの少なくともいくつかのマイクロウェルにおける化学的活性を感知する、前記流体アセンブリ。 - フローチャンバの天井に沿った流体に接触するように、第1のポートと第2のポートの間の第2の要素の内部または上に形成された電極をさらに含む、請求項98または99に記載の流体アセンブリ。
- 第2のポート内に装着され、該ポートを通って流れる流体と接触する導電性毛細管を含む、参照電極をさらに含む、請求項98または99に記載の流体アセンブリ。
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