WO2021183095A1

WO2021183095A1 - Clamps for power transistors

Info

Publication number: WO2021183095A1
Application number: PCT/US2020/021645
Authority: WO
Inventors: Eric T. Martin; Rogelio CICILI; S. Jonathan Wang
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2020-03-09
Filing date: 2020-03-09
Publication date: 2021-09-16

Abstract

In some examples, a circuit includes a substrate, and a power transistor to connect a power supply voltage to an activatable device, where the power transistor has an n-type source in a first p-body region. The circuit includes a clamp between a control gate of the power transistor and the n-type source of the power transistor, where the clamp includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) having a node arranged in a second p-body region, the first p-body region and the second p-body region being part of a same layer in the substrate.

Description

CLAMPS FOR POWER TRANSISTORS

Background

[0001] A fluid dispensing system can dispense fluid towards a target. In some examples, a fluid dispensing system can include a printing system, such as a two- dimensional (2D) printing system or a three-dimensional (3D) printing system. A printing system can include printhead devices that include fluidic actuators to cause dispensing of printing fluids.

Brief Description of the Drawings

[0002] Some implementations of the present disclosure are described with respect to the following figures.

[0003] Figs. 1 A-1 B are schematic diagrams of fluidic actuator control assemblies, according to some examples.

[0004] Fig. 2 is a circuit diagram of an over-voltage protection clamp for a power transistor according to some examples.

[0005] Fig. 3 is a cross-sectional view of layers of portions of a power transistor and an over-voltage protection clamp, in accordance with some examples.

[0006] Fig. 4 is a schematic diagram of a circuit including a power transistor and an over-voltage protection clamp, according to some examples.

[0007] Fig. 5 is a schematic diagram of a fluid dispensing device according to some examples.

[0008] Fig. 6 is a flow diagram of a process of forming a device, according to some examples.

[0009] Figs. 7A-7B illustrate the formation of a p-body region for a power transistor, according to some examples. [0010] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

Detailed Description

[0011] In the present disclosure, use of the term “a,” “an”, or “the” is intended to include the plural forms as well, unless the context clearly indicates otherwise. Also, the term “includes,” “including,” “comprises,” “comprising,” “have,” or “having” when used in this disclosure specifies the presence of the stated elements, but do not preclude the presence or addition of other elements.

[0012] A fluid dispensing device can include fluidic actuators that when activated cause dispensing (e.g., ejection or other flow) of a fluid. For example, the dispensing of the fluid can include ejection of fluid droplets by activated fluidic actuators from respective nozzles of the fluid dispensing device. In other examples, an activated fluidic actuator (such as a pump) can cause fluid to flow through a fluid conduit or fluid chamber. Activating a fluidic actuator to dispense fluid can thus refer to activating the fluidic actuator to eject fluid from a nozzle or activating the fluidic actuator to cause a flow of fluid through a flow structure, such as a flow conduit, a fluid chamber, and so forth.

[0013] Activating a fluidic actuator can also be referred to as firing the fluidic actuator. In some examples, the fluidic actuators include thermal-based fluidic actuators including heating elements, such as resistive heaters. When a heating element is activated, the heating element produces heat that can cause vaporization of a fluid to cause nucleation of a vapor bubble (e.g., a steam bubble) proximate the thermal-based fluidic actuator that in turn causes dispensing of a quantity of fluid, such as ejection from an orifice of a nozzle or flow through a fluid conduit or fluid chamber. In other examples, a fluidic actuator may be a piezoelectric membrane based fluidic actuator that when activated applies a mechanical force to dispense a quantity of fluid.

[0014] In examples where a fluid dispensing device includes nozzles, each nozzle includes a fluid chamber, also referred to as a firing chamber. In addition, a nozzle can include an orifice through which fluid is dispensed, a fluidic actuator, and possibly a sensor. Each fluid chamber provides the fluid to be dispensed by the respective nozzle. In other examples, a fluid dispensing device can include a microfluidic pump that has a fluid chamber.

[0015] Generally, a fluidic actuator can be an ejecting-type fluidic actuator to cause ejection of a fluid, such as through an orifice of a nozzle, or a non-ejecting- type fluidic actuator to cause displacement of a fluid.

[0016] In some examples, a fluid dispensing device can be in the form of a fluidic die. A “die” refers to an assembly where various layers are formed onto a substrate to fabricate circuitry, fluid chambers, and fluid conduits. Multiple fluidic dies can be mounted or attached to a support structure. In other examples, a fluidic die can be in the form of a fluidic die sliver, which includes a thin substrate (e.g., having a thickness on the order of 650 micrometers (pm) or less) with a ratio of length to width (L/W) of at least three, for example. A die sliver can have other dimensions in other examples. Multiple fluidic die slivers can be molded into a monolithic molding structure, for example.

[0017] In some examples, a fluidic die can include a printhead die, which can be mounted to a print cartridge, a carriage assembly, and so forth. A printhead die includes nozzles through which a printing fluid (e.g., an ink, a liquid agent used in a 3D printing system, etc.) can be dispensed towards a target (e.g., a print medium such as a paper sheet, a transparency foil, a fabric, etc., or a print bed including 3D parts being formed by a 3D printing system to build a 3D object).

[0018] In a fluid dispensing device, a fluidic actuator can be activated by connecting a high power supply voltage to the fluidic actuator through a power transistor. As used here, a “power supply voltage” can refer to a voltage provided by a power supply. A power supply receives power from a power source (e.g., a battery, a wall outlet, etc.) and produces a power supply voltage (or multiple power supply voltages) that is (are) provided to various components to power the components. A “high power supply voltage” refers to a power supply voltage that is at a higher level than another power supply voltage (which can be referred to as a “low power supply voltage”). A low power supply voltage can be used to control digital circuits and other circuits of the fluid dispensing device. In some examples, the high power supply voltage can exceed 30 volts (V), or can exceed 20 V, or can exceed 15 V, or can exceed 10 V, and so forth. In some examples, the low power supply voltage can be less than 10 V, such as in the range of 4 V to 6 V, or in the range of 3 V to 5 V, and so forth.

[0019] Fig. 1A shows an example arrangement of a fluidic actuator control assembly for use in a fluid dispensing device. The fluidic actuator control assembly includes a fluidic actuator 102 that can be energized in response to activation of a power transistor 104. In the example of Fig. 1A, the fluidic actuator 102 includes a firing resistor. In another example, the fluidic actuator 102 can include a piezoelectric element or another type of fluidic actuator.

[0020] The power transistor 104 has a drain connected to the high power supply voltage (referred to as “VPP” in the ensuing discussion), and a source connected to a node 106 of the fluidic actuator 102. In some examples, the power transistor 104 includes an n-type metal-oxide-semiconductor field effect transistor (MOSFET). A n- type MOSFET has an n+ doped drain and an n+ doped source. An n+ doped region is a substrate region doped with n-type dopants at a concentration that exceeds a specified threshold. A n-type dopant can include phosphorus or another substance.

In some examples, the n-type MOSFET used to implement the power transistor 104 is according to a laterally-diffused metal-oxide semiconductor (LDMOS) technology, which is a high-voltage tolerant type of MOSFET.

[0021 ] The fluidic actuator 102 is connected between the source of the power transistor 104 and a low reference voltage (such as ground). In such an arrangement, the power transistor 104 is referred to as a high-side switch (HSS), since the power transistor 104 is electrically connected between VPP and the fluidic actuator 102.

[0022] As a result of a manufacturing issue or during operation, the fluidic actuator 102 may exhibit a defect. For example, if the fluidic actuator 102 is a firing resistor, the firing resistor may short out, which can cause the source of the power transistor 104 to be connected through a low resistance path (the shorted firing resistor) to ground. In another example, if the fluidic actuator 102 includes a piezoelectric element, the piezoelectric element may also experience a defect that can cause the defective piezoelectric element to provide a low resistance path between the source of the power transistor 104 and ground.

[0023] If the source of the power transistor 104 is connected to ground through a low resistance path, then when a high power supply voltage is applied to the gate of the power transistor 104, a large voltage difference can be established between the gate and source of the power transistor 104 (assuming an over-voltage protection clamp 108 as shown in Fig. 1A is not present), and also between the drain and the source of the power transistor 104. The large gate-source voltage of the power transistor 104 can break down the gate oxide of the power transistor 104, and cause a short circuit at the gate of the power transistor 104.

[0024] The large gate-source voltage of the power transistor 104 can also cause a snapback phenomenon of the power transistor 104 due to the voltage difference between the drain and source of the power transistor 104. Snapback is a result of impact ionization due to hot carriers in a p-body region of the power transistor 104. A “p-body region” refers to a region in a substrate that is doped with p-type dopants (e.g., boron or another substance). The p-body region can be formed in an n-well. An “n-well” refers to a region in the substrate that is doped with n-type dopants (e.g., phosphorus or another substance). The increased holes due to the snapback phenomenon can elevate the local potential of the p-body region, which can forward- bias the p-n junction between the p-body region and the n+ source of the power transistor 104. This forward-bias can result in a parasitic n-p-n (n-well/p-body/n+ source) to turn on resulting in a highly conductive parallel path for current to flow.

[0025] The snapback phenomenon can lead to thermal runaway in the region including the power transistor 104 and the fluidic actuator 102. During snapback, the increased currents result in joule heating. The joule heating increases the diffusion coefficient of minority carriers in the parasitic n-p-n to cause more current flow. The increased current flow can result in a catastrophic positive feedback loop that increases heating in the region around the power transistor 104 and the fluidic actuator 102. The thermal runaway can cascade to other nearby devices in the fluid dispensing device, which can cause damage to an extended part of the fluid dispensing device.

[0026] To provide over-voltage protection for the power transistor 104, the over voltage protection clamp 108 can be connected between the gate and the source of the power transistor 104. The clamp 108 can restrict the voltage difference between the gate and the source of the power transistor 104 to a specified voltage range when a high voltage is applied at the gate of the power transistor 104. The specified voltage range can be between 4 V to 6 V, or approximately 5 V in some examples. In other examples, the clamp 108 can restrict the voltage difference between the gate and the source of the power transistor 104 to another voltage range.

[0027] Fig. 1A shows the clamp 108 as being an “NMOS-based” clamp, which means that the clamp 108 includes n-type MOSFETs.

[0028] In other examples, instead of using the NMOS-based clamp 108 of Fig.

1 A, another type of clamp (PMOS-based clamp) may include p-type MOSFETs. The p-type MOSFETs of the PMOS-based clamp are provided in an n-well in a substrate of the fluid dispensing device. The n-well for the p-type MOSFETs of the PMOS- based clamp are isolated from neighboring n-wells. The isolation is accomplished by defining a gap between n-wells, which incurs a spacing penalty resulting in a less dense arrangement of circuits in a fluid dispensing device. Additionally, due to reduced carrier mobility of p-type MOSFETs relative to n-type MOSFETs, the p-type MOSFETs of the PMOS-based clamp are built with larger gate widths, which also leads to a spacing penalty and less density.

[0029] In accordance with some implementations of the present disclosure, the NMOS-based clamp 108 is used instead of a PMOS-based clamp. The drains and sources of the n-type MOSFETs of the NMOS-based clamp 108 are arranged in a p- body region. The p-body region is formed in an n-well. Since the power transistor 104 is also formed using an n-type MOSFET, the source of the power transistor 104 is also placed in a p-body region that sits in the n-well.

[0030] The p-body region for the source of the power transistor 104 is formed in the same layer as the p-body region for the drains and sources of the n-type MOSFETs of the clamp 108. Since the manufacturing process of a fluid dispensing device already includes a process task of forming the p-body region for the power transistor, the formation of the p-body region for the n-type MOSFETs of the clamp 108 can be part of the same process task. As a result, forming n-type MOSFETs of the clamp in p-body regions does not add to the complexity and/or cost of the manufacturing process of the fluid dispensing device.

[0031 ] In some examples, the p-body region for the power transistor 104 and the p-body region for the drains and sources of the n-type MOSFETs of the clamp 108 are continuously formed in the substrate (i.e. , there is no break between the p-body region for the power transistor 104 and the p-body region for the drains and sources of the n-type MOSFETs of the clamp 108). In other examples, the p-body region for the power transistor 104 and the p-body region for the drains and sources of the n- type MOSFETs of the clamp 108 are discrete p-body regions (of the same layer formed using the same manufacturing process task).

[0032] The gate of the power transistor 104 is connected to an output of a level shifter 110. The level shifter 110 has a power node connected to a high power supply voltage (referred to as VPP_L), which can be at the same voltage or a different voltage than VPP. The input of the level shifter 110 is connected to a low voltage control signal (referred to as LV_Control). The level shifter 110 effectively shifts the voltage level of LV_Control (which ranges between zero and a low power supply voltage) to a voltage range between zero and a high power supply voltage VPP_L).

[0033] When the level shifter 110 outputs a first logic state (e.g., ground voltage), the power transistor 104 is off, and no electrical energy is delivered to the fluidic actuator 102. However, if the level shifter 110 outputs a second logic state (e.g., a high voltage referred to as VPP_L) onto the gate of the power transistor 104, then the power transistor 104 is turned on, which causes current to flow from the drain of the power transistor 104 to the source of the power transistor 104 and through the fluidic actuator 102 (which energizes the fluidic actuator 102). Consequently, the voltage at the source of the power transistor 104 is approximately one threshold voltage of the power transistor 104 below the gate voltage (e.g., approximately one threshold voltage below VPP_L).

[0034] Fig. 1A shows an example where the power transistor 104 is connected to an individual fluidic actuator 102, such that the activation of the power transistor 104 causes activation of just the individual fluidic actuator 102.

[0035] Fig. 1 B shows another example in which the power transistor 104 is used to provide power to any of multiple fluidic actuators 120-1 to 120-N (N > 2). Elements of Fig. 1 B that are similar to those of Fig. 1 A are assigned the same reference numerals.

[0036] In the example of Fig. 1 B, first nodes of the fluidic actuators 120-1 to 120- N are connected in parallel between the source of the power transistor 104 and drains of respective control transistors 122-1 to 122-N. In some examples, the control transistors 122-1 to 122-N are implemented using the same type of n-type MOSFETs as the power transistor 104 (e.g., LDMOS transistors). Each control transistors 122-i (i = 1 to N) is connected between a second node of the fluidic actuator 120-i and ground. The control transistor 122-i is controlled by a control signal that transitions between ground and a low power supply voltage. In some examples, each of the control transistors 122-1 to 122-N can be implemented using n-type MOSFETs. When the power transistor 104 is activated, the power delivered by the power transistor 104 can be caused to be delivered to any fluidic actuator 120-i whose connected control transistor 122-i is turned on.

[0037] The arrangement shown in Fig. 1B can be referred to as a hybrid FISS arrangement, since the Fig. 1 B arrangement uses both an HSS (in the form of the power transistor 104) and low-side switches (LSS’s) that are connected between respective fluidic actuators 120-1 to 120-N and ground.

[0038] Fig. 2 is a circuit diagram of the clamp 108 according to some examples. The clamp 108 includes a stack of diode-connected n-type MOSFETs 202, 204, and 206 connected in parallel with a current mirror 208 between a node G-FISS (which is the gate of the power transistor 104 of Fig. 1 A or 1 B) and a node S-FISS (which is the source of the power transistor 104 of Fig. 1A or 1B). The n-type MOSFETs 202, 204, and 206 are connected in series to provide a series arrangement of n-type MOSFETs.

[0039] A diode-connected transistor refers to a transistor whose gate is connected to the drain of the transistor. In Fig. 2, the gate of each respective n-type MOSFET of the n-type MOSFETs 202, 204, or 206 is connected to the drain of the respective n-type MOSFET. The channel of each of the n-type MOSFETs 202, 204, and 206 is formed in a p-body region represented generally as 210 in Fig. 2. The p- body region 210 is in turn connected to the node S-FISS.

[0040] Although Fig. 2 shows a stack of three transistors, 202, 204, and 206, it is noted that in other examples, there can be a different number of transistors (one or greater than one) on the left side of the clamp 108.

[0041] The current mirror 208 includes an n-type MOSFET 212, which has a gate connected to the gate of n-type MOSFET 206. The channel of the n-type MOSFET 212 is also formed in the p-body region 210.

[0042] A ratio “1 :N" indicated in Fig. 2 represents the relative current carrying capacities (e.g., based on width-to-length ratio) of the channel of the n-type MOSFET 206 and the channel of the n-type MOSFET 210. More specifically, 1 : N may represent the ratio of the width of the channel of the n-type MOSFET 206 to the width of the channel of the n-type MOSFET 210. The ratio 1 : N affects the amount of current (Nl) that flows through the current mirror 208 based on the current (I) flowing through the stack of diode-connected transistors 202, 204, and 206. The current flowing through the current mirror 208 is N times the current (I) flowing through the stack of diode-connected transistors 202, 204, and 206.

[0043] Fig. 3 is a cross-sectional view of layers of portions of the n-type MOSFETs 202, 204, 206, and 212 of Fig. 2 and a portion of the power transistor 104 of Fig. 1A or 1B.

[0044] The various layers shown in Fig. 1 A or 1 B and in Fig. 2 can be formed in and over a substrate 302, which can be formed of silicon or a different material. In some examples, the substrate 302 can be doped with a p-type dopant. The substrate 302 in such examples can in turn be formed in a larger substrate that is not doped.

[0045] An n-well 304 is formed in the substrate 302, by doping the region making up the n-well 304 using an n-type dopant. Following formation of the n-well 304, p- body regions 306 and 308 are formed in the n-well 304. The p-body regions 306 and 308 are formed using the same process task during manufacture of the device that includes the power transistor 104 and the clamp 108. The p-body regions 306 and 308 are part of the same layer in the substrate 302. In examples according to that shown in Fig. 3, the p-body regions 306 and 308 are discrete regions. In other examples, the p-body regions 306 and 308 can be part of a single continuous region.

[0046] Some structures that make up the clamp 108 are formed in the p-body region 306, while some structures that make up the power transistor 104 are formed in the p-body region 308. The structures of the clamp 108 formed in the p-body region 306 include n+ regions 310, 312, 314, 316, 318, and 320. The n+ region 310 forms the drain of the transistor 202, the n+ region 312 forms the source of the transistor 202 and the drain of the transistor 204, the n+ region 314 forms the source of the transistor 204 and the drain of the transistor 206, and the n+ region 316 forms the source of the transistor 206.

[0047] The n+ region 318 forms the source of the transistor 212, and the n+ region 320 forms the drain of the transistor 212. A p+ region 322 is formed in the p- body region 306. The p+ region 322 is doped with p-type dopants at a concentration that exceeds a specified threshold. The p+ region 322 is provided between the n+ region 316 and the n+ region 318.

[0048] A metal electrode 324 (formed of aluminum or another metal or another electrically conductive material) is electrically contacted to the n+ region 310 through a contact via formed in an insulating layer 326. The insulating layer 326 can be formed of silicon dioxide, silicon nitride, or another electrically insulating material.

The metal electrode 324 can be electrically connected to the node G-HSS by an electrically conductive layer (not shown).

[0049] A metal electrode 328 is electrically contacted to the n+ region 312 through a contact via formed in the insulating layer 326. A metal electrode 330 is electrically contacted to the n+ region 314 through a contact via formed in the insulating layer 326.

[0050] A metal electrode 332 is electrically contacted to n+ regions 316 and 318 and the region 322 through contact vias formed in the insulating layer 326. The metal electrode 332 is electrically connected to the node S-HSS by an electrically conductive layer (not shown). The metal electrode 332 is also electrically contacted to the p+ region 322 through a contact via formed in the insulating layer 326. The p+ region 322 provides a low resistance connection between the metal electrode 332 (and thus S-HSS) and the p-body region 306.

[0051] A metal electrode 334 is electrically contacted to the n+ region 320 through a contact via formed in the insulating layer 326. The metal electrode 334 is electrically connected to the node G-HSS using an electrically conductive layer (not shown). [0052] Gate layers 336, 338, 340, and 342 are formed over a gate oxide layer 344. In some examples, the gate layers 336, 338, 340, and 342 can be formed using polysilicon or another electrically conductive material. The gate layers 336, 338, 340, and 342 form respective gates of the transistors 202, 204, 206, and 212.

[0053] Although not shown in the cross-section of Fig. 3, the gate layers 336,

338, 340, and 342 are electrically connected by electrically conductive layers to other structures to form the circuit shown in Fig. 2. For example, the gate layer 336 is electrically connected to the metal electrode 324, the gate layer 338 is electrically connected to the metal electrode 328, the gate layer 340 is electrically connected to the metal electrode 330, and the gate layer 342 is electrically connected to the metal electrode 330.

[0054] Fig. 3 also shows a field oxide layer 346 that forms field oxide regions to electrically isolate different parts of the device. Afield oxide includes silicon dioxide.

In other examples, instead of using a field oxide layer, the layer 346 can be formed using a different electrically insulating material.

[0055] The foregoing refers to structures of the clamp 108 in Fig. 3.

[0056] The following refers to structures of the power transistor 104. An n+ region 348 of the power transistor 104 is formed in the p-body region 308. A p+ region 352 is formed in the p-body region 308 to allow a low resistance connection between the p-body region 308 and a metal electrode 358 that is electrically contacted to the p+ region 352 through a contact via formed in the insulating layer 326. The metal electrode 358 is electrically connected to the node S-FISS by an electrically conductive layer (not shown).

[0057] A gate layer 354 is formed over a gate oxide layer 356. In some examples, the gate layer 354 is generally in the shape of a ring when viewed from the top of the arrangement of layers of Fig. 3. The gate layer 354 forms the gate of the power transistor 104, and is electrically connected to the output of the level shifter 110 by an electrically conductive layer (not shown). [0058] The n+ region 348 forms the source of the power transistor 104. The n+ region 348 is also generally ring shaped and is concentrically arranged inside the gate layer 354 when viewed from the top of the arrangement of layers of Fig. 3.

[0059] As further shown in Fig. 3, n+ regions 360 and 366 of the power transistor 104 are formed in the n-well 304. A metal electrode 364 is electrically contacted to the n+ region 360 through a contact via formed in the insulating layer 326, and a metal electrode 366 is electrically contacted to the n+ region 362 through a contact via formed in the insulating layer 326.

[0060] The metal electrodes 364 and 366 are electrically connected using an electrically conductive layer to a node D-FISS, which is the drain of the power transistor 104 that is connected to VPP.

[0061] Fig. 4 is a schematic diagram of a circuit 400 that includes an over-voltage protection clamp 402 (similar to the clamp 108 of Fig. 1A or 1B, for example), and power transistor 404 (similar to the power transistor 104 of Fig. 1A or 1 B, for example). The circuit 400 includes a substrate 406. The power transistor 404 electrically connects a power supply voltage 408 (e.g., VPP) to an activatable device 410 (e.g., a fluidic actuator). The power transistor 404 has an n-type source 412 in a first p-body region 414.

[0062] The clamp 402 is electrically connected (by electrical connections 416 and 418) between a control gate 420 of the power transistor 404 and the n-type source 412 of the power transistor 404. The clamp 402 includes an n-channel MOSFET 422 that has a node 424 (e.g., a drain or source) arranged in a second p-body region 426. The first p-body region 414 and the second p-body region 426 are part of a same layer in the substrate 406.

[0063] Fig. 5 is a schematic diagram of a fluid dispensing device 500 according to some examples. The fluid dispensing device 500 includes a fluidic actuator 502, a power transistor 504, and a clamp 506. [0064] The fluid dispensing device 500 includes a substrate 508. The fluidic actuator 502 is arranged over the substrate 508, and the fluidic actuator 502 upon activation causes a fluid flow of the fluid dispensing device 500.

[0065] The power transistor 504 electrically connects a power supply voltage 510 to the fluidic actuator 502. The power transistor 504 has an n-type source 512 in a first p-body region 514.

[0066] The clamp 506 is electrically connected (by electrical connections 516 and 518) between a control gate 520 of the power transistor 504 and the n-type source 512 of the power transistor 504. The clamp 506 includes n-channel MOSFETs 522 and 522, where each n-channel MOSFET 522 has a node (drain or source) 524 arranged in a second p-body region 526. The first p-body region 514 and the second p-body region 526 are part of a same layer in the substrate 508.

[0067] Fig. 6 is a flow diagram of a process 600 of forming a device, such as a fluid dispensing device. The process 600 includes forming (at 602), in a layer in a substrate, a first p-body region and a second p-body region.

[0068] The process 600 further includes forming (at 604), in the first p-body region, an n-type source of a power transistor that is to connect a power voltage to an activatable device.

[0069] The process 600 further includes forming (at 606), in the second p-body region, an n-type drain and an n-type source of n-channel MOSFET that is part of an over-voltage protection clamp connecting a gate of the power transistor to the n-type source of the power transistor.

[0070] Figs. 7A-7B illustrate different states of layers of a power transistor when forming a p-body region (e.g., 308 in Fig. 3, 414 in Fig. 4 or 514 in Fig. 5) for the power transistor. Fig. 7A shows that the gate 354 of the power transistor has been formed over the n-well 304. Following formation of the gate 354 p-type dopants 704 are implanted into the n-well 304 to form an initial p-type region 702 in the n-well 304. Note that during the implantation of the p-type dopants 704, the gate 354 acts as a mask that prevents implantation of the p-type dopants in the portion of the n- well 304 underneath the gate 354.

[0071] Following formation of the initial p-body region 702, heat is applied to cause the p-body region 702 to grow in size to a larger p-body region 706, as shown in Fig. 7B. The larger p-body region 706 has extended underneath the gate 354. The portion of the p-body region 706 underneath the gate 354 is where a channel between the drain and source of the power transistor is formed in response to application of a high voltage to the gate 354.

[0072] In the foregoing description, numerous details are set forth to provide an understanding of the subject disclosed herein. Flowever, implementations may be practiced without some of these details. Other implementations may include modifications and variations from the details discussed above. It is intended that the appended claims cover such modifications and variations.

Claims

What is claimed is:

1. A circuit comprising: a substrate; a power transistor to connect a power supply voltage to an activatable device, the power transistor having an n-type source in a first p-body region; and a clamp between a control gate of the power transistor and the n-type source of the power transistor, wherein the clamp comprises: an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) having a node arranged in a second p-body region, the first p-body region and the second p-body region being part of a same layer in the substrate.

2. The circuit of claim 1 , further comprising an n-well in the substrate, wherein the first p-body region and the second p-body region are in the n-well.

3. The circuit of claim 1 , wherein the n-channel MOSFET of the clamp is a diode-connected MOSFET.

4. The circuit of claim 1 , wherein the n-channel MOSFET of the clamp is a first n-channel MOSFET, and wherein the clamp further comprises a second n-channel MOSFET in series with the first n-channel MOSFET.

5. The circuit of claim 4, wherein the clamp further comprises a third n-channel MOSFET in series with the first n-channel MOSFET and the second n-channel MOSFET.

6. The circuit of claim 4, wherein the clamp further comprises a current mirror in parallel with a series arrangement including the first n-channel MOSFET and the second n-channel MOSFET.

7. The circuit of claim 6, wherein the current mirror comprises an n-channel MOSFET having a node arranged in the second p-body region.

8. The circuit of claim 1 , wherein the node of the n-channel MOSFET in the second p-body region is a drain, and wherein a source of the n-channel MOSFET is also in the second p-body region.

9. A fluid dispensing device comprising: a substrate; a fluidic actuator arranged over the substrate and that upon activation causes a fluid flow of the fluid dispensing device; a power transistor to connect a power supply voltage to the fluidic actuator, the power transistor having an n-type source in a first p-body region; and a clamp between a control gate of the power transistor and the n-type source of the power transistor, wherein the clamp comprises: a plurality of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein each n-channel MOSFET of the plurality of n- channel MOSFETs has a node arranged in a second p-body region, the first p-body region and the second p-body region being part of a same layer in the substrate.

10. The fluid dispensing device of claim 9, wherein the plurality of n-channel MOSFETs are arranged in series.

11. The fluid dispensing device of claim 10, wherein the clamp further comprises a current mirror in parallel with the plurality of n-channel MOSFETs, and wherein the current mirror comprises an n-channel MOSFET having a node in the second p-body region.

12. The fluid dispensing device of claim 11 , wherein a gate of the n-channel MOSFET in the current mirror is electrically connected to a gate of an n-channel MOSFET of the plurality of n-channel MOSFETs.

13. The fluid dispensing device of claim 9, wherein the fluidic actuator comprises a firing resistor or a piezoelectric element.

14. A method of forming a device, comprising: forming, in a layer in a substrate, a first p-body region and a second p-body region; forming, in the first p-body region, an n-type source of a power transistor that is to connect a power voltage to an activatable device; and forming, in the second p-body region, an n-type drain and an n-type source of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) that is part of an over-voltage protection clamp connecting a gate of the power transistor to the n- type source of the power transistor.

15. The method of claim 14, wherein the forming of the first p-body region comprises: forming the gate of the power transistor over an n-well that is over the substrate; implanting p-type dopants into the n-well to form a p-type region in the n-well; and applying heat to grow the p-type region to extend under the gate of the power transistor, the grow the p-type region forming the first p-body region.