CN106932456B - 用于测试isfet阵列的方法和装置 - Google Patents

用于测试isfet阵列的方法和装置 Download PDF

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CN106932456B
CN106932456B CN201710023469.0A CN201710023469A CN106932456B CN 106932456 B CN106932456 B CN 106932456B CN 201710023469 A CN201710023469 A CN 201710023469A CN 106932456 B CN106932456 B CN 106932456B
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J.博兰德
K.G.法伊夫
M.J.米尔格鲁
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Abstract

本发明提供了化学敏感的晶体管器件(诸如ISFET装置)的测试，无需将所述装置暴露于液体。在一个实施方案中，本发明执行第一试验来计算晶体管的电阻。基于所述电阻，本发明执行第二试验，以使试验晶体管在多个模式之间转变。基于对应的测量结果，然后在几乎没有至没有电路开销的情况下计算浮动栅电压。在另一个实施方案中，使用至少任一个源或排出装置的寄生电容来偏压ISFET的浮动栅。施加驱动电压和偏压电流，以利用寄生电容来测试晶体管的功能性。

Description

用于测试ISFET阵列的方法和装置
相关申请
本申请要求2010年6月30日提交的美国临时申请系列号61/360,493和2010年7月1日提交的美国临时申请系列号61/360,495的优先权权益，它们每篇的公开内容通过引用整体并入本文。
背景技术
电子装置和组件已经在化学和生物学(更一般地，“生命科学”)中得到众多应用，特别是用于检测和测量不同的化学和生物反应，以及鉴别、检测和测量不同的化合物。一种这样的电子装置被称作离子敏感的场效应晶体管，在相关文献中经常表示为ISFET(或pHFET)。ISFET常规地主要在科学和研究团体中采用，用于便利溶液的氢离子浓度(通常表示为“pH”)的测量。
更具体地，ISFET是一种阻抗转化装置，其以类似于MOSFET(金属氧化物半导体场效应晶体管)的方式运行，且为选择性地测量溶液中的离子活性而特别构建(例如，溶液中的氢离子是“分析物”)。在“Thirty years of ISFETOLOGY：what happened in the past30years and what may happen in the next 30years，”P.Bergveld，Sens.Actuators，88(2003)，第1-20页(所述出版物通过引用整体并入本文)中，给出了ISFET的详细运行理论。
使用常规CMOS(互补金属氧化物半导体)方法来制造ISFET的细节，可以参见：Rothberg，等人，美国专利公开号2010/0301398，Rothberg，等人，美国专利公开号2010/0282617，和Rothberg等人，美国专利公开2009/0026082；这些专利公开统称为“Rothberg”，并且都通过引用整体并入本文。但是，除了CMOS以外，也可以使用biCMOS(即，两极的和CMOS)加工，诸如包括PMOS FET阵列的方法，所述阵列具有在外围上的两极结构。可替换地，可以采用其它技术，其中敏感元件可以用三端装置来制作，其中感知的离子会导致信号的形成，所述信号控制3个终端之一；这样的技术还可以包括，例如，GaAs和碳纳米管技术。
以CMOS为例，P-型ISFET制造是基于p-型硅衬底，其中形成n-型孔，它构成晶体管“主体”。在n-型孔内形成高度掺杂的p-型(p+)区域S和D，它们构成ISFET的源和排出装置。在n-型孔内还形成高度掺杂的n-型(n+)区域B，以提供与n-型孔的传导体(或“块”)的连接。氧化物层可以安置在源、排出装置和主体接头区上面，穿过它们制作开口，以提供与这些区域的电连接(通过电导体)。在源和排出装置之间，在n-型孔区域上面的位置，可以在氧化物层上面形成多晶硅栅。因为它安置在多晶硅栅和晶体管主体(即，n-型孔)之间，所述氧化物层经常被称作“栅氧化物”。
类似于MOSFET，ISFET的运行是基于由MOS(金属氧化物半导体)电容造成的电荷浓度(和因而通道电导)的调节，所述电容由多晶硅栅、栅氧化物和在源和排出装置之间的孔(例如，n-型孔)区域组成。当在栅和源区域之间施加负电压时，通过剥夺该区域的电子，在该区域和栅氧化物的界面处建立通道。就n-孔而言，所述通道是p-通道(反之亦然)。在n-孔的情况下，所述p-通道在源和排出装置之间延伸，且当栅-源负电势足以从源吸收孔进入通道时，传导电流穿过p-通道。通道开始传导电流时的栅-源电势称作晶体管的阈值电压vth(当vgs具有大于阈值电压vth的绝对值时，晶体管传导)。源因此得名，因为它是流过通道的电荷载体(p-通道的孔)的源；类似地，排出装置是电荷载体离开通道的地方。
如Rothberg所述，可以制造具有浮动栅结构的ISFET，所述浮动栅结构如下形成：将多晶硅栅联接到多个金属层上，所述金属层安置在一个或多个额外的氧化物层内，所述氧化物层安置在栅氧化物的上面。浮动栅结构由此得名，因为它与其它的ISFET相关导体在电学上分离；也就是说，它夹在栅氧化物和钝化层之间，所述钝化层安置在浮动栅的金属层(例如，顶金属层)的上面。
如Rothberg进一步所述，ISFET钝化层构成离子敏感的膜，其产生装置的离子灵敏度。与钝化层(尤其可以位于浮动栅结构上面的敏感区域)相接触的分析物溶液(即，含有目标分析物(包括离子)的溶液，或被测试目标分析物存在的溶液)中的分析物(诸如离子)的存在，会改变ISFET的电特征，从而调节流过ISFET的源和排出装置之间的通道的电流。钝化层可以包含多种不同材料中的任一种，以促进对特定离子的灵敏度；例如，包含氮化硅或氮氧化硅以及金属氧化物(诸如硅、铝或钽的氧化物)的钝化层通常会提供对分析物溶液中氢离子浓度(pH)的灵敏度，而包含聚氯乙烯(含有缬氨霉素)的钝化层会提供对分析物溶液中钾离子浓度的灵敏度。适用于钝化层且对其它离子(诸如钠、银、铁、溴、碘、钙和硝酸盐)敏感的物质是已知的，且钝化层可以包含多种材料(例如，金属氧化物、金属氮化物、金属氮氧化物)。关于在分析物溶液/钝化层界面处的化学反应，用于ISFET的钝化层的特定材料的表面可以包括这样的化学基团：其可以为分析物溶液捐献质子，或接受来自分析物溶液的质子，在任意给定的时间在分析物溶液界面处的钝化层的表面上剩下带负电荷的、带正电荷的和中性的位点。
关于离子灵敏度，通常称作“表面电势”的电势差出现在钝化层和分析物溶液的固/液界面处，随敏感区域中的离子浓度而变化，这是由于化学反应(例如，通常包含在敏感区域附近的分析物溶液中的离子对氧化物表面基团的解离)。该表面电势又影响ISFET的阈值电压；因而，ISFET的阈值电压随着在敏感区域附近的分析物溶液中的离子浓度的变化而变化。如Rothberg所述，由于ISFET的阈值电压VTH对离子浓度敏感，源电压Vs提供与在ISFET的敏感区域附近的分析物溶液中的离子浓度直接有关的信号。
化学敏感的FET(“chemFET”)的阵列或更具体地ISFET，可以用于监测反应——包括例如核酸(例如，DNA)测序反应，这基于监测在反应过程中存在的、产生的或使用的分析物。更通常地，包括chemFET的大阵列在内的阵列可以用于检测和测量在众多化学和/或生物学过程(例如，生物学或化学反应、细胞或组织培养或监测、神经活性、核酸测序等)中的多种分析物(例如，氢离子、其它离子、非离子型分子或化合物等)的静态和/或动态量或浓度，其中基于这样的分析物测量可以得到有价值的信息。这样的chemFET阵列可以用于检测分析物的方法中和/或通过在chemFET表面处的电荷的变化而监测生物学或化学过程的方法中。ChemFET(或ISFET)阵列的这种用途包括：检测溶液中的分析物，和/或检测在chemFET表面(例如ISFET钝化层)上结合的电荷的变化。
关于ISFET阵列制造的研究记载在下述出版物中：“A large transistor-basedsensor array chip for direct extracellular imaging，”M.J.Milgrew，M.O.Riehle，and D.R.S.Cumming，Sensors and Actuators，B：Chemical，111-112，(2005)，第347-353页，和“The development 0f scalable sensor arrays using standard CMOStechnology，”M.J.Milgrew，P.A.Hammond，和D.R.S.Cumming，Sensors and Actuators，B；Chemical，103，(2004)，第37-42页，所述出版物通过引用并入本文，且在下文中共同称作“Milgrew等人”。在Rothberg中，含有关于制造和使用ChemFET或ISFET阵列的描述，所述阵列用于化学检测，包括与DNA测序有关的离子的检测。更具体地，Rothberg描述了使用chemFET阵列(特别是ISFET)来对核酸测序，其包括：将已知的核苷酸掺入反应室中的多个相同核酸中，所述反应室与chemFET接触或电容式联接，其中所述核酸与反应室中的单个珠子结合，并检测在chemFET处的信号，其中信号的检测指示一个或多个氢离子的释放，所述氢离子源自已知的三磷酸核苷酸向合成的核酸中的掺入。
用于测试以化学敏感的晶体管为基础的阵列(诸如离子敏感的场效应晶体管(ISFET)阵列)的现有技术包括“湿试验”。ISFET阵列对流体中的化学组成的变化敏感。因此，通常如下测试1SFET阵列：使一种或多种液体(例如具有不同pH值的液体)在阵列上面流动，读出所述阵列中的每个ISFET元件的应答，并确定所述元件是否适当地运行。尽管湿试验具有在预期的运行条件下测试ISFET的益处，在大多数情况下认为湿试验是不实用的。
具体地，湿试验对于高体积生产而言是麻烦的且不实用的。并且，湿试验将装置暴露于流体，所述流体可能造成腐蚀和阻止所述装置在正常运行之前完全干燥。此外，装置向液体的暴露，可能产生在装置中或将来污染的缺陷。因为这些原因，一旦装置暴露于流体，生产商通常不再接受该装置。
因此，本领域需要以化学敏感的晶体管为基础的装置的干试验。
附图说明
图1图示了离子敏感的场效应晶体管(ISFET)的横截面。
图2图示了元件阵列的框图。
图3图示了用于测试元件阵列的简化流程图。
图4图示了2-T像素阵列的一个实施例。
图5图示了3-T像素的一个实施例。
图6图示了浮动栅终端晶体管的横截面。
图7图示了与浮动栅终端晶体管等效的电路示意图。
图8图示了在测试阶段中的与浮动栅终端晶体管等效的电路示意图。
具体实施方式
本发明的实施方案提供了一种测试化学检测装置的方法，所述装置包括像素元件阵列，其中每个像素元件包括化学敏感的晶体管，所述晶体管具有源终端、排出装置终端和浮动栅终端。所述方法可以包括：共同地连接一组化学敏感的晶体管的源终端，在该组的源终端处施加第一试验电压，测量由第一试验电压在排出装置终端处产生的对应的第一电流，并基于所述第一试验电压和电流计算电阻值。所述方法还可以包括：在该组的源终端处施加第二试验电压，以在不同运行模式下运行该组，其中所述第二试验电压至少部分地基于所述电阻值，并测量由第二试验电压在排出装置终端处产生的对应的第二组电流。基于化学敏感的晶体管的第二试验电压和电流和运行性能，计算该组中的每个化学敏感的晶体管的浮动栅电压。
本发明的实施方案提供了化学敏感的晶体管阵列的干试验方法，所述晶体管具有源、排出装置和浮动栅。所述方法可以包括：将第一试验电压施加于公共源连接的化学敏感的晶体管的组；基于由第一组试验电压产生的第一试验电压和电流，计算电阻；施加第二试验电压，其中所述第二试验电压驱动化学敏感的晶体管在多个运行模式之间转变，且其中所述第二试验电压部分地基于计算的电阻；计算每个驱动的化学敏感的晶体管的浮动栅电压；和确定每个计算的浮动栅电压是否在预定的阈值内。
本发明的实施方案提供了一种装置，所述装置包括化学检测元件阵列和测试电路。每个元件可以包括化学敏感的场效应晶体管，所述晶体管具有半导体主体终端、源终端、排出装置终端和浮动栅终端。所述测试电路可以包括：在所述阵列的每侧处的多个驱动电压终端，其中所述多个驱动电压终端与多个源终端和多个主体终端联接，和电流源，所述电流源与所述阵列中的至少一个元件的排出装置终端联接，以通过将排出装置电流转化成对应的电压测量值来测量排出装置电流。
本发明的实施方案提供了一种测试晶体管的方法，所述晶体管具有浮动栅和重叠电容，所述重叠电容是在所述浮动栅与第一和第二终端中的至少一个之间。所述方法可以包括：将试验电压施加于所述晶体管的第一终端，偏压所述晶体管的第二终端，测量在所述第二终端处的输出电压，和确定所述输出电压是否在预定范围内。经由重叠电容的试验电压可以将晶体管置于活化模式。
本发明的实施方案提供了一种装置，所述装置包括检测元件阵列和试验电路。每个元件可以包括场效应晶体管，所述晶体管具有浮动栅、第一终端、第二终端和重叠电容，所述重叠电容是在所述浮动栅与所述第一和第二终端中的至少一个之间。所述测试电路可以包括：与至少一个第一终端联接的驱动电压终端、与至少一个第二终端联接的偏压电流终端、和与至少一个第二终端联接的输出电压测量终端。
本发明的实施方案涉及用于测试离子感知装置(诸如ISFET装置)的系统和方法。通常，ISFET感知在所述ISFET上面形成的微孔中的化学组成的变化。这样的化学变化可以由所述微孔含有的流体中的化学反应造成。图1是ISFET 100的简化图。ISFET 100被解释为NMOS装置；但是，PMOS装置也可以用于本发明的方面中。在该实施方案中，ISFET 100是具有4个终端的半导体器件。所述4个终端是栅终端110、排出装置终端120、源终端130和主体终端140。所述栅终端110可以是浮动栅。
ISFET 100可以包括浮动栅，在所述浮动栅上面存在微孔。该微孔可以含有氧化物(或其它材料)，所述氧化物具有造成特定离子物质结合的表面位点，从而诱导电荷分布的变化，和造成在所述表面处的电势变化。该表面电势的变化然后可以由ISFET检测，并由读出电路测量，其代表所述微孔内含有的离子的量。以此方式，阵列(例如，图2的ISFET元件阵列210)中的每个ISFET可以用于检测在所述阵列上面存在的样品液体的离子浓度的局部变化。
ISFET 100可以与标准MOSFET装置类似地运行，且可以在几个运行区域之间转换。当ISFET 100被偏压使得VGS-Vth为正值且大于VDS时，所述晶体管是处于三极管区域，它也通常称作线性区域。在所述三极管区域，可以将穿过排出装置终端120的电流ID定义为：
Figure BDA0001208116900000071
三极管区域方程式
其中μn是电荷-载体有效迁移系数，Cox是每单位面积的栅氧化物电容系数，W是栅宽度，L是栅长度，VGS是栅和源终端之间的电压，Vth是阈值电压，且VDS是排出装置和源终端之间的电压。在三极管区域中，所述晶体管具有在排出装置和源之间的欧姆性能，且所述排出装置电流没有饱和。
当VGS-Vth为正值且小于VDS时，ISFET 100运行在饱和区域，它也通常称作活化区域。在饱和区域中，穿过排出装置终端120的电流ID可以定义为：
Figure BDA0001208116900000072
饱和区域方程式
其中μn是电荷-载体有效迁移系数，Cox是每单位面积的栅氧化物电容系数，W是栅宽度，L是栅长度，VGS是栅和源终端之间的电压，Vth是阈值电压，VDS是排出装置和源终端之间的电压，且λ是通道长度调节因子。
ISFET 100也具有依赖于体电势的阈值电压。所述体电势称作在终端140处的体电压，且可以作为第二栅运行。体效应可以定义为：
Figure BDA0001208116900000073
体效应方程式
其中VTN是当衬底偏置存在时的阈值电压，VTO是零-阈值电压的VSB值，VSB是源和主体终端之间的电压，γ是体效应参数，且2φ是表面电势参数。
ISFET 100可以放入像素元件中，所述像素元件可以是阵列的一部分。图2解释了具有ISFET元件阵列210的装置200。在阵列210中的每个元件可以包括上面图1所述的ISFET，且还可以包括其它晶体管和电组件。阵列210可以排列为多个行和列。阵列210还可以具有在列的两端和在行的两侧处的ISFET终端连接，且因而可以具有在阵列210的4个边缘中的每一个处的ISFET终端连接。所述主体连接可以设定为偏置电压。例如，每个边缘可以具有在如下所述的阵列210中的ISFET的源连接。
阵列210通常较大，因而沿着所述阵列的源电阻可以在晶体管孔的固有电阻和与源的连接方面存在差异。在本发明的一个实施方案中，通过策略性地将主体和源连接通路放在阵列周围的不同物理位置处，可以测试ISFET阵列210。然后可以校准源连接的电阻，以确定希望的浮动栅电压的准确表示。
图3解释了根据本发明的一个实施方案，用于测试ISFET阵列的方法300的简化流程图，其中不存在与阵列接触或邻近的流体。最初，可以使所述装置进入试验模式，其中装置电路可以共同地连接所有ISFET的源(即，所有ISFET源连接到一起)(步骤310)。在另一个实施方案中，所述阵列电路可以共同地连接交替行或列的源(例如，奇数行的源连接到一起，且偶数行的源连接到一起)。交替的行或列排列可以是结构阵列测试技术，以允许试验操作测试行和列的阵列的完整性。例如，可以如下测试列缺陷的存在(例如，由生产缺陷导致2列一起缩短)：驱动奇数列(但是偶数列不然)升高(例如通过施加电压)，并测量偶数列以观察偶数列是否保持较低。如果偶数列测得较高，这鉴别出缺陷列。就行测试而言，可以驱动一行，并可以测量该行的另一侧，以确保信号穿过该阵列。因而，结构阵列试验可以测试阵列中的行和列的连接性。除了根据需要连接阵列中的ISFET的源以外，还可以建立与ISFET的排出装置的其它或类似连接。
在建立源连接以后，可以进行第一试验(步骤320)。在第一试验中，可以强制(施加)第一试验电压穿过阵列。所述第一试验电压可以施加于装置的多侧，诸如阵列中列的任一端或行的任一侧。例如，可以将第一试验电压顺序地施加于每一侧。可以将第一试验电压施加于连接的ISFET的主体和源终端。所述第一试验电压可以包括初始电压扫除，以鉴别合适的运行(或偏压)电压，从而测试像素阵列。
然后可以得到与第一试验相对应的第一试验测量(步骤330)。第一试验电压可以生成穿过每个连接的ISFET的对应电流。然后可以测量生成的电流。在本发明的实施方案中，可以提供不同的电压和电流测量范围。例如，当将主体设置给模拟供给电压或模拟接地(取决于ISFET是PMOS或NMOS装置)的偏置电压时，可以强制源和排出装置电压。然后可以通过电流源将测量的电流转化成对应的电压值，测量得到的排出装置电流。在另一个实施例中，大体而言，可以将主体设置给在模拟供给电压和模拟接地之间的电压。此外，可以将所有主体终端设置给在ISFET阵列中的相同电压，并因而，可以类似地偏压所述阵列中的所有ISFETS。另一个试验可以表征阵列之间的阈值电压失配。
基于第一试验电压值和对应的测量电流，可以计算源连接的电阻值(步骤340)。例如，可以计算源连接的电阻梯度，其显示试验电压和测量的电流之间的电阻关系。
在计算源连接的电阻值以后，可以建立与装置的一侧(例如，列的一端)有关的主体和源连接。然后可以进行第二试验(步骤350)。在第二试验中，可以通过阵列强制或施加第二试验电压和电流。所述第二试验电压可以是在不同运行(或偏压)电压点处的电压扫除。因此，相应地可以设置主体连接，其是偏置电压。所述第二试验电压和电流可以是将以如上所述的不同运行模式(诸如三极管模式和饱和模式)运行ISFET的电压范围的扫除。此外，通过使用主体终端作为第二栅，可以以体效应模式运行ISFET。
然后可以得到与第二试验相对应的第二试验测量结果(步骤360)。在强制或施加第二试验电压和电流的每次重复中，可以测量在阵列上看到的不同的电流和电压。例如，可以强制源和排出装置电压，同时体电压在模拟供给电压和模拟接地电压之间的范围内。通过可以将电流转化成对应的电压值的电流源，可以测量生成的排出装置电流。基于强制的和测量的电压和电流，可以计算ISFET的栅电压(步骤370)。具体地，上述的不同模式的运行方程式可以用于基于强制的和测量的电压和电流来计算栅电压。因而，可以计算每个ISFET元件的栅电压，以确定ISFET是否适当地工作。
在一个实施方案中，可以针对装置的一个或多个其它侧(例如，列的相对端)，重复步骤350-370。在另一个实施方案中，可以在增加或降低强制的电压和电流例如2倍以后，重复步骤350-370。然后可以从调节的电压(偏压点)计算栅电压。也可以针对装置的一个或多个其它侧，重复增加或降低重复。并且，增加或降低重复可以重复多次，在每次中，通过每次重复的某种因子，调节强制的电压和电流。在所有重复结束以后，可以将计算的栅电压一起取平均值，以得到ISFET栅电压的更准确表示。然后可以将平均的栅电压与希望的阈值范围进行对比，以确定每个ISFET是否适当地工作。此外，每个ISFET栅电压的位置(例如，阵列中的X和Y列和行)值和/或每个ISFET的工作条件可以记录在例如寄存器中。可以提供额外电路，以允许编程和/或擦除每个像素元件，其中可以编程和/或擦除每个ISFET的浮动栅电压。在有些实施方案中，编程/擦除能力可以提供更高的故障检测覆盖水平。但是，编程/擦除电路可以在比其它电路组件更高的电压运行，可能需要施加用于分离更高电压电路的设计技术，以确保电路组件不受损伤。
在另一个实施方案中，除了电压和电流以外，也可以改变装置的温度，以调节ISFET元件的阈值电压。通过改变温度，可以观察交替的数据点，并用于计算ISFET元件的栅电压。
此外，各个像素元件的电路可以采取多种不同的形式。图4解释了显示4个像素元件的双晶体管(2-T)像素阵列400，其可以用于本发明的方面中。所述像素阵列400可以包括多个像素元件401.1-401.n。每个像素元件401可以包括1个ISFET 410和另一个晶体管420。在2-T像素实施方案中，通过控制和/或测量除了ISFET的浮动栅终端以外的所有结，可以测试该阵列。
图5解释了三-晶体管(3-T)像素元件500，其可以用于本发明的方面中。所述像素元件500可以包括1个ISFET 510和2个其它的晶体管520、530。在3-T像素实施方案中，通过控制和/或测量除了ISFET的浮动栅终端以外的所有结，可以测试该阵列。所述1-Sink可以是可控制的电流源，以给ISFET提供恒定电流。在该实施方案中，所述I Sink容量会添加另一个测量点，后者可以用于更准确地计算栅电压。像素电路的其它变化可以与本发明的实施方案一起使用。
上述的本发明的干试验实施方案利用浮动栅晶体管的特征来测试浮动栅晶体管的功能性。因此，可以在几乎没有至没有电路开销的情况下测试装置的运行，且可以优化阵列大小，因为在阵列区域中不需要额外的试验电路。此外，本发明的实施方案不需要液体来完全测试阵列；因此，会避免可能的污染。
尽管已经描述了本发明的方面，其中可以在不使用液体的情况下测试ISFET阵列，本发明的方面可以与液体使用结合地用于测试目的。例如，可以在本文所述的干试验技术之前、过程中或之后，施加具有已知pH的液体。因而，如果需要的话，本文所述的干试验技术可以与湿试验技术一起使用。
此外，已经使用ISFET描述了本文的本发明的不同实施方案。但是，本发明不限于ISFET，且可以适用于其它合适的浮动栅晶体管器件或其它合适的化学敏感的晶体管。
在本发明的另一个实施方案中，可以使用与浮动栅联接的寄生电容来测试浮动栅晶体管的功能性。图6显示了浮动栅晶体管600(诸如ISFET)的简化图。所述晶体管600可以包括浮动栅612、排出装置614和源616。在该实施方案中，所述排出装置614和源616可以是在n-型衬底内的p-型植入物，从而形成p-通道FET装置。但是，本领域技术人员会理解，使用n-通道FET装置(其具有使用在p-型半导体内的n-型植入物形成的排出装置和源)，可以形成所述晶体管600。
通常，使用自对齐的方法，可以形成ISFET。可以形成多晶硅栅，且可以在栅氧化物615或其它合适的栅绝缘体上形成浮动栅612。可以在几个步骤中制备源和排出装置植入物。在施加氮化物隔离物之前，可以制备LDD(轻度掺杂的排出装置)植入物。所述LDD植入物在栅下面扩散小距离，以减小电场和减小晶体管性能的不利方面诸如热载体。所述LDD植入物与变性掺杂植入步骤一起，形成排出装置614和源616。所述排出装置614和源616可以具有部分地重叠的部分607、608，所述部分排列在栅氧化物615的各个部分下面。所述重叠部分607、608形成在它们各自的植入物内，使得植入物部分是在建立寄生电容的浮动栅电极的下面。可以调节与重叠部分的大小有关的工艺参数，以控制重叠部分和它们的电容的大小。
图7显示了与晶体管600等效的电路示意图，其解释了在栅和源之间的寄生电容(CGS)和在栅和排出装置之间的寄生电容(CGD)。可替换地，寄生电容可以仅存在于栅和排出装置之间，或仅存在于栅和源之间。
在本发明的一个实施方案中，无需使用流体偏压来运行浮动栅，使用上述的寄生电容，即可测试浮动栅晶体管。图8解释了在根据本发明的一个实施方案的阵列中，像素元件的浮动栅晶体管试验结构。图8的浮动栅晶体管(例如ISFET)排列成源极跟随器构型；但是，本领域技术人员会理解，其它构型适用于诸如公共源。浮动栅晶体管的排出装置可以联接至电压电源VDD，以驱动晶体管。例如，VDD可以是3伏特。可以用电流源偏压浮动栅晶体管的源。例如，所述电流源可以是1μA电流源。
然后可以测量在源处的电压(在图8中显示为VOUT)。所述源电压VOUT可以代表在浮动栅上的电压。晶体管的寄生电容会强制浮动栅进入饱和区域，且因而，所述晶体管可以生成源电压VOUT，其跟随目标栅电势。可以设计晶体管的阈值电压和寄生电容值，以允许与浮动栅适当联接，所述浮动栅足以使晶体管进入它的运行范围内。
如果源电压VOUT是在阵列的正态分布的预期范围内，可以认为像素是运行的，因为所述试验确定，浮动栅晶体管可以生成有效的且可测量的信号。但是，如果测量的信号与正态分布相比太高或太低，它可以指示，过量捕集的电荷可以存在于浮动栅处。并且，如果在测试的阵列中的测量值的分布明显较宽，它可以指示各个像素元件的较大不均匀度。较大不均匀度通常被认为是不可靠的，且因而所述阵列可能是不可用的。
在另一个实施方案中，可以扩展浮动栅晶体管试验，以测量像素的增益和/或确定其它像素性质。此外，可以如下进行试验：不使用流体偏压来运行浮动栅，并因此维持阵列的完整性。
在一个实施方案中，可以改变排出装置电压，同时测量对应的测量源电压。源偏压电流可以保持恒定，同时改变排出装置电压。在第一步中，可以将第一电压施加于排出装置，例如3V，并相应地可以偏压源。在第二步中，可以将排出装置电压调节至第二电压，例如2.8V，同时将在源处的偏压电流从第一步保持恒定。可以测量对应的源电压。排出装置电压差(在实施例中，200mV)联接至浮动栅，因为重叠电容CGD。得到的源电压因而可以是排出装置电压差的分数。测量值与输入电压之比代表像素增益，且可以用于确定其它感兴趣的像素性质。
本文具体地解释和描述了本发明的几个实施方案。但是，应当理解，上述教导覆盖本发明的改进和变体。在其它情况下，没有详细描述公知的操作、组件和电路，以免影响对实施例的理解。可以理解，本文所公开的具体结构和功能细节可以是代表性的，而不一定限制实施方案的范围。
本领域技术人员从前面的描述可以理解，本发明可以以多种形式实现，且各个实施方案可以单独地或组合地实现。因此，尽管已经结合其具体实施例描述了本发明的实施方案，不应如此限制本发明的实施方案和/或方法的真实范围，因为熟练的从业人员在研究附图、说明书和下述权利要求以后会明白其它修改。
各个实施方案可使用硬件元件、软件元件或者它们的结合来实现。硬件元件的实例可以包括：处理器、微处理器、电路、电路元件(例如晶体管、电阻器、电容器、电感器等)、集成电路、专用集成电路(ASIC)、可编程逻辑装置(PLD)、数字信号处理器(DSP)、现场可编程门阵列(FPGA)、逻辑门、寄存器、半导体器件、芯片、微芯片、芯片组等。软件的实例可以包括：软件组件、程序、应用、计算机程序、应用程序、系统程序、机器程序、操作系统软件、中间件、固件、软件模块、例程、子例程、函数、方法、过程、软件接口、应用程序接口(API)、指令集、计算代码、计算机代码、代码段、计算机代码段、字、值、符号或者它们的任何结合。确定实施方案是否使用硬件元件和/或软件元件来实现，可根据任何数量的因素而改变，所述因素例如希望的计算速率、功率级、耐热性、处理周期预算、输入数据速率、输出数据速率、存储器资源、数据总线速度以及其它设计或性能限制。
一些实施方案可以例如使用计算机可读介质或产品来实现，所述介质或产品可存储指令或指令集，所述指令或指令集如果被机器执行，会使所述机器执行根据实施方案的方法和/或操作。这样的机器可包括例如：任何适当的处理平台、计算平台、计算装置、处理装置、计算系统、处理系统、计算机、处理器等，并且可使用硬件和/或软件的任何适当组合来实现。所述计算机可读介质或产品可包括例如：任何适当类型的存储器单元、存储器装置、存储器产品、存储器介质、存储装置、存储产品、存储介质和/或存储单元，例如存储器、可移动或不可移动介质、可擦除或不可擦除介质、可写或可重写介质、数字或模拟介质、硬盘、软盘、光盘只读存储器(CD-ROM)、可记录光盘(CD-R)、可重写光盘(CD-RW)、光盘、磁介质、磁光介质、可移动存储卡或盘、各种类型的数字多功能光盘(DVD)、磁带、盒式磁带等。所述指令可以包括任何适当类型的代码，例如源代码、编译代码、解释代码、可执行代码、静态代码、动态代码、加密代码等，所述代码使用任何适当的高级的、低级的、面向对象的、可视的、编译的和/或解释的编程语言来实现。

Claims (6)

1.一种测试晶体管的方法，所述晶体管具有浮动栅和重叠电容，所述重叠电容是在所述浮动栅与第一和第二终端中的至少一个之间，所述方法包括：
将试验电压施加于所述晶体管的所述第一终端；
偏压所述晶体管的第二终端；
测量在所述第二终端处的输出电压；和
确定所述输出电压是否在预定范围内；
其中经由所述重叠电容的试验电压将所述晶体管置于活化模式，并且
其中所述第一终端是排出装置终端并且所述第二终端是源终端。
2.根据权利要求1所述的方法，其中所述晶体管是ISFET。
3.根据权利要求1所述的方法，其另外包括：
调节所述试验电压至另一电压值；
将调节过的试验电压施加于所述第一终端；
测量在所述第二终端处的第二输出电压；和
基于所述输出电压，测定晶体管性能。
4.根据权利要求3所述的方法，其中所述晶体管性能是晶体管增益。
5.根据权利要求1所述的方法，其中由与所述晶体管的终端植入物部分地重叠的栅氧化物层材料形成所述重叠电容。
6.根据权利要求2所述的方法，其中没有流体样品与所述浮动栅终端接触或邻近。
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TWI539172B (zh) 2016-06-21
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US20220082607A1 (en) 2022-03-17
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