TWI557859B - 內埋式半導體封裝件及其製作方法 - Google Patents
內埋式半導體封裝件及其製作方法 Download PDFInfo
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Description
本發明是有關於一種具有電性電路的基板及其製作方法,且特別是有關於一種內埋式半導體封裝件及其製作方法。
半導體元件變得日益複雜、透過對更小尺寸的需求以驅動至少一部分以及提升處理速度。同時,更包括對許多小型化電子產品的需求,其中電子產品包括這些半導體元件。半導體元件為一典型的封裝體,之後也許可被安裝於包括電子電路的一基板中,此基板例如是一電路板。此導致半導體元件封裝以及基板佔據了封裝空間,且半導體元件封裝佔據基板的表面區域。此外,透過進行封裝製程、製作電路板以及組裝這些分開的過程亦會增加額外的成本。如何減少基板上之半導體元件所佔據的封裝空間以及簡化與結合封裝製程、製作電路板以及應用於半導體元件以及基板的組裝過程已成為非常重要的課題。
以此背景技術而言,需要提升技術以發展元件內埋式基板及其所述之相關的方法。
本發明提供一種內埋式半導體封裝件。在一實施例中,內埋式半導體封裝件包括一具有一電性接點的半導體元件、一上方圖案化導電層、一介於上方圖化導電層與半導體元件之間的介電層、一第一內層電性連接層、一下方圖案化導電層、一導通孔以及一第二內層電性連接層。介電層具有一暴露電性接點的第一開口以及一從下方圖案化導電層延伸至上方圖案化導電層的第二開口。第一內層電性連接層從電性接點延伸至上方圖案化導電層,且填充第一開口。第二開口具有一上部分與一下部分,其中上部分暴露出上方圖案化導電層的,而下部分暴露出下方圖案化導電層。導通孔填充第二開口的下部分。第二內層電性連接層填充第二開口的上部分。
本發明的另一方面是有關於一內埋式半導體封裝件的製作方法。於一實施例中,內埋式半導體封裝件的製作方法包括:(1)提供一第一圖案化導電層以及一半導體元件;(2)形成一從第一圖案化導電層垂直延伸的導通孔,導通孔具有一上表面;(3)配置一介電層與一覆蓋半導體元件與導通孔的導電片,其中導電片鄰近介電層的一上表面,且介電層分離導電片與半導體元件以及導電片與導通孔;(4)形成一第一開口,第一開口延伸穿過導電片與介電層,以暴露導通孔的上表面;(5)形成一第一內層電性連接層,連接導通孔至導電片,其中第一內層電性連接層填充第一開口;以及(6)從導電片形成一第二圖案化導電層。
本發明的另一方面是有關於一內埋式半導體封裝件的製作方法。於一實施例中,內埋式半導體封裝件的製作方法包括:(1)提供一半導體元件以及一具有一下表面的第一導電片;(2)形成一鄰近第一導電片之下表面的導電塊;(3)配置一鄰近第一導電片之下表面且覆蓋導電塊之一側表面的介電層;(4)配置一鄰近介電層與導電塊的下方介電層,下方介電層覆蓋導電塊的一下表面;(5)從第一導電片形成一第一圖案化導電層,第一圖案化導電層具有一鄰近下方介電層的下表面以及一上表面;(6)形成一從第一圖案化導電層之上表面垂直延伸的導通孔;(7)於形成導通孔之後,移除導電塊以形成一延伸穿過介電層且暴露出部分下方介電層的第一開口;以及(8)配置半導體元件的至少一部分於第一開口內且鄰近部分下方介電層。
發明的其他方面和實施例亦可被預期。前面總結和以下詳細描述並非用以限定本發明,而是僅僅描述本發明的一些實施例。
請參考圖1,其繪示為本發明之一實施例之一種內埋式半導體封裝件100的透視圖。內埋式半導體封裝件100亦可意指為一內埋式封裝體、基板與/或模組,且可包括主動元件、被動元件或主動元件與被動元件兩者。在此實施例中,內埋式半導體封裝件100的多個側邊實質上為平的且具有一實質上垂直的方位,以定義出一實質上延伸環繞一內埋式半導體封裝件100之整個周圍的側向外形。此垂直的側向外形可透過降低或縮小內埋式半導體封裝件100的區域來減少整體的尺寸。此區域的減少也許是有利的,因為當堆疊至其他裝置時,此區域可對應內埋式半導體封裝件100的腳位區域。然而,內埋式半導體封裝件的側向外形,一般來說,可為任何一種形態,例如是彎曲、傾斜、階梯狀或具有粗糙的結構。內埋式半導體封裝件100的內部結構說明於圖2至圖5之實施例中。
圖2為本發明之一實施例之一種內埋式半導體封裝件200的剖面示意圖。此剖面圖是沿著圖1之線A-A所繪示,其中內埋式半導體封裝件200為內埋式半導體封裝件100的一實施例。請參考圖2,內埋式半導體封裝件200包括一半導體元件,例如是一半導體元件202,其具有一下表面204、一上表面206以及多個配置鄰近半導體元件202的一周圍且延伸於下表面204與上表面206之間的側表面208、210。在此實施例中,下表面204、上表面206、這些側表面208、210實質上皆為平的,且這些側表面208、210具有一實質上垂直於下表面204或上表面206的方位,但於其他實施例中,下表面204、上表面206、這些側表面208、210的型態與方位亦可以是其他變化。於圖2中,下表面204為半導體元件202的一背表面,且上表面206為半導體元件202的一主動面。於一實施例中,多個電性接點212a、212b配置鄰近上表面206。這些接點212提供半導體元件202與內埋式半導體封裝件200中之導電結構,例如是一圖案化導電層240(說明如下),之間的輸入與輸出電性連接。於一實施例中,下表面204與一圖案化導電層230(說明如下)之間亦可隨意地添加一黏著層213。黏著層213可包括環氧樹脂(epoxy)、樹脂或其他適當材料,以及其亦可為一漿糊。在本實施例中,雖然半導體元件202具體化為一半導體晶片,但一般來說,半導體元件202亦可為任一主動元件、任一被動元件或上述之組合。半導體元件202亦可例如是一晶圓級封裝。
圖2亦說明一被動電子元件203,其具有多個電性接點205a、205b。內埋式半導體封裝件200內亦可隨意地包括含被動電子元件203。這些接點205提供被動電子元件203與例如是圖案化導電層230、240之間的電性連接。於一實施例中,被動電子元件203與圖案化導電層230之間亦可隨意地填加一黏著層207。黏著層207亦可包括環氧樹脂、樹脂或其他適當材料,以及其亦可為一漿糊。於其他實施例中,亦可包括其他半導體元件、主動元件與或被動元件。
如圖2所繪示,半導體元件裝置200亦包括一介電層214,此介電層214配置鄰近半導體元件202與被動電子元件203。介電層214具有一下表面216與一上表面218。於此實施例中,介電層214實質上覆蓋或包覆半導體元件202、被動電子元件203、黏著層213、黏著層207與圖案化導電層230,以提供機械穩定度同時保護以阻絕氧氣、溼氣或其他環境狀態。於此實施例中,介電層214實質上覆蓋半導體元件202的上表面206與這些側表面208、210。圖案化導電層240配置鄰近上表面218,而圖案化導電層230配置鄰近下表面216。雖然於圖2之部分內埋式半導體封裝件200中僅繪示包括一介電層214來包覆一半導體元件,但於其他實施例中,並不限定內埋式半導體封裝件內包括多少介電層來包覆半導體元件。
於一實施例中,一上方介電層250可配置鄰近圖案化導電層240與介電層214的上表面218,而一附加介電塗佈層251可配置鄰近上方介電層250。或者或另外,一下方介電層260亦可配置鄰近圖案化導電層230與介電層214的下表面216。於一實施例中,一附加介電層270亦可配置鄰近下方介電層260。於其他實施例中,介電層214的上方與/或下方亦可包含多個介電層。
於一實施例中,介電層214、上方介電層250、下方介電層260以及附加介電層270可由一介電層材料例如是一聚合物(polymeric)或非聚合物(non-polymeric)所形成。舉例來說,至少一介電層214、上方介電層250、下方介電層260以及附加介電層270可由至少一液晶聚合物(liquid crystal polymer,LCP)、雙順丁烯二酸醯亞胺樹脂(bismaleimide-triazine,BT)、膠片(prepreg,PP)、含有玻璃顆粒的環氧樹脂(Ajinomoto Build-up Film,ABF)、環氧樹脂(epoxy)或聚醯亞胺(polyimide)所形成,但並不以此為限。介電層214、上方介電層250、下方介電層260以及附加介電層270可由相同介電材料或不同介電材料所形成。於其他實施例中,至少一介電層214、上方介電層250、下方介電層260以及附加介電層270可由一光成像(photoimageable)或感光(photoactive)的介電材料所形成。另外,介電層214亦可為具有纖維強化的樹脂材料,例如是玻璃纖維或克維拉纖維(Kevlar fiber),來強化介電層214的強度。藉由纖維來強化樹脂材料的例子亦可應用於介電層214包括含有玻璃顆粒的環氧樹脂(ABF)、雙順丁烯二酸醯亞胺樹脂(BT)、聚醯亞胺(polyimide)、液晶聚合物(LCP)、環氧樹脂(epoxy)或其他樹脂材料中。如下述圖6E所示,玻纖290最初在層壓而形成介電層214之前的定向是沿著一介電層614的一般水平平面。請參考圖2,玻纖290於後續介電層214之層壓後被重新定向,隨著部分鄰近導通孔224、半導體元件202以及沿著導通孔224之一垂直延伸方向伸出之被動電子元件203、半導體元件202以及被動元件203,且遠離圖案化導電層230。
請參考圖2,所形成之介電層214定義出多個開口220、221、222、223。這些開口220暴露出圖案化導電層230。每一開口220亦可實質上對齊暴露出圖案化導電層240的一對應開口221。這些開口222可暴露出半導體元件202的這些電性接點212。這些開口223可暴露出被動電子元件203的這些電性接點205。一導通孔224可實質上填入於每一開口220內,且一內層電性連接層225可實質上填入於每一開口221中。或者,導通孔224可位於每一開口220內。舉例來說,導通孔224可為一電鍍導電柱。雖然於圖2中僅示意地繪示兩個導通孔224,但於其他實施例中,內埋式半導體封裝件220亦可包括少於兩個或多於兩個導通孔224。導通孔224具有一上表面233與一下表面234。於一實施例中,上表面233可實質上與半導體元件202的主動表面206共平面。或者,若主動表面206替代圖案化導電層240面向圖案化導電層230,則上表面233可實質上與半導體元件202的背表面204共平面。導通孔224可從圖案化導電層230延伸至內層電性連接層225,且內層電性連接層225可從導通孔224延伸至圖案化導電層240。此電性連接(形成一電流於其間的導電路徑)部分圖案化導電層230與部分圖案化導電層240。一內層電性連接層226可實質上填入於每一開口222,且一內層電性連接層227可實質上填入於每一開口223。內層電性連接層226可從電性接點212延伸至圖案化導電層240,以電性連接半導體元件202至部分圖案化導電層230。內層電性連接層227可從電性接點205延伸至圖案化導電層240,以電性連接被動電子元件203至部分圖案化導電層240。
於一實施例中,每一內層電性連接層225、226、227分別具有一高度,其高度範圍介於30微米(μm)至150微米(μm)之間,例如是從約30微米(μm)至約50微米(μm)、從約30微米(μm)至100微米(μm)、從約50微米(μm)至100微米(μm)以及從約100微米(μm)至150微米(μm)。每一內層電性連接層225、226、227的直徑亦可介於150微米(μm)至250微米(μm)之間,例如是約200微米(μm)。於一實施例中,每一導通孔224可具有一高度,其高度範圍介於100微米(μm)至500微米(μm)之間,例如是從約100微米(μm)至約300微米(μm)、從約100微米(μm)至200微米(μm),以及從約140微米(μm)至160微米(μm)。
於一實施例中,每一內層電性連接層225具有一上表面231以及一下表面232,其中上表面231具有一第一區域,而下表面232具有一第二區域。同理,每一內層電性連接層226可具有一上表面235以及一下表面236,其中上表面235具有一第一區域,而下表面236具有一第二區域。每一內層電性連接層227可具有一上表面237以及一下表面238,其中上表面237具有一第一區域,而下表面238具有一第二區域。於一實施例中,第一區域大於第二區域。此外,每一導通孔224的上表面233具有一第三區域。這些導通孔224的直徑可從約150微米(μm)至約300微米(μm)。因此,於一實施例中,第三區域大於下表面232的第二區域。或者,第三區域亦可小於或等於下表面232的第二區域。於一實施例中,這些上表面231、233、235、237以及這些下表面232、234、236、238可具有一形狀包括實質上圓形、實質上橢圓形、實質上方形與實質上矩形,但並不以此為限。
於一實施例中,從導通孔224的上表面233至圖案化導電層240之間的一第一距離280小於從半導體元件202的上表面206至圖案化導電層240的一第二距離281。或者,第一距離280亦可大於或等於第二距離281。
藉由提供電性連接至圖案化導電層240、這些內層電性連接層225、226、227以允許導通孔224、半導體元件202以及被動電子元件203內埋於介電層214的上表面218。此設計可內埋半導體元件202以及被動電子元件203於介電層214中以降低內埋式半導體封裝件200的厚度。此外,藉由實質上填充的這些220、221、222、223、這些導通孔224以及這些內層電性連接層225、226、227亦可增加電性連接特徵。再者,這些內層電性連接層225、226、227無需透過孔,例如是電鍍通孔,即可提供電性連接。此設計可顯著地降低內埋式半導體封裝件200的成本。
於一實施例中,上方介電層250可定義出多個暴露圖案化導電層240的開口252。一內層電性連接層253可實質上填充每一開口252。內層電性連接層253可具有與導通孔224相似的特徵,或者,可具有與內層電性連接層225相似的特徵。一附加介電層251可配置鄰近上方介電層250。內層電性連接層253可從圖案化導電層240延伸至被附加介電層251之開口所暴露出的多個接墊254上。這些接墊254亦可使內埋式半導體封裝件200電性連接至外界。一表面處理層255亦可鄰近每一接墊254。
於一實施例中,電性連接至這些接墊254的一半導體元件(請參考圖6R之半導體元件690)亦可透過一包括內層電性連接層253與內層電性連接層226的導電路徑而電性連接至半導體元件202。導電路徑亦可包括部分圖案化導電層240。
於一實施例中,下方介電層260可定義出多個暴露出圖案化導電層230的開口262。一內層電性連接層263可實質上填充每一開口262。內層電性連接層263可具有與導通孔224相似的特徵,或者,可具有與內層電性連接層225相似的特徵。一附加介電層271可配置鄰近下方介電層260。或者,附加介電層270亦可配置於下方介電層260與附加介電層271之間。附加介電層271的開口亦可暴露出多個接墊274。這些接墊274亦可使內埋式半導體封裝件200電性連接至外界。一表面處理層275亦可鄰近每一接墊274。
於一實施例中,半導體元件202可透過一包括內層電性連接層263的導電路徑而電性連接至這些接墊274。導電路徑亦可包括一或多個導通孔224、內層電性連接層225以及內層電性連接層226。導電路徑亦可包括部分圖案化導電層230。
於一實施例中,圖2之每一圖案化導電層、內層電性連接層以及導通孔可由一金屬、一金屬合金、一具有金屬或金屬合金擴散於其內的金屬基質或其他適當導電材料所形成。舉例來說,圖2中之每一圖案化導電層、內層電性連接層以及導通孔可由鋁、銅、鈦或上述之其組合所形成。圖2中之這些圖案化導電層、這些內層電性連接層以及這些導通孔亦可由相同電性導電材料或不同電性導電材料所形成。
於一實施例中,這些表面處理層255、275的形成相似於上述圖2所述之這些圖案化導電層、這些內層電性連接層以及這些導通孔。或者,這些表面處理層225、275的形成方式亦可不同於上述。舉例來說,這些表面處理層255、275可由至少一錫、鎳與金或包含錫或鎳與金的合金所形成。這些表面處理層255、275可由相同電性導電材料或不同電性導電材料所形成。
於一實施例中,這些附加介電層251、271的形成相似於上述所述之這些介電層214、250、260、270。這些附加介電層251、271可利用焊罩層,例如是乾膜成像焊罩層(dry film imageable solder mask)或其他形式之圖案化層或介電層。於這些附加介電層251、271中分別暴露出這些電性接點274、275的這些開口可具有任何一種形態。這些型態包括一圓柱形狀,例如是一圓形圓柱形狀、一橢圓圓柱形狀、一方形圓柱形狀或一矩形圓柱形狀、或一非圓柱形狀,例如是一圓錐形、一漏斗形或其他一頭逐漸變尖細的形狀。此外,這些開口的側邊界可為曲線或具有粗糙的結構。
於一實施例中,下方介電層260可為一基材264,因此此基材264具有一單層。或者,基材264可包括二或多層,例如是下方介電層260與附加介電層270。基材264可為無核心。基材264可定義出一凹穴(請參考圖5)。透過基材264的電性連接可為這些導電連接結構,例如是內層電性連接層263。或者或此外,透過基材264的電性連接可為電鍍穿孔結構或其他已知型態之電性連接。
圖3為本發明之一實施例之一種內埋式半導體封裝件300的剖面示意圖。內埋式半導體封裝件300與圖2所述之內埋式半導體封裝件200相似,惟二者主要差異之處在於:半導體元件302為一覆晶接合之半導體元件。部分位於半導體元件302下方的圖案化導電層230可透過一熔融的導電凸塊304電性連接至晶片302,其中熔融的導電凸塊304可由一導電材料,例如是焊料,所形成。
於一實施例中,電性連接至這些接墊254的一半導體元件(未繪示)可透過一包括內層電性連接層253、內層電性連接層225以及導通孔224的導電路徑而電性連接至半導體元件302。導電路徑可包括部分圖案化導電層230、240(一些部分未繪示)。
於一實施例中,半導體元件302可透過一包括內層電性連接層263的導電路徑而電性連接至這些接墊274。導電路徑可包括部分圖案化導電層230(一些部分未繪示)。
圖4為本發明之一實施例之一種內埋式半導體封裝件400的剖面示意圖。內埋式半導體封裝件400與圖2所述之內埋式半導體封裝件200相似,惟二者主要差異之處在於:半導體元件402為一打線接合之半導體元件。部分位於半導體元件402下方的圖案化導電層230可透過多條焊線404電性連接至晶片402。
於一實施例中,電性連接至這些接墊254的一半導體元件(未繪示)可透過一包括內層電性連接層253、內層電性連接層225以及導通孔224的導電路徑而電性連接至半導體元件402。導電路徑可包括部分圖案化導電層230、240(一些部分未繪示)。
於一實施例中,半導體元件402可透過一包括內層電性連接層263的導電路徑而電性連接至這些接墊274。導電路徑亦可包括部分圖案化導電層230(一些部分未繪示)。
圖5為本發明之一實施例之一種內埋式半導體封裝件500的剖面示意圖。內埋式半導體封裝件500與圖2所述之內埋式半導體封裝件200相似,惟二者主要差異之處在於:半導體元件502至少一部分配置於介電層260所定義的一凹穴504內。於一實施例中,黏著層213配置於凹穴504內。
半導體元件502配置於凹穴504內好處是在於一較高的半導體元件502,其可支撐內埋式半導體封裝件500且無需相對於內埋式半導體封裝件200而增加內埋式半導體封裝件500之整體厚度。於一實施例中,半導體元件502具有一高度506,其中高度506大於導通孔224之一高度508與圖案化導電層230之一厚度509的總和。為了避免增加導通孔224的高度508,半導體元件502的至少一部分可配置於凹穴504內。
圖7為本發明之一實施例之一種內埋式半導體封裝件700的剖面示意圖。內埋式半導體封裝件700與圖2所述之內埋式半導體封裝件200相似,惟二者主要差異之處在於:半導體元件202的至少一部分配置於一延伸穿過一介電層715的開口704中。且,被動元件203至少部分地配置於延伸穿過介電層715且暴露出介電層260的一開口705內。(需注意的是,於此說明書中所採用之“半導體元件”亦可為任一主動元件、任一被動元件或上述之組合。)於一實施例中,半導體元件202配置鄰近介電層260。黏著層213可配置於半導體元件202與介電層260之間。於一實施例中,被動電子元件203配置鄰近介電層260。於一實施例中,黏著層207配置於被動電子元件203與介電層260之間。除此之外,介電層715具有與先前所提及之介電層260相似的特徵。
於此實施例中,單一介電層於製程中可包括多個介電層。舉例來說,介電層701包括介電層715與介電層260。位於介電層715中的開口704亦可稱為一位於介電層701中的凹穴706,其中凹穴706具有一凹穴底部716。位於介電層715中的開口705亦可稱為一位於介電層701中的凹穴707,其中凹穴707俱有一凹穴底部717。半導體元件202配置鄰近凹穴底部716,而被動電子元件203配置鄰近凹穴底部717。每一凹穴底部716與每一凹穴底部717亦可具有介電層260之一表面的至少一部分。
藉由配置半導體元件202於凹穴706中,內埋式半導體封裝件700可支撐較高的半導體元件202,而無須增加內埋式半導體封裝件700相對於內埋式半導體封裝件200的高度。於一實施例中,此可藉由部分配置半導體元件202於凹穴706中而達成。舉例來說,半導體元件202亦可具有一高於凹穴706之一高度721的高度720,但此高度720小於高度721與介電層214之一厚度722(在凹穴706上)的總和。
再者,由於凹穴706的設置,因此半導體元件202的表面一點也沒有被暴露於內埋式半導體封裝件700的一外部表面。於一實施例中,介電層214包覆半導體元件202。此不但可提供結構穩定度,亦可提供足夠的保護來避免半導體元件202受到氧化、溼氣以及其他環境條件的影響。具體來說,介電層214可實質上覆蓋半導體元件202之上表面(主動面)206的至少一部分。介電層214亦可覆蓋半導體元件202的側表面208、210。半導體元件202的下表面(背表面)204可配置鄰近凹穴716與/或介電層260。
內埋式半導體封裝件700亦可包括一延伸穿過介電層715且連接圖案化導電層230至一圖案化導電層740的導通孔。圖案化導電層230具有一底表面231。於一實施例中,半導體元件202的底表面204低於圖案化導電層230的底表面231。圖案化導電層740介於介電層715與介電層260之間。一導通孔742延伸穿過介電層260且連接圖案化導電層740至一圖案化導電層750。圖案化導電層750介於介電層260與介電層270之間。圖7中剩餘的元件標號說明於圖2中。
於一實施例中,介電層214的厚度722介於約10微米(μm)至約150微米(μm)的範圍內,例如是從約10微米(μm)至約120微米(μm)、從約10微米(μm)至100微米(μm)、從約30微米(μm)至100微米(μm)以及從約50微米(μm)至100微米(μm)。
於一實施例中,從凹穴716之一側表面736至半導體元件202之最鄰近側表面208之間的一距離738是介於約10微米(μm)至約100微米(μm)的範圍內,例如是從約10微米(μm)至約50微米(μm)、從約30微米(μm)至50微米(μm)以及從約50微米(μm)至100微米(μm)。減少距離738的優點在於可降低封裝膠體填入凹穴716內之空間所需的量,其中此凹穴716介於半導體元件202與側表面735之間。於另一方面,距離738相對於精確度應大於最小公差,而使得凹穴716與半導體元件202於製程中可以被配置。於其他實施例中,距離738可大於100微米(μm)。
圖8為本發明之一實施例之一種內埋式半導體封裝件800的剖面示意圖。內埋式半導體封裝件800與圖7所述之內埋式半導體封裝件700相似,惟二者主要差異之處在於:半導體元件302為一為一覆晶接合之半導體元件。一圖案化導電層830的一部分840透過開口704而被暴露出來,且亦可由凹穴706的凹穴底部716而被暴露出來。此外,圖案化導電層830可具有與前述圖案化導電層230相似的特徵。半導體元件302的電性接點304可配置鄰近部分840。於一實施例中,部分840可透過一熔融的導電凸塊304而電性連接至半導體元件302,其中熔融的導電凸塊304可由一導電材料,例如是焊料,所形成。
圖9為本發明之一實施例之一種內埋式半導體封裝件900的剖面示意圖。內埋式半導體封裝件900與圖7所述之內埋式半導體封裝件700相似,惟二者主要差異之處在於:半導體元件402為一打線接合之半導體元件。圖案化導電層230的部分可透過多條焊線404電性連接至半導體元件402。
圖10為本發明之一實施例之一種內埋式半導體封裝件1000的剖面示意圖。內埋式半導體封裝件1000與圖7所述之內埋式半導體封裝件700相似,惟二者主要差異之處在於:一半導體元件1002至少部分地配置於一雙層凹穴1006內。再者,一被動電子元件1003至少部分地配置於一雙層凹穴1007內。半導體元件1002具有與半導體元件202相似的特徵,除了半導體元件1002的一高度1010大於半導體元件202的高度210。雙層凹穴1006具有與雙層凹穴1007相似的特徵,因此於此僅對雙層凹穴1006作更進一步的說明。雙層凹穴1006具有由介電層715所定義出的一上部分1006a以及由一介電層1060所定義出的一下部分1006b。此外,介電層1060具有與前述所述之介電層260相似的特徵。上部分1006a延伸穿過介電層715,且下部分1006b延伸穿過介電層1060,也就是說,雙層凹穴1006延伸穿過二介電層。
雙層凹穴1006的一高度1021可大於單層凹穴706的高度721。藉由配置半導體元件1002於雙層凹穴1006內,內埋式半導體封裝件700可支撐半導體元件1002,而無須增加(或甚至減少)內埋式半導體封裝件1000相對於內埋式半導體封裝件700的高度。於其他實施例中,凹穴亦可延伸穿過多於兩層之介電層。
於一實施例中,上部分1006a的一寬度1008大於下部分1006b的一寬度1012,相差的總合至少小於或等於約50微米(μm),例如是從約10微米(μm)至約20微米(μm)、從約10微米(μm)至30微米(μm)以及從約10微米(μm)至50微米(μm)。
圖6A至圖6R繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。為了方便說明起見,以下將配合圖2之內埋式半導體封裝件200對內埋式半導體封裝件的製作方法進行詳細的說明。然而,這些製作過程可同樣地被執行以形成其他內埋式半導體封裝件,其可具有不同於內埋式半導體封裝件200的初始結構,例如是圖3至圖5所繪示之內埋式半導體封裝件。這些製作過程亦可被執行以形成包括一連接內埋式半導體封裝件之陣列的裝置條,其中每一裝置條對應如圖1至圖5之一內埋式半導體封裝件。如圖6Q所描述,連接內埋式半導體封裝件的陣列可單體化以形成如圖1至圖5之單獨的內埋式半導體封裝件。
請先參考圖6A,提供一基材條600,繪示於圖6A中的部分對應於圖2中的基材264。多個圖案化導電層602、604配置鄰近基材條600。圖6A中的部分圖案化導電層602對應於圖2中的圖案化導電層230。基材條600定義出這些開口262。這些導電連接結構263延伸於這些圖案化導電層602、604之間,且實質上填充這些開口262。每一圖案化導電層602、604可具有一從約10微米(μm)至約30微米(μm)之間的厚度,例如是從15微米(μm)至約25微米(μm)。
接著,請參考圖6B,可形成一鄰近圖案化導電層602的光阻材料。光阻材料可為一乾膜光阻或其他型態之圖案化層或介電層。可透過塗佈、印刷或其他適當的方式來形成一光阻層606。光阻層606預先決定或選擇的部分可以經由曝光與顯影,以產生多個暴露出圖案化導電層602的開口607。光阻層606可以透過一光罩(未繪示)以光化學的方式來定義。曝光與顯影相較於其他相近於光阻層606中製作開口的技術而言,可具有低成本與降低製程時間的優勢。所得到之這些開口可具有任何一種形態,包括一圓柱形狀,例如是一圓形圓柱形狀、一橢圓圓柱形狀、一方形圓柱形狀或一矩形圓柱形狀、或一非圓柱形狀,例如是一圓錐形、一漏斗形或其他一頭逐漸變尖細的形狀。此外,這些開口的側邊界可為曲線或具有粗糙的結構。
接著,請參考圖6C,填入一電性導電材料於光阻層606所定義的這些開口607內,以形成從圖案化導電層602垂直延伸的這些導通孔224。這些導通孔224可利用一些塗佈技術,例如是化學氣相沈積法(CVD)、無電電鍍法(electroless plating)、電解電鍍法(electrolytic plaitng)、電鍍法(plating)、旋轉法(spinning)、噴塗法(spraying)、濺鍍法(sputting)或真空蒸鍍法(vacuum deposition)。
接著,請參考圖6D,剝離光阻層606以暴露出圖案化導電層602。
接著,請參考圖6E,半導體元件202配置鄰近圖案化導電層602。黏著層213可配置於半導體元件202與圖案化導電層602之間。被動電子元件203配置鄰近圖案化導電層602。黏著層207可配置於被動地電性元件203與圖案化導電層602之間。
或者,請參考圖6F,於基材條600中形成凹穴504。半導體元件502可至少部分地配置於凹穴504中。於一實施例中,黏著層213配置於凹穴504內。
接著,請再參考圖6E,提供一介電層614,其中介電層614與一組第一開口614a是被預先形成,且第一開口614a的位置分別對應導通孔224、半導體元件202以及被動電子元件203。於一實施例中,介電層614包括一纖維強化的樹脂材料,例如是膠片(prepreg,PP),包括玻纖290以強化介電層614的強度。如圖6E所示,玻纖290最初是沿著介電層614的一般水平平面延伸定向。如圖6E所示之開口614a可完全延伸穿過介電層614,但開口614亦可部分地延伸穿過介電層614。
接著,請參考圖6G,介電層614配置鄰近基材條600,且覆蓋半導體元件202、被動電子元件203以及這些導通孔224。介電層614亦可覆蓋圖案化導電層602。介電層614可分開一導電片616從半導體元件202、被動電子元件203以及這些導通孔224。繪示於圖6G中的部分介電層614對應於圖2中的介電層214。於一實施例中,玻纖290於後續介電層614之層壓後被重新定向,隨著部分鄰近導通孔224、半導體元件202以及沿著導通孔224之一垂直延伸方向伸出之被動電子元件203、半導體元件202以及被動元件203,且遠離圖案化導電層230。導電片616,例如是一銅箔,可配置鄰近介電層614,舉例來說,以形成一覆蓋半導體元件202、被動電子元件203以及這些導通孔224的樹脂銅箔層。介電層614可具有一單一樹脂層或可具有一由樹脂所形成之第一子層以及一由強化樹脂所形成之第二子層,其中強化樹脂例如是具有玻璃纖維或克維拉纖維(Kevlar fiber)的強化樹脂。
於其他實施例中,介電層614可由膠片材料所形成,且導電片616可配置鄰近於介電層614。膠片材料可配置鄰近於基材條600,且可預先形成以定義這些開口於半導體元件202、被動電子元件203以及這些導通孔224上的位置。此外,膠片材料可覆蓋半導體元件202、被動電子元件203以及這些導通孔224。膠片材料可被形成一層膠層、或二層或多層膠層。或者,介電層614可包括一膠片子層與一樹脂子層的一複合層,以及導電片616可配置鄰近介電層614。膠片子層可配置鄰近基材條600,且可預先形成以定義這些開口於半導體元件202、被動電子元件203以及這些導通孔224上的位置。樹脂子層可配置鄰近膠片子層,且亦可配置鄰近基材條600由膠片子層所定義出的這些開口內。
於其他實施例中,介電層614亦可由一環氧封裝膠體所形成,例如是一封裝材料,且導電片616可配置鄰近介電層614。
於一實施例中,介電層614可壓合於基材條600上。或者,介電層614可利用任何一種成形技術來形成,例如是射出成形。一旦應用此技術,成形材料是硬的或是固體的,例如是藉由低於成形材料之熔化點的溫度以形成介電層614。或者,介電層614可利用任何一種塗佈技術來形成,例如是印刷法、轉法或噴塗法。
於一實施例中,導電片616亦可在介電層614配置鄰近於基材條600之前貼附於介電層614上。於一實施例中,已貼附有導電片616的介電層614可配置鄰近基材條600。
接著,請參考圖6H,形成包括這些開口221、222、223的這些開口。這些開口221延伸穿過導電片616與介電層614,以暴露出每一導通孔224的上表面233。這些開口222延伸穿過導電片616與介電層614,以暴露出半導體元件202的這些電性接點212。這些開口223延伸穿過導電片616與介電層614,以暴露出被動電子元件203的這些電性接點215。這些開口221、222、223可由雷射鑽孔或其他適當已知之習知技術所形成。
接著,請參考圖6I,這些開口221、222、223填入一導電材料以形成導通孔,例如是圖2中的這些內層電性連接層225、226、227。這些內層電性連接層225、226、227可利用任何一種塗佈技術,例如是無電電鍍與/或電解電鍍法所形成。
接著,於圖6J至圖6L中說明一減成法,以形成一包括圖2之圖案化導電層240的圖案化導電層。於圖6J中,附加導電材料配置鄰近這些內層電性連接層225、226、227,且鄰近導電片616。此附加導電材料形成一導電層618以電性連接至這些內層電性連接層225、226、227。
於圖6K中,形成一鄰近導電層618的光阻層620。光阻層620已預先決定或選擇的部分可曝光與顯影以形成這些開口622。這些開口622暴露出導電層618。光阻層620(與這些開口622)與圖6B之光阻層606(與這些開口607)具有相同特徵與類似的形成方式。
於圖6L中,形成暴露出介電層614的這些開口624於導電層618中,以形成一圖案化導電層640。圖6L所示之部分圖案化導電層640對應於圖2之圖案化導電層240。圖案化以形成圖案化導電層640的方式可採用任何一種方式,例如是化學蝕刻法、雷射鑽孔法或機械鑽孔法,而所形成之這些開口可為任何一種形態,例如是一圓柱形態,例如是一圓形圓柱形狀、一橢圓圓柱形狀、一方形圓柱形狀或一矩形圓柱形狀、或一非圓柱形狀,例如是一圓錐形、一漏斗形或其他一頭逐漸變尖細的形狀。此外,這些開口的側邊界可為曲線或具有粗糙的結構。
與圖6J至圖6L所說明之減層法兩者擇一,圖6M至圖6O中說明一修改半加成法(modified semi-additive process,MSAP)過程以形成一包括圖2之圖案化導電層240的圖案化導電層。修改半加成法過程是用來形成一相對於減成法具有微細間距以及較窄線路的圖案化導電層。於圖6M中,形成一鄰近導電片616的光阻層630。光阻層630之預先決定或選擇的部分可曝光與顯影以形成這些開口632。這些開口632暴露出導電片616。光阻層630(與這些開口632)與圖6B之光阻層606(與這些開口607)具有相同特徵與類似的形成方式。
於圖6N中,附加導電材料配置鄰近這些內層電性連接層225、226、227,且鄰近導電片616。附加導電材料形成一導電層634以電性連接至這些內層電性連接層225、226、227。導電片616與導電層634的結合具有一厚度635。
於圖6O中,移除圖案化光阻層630。接著,移除部分導電層634,例如是透過快速蝕刻法(flash etching),以形成圖案化導電層640。由於快速蝕刻法,圖案化導電層640的一厚度641可從圖6N之厚度635減少。
接著,於圖6P中,介電層650配置鄰近介電層614,且介電層670配置鄰近基材條600。圖6P中的部分這些介電層650、670分別對應圖2中的這些介電層250、270。這些介電層650、670的形成方式可與上述圖6G所述之介電層614的形成方式相同。這些延伸穿過這些介電層650、670的內層電性連接層,例如是這些內層電性連接層253,可採用與上述圖6C所述之這些導通孔224相同的形成方式。這些電性接點254、274的形成方式可採用與上述圖6K與圖6L所述之圖案化導電層640相同的形成方式。
接著,請參考圖6Q,一介電層651配置鄰近介電層650,且一介電層671配置鄰近介電層670。圖6Q中的部分這些介電層651、671分別對應於圖2中的這些介電層251、271。這些介電層651、671的形成方式可採用與上述圖6G所述之介電層614相同的形成方式。這些表面處理層255、275的形成方式可採用與上述圖6C所述之這些導通孔224相同的形成方式。之後,沿著多條虛線680、681進行一單體化製程,以得到單獨的內埋式半導體封裝件,例如是圖2之內埋式半導體封裝件200。
接著,請參考圖6R,一第二半導體元件690以及一被動電子元件692可電性連接至這些電性接點254。
圖11A至圖11S繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。為了方便說明起見,以下將配合圖7之內埋式半導體封裝件700,其包括圖2之內埋式半導體封裝件200的觀點,對內埋式半導體封裝件的製作方法進行詳細的說明。然而,這些製作過程可同樣地被執行以形成其他內埋式半導體封裝件,其可具有不同於內埋式半導體封裝件700的初始結構,例如是圖8至圖10所繪示之內埋式半導體封裝件。這些製作過程亦可被執行以形成包括一連接內埋式半導體封裝件之陣列的裝置條,其中每一裝置條對應如圖8至圖10之一內埋式半導體封裝件。如圖11R所描述,連接內埋式半導體封裝件的陣列可單體化以形成如圖8至圖10之單獨的內埋式半導體封裝件。
請先參考圖11A,提供一承載器1100。於一實施例中,承載器110包括一核心層(未繪示)以及二承載導電層(未繪示),其中核心層介於兩承載導電層之間,且兩承載導電層貼附核心層。每一承載導電層可由一金屬、一金屬合金、一具有金屬或金屬合金擴散於其內的金屬基質或其他適當導電材料所形成。舉例來說,每一承載導電層可包括由銅或含銅的合金所形成的一金屬銅箔。金屬銅箔可具有一介於約10微米(μm)至約30微米(μm)之間的厚度,例如是從15微米(μm)至約25微米(μm)。
承載器1100具有一上表面1102與一下表面1104。導電層1105(導電片1105)配置鄰近下表面1104。圖11A至圖11H繪示承載器1100對應下表面1104之單一側的製作方法。可預期相似的製作方法可發生於製作承載器1100之相對兩側,包括承載器1100相對於上表面1102的一側。以雙側製作為例,具有與導電片1105相似的特徵的一導電層(未繪示)可配置鄰近上表面1102。
導電片1105可由一金屬、一金屬合金、一具有金屬或金屬合金擴散於其內的金屬基質或其他適當導電材料所形成。舉例來說,導電片1105可包括由銅或含銅的合金所形成的一可剝離金屬銅箔(releasable metal foil)。導電片1105可透過一離形層(release layer)(未繪示)貼附於承載器1100上。於一實施例中,離形層可為一黏著層,其可為有機或無機,例如是膠帶。膠帶可為一單面或雙面黏著膠帶,固定元件相對於彼此於一適當間隔,且允許後續製程操作可執行元件配置鄰近承載器1100。導電片1105可具有一介於約2微米(μm)至約10微米(μm)之間的一厚度,例如是從3微米(μm)至約5微米(μm)。
接著,請參考圖11B,導電塊1106以及導通孔741形成鄰近導電片1105的一下表面1107。導電塊1106與導通孔741的形成過程相似於前述圖6B至圖6D的製作步驟。光阻材料形成鄰近下表面1107。於光阻內的開口被形成,例如是透過曝光與顯影,其對應導電塊1106與導通孔741的位置。電性連接材料應用於開口以形成導電塊1106與導通孔741。導電塊1106與導通孔741可作緩衝器。之後剝離光阻層以暴露出導電片1105。
接著,請參考圖11C,一介電層1115配置鄰近導電片1105的下表面1107。圖11C所示之介電層1115的部分對應於圖7之介電層715。介電層1115可覆蓋導電塊1106的一側表面1108。介電層1110(導電片1110)可配置鄰近介電層1115、導電塊1106以及導通孔741。於一實施例中,介電層1115可由一樹脂材料所構成。導電片1110,例如是一銅箔,可配置鄰近介電層1115,舉例來說,以形成一樹脂銅箔層。導電片1110可為一金屬,例如是一銅箔或一含銅的合金。導電片1110可透過無電電鍍法、濺鍍法或其他習知已知之適當的方式來形成。介電層1115可具有一單一樹脂層或可具有一由樹脂所形成之第一子層以及一由強化樹脂所形成之第二子層,其中強化樹脂例如是具有玻璃纖維或克維拉纖維(Kevlar fiber)的強化樹脂。
於其他實施例中,介電層1115可由膠片材料所形成,且導電片1110可配置鄰近於介電層1115。膠片材料可配置鄰近於導電片1105,且可預先形成以定義這些開口於導電塊1106以及導通孔741上的位置。膠片材料可被形成一層膠層、或二層或多層膠層。或者,介電層1115可包括一膠片子層與一樹脂子層的一複合層,以及導電片1110可配置鄰近介電層1115。膠片子層可配置鄰近導電片1105,且可預先形成以定義這些開口於導電塊1106以及這些導通孔741上的位置。樹脂子層可配置鄰近膠片子層,且亦可配置鄰近導電片1105由膠片子層所定義出的這些開口內。
接著,請參考圖11D,一圖案化導電層1140是由導電片1110所形成,且導通孔742形成鄰近圖案化導電層1140。圖11D之圖案化導電層1140的位置對應於圖7之圖案化導電層740。圖案化導電層1140與導通孔742的形成過程相似於前述圖6B至圖6D的製作步驟。光阻材料形成鄰近導電片1110,例如是透過乾膜層壓。於光阻內的開口被形成,例如是透過曝光與顯影,其對應圖案化導電層1140。電性連接材料應用於開口以形成對應圖案化導電層1140的一導電層。之後剝離光阻層。然後,再次形成一鄰近導電片1110的光阻材料。於光阻內之開口被形成,例如是透過曝光與顯影,其對應導通孔742。電性連接材料應用於開口以形成導通孔742。導通孔742可作緩衝器。之後剝離光阻層。然後,進行快速蝕刻以移除導電片1110殘餘的部分,以及形成圖案化導電層1140。
圖11E繪示一實施例之一種形成一對應圖10之雙層凹穴1006的導電塊1112。導電塊1112包括一第一導電部1112a以及一第二導電部1112b。第二導電部1112b的形成與如何形成導通孔742相似(請參考圖11D的描述)。於一實施例中,第一導電部1112a具有一寬度1111,此寬度1111大於第二導電部1112b的一寬度1117。第一導電部1112a的一側表面1113被介電層1115所覆蓋。第二導電部1112b的一側表面1116被一對應於圖2與圖7之介電層260的介電層所覆蓋。
接著,請參考圖11F,一介電層1160配置鄰近介電層1115且覆蓋圖案化導電層1140以及導通孔742。圖11F之介電層1160的部分對應於圖2與圖7之介電層260。一介電層1118(導電片1118)可配置鄰近介電層1160與導通孔742。介電層1160與導電片1118具有相似之特徵,且其形成方法分別與形成介電層1115與導電片1110的方法相似,請參考圖11C之描述,於此不再贅述。
接著,請參考圖11G,一圖案化導電層1150是由導電片1118所形成,且導通孔744形成鄰近圖案化導電層1150。圖11G之圖案化導電層1150的部分對應於圖7之圖案化導電層750。圖案化導電層1150與導通孔744具有相似的特徵,且其形成方法分別與形成圖案化導電層1142及導通孔742的方法相似,請參考圖11D之描述,於此不再贅述。
接著,請參考圖11H,一介電層1170配置鄰近介電層1160,且覆蓋圖案化導電層1150與導通孔744。圖11H之介電層1170的部分對應於圖2與圖7之介電層270。介電層1119(導電片1119)可配置鄰近介電層1170與導通孔744。介電層1170與導電片1119具有相似的特徵,且其形成方法分別與介電層1115與導電片1110的形成方法相似,請參考圖11C的描述,於此不再贅述。
接著,請參考圖11I,移除承載器1110,以暴露出導電片1105。
接著,請參考圖11J,一圖案化導電層1130是由導電片1105所形成,且導通孔224形成鄰近圖案化導電層1130。圖11J之圖案化導電層1130的部分對應圖2與圖7之圖案化導電層230。圖案化導電層1130與導通孔224具有相似的特徵,且其形成的方法分別與形成圖案化導電層1142及導通孔742的方法相似,請參考圖11D之描述,於此不再贅述。
接著,請參考圖11K,一光阻材料形成鄰近介電層1115,且位於光阻內的開口被形成,透過相似於前述圖6B之形成方法。位於光阻內的開口被形成,例如是透過曝光與顯影,以暴露出導電塊1106。
接著,請參考圖11L,移除導電塊1106以形成延伸穿過介電層1115的開口704與705。每一開口704與705暴露出介電層1160。開口704亦可視為具有凹穴底部716的凹穴706。開口705亦可視為具有凹穴底部717的凹穴707。於一實施例中,移除導電塊1106的方法為化學蝕刻法。化學蝕刻的好處在於可透過相同的製程步驟來同時移除導電塊1106。於其他實施例中,替代蝕刻導電塊1106的方法,凹穴706可透過雷射與/或機械鑽孔穿過介電層1115。這些鑽孔製程可多次消耗化學蝕刻,因為凹穴的形成每次都是利用這些方法。
接著,請參考圖11M,半導體元件202配置鄰近介電層1160(亦鄰近凹穴底部716)。黏著層213可配置於半導體元件202與凹穴底部716之間。被動電子元件203配置鄰近介電層1160(亦鄰近凹穴底部717)。黏著層207可配置於被動電子元件203與凹穴底部717之間。
接著,請參考圖11N,一介電層1114配置鄰近介電層1115,且覆蓋半導體元件202、被動電子元件203以及導通孔224。介電層1114可分離一導電片1120與半導體元件202、被動電子元件203以及導通孔224。圖6G之介電層1114的部分對應於圖2與圖7之介電層214。介電層1114與導電片1120具有相似的特徵,且其形成方法分別與形成介電層614及導電片616的方法相似,請參考圖6G之描述,於此不再贅述。
接著,請參考圖11O,形成包括這些開口221、222、223的這些開口。這些開口221延伸穿過導電片1120與介電層1114,以暴露出每一導通孔224的上表面233。這些開口222延伸穿過導電片1120與介電層1114,以暴露出半導體元件202的這些電性接點212。這些開口223延伸穿過導電片1120與介電層1114,以暴露出被動電子元件203的這些電性接點205。這些開口221、222、223可由雷射鑽孔或其他適當已知之習知技術所形成。
接著,請參考圖11P,這些開口221、222、223填入一導電材料以形成導通孔,例如是圖2與圖7中的這些內層電性連接層225、226、227。這些內層電性連接層225、226、227可利用任何一種塗佈技術,例如是無電電鍍與/或電解電鍍法所形成。於一實施例中,接著,進行一減成法,以形成一圖案化導電層1140。減成法相似於前述圖6J至圖6L的描述,於此不再贅述。於其他實施例中,一修改半加成法(modified semi-additive process,MSAP)過程以形成一包括圖2與圖7之圖案化導電層240的圖案化導電層。修改半加成法相似於圖6M至圖6O,於此不再贅述。圖11P之圖案化導電層1140的部分對應圖2與圖7之圖案化導電層240。
接著,請參考圖11Q,一介電層1150配置鄰近介電層1114,且介電層1170配置鄰近介電層1160。圖11Q所示之介電層1150及1170的部分分別對應於圖2與圖7之介電層250及270。介電層1150及1170的形成方法相似於前述圖6G所述之介電層614的形成方法。電性內連接延伸穿過介電層1150及1170,例如是內部電性連接253,其形成方法相似於前述圖11D所述之導通孔742的形成方法。電性接點254及274的形成方法相似於前述圖11P所述之圖案化導電層1140的形成方法。
接著,請參考圖11R,一介電層1151配置鄰近介電層1150,且一介電層1171配置鄰近介電層1170。圖11R之介電層1151及1171的部分分別對應於圖2及圖7之介電層251及271。介電層1151及1171的形成方法相似於前述圖6G之介電層614的形成方法。表面處理層255及274的形成方法相似於前述圖6C之導通孔224的形成方法。然後,沿著切割線1180及1181進行單體化製程,以形成多個個自獨立的內埋式半導體封裝件,例如是圖7之內埋式半導體封裝件700。
接著,請參考圖11S,一第二半導體元件1190及一被動電子元件1192可電性連接至電性接點254。
於圖11至11S的製作步驟中,這些介電層與這些導電元件可形成於半導體元件202的上方與下方。因此,半導體元件202每有一個表面是暴露於內埋式半導體封裝件700的一外側表面。於一實施例中,介電層214覆蓋半導體元件202。此可提供機械穩定度同時亦可保護半導體元件202以阻絕氧氣、溼氣或其他環境狀態。
圖12A至圖12E繪示為本發明之一實施例的一種內埋式半導體封裝件1280(請參考圖12E)的製作方法。為了方便說明起見,以下將配合圖6A至圖6R的製作步驟與不同之處於下述進行詳細的說明。然而,這些製作過程可同樣地被執行以形成其他內埋式半導體封裝件,其可具有不同於內埋式半導體封裝件1280的初始結構。這些製作過程亦可被執行以形成包括一連接內埋式半導體封裝件之陣列的裝置條。
請先參考圖12A,提供一裝置條1200,例如是一印刷電路板。裝置條1200包括位於基材1200內的導電元件1201以及位於基材條1200之表面上的導電元件1202。導通孔1224從導電元件1202垂直延伸。於一實施例中,導通孔1224具有與導通孔224相似的特徵及相似的形成方法,請參考圖6B至圖6D的描述。
請參考圖12B,一介電層1214配置鄰近基材條1200。介電層1214具有與介電層614相似的特徵,請參考圖6E之描述。介電層1214的配置方式亦相似於介電層614,請參考圖6G,除了介電層1214在配置於半導體元件1202(請參考圖12D)上之前是配置於基材條1200上。介電層1214具有一凹穴1225,而半導體元件1202配置於凹穴1225內(請參考圖12D)。於一實施例中,介電層1214透過研磨與/或鑽孔的方式來暴露出導通孔1224。
請參考圖12C,一光阻層1220,例如一光成像焊料光阻(photo-imageable solder resist),形成鄰近介電層1214。光阻層1220預定或選擇的部分可曝光與顯影而形成開口1222。開口1222暴露出導通孔1224。光阻層1220(以及開口1222)具有相似的特徵,且其形成方法相似於圖6B所描述之形成光阻層606(以及開口607)的方法。於一實施例中,電性接點,例如是焊球,可配置於開口1222內,且電性連接至導通孔1224。這些電性接點可提供電性導通至,舉例來說,一圖案化導電層與/或其他配置於光阻層1220上的封裝。
請參考圖12D至圖12E,半導體元件1202配置於位於介電層1214的凹穴1225內。接著,填充介電層1234於凹穴1225內。介電層1234可為一環氧樹脂、一封裝膠體、一液態封裝膠體或其他不同於膠片的適當材料。於一實施例中,半導體元件1202可覆晶接合至一或多個導電元件1202。或者,一相似於半導體元件202(請參考圖6E)的半導體元件配置鄰近基材條1200。於此實施例中,半導體元件202的電性接點212被暴露出來,請參考圖6H的描述。再者,於此實施例中,導電片616(請參考圖6G)的形成以及配合圖6H至6R的操作步驟可與圖12E的操作步驟聯想在一起。
於一實施例中,一凹穴可透過如圖6F所描述之機械鑽孔法的方式形成於基材條1200上。接著,半導體元件1202至少部分地配置於基材條1200的凹穴內。於一實施例中,一相似於黏著層213的黏著層可配置於凹穴內。
圖13A至圖13H繪示為本發明之一實施例的一種內埋式半導體封裝件1390(請參考圖13H)的製作方法。為了方便說明起見,以下將配合圖6A至圖6R以及圖11A至圖11S的製作步驟與不同之處於下述進行詳細的說明。然而,這些製作過程可同樣地被執行以形成其他內埋式半導體封裝件,其可具有不同於內埋式半導體封裝件1390的初始結構。這些製作過程亦可被執行以形成包括一連接內埋式半導體封裝件之陣列的裝置條。
請先參考圖13A,提供一導電層1105(先前描述於圖11A中)。於一實施例中,導電層1105(導電片1105)可包括一由銅或含銅的合金所形成之可剝離金屬銅箔。金屬銅箔可具有一介於約10微米(μm)至約30微米(μm)之間的一厚度,例如是從15微米(μm)至約25微米(μm)。導電片1105可配置鄰近於一承載器(未繪示),例如是繪示於圖11A的承載器1100。導電片1105可透過一離形層(未繪示)貼附於承載器1100。於一實施例中,離形層為一黏著層,其為有機或無機,例如是膠帶。
一圖案化導電層1300可配置鄰近導電片1105,且導通孔1302可從圖案化導電層1300垂直延伸。圖案化導電層1300可具有與前述圖11D所描述之圖案化導電層1140相似的特徵。導通孔1302可具有與前述圖11D所描述之圖案化導電層742相似的特徵。圖案化導電層1300與導通孔1302的形成方法具有與前述圖11D所描述之製作步驟相似的觀點。一光阻材料形成鄰近導電片1105,例如是透過乾膜層壓。於光阻內的開口被形成,例如是透過曝光與顯影,其對應圖案化導電層1300。一電性導電材料應用於開口內以形成一對應圖案化導電層1300的導電層。接著,剝離光阻層。然後,再次形成一鄰近導電片1105的光阻材料。於光阻內的開口被形成,例如是透過曝光與顯影,其對應導通孔1302。一電性導電材料應用於開口內,以形成導通孔1302。導通孔1302可作緩衝器。之後,剝離光阻層。
於一實施例中,於剝離光阻層,一介電子層1304配置鄰近導電片1105。介電子層1304具有與前述圖11C所述之介電層1115相似之特徵。於一實施例中,介電子層1304可由一樹脂材料所形成。導電片1105可配置鄰近介電子層1304以形成,舉例來說,一樹脂銅箔層。介電子層1304可具有一單一樹脂層或可具有一由樹脂所形成之第一子層以及一由強化樹脂所形成之第二子層,其中強化樹脂例如是具有玻璃纖維或克維拉纖維(Kevlar fiber)的強化樹脂。或者,介電層1304可由膠片材料所形成。膠片材料可預先形成以定義這些開口於這些導通孔1302上的位置。介電子層1304可包括一膠片子層與一樹脂子層的一複合層。於一實施例中,於形成鄰近導電片1105的介電子層1304之後,形成一鄰近介電子層1304的導電片1306。導電片1306具有與前述圖11C之導電片1110相似的特徵與相似的形成方法。導電片1306可為一金屬,例如是銅或一含銅的合金。導電片1306可透過無電電鍍法、濺鍍法或其他習知已知的方法來形成。
或者,導電片1306可在配置於鄰近導電片1105的介電子層1304上之前貼附於介電子層1304上。於一實施例中,已貼附有導電片1306的介電子層1304可配置鄰近導電片1105。此步驟可與配置導電片1306於鄰近的導通孔1302上同時進行。
接著,請參考圖13B,導通孔1308與導電塊1310形成鄰近導電片1306。導通孔1308延伸至導通孔1302(請參考圖13A)以形成導通孔1312。導通孔1312及導電塊1310具有於前述圖11B所述之導通孔741及導電塊1106相似的特徵與相似的形成方法。一光阻材料形成鄰近導電片1306。於光阻內的開口被形成,例如是透過曝光與顯影,其對應於導電塊1310與導通孔1312的位置。電性連接材料應用於開口內,以形成導電塊1310與導通孔1312。導電塊1310與導通孔1312可做緩衝器。之後,剝離光阻層以暴露出導電片1306。
接著,請參考圖13C,之後,透過快速蝕刻來移除導電片1306。一具有與前述圖11C所描述之介電層1115相似特徵的附加介電子層配置鄰近介電子層1304(請參考圖13A),以形成介電層1314。導電塊1310與導通孔1312可作緩衝器。接著,導電片1316可形成鄰近介電層1314。導電片1316具有與前述圖13A所述之導電片1306相似的特徵與相似的形成方法。或者,導電片1316可於配置附加介電子層鄰近於介電子層1304以形成介電層1314之前貼附於介電子層上。於一實施例中,已貼附有導電片1316的附加介電子層可配置鄰近介電層1304,以形成介電層1314。此步驟可與配置導電片1316於鄰近的導通孔1312上同時進行。
接著,請參考圖13D,一圖案化導電層1318配置鄰近導電片1316。圖案化導電層1318可具有與前述圖13A之圖案化導電層1300相似的特徵與相似的形成方法。
接著,請參考圖13E,導通孔1322形成鄰近圖案化導電層1318,且導電塊1320形成鄰近導電片1316。導電塊1320延伸穿過導電塊1310(請參考圖13C)以形成導電塊1321。導通孔1322與導電塊1321具有與前述圖13B之導通孔1312與導電塊1310相似的特徵與相似的形成方法。之後,透過快速蝕刻法來移除導電片1316。一具有與前述圖11C所述之介電層1115相似特徵的附加介電子層配置鄰近於介電層1314。導電塊1321與導通孔1312可作緩衝器。之後,形成一鄰近介電子層1324的導電片1326。導電片1326具有與前述圖13A之導電片1306相似的特徵與相似的形成方法。或者,導電片1326可於配置介電層1324鄰近介電層1314之前貼附於介電子層1324。於一實施例中,已貼附有導電片1326的介電子層1324可配置鄰近介電層1314。此步驟可與配置導電片1326於鄰近的導通孔1322上同時進行。
或者,請參考圖13F,導通孔1332形成鄰近導電片1326,且導電塊1330形成鄰近導電片1326。導通孔1332延伸至導通孔1322(請參考圖13E)以形成導通孔1333。導電塊1330延伸至導電塊1321(請參考圖13E)以形成導電塊1331。導通孔1333與導電塊1331具有與前述圖13B所述之導通孔1312與導電塊1310相似的特徵與相似的形成方法。接著,透過快速蝕刻來移除導電片1326。一具有與前述圖11C所述之介電層1115相似特徵的附加介電層配置鄰近介電子層1324(請參考圖13E),以形成介電層1334。導電塊1331與導通孔1333可作緩衝器。導電片1336可形成鄰近於介電層1334。導電片1336可具有與前述圖13A相似特徵及相同製作方法。或者,導電片1336可於配置附加介電子層鄰近於介電子層1324以形成介電層1334之前貼附於介電子層上。於一實施例中,已貼附於導電片1336的附加介電子層可配置鄰近於介電層1324,以形成介電層1334。此步驟可與配置導電片1336於鄰近的導通孔1332上同時進行。
接著,一圖案化導電層1338配置鄰近導電片1336。圖案化導電層1338可具有與前述圖13A之圖案化導電層1300相同的特徵與相似的形成方法。
接著,請參考圖13G,可透過快速蝕刻來移除導電片1336。之後,形成一鄰近介電層1334的光阻材料層,且透過與前述圖11K所描述之製作方法來形成位於光阻內的開口。光阻內的開口被形成,例如是透過曝光與顯影,以暴露出導電塊1331(請參考圖13F)。移除導電塊1331以形成延伸穿過介電層1334至介電層1314內的開口1340。開口1340一可視為具有凹穴底部1342的凹穴1340。於一實施例中,可透過化學蝕刻來移除導電塊1331。此化學蝕刻的好處在於可透過相同的製程步驟來同時移除導電塊1331。於其他實施例中,替代蝕刻導電塊1331的方法,凹穴1340可透過雷射與/或機械鑽孔穿過介電層1331。這些鑽孔製程可多次消耗化學蝕刻,因為凹穴的形成每次都是利用這些方法。
圖13H繪示內埋式半導體封裝件1390。晶片202配置於凹穴1340內。介電層1344形成鄰近介電層1334。介電層1344具有與前述圖11C之介電層1115相似的特徵。圖案化導電層1346可採用於前述圖11N至圖11P相似步驟的製作方法。於一實施例中,一相似於圖6J至圖6L之減成法被採用,故於此不再贅述。於其他實施例中,一相似於圖6M至圖6O所述之修改半加成法(modified semi-additive process,MSAP)被採用,故於此不再贅述。
或者,圖案化導電層1346亦可透過位於界但層1344內的開口1347來形成,接著,透過配置一介電材料層於開口1347內。開口1347可透過機械鑽孔或其他習知已知的適當方式來形成。導電層可透過濺鍍法、無電電鍍法或其他以之適當方式來配置於開口1347內。之後,圖案化此導電層以形成圖案化導電層1346。圖案化導電層1346可具有與前述圖13A之圖案化導電層1300相似的特徵與相同的形成方法。
接著,介電層1350與1352可分別配置鄰近圖案化導電層1346與1300。介電層1350與1352可為焊罩層。介電層1350及1352暴露出圖案化導電層1346及1300的部分,以形成電性接點1354及1356於內埋式半導體封裝件1390的外部周圍。電性接點1354及1356可分別具有表面處理層1358及1360,且其可包括一或多鎳子層與金子層。
圖13A至圖13H繪示形成一延伸穿過多個於內埋式半導體封裝件內之圖案化導電層的凹穴。特別是,凹穴1340從圖案化導電層1338延伸經過導電層1318。於一實施例中,凹穴底部1342可配置於圖案化導電層1318與圖案化導電層1300之間,且位於介電層1314內。凹穴1342可配置於圖案化導電層1300與圖案化導電層1318之間,透過配置導電塊1310與導通孔1308鄰近導電片1306,而無形成一鄰近導電片1306之分離的圖案化導電層。或者,凹穴底部1342可配置於圖案化導電層的一深度中,舉例來說,透過形成一鄰近導電片1306之分離的圖案化導電層。於一實施例中,凹穴1340可延伸經過圖案化導電層1318,透過形成圖13D與圖13E之導電塊1321。凹穴1340可形成具有一深度,此深度對應配置於以導電片1306(請參考圖13B)及導電片1336(請參考圖13F)的位置為基準之凹穴1340內晶片202。於繪示的實施例中,凹穴1340的深度大於介電層1334的厚度。
圖14A至圖14C繪示為本發明之一實施例的一種內埋式半導體封裝件1490(請參考圖14C)的製作方法。為了方便說明起見,以下將配合圖11A至圖11S以及圖13A至圖11H的製作步驟與不同之處於下述進行詳細的說明。然而,這些製作過程可同樣地被執行以形成其他內埋式半導體封裝件,其可具有不同於內埋式半導體封裝件1490的初始結構。這些製作過程亦可被執行以形成包括一連接內埋式半導體封裝件之陣列的裝置條。
請先參考圖14A,提供一導電層1105(先前描述於圖11A中)。於一實施例中,導電塊1105(導電片1105)可包括一由銅或含銅的合金所形成之可掀離金屬銅箔。導電片1105可配置鄰近一承載器(未繪示),例如是圖11A所繪示之承載器1100。導電片1105可透過一離形層(未繪示)貼附於承載器1100上。
導通孔1406與導電塊1404形成鄰近導電片1105。導通孔1406與導電塊1404具有與前述圖11B之導通孔741與導電塊1106相似的特徵與相似的形成方法。形成一鄰近導電片1105的光阻材料。形成於光阻內的開口,例如是透過曝光與顯影,其對應導電塊1404與導通孔1406的位置。一電性導電材料應用於開口內以形成導電塊1404與導通孔1406。導電塊1404與導通孔1406可作緩衝器。之後,剝離光阻層以暴露出導電片1105。
接著,一具有與圖11C之介電層1115相似特徵的介電層1402配置鄰近導電片1105。之後,導電塊1404與導通孔1406可作緩衝器。導電片1400可形成鄰近介電層1402。導電片1400具有與導電片1105相似的特徵及相似的形成方法。
接著,一圖案化導電層1410可配置鄰近導電片1400。圖案化導電層1410可具有與前述圖11D之圖案化導電層1140相似的特徵。圖案化導電層1410的形成過程相似於前述圖13A所述之圖案化導電層1300的形成方式。
於一實施例中,接著,導電片1105可分離承載器且翻轉以使圖案化導電層1410可配置於承載器上。之後,一圖案化導電層1408配置鄰近導電片1105。圖案化導電層可具有與圖案化導電層1410相似的特徵與相似的形成方法。
或者,進行附加步驟於導電片1105分離承載器之前。舉例來說,介電層1417、導通孔1422以及圖案化導電層1414(請參考圖14B)可形成鄰近與/或圖案化導電層1410的上方,相似於圖11D、圖11F及圖11G的製作步驟。
如圖14B所示,於導電片1105分離於承載器且翻轉後,相似於圖13E、圖13F以及圖13G之步驟可被執行,以得到結構1430。結構1430可包括一凹穴1420,其延伸穿過介電層1416與1402,且暴露出介電層1417。凹穴1420可從圖案化導電層1412延伸經過圖案化導電層1408至圖案化導電層1410。
請參考圖14C,額外增加的製程,類似圖11M至11R,可得到內埋式半導體封裝件1490。此導致半導體元件202配置於內埋式半導體封裝件1490的內部,因此半導體元件202位於兩內部圖案化導電層之間:圖案化導電層1412及圖案化導電層1410。於一實施例中,至少一介電層1417分離圖案化導電層1410與一鄰近內埋式半導體封裝件1490之一外部周圍的圖案化導電層1414。於一實施例中,至少一介電層1430、一圖案化導電層1431以及一介電層1432分離圖案化導電層1412與一鄰近內埋式半導體封裝件1490之一外部周圍1441的圖案化導電層1433。半導體裝置透過內層電性連接層1435電性連接至圖案化導電層1431。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。此外,許多修改可使一事件、方法或過程的特殊情況、材料或合成物來適應本發明之宗旨、精神和範圍。這一類的修改亦被預期為可能在附加之申請專利範圍中之一些項中陳述。特別是,於此中被揭露的方法描述了關於按特殊順序進行的特殊操作,這些操作也許可被結合、被細分或者被重新調整而形成一個等效方法,此仍不脫離本發明所教示的範圍內。因此,除非此文中明確地說明,否則順序和編組操作非用以限定本發明。
100、200、300、400、500、700、800、900、1000、1280、1390、1490...內埋式半導體封裝件
202、302、402、502、1002...半導體元件
203、692、1003、1192...被動電子元件
204、216、232、234、236、238、1104、1107...下表面
205、212...接點
207、213...黏著層
206、218、231、233、235、237、1102...上表面
205a、205b、212a、212b、1354、1356...電性接點
208、210、736、1108、1113、1116...側表面
214、614、650、651、670、671、701、715、1060、1110、1114、1115、1118、1119、1150、1151、1160、1170、1171、1214、1234、1314、1334、1344、1350、1352、1402、1416、1417、1432...介電層
224、741、742、744...導通孔
254、274...接墊
220、221、222、223、252、262...開口
225、226、227、253、263...內層電性連接層
230、240、602、604、640、740、750、830、1130、1140、1300、1318、1338、1346、1408、1410、1412、1414、1431、1433...圖案化導電層
250...上方介電層
251...附加介電塗佈層
255、275、1358、1360...表面處理層
260...下方介電層
264...基材
270、271...附加介電層
280...第一距離
281...第二距離
304...導電凸塊
404...焊線
504、706、707、1225、1420...凹穴
506、508、720、721、1010、1021...高度
509、635、641、722...厚度
600...基材條
606、620、630、1220...光阻層
614a...第一開口
616、1120、1306、1316、1326、1336、1400...導電片
607、622、624、632、704、705、1222、1340、1347...開口
618、634、1105...導電層
680、681...虛線
690、1190...第二半導體元件
716、717、1342...凹穴底部
738...距離
840...部分
1006a...上部分
1006b...下部分
1007...雙層凹穴
1008、1012、1111、1117...寬度
1106、1112、1310、1312、1320、1321、1330、1331、1404...導電塊
1112a...第一導電部
1112b...第二導電部
1180、1181...切割線
1200...裝置條
1201、1202...導電元件
1224、1302、1308、1322、1332、1333、1406、1422...導通孔
1304、1324...介電子層
1430...結構
1435...電性連接層
1441...外部周圍
圖1為本發明之一實施例之一種內埋式半導體封裝件的透視圖。
圖2為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖3為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖4為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖5為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖6A至圖6R繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。
圖7為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖8為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖9為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖10為本發明之一實施例之一種內埋式半導體封裝件的剖面示意圖。
圖11A至圖11S繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。
圖12A至圖12E繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。
圖13A至圖13H繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。
圖14A至圖14C繪示為本發明之一實施例的一種內埋式半導體封裝件的製作方法。
為更好地理解本發明之一些實施例的性質及目的,應參考結合附隨圖式作出之以下詳細描述。在圖式中,除非上下文另外清楚地規定,否則相同參考標號表示相同元件。
200...內埋式半導體封裝件
202...半導體元件
203...被動電子元件
204、216...下表面
205a、205b、212a、212b...電性接點
206、218...上表面
207、213...黏著層
208、210...側表面
214...介電層
220、221、222、223、252、262...開口
225、226、227、253、263...內層電性連接層
230、240...圖案化導電層
224...導通孔
231、233、235、237...上表面
290...玻纖
232、234、236、238...下表面
250...上方介電層
251...附加介電塗佈層
254、274...接墊
255、275...表面處理層
260...下方介電層
264...基材
270、271...附加介電層
280...第一距離
281...第二距離
Claims (16)
- 一種內埋式半導體封裝件,包括:一半導體元件,具有一電性接點;一上方圖案化導電層;一介電層,介於該上方圖案化導電層與該半導體元件之間,該介電層具有一第一開口且暴露該電性接點;一第一內層電性連接層,從該電性接點延伸至該上方圖案化導電層,其中該第一內層電性連接層填充於該第一開口;一下方圖案化導電層,該介電層具有一從該下方圖案化導電層延伸至該上方圖案化導電層的第二開口,該第二開口具有一上部分及一下部分,其中該上部分暴露出該上方圖案化導電層,該下部分暴露出該下方圖案化導電層;一導通孔,位於該第二開口的該下部分;以及一第二內層電性連接層,填充於該第二開口的該上部分,其中該第二內層電性連接層包括一具有一第一面積之頂表面,且包括一具有一第二面積之底表面,該第一面積不同於該第二面積,及其中該導通孔具有實質上平行於該第二面積的一第三面積之上表面,且該第三面積大於該第二面積。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中該上方圖案化導電層透過一導電路徑電性連接至該下方圖案化導電層,而該導電路徑包括該導通孔以及該第二內層電性連接層。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中該導通孔為一電鍍導電柱。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中從該導通孔的一上表面至該上方圖案化導電層的一第一距離小於 從該半導體元件的一上表面至該上方圖案化導電層的一第二距離。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中該半導體元件係一主動元件及一被動元件之至少一者。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中該介電層包括至少一膠層、一樹脂層以及一環氧層。
- 如申請專利範圍第6項所述之內埋式半導體封裝件,其中該介電層包括一玻纖,且該玻纖的部分定向遠離該下方圖案化導電層。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中該半導體元件具有一背表面,且該背表面配置鄰近該下方圖案化導電層。
- 如申請專利範圍第1項所述之內埋式半導體封裝件,其中該導通孔的一上表面實質上與該半導體元件的一主動表面共平面。
- 一種內埋式半導體封裝件的製作方法,包括:提供一第一圖案化導電層以及一半導體元件;形成一從該第一圖案化導電層垂直延伸的導通孔,該導通孔具有一上表面;配置該半導體元件,以使該半導體元件電性連接至該第一圖案化導電層;配置一介電層、一覆蓋該半導體元件的導電片以及一導通孔,其中該導電片鄰近該介電層的該上表面,該介電層分離該導電片與該半導體元件以及分離該導電片與該導通孔;形成一第一開口,該第一開口延伸穿過該導電片與該介電層,以暴露該導通孔的該上表面; 形成一第一內層電性連接層,連接該導通孔至該導電片,其中該第一內層電性連接層填充該第一開口;從該導電片形成一第二圖案化導電層;形成一第二開口,該第二開口延伸穿過該導電片與該介電層,以暴露該半導體元件的一電性接點;以及形成一第二內層電性連接層,連接該半導體元件的該電性接點至該導電片,其中該第二內層電性連接層填充該第二開口,其中該第二內層電性連接層包括一具有一第一面積之頂表面,且包括一具有一第二面積之底表面,該第一面積不同於該第二面積,及其中該導通孔具有實質上平行於該第二面積的一第三面積之上表面,且該第三面積大於該第二面積。
- 如申請專利範圍第10項所述之內埋式半導體封裝件的製作方法,其中形成該第一內層電性連接層與形成該第二圖案化導電層,更包括:配置一導電材料的一第一部分,以填充該第一開口;藉由配置鄰近該導電片之該導電材料的一第二部分來形成一導電層;形成一圖案化乾膜,該圖案化乾膜鄰近該導電層,該圖案化乾膜暴露部分該導電層;藉由移除被該圖案化乾膜所暴露的部分該導電層,以形成該第二圖案化導電層;以及於形成該第二圖案化導電層之後,移除該圖案化乾膜。
- 如申請專利範圍第10項所述之內埋式半導體封裝件的製作方法,其中形成該第一內層電性連接層與形成該第二圖案化導電層,更包括:配置一導電材料的一第一部分,以填充該第一開口; 形成一鄰近該導電片的圖案化乾膜,該圖案化乾膜暴露部分該導電片;藉由配置鄰近被該圖案化乾膜所暴露的部分該導電片之該導電材料的一第二部分來形成一導電層;移除該圖案化乾膜;以及於移除該圖案化乾膜之後,藉由移除部分該導電層以形成該第二圖案化導電層。
- 如申請專利範圍第10項所述之內埋式半導體封裝件的製作方法,更包括:提供一基材條;形成鄰近該基材條的該第一圖案化導電層;形成一凹穴於該基材條內;以及配置該半導體元件的至少一部分於該凹穴內。
- 一種內埋式半導體封裝件的製作方法,包括:提供一半導體元件以及一第一導電片,其中該第一導電片具有一下表面;形成一鄰近該第一導電片之該下表面的導電塊;配置一鄰近該第一導電片之該下表面且覆蓋該導電塊之一側表面的介電層;配置一鄰近該介電層與該導電塊的下方介電層,該下方介電層覆蓋該導電塊的一下表面;從該第一導電片形成一第一圖案化導電層,該第一圖案化導電層具有一鄰近該下方介電層的下表面以及一上表面;形成一從該第一圖案化導電層之該上表面垂直延伸的導通孔;於形成該導通孔之後,移除該導電塊以形成一延伸穿過該介 電層且暴露出部分該下方介電層的第一開口;配置該半導體元件的至少一部分於該第一開口內且鄰近部分該下方介電層;配置一上方介電層以及一覆蓋該半導體元件與該導通孔的第二導電片,其中該第二導電片鄰近該上方介電層的一上表面,該上方介電層分離該第二導電片與該半導體元件以及分離該第二導電片與該導通孔;形成一延伸穿過該第二導電片與該上方介電層的第二開口,以暴露出該導通孔的該上表面;形成一第一內層電性連接層,連接該導通孔至該第二導電片,其中該第一內層電性連接層填充該第二開口;從該第二導電片形成一第二圖案化導電層;形成一延伸穿過該第二導電片與該上方介電層的第三開口,以暴露出該半導體元件的一電性接點;以及形成一第二內層電性連接層,連接該半導體元件的該電性接點至該第二導電片,其中該第二內層電性連接層填充該第三開口,其中該第二內層電性連接層包括一具有一第一面積之頂表面,且包括一具有一第二面積之底表面,該第一面積不同於該第二面積,及其中該導通孔具有實質上平行於該第二面積的一第三面積之上表面,且該第三面積大於該第二面積。
- 如申請專利範圍第14項所述之內埋式半導體封裝件的製作方法,其中形成該第一內層電性連接層與形成該第二圖案化導電層,更包括:配置一導電材料的一第一部分,以填充該第二開口;藉由配置鄰近該第二導電片之該導電材料的一第二部分來形成一導電層;形成一圖案化乾膜,該圖案化乾膜鄰近該導電層,該圖案化乾膜暴露部分該導電層; 藉由移除被該圖案化乾膜所暴露的部分該導電層,以形成該第二圖案化導電層;以及於形成該第二圖案化導電層之後,移除該圖案化乾膜。
- 如申請專利範圍第14項所述之內埋式半導體封裝件的製作方法,其中:該導電塊,包括:一第一導電部,具有一第一寬度;以及一第二導電部,配置鄰近該第一導電部,該第二導電部具有一小於該第一寬度的第二寬度;以及該介電層,包括:一第一介電層,覆蓋該第一導電部的一側表面;以及一第二介電層,覆蓋該第二導電部的一側表面。
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CN104332417B (zh) | 2017-08-15 |
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US9406658B2 (en) | 2016-08-02 |
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