CN102214626B - 内埋式半导体封装件及其制作方法 - Google Patents
内埋式半导体封装件及其制作方法 Download PDFInfo
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Abstract
本发明公开一种内埋式半导体封装件及其制作方法,该半导体封装件包括具有电性接点的半导体元件、上方图案化导电层、介于上方图案化导电层与半导体元件之间的介电层、第一内层电性连接层、下方图案化导电层、导通孔以及第二内层电性连接层。介电层具有暴露出电性接点的第一开口以及从下方图案化导电层延伸至上方图案化导电层的第二开口。第一内层电性连接层从电性接点延伸至上方图案化导电层且填充于第一开口中。第二开口具有暴露出上方图案化导电层的上部分以及暴露出下方图案化导电层的下部分。导通孔位于第二开口的下部分。第二内层电性连接层填充于第二开口的上部分。
Description
技术领域
本发明涉及一种具有电性电路的基板及其制作方法,且特别是涉及一种内埋式半导体封装件及其制作方法。
背景技术
半导体元件变得日益复杂、透过对更小尺寸的需求以驱动至少一部分以及提升处理速度。同时,还包括对许多小型化电子产品的需求,其中电子产品包括这些半导体元件。半导体元件为典型的封装体,之后也许可被安装于包括电子电路的基板中,此基板例如电路板。此导致半导体元件封装以及基板占据了封装空间,且半导体元件封装占据基板的表面区域。此外,透过进行封装工艺、制作电路板以及组装这些分开的过程亦会增加额外的成本。如何减少基板上的半导体元件所占据的封装空间以及简化与结合封装工艺、制作电路板以及应用于半导体元件以及基板的组装过程已成为非常重要的课题。
以此背景技术而言,需要提升技术以发展元件内埋式基板及其所述的相关的方法。
发明内容
本发明提供一种内埋式半导体封装件。在实施例中,内埋式半导体封装件包括具有电性接点的半导体元件、上方图案化导电层、介于上方图化导电层与半导体元件之间的介电层、第一内层电性连接层、下方图案化导电层、导通孔以及第二内层电性连接层。介电层具有暴露电性接点的第一开口以及从下方图案化导电层延伸至上方图案化导电层的第二开口。第一内层电性连接层从电性接点延伸至上方图案化导电层,且填充第一开口。第二开口具有上部分与下部分,其中上部分暴露出上方图案化导电层的,而下部分暴露出下方图案化导电层。导通孔填充第二开口的下部分。第二内层电性连接层填充第二开口的上部分。
本发明的另一方面是有关于内埋式半导体封装件的制作方法。于实施例中,内埋式半导体封装件的制作方法包括:(1)提供第一图案化导电层以及半导体元件;(2)形成从第一图案化导电层垂直延伸的导通孔,导通孔具有上表面;(3)配置介电层与覆盖半导体元件与导通孔的导电片,其中导电片邻近介电层的上表面,且介电层分离导电片与半导体元件以及导电片与导通孔;(4)形成第一开口,第一开口延伸穿过导电片与介电层,以暴露导通孔的上表面;(5)形成第一内层电性连接层,连接导通孔至导电片,其中第一内层电性连接层填充第一开口;以及(6)从导电片形成第二图案化导电层。
本发明的另一方面是有关于内埋式半导体封装件的制作方法。于实施例中,内埋式半导体封装件的制作方法包括:(1)提供半导体元件以及具有下表面的第一导电片;(2)形成邻近第一导电片的下表面的导电块;(3)配置邻近第一导电片的下表面且覆盖导电块的侧表面的介电层;(4)配置邻近介电层与导电块的下方介电层,下方介电层覆盖导电块的下表面;(5)从第一导电片形成第一图案化导电层,第一图案化导电层具有邻近下方介电层的下表面以及上表面;(6)形成从第一图案化导电层的上表面垂直延伸的导通孔;(7)于形成导通孔之后,移除导电块以形成延伸穿过介电层且暴露出部分下方介电层的第一开口;以及(8)配置半导体元件的至少一部分于第一开口内且邻近部分下方介电层。
发明的其他方面和实施例亦可被预期。前面总结和以下详细描述并非用以限定本发明,而是仅仅描述本发明的一些实施例。
附图说明
图1为本发明的的实施例的一种内埋式半导体封装件的透视图。
图2为本发明的实施例的一种内埋式半导体封装件的剖面示意图。
图3为本发明的实施例的一种内埋式半导体封装件的剖面示意图。
图4为本发明的实施例的一种内埋式半导体封装件的剖面示意图。
图5为本发明的实施例的一种内埋式半导体封装件的剖面示意图。
图6A至图6R绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。
图7为本发明的实施例一种内埋式半导体封装件的剖面示意图。
图8为本发明的实施例一种内埋式半导体封装件的剖面示意图。
图9为本发明的实施例一种内埋式半导体封装件的剖面示意图。
图10为本发明的实施例一种内埋式半导体封装件的剖面示意图。
图11A至图11S绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。
图12A至图12E绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。
图13A至图13H绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。
图14A至图14C绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。
为更好地理解本发明的一些实施例的性质及目的,应参考结合附图作出的以下详细描述。在附图中,除非上下文另外清楚地规定,否则相同参考标号表示相同元件。
附图标记说明
100、200、300、400、500、700、800、900、1000、1280、1390、1490:内埋式半导体封装件
202、302、402、502、1002:半导体元件
203、692、1003、1192:无源电子元件
204、216、232、234、236、238、1104、1107:下表面
205、212:接点 207、213:粘着层
206、218、231、233、235、237、1102:上表面
205a、205b、212a、212b、1354、1356:电性接点
208、210、736、1108、1113、1116:侧表面
214、614、650、651、670、671、701、715、1060、1110、1114、1115、1118、1119、1150、1151、1160、1170、1171、1214、1234、1314、1334、1344、1350、1352、1402、1416、1417、1432:介电层
224、741、742、744:导通孔 254、274:接垫
220、221、222、223、252、262:开口
225、226、227、253、263:内层电性连接层
230、240、602、604、640、740、750、830、1130、1140、1300、1318、1338、1346、1408、1410、1412、1414、1431、1433:图案化导电层
250:上方介电层 251:附加介电涂布层
255、275、1358、1360:表面处理层
260:下方介电层 264:基底
270、271:附加介电层 280:第一距离
281:第二距离 304:导电凸块
404:焊线
504、706、707、1225、1420:凹穴
506、508、720、721、1010、1021:高度
509、635、641、722:厚度 600:基底条
606、620、630、1220:光致抗蚀剂层 614a:第一开口
616、1120、1306、1316、1326、1336、1400:导电片
607、622、624、632、704、705、1222、1340、1347:开口
618、634、1105:导电层 680、681:虚线
690、1190:第二半导体元件
716、717、1342:凹穴底部
738:距离 840:部分
1006a:上部分 1006b:下部分
1007:双层凹穴 1008、1012、1111、1117:宽度
1106、1112、1310、1312、1320、1321、1330、1331、1404:导电块
1112a:第一导电部 1112b:第二导电部
1180、1181:切割线 1200:装置条
1201、1202:导电元件
1224、1302、1308、1322、1332、1333、1406、1422:导通孔
1304、1324:介电子层 1430:结构
1435:电性连接层 1441:外部周围
具体实施方式
请参考图1,其绘示为本发明的实施例的一种内埋式半导体封装件100的透视图。内埋式半导体封装件100亦可指内埋式封装体、基板与/或模块,且可包括有源元件、无源元件或有源元件与无源元件两者。在此实施例中,内埋式半导体封装件100的多个侧边实质上为平的且具有实质上垂直的方位,以定义出实质上延伸环绕内埋式半导体封装件100的整个周围的侧向外形。此垂直的侧向外形可透过降低或缩小内埋式半导体封装件100的区域来减少整体的尺寸。此区域的减少也许是有利的,因为当堆叠至其他装置时,此区域可对应内埋式半导体封装件100的脚位区域。然而,内埋式半导体封装件的侧向外形,一般来说,可为任何一种形态,例如弯曲、倾斜、阶梯状或具有粗糙的结构。内埋式半导体封装件100的内部结构说明于图2至图5的实施例中。
图2为本发明的实施例的一种内埋式半导体封装件200的剖面示意图。此剖面图是沿着图1的线A-A所绘示,其中内埋式半导体封装件200为内埋式半导体封装件100的实施例。请参考图2,内埋式半导体封装件200包括半导体元件,例如半导体元件202,其具有下表面204、上表面206以及多个配置邻近半导体元件202的周围且延伸于下表面204与上表面206之间的侧表面208、210。在此实施例中,下表面204、上表面206、这些侧表面208、210实质上皆为平的,且这些侧表面208、210具有实质上垂直于下表面204或上表面206的方位,但于其他实施例中,下表面204、上表面206、这些侧表面208、210的型态与方位亦可以有其他变化。于图2中,下表面204为半导体元件202的背表面,且上表面206为半导体元件202的有源面。于实施例中,多个电性接点212a、212b配置邻近上表面206。这些接点212提供半导体元件202与内埋式半导体封装件200中的导电结构,例如图案化导电层240(说明如下),之间的输入与输出电性连接。于实施例中,下表面204与图案化导电层230(说明如下)之间亦可随意地添加粘着层213。粘着层213可包括环氧树脂(epoxy)、树脂或其他适当材料,以及其亦可为浆糊。在本实施例中,虽然半导体元件202具体化为半导体芯片,但一般来说,半导体元件202亦可为任有源元件、任无源元件或上述的任意组合。半导体元件202亦可例如是晶片级封装。
图2亦说明无源电子元件203,其具有多个电性接点205a、205b。内埋式半导体封装件200内亦可随意地包括含无源电子元件203。这些接点205提供无源电子元件203与例如图案化导电层230、240之间的电性连接。于实施例中,无源电子元件203与图案化导电层230之间亦可随意地填加粘着层207。粘着层207亦可包括环氧树脂、树脂或其他适当材料,以及其亦可为浆糊。于其他实施例中,亦可包括其他半导体元件、有源元件与或无源元件。
如图2所绘示,半导体元件装置200亦包括介电层214,此介电层214配置邻近半导体元件202与无源电子元件203。介电层214具有下表面216与上表面218。于此实施例中,介电层214实质上覆盖或包覆半导体元件202、无源电子元件203、粘着层213、粘着层207与图案化导电层230,以提供机械稳定度同时保护以阻绝氧气、湿气或其他环境状态。于此实施例中,介电层214实质上覆盖半导体元件202的上表面206与这些侧表面208、210。图案化导电层240配置邻近上表面218,而图案化导电层230配置邻近下表面216。虽然于图2的部分内埋式半导体封装件200中仅绘示包括介电层214来包覆半导体元件,但于其他实施例中,并不限定内埋式半导体封装件内包括多少介电层来包覆半导体元件。
于实施例中,上方介电层250可配置邻近图案化导电层240与介电层214的上表面218,而附加介电涂布层251可配置邻近上方介电层250。或者或另外,下方介电层260亦可配置邻近图案化导电层230与介电层214的下表面216。于实施例中,附加介电层270亦可配置邻近下方介电层260。于其他实施例中,介电层214的上方与/或下方亦可包含多个介电层。
于实施例中,介电层214、上方介电层250、下方介电层260以及附加介电层270可由介电层材料例如聚合物(polymeric)或非聚合物(non-polymeric)所形成。举例来说,至少一介电层214、上方介电层250、下方介电层260以及附加介电层270可由至少一液晶聚合物(liquid crystalpolymer,LCP)、双顺丁烯二酸酰亚胺树脂(bismaleimide-triazine,BT)、胶片(prepreg,PP)、含有玻璃颗粒的环氧树脂(Ajinomoto Build-up Film,ABF)、环氧树脂(epoxy)或聚酰亚胺(polyimide)所形成,但并不以此为限。介电层214、上方介电层250、下方介电层260以及附加介电层270可由相同介电材料或不同介电材料所形成。于其他实施例中,至少一介电层214、上方介电层250、下方介电层260以及附加介电层270可由光成像(photoimageable)或感光(photoactive)的介电材料所形成。另外,介电层214亦可为具有纤维强化的树脂材料,例如玻璃纤维或克维拉纤维(Kevlarfiber),来强化介电层214的强度。通过纤维来强化树脂材料的例子亦可应用于介电层214,包括含有玻璃颗粒的环氧树脂(ABF)、双顺丁烯二酸酰亚胺树脂(BT)、聚酰亚胺(polyimide)、液晶聚合物(LCP)、环氧树脂(epoxy)或其他树脂材料中。如下述图6E所示,玻纤290最初在层压而形成介电层214之前的定向是沿着介电层614的一般水平平面。请参考图2,玻纤290于后续介电层214的层压后被重新定向,随着部分邻近导通孔224、半导体元件202以及沿着导通孔224的垂直延伸方向伸出的无源电子元件203、半导体元件202以及无源元件203,且远离图案化导电层230。
请参考图2,所形成的介电层214定义出多个开口220、221、222、223。这些开口220暴露出图案化导电层230。每一开口220亦可实质上对齐暴露出图案化导电层240的对应开口221。这些开口222可暴露出半导体元件202的这些电性接点212。这些开口223可暴露出无源电子元件203的这些电性接点205。导通孔224可实质上填入于每一开口220内,且内层电性连接层225可实质上填入于每一开口221中。或者,导通孔224可位于每一开口220内。举例来说,导通孔224可为电镀导电柱。虽然于图2中仅示意地绘示两个导通孔224,但于其他实施例中,内埋式半导体封装件220亦可包括少于两个或多于两个导通孔224。导通孔224具有上表面233与下表面234。于实施例中,上表面233可实质上与半导体元件202的有源表面206共平面。或者,若有源表面206替代图案化导电层240面向图案化导电层230,则上表面233可实质上与半导体元件202的背表面204共平面。导通孔224可从图案化导电层230延伸至内层电性连接层225,且内层电性连接层225可从导通孔224延伸至图案化导电层240。此电性连接(形成电流于其间的导电路径)部分图案化导电层230与部分图案化导电层240。内层电性连接层226可实质上填入于每一开口222,且内层电性连接层227可实质上填入于每一开口223。内层电性连接层226可从电性接点212延伸至图案化导电层240,以电性连接半导体元件202至部分图案化导电层230。内层电性连接层227可从电性接点205延伸至图案化导电层240,以电性连接无源电子元件203至部分图案化导电层240。
于实施例中,每一内层电性连接层225、226、227分别具有高度,其高度范围介于30微米(μm)至150微米(μm)之间,例如从约30微米(μm)至约50微米(μm)、从约30微米(μm)至100微米(μm)、从约50微米(μm)至100微米(μm)以及从约100微米(μm)至150微米(μm)。每一内层电性连接层225、226、227的直径亦可介于150微米(μm)至250微米(μm)之间,例如约200微米(μm)。于实施例中,每一导通孔224可具有高度,其高度范围介于100微米(μm)至500微米(μm)之间,例如从约100微米(μm)至约300微米(μm)、从约100微米(μm)至200微米(μm),以及从约140微米(μm)至160微米(μm)。
于实施例中,每一内层电性连接层225具有上表面231以及下表面232,其中上表面231具有第一区域,而下表面232具有第二区域。同理,每一内层电性连接层226可具有上表面235以及下表面236,其中上表面235具有第一区域,而下表面236具有第二区域。每一内层电性连接层227可具有上表面237以及下表面238,其中上表面237具有第一区域,而下表面238具有第二区域。于实施例中,第一区域大于第二区域。此外,每一导通孔224的上表面233具有第三区域。这些导通孔224的直径可从约150微米(μm)至约300微米(μm)。因此,在实施例中,第三区域大于下表面232的第二区域。或者,第三区域亦可小于或等于下表面232的第二区域。于实施例中,这些上表面231、233、235、237以及这些下表面232、234、236、238可具有形状包括实质上圆形、实质上椭圆形、实质上方形与实质上矩形,但并不以此为限。
于实施例中,从导通孔224的上表面233至图案化导电层240之间的第一距离280小于从半导体元件202的上表面206至图案化导电层240的第二距离281。或者,第一距离280亦可大于或等于第二距离281。
通过提供电性连接至图案化导电层240、这些内层电性连接层225、226、227以允许导通孔224、半导体元件202以及无源电子元件203内埋于介电层214的上表面218。此设计可内埋半导体元件202以及无源电子元件203于介电层214中以降低内埋式半导体封装件200的厚度。此外,通过实质上填充的这些开口220、221、222、223,这些导通孔224以及这些内层电性连接层225、226、227亦可增加电性连接特征。再者,这些内层电性连接层225、226、227无需透过孔,例如电镀通孔,即可提供电性连接。此设计可显著地降低内埋式半导体封装件200的成本。
于实施例中,上方介电层250可定义出多个暴露图案化导电层240的开口252。内层电性连接层253可实质上填充每一开口252。内层电性连接层253可具有与导通孔224相似的特征,或者,可具有与内层电性连接层225相似的特征。附加介电层251可配置邻近上方介电层250。内层电性连接层253可从图案化导电层240延伸至被附加介电层251的开口所暴露出的多个接垫254上。这些接垫254亦可使内埋式半导体封装件200电性连接至外界。表面处理层255亦可邻近每一接垫254。
于实施例中,电性连接至这些接垫254的半导体元件(请参考图6R的半导体元件690)亦可透过包括内层电性连接层253与内层电性连接层226的导电路径而电性连接至半导体元件202。导电路径亦可包括部分图案化导电层240。
于实施例中,下方介电层260可定义出多个暴露出图案化导电层230的开口262。内层电性连接层263可实质上填充每一开口262。内层电性连接层263可具有与导通孔224相似的特征,或者,可具有与内层电性连接层225相似的特征。附加介电层271可配置邻近下方介电层260。或者,附加介电层270亦可配置于下方介电层260与附加介电层271之间。附加介电层271的开口亦可暴露出多个接垫274。这些接垫274亦可使内埋式半导体封装件200电性连接至外界。表面处理层275亦可邻近每一接垫274。
于实施例中,半导体元件202可透过包括内层电性连接层263的导电路径而电性连接至这些接垫274。导电路径亦可包括一或多个导通孔224、内层电性连接层225以及内层电性连接层226。导电路径亦可包括部分图案化导电层230。
于实施例中,图2的每一图案化导电层、内层电性连接层以及导通孔可由金属、金属合金、具有金属或金属合金扩散于其内的金属基质或其他适当导电材料所形成。举例来说,图2中的每一图案化导电层、内层电性连接层以及导通孔可由铝、铜、钛或上述材料的任意组合所形成。图2中的这些图案化导电层、这些内层电性连接层以及这些导通孔亦可由相同电性导电材料或不同电性导电材料所形成。
于实施例中,这些表面处理层255、275的形成相似于上述图2所述的这些图案化导电层、这些内层电性连接层以及这些导通孔。或者,这些表面处理层225、275的形成方式亦可不同于上述。举例来说,这些表面处理层255、275可由至少一锡、镍与金或包含锡或镍与金的合金所形成。这些表面处理层255、275可由相同电性导电材料或不同电性导电材料所形成。
于实施例中,这些附加介电层251、271的形成相似于上述所述的这些介电层214、250、260、270。这些附加介电层251、271可利用焊罩层,例如干膜成像焊罩层(dry film imageable solder mask)或其他形式的图案化层或介电层。于这些附加介电层251、271中分别暴露出这些电性接点274、275的这些开口可具有任何一种形态。这些型态包括圆柱形状,例如圆形圆柱形状、椭圆圆柱形状、方形圆柱形状或矩形圆柱形状、或非圆柱形状,例如圆锥形、漏斗形或其他一头逐渐变尖细的形状。此外,这些开口的侧边界可为曲线或具有粗糙的结构。
于实施例中,下方介电层260可为基底264,因此此基底264具有单层。或者,基底264可包括二或多层,例如下方介电层260与附加介电层270。基底264可为无核心。基底264可定义出凹穴(请参考图5)。透过基底264的电性连接可为这些导电连接结构,例如内层电性连接层263。或者或此外,透过基底264的电性连接可为电镀穿孔结构或其他已知型态的电性连接。
图3为本发明的实施例的一种内埋式半导体封装件300的剖面示意图。内埋式半导体封装件300与图2所述的内埋式半导体封装件200相似,二者主要差异之处在于:半导体元件302为倒装接合的半导体元件。部分位于半导体元件302下方的图案化导电层230可透过熔融的导电凸块304电性连接至芯片302,其中熔融的导电凸块304可由导电材料(例如焊料)所形成。
于实施例中,电性连接至这些接垫254的半导体元件(未绘示)可透过包括内层电性连接层253、内层电性连接层225以及导通孔224的导电路径而电性连接至半导体元件302。导电路径可包括部分图案化导电层230、240(一些部分未绘示)。
于实施例中,半导体元件302可透过包括内层电性连接层263的导电路径而电性连接至这些接垫274。导电路径可包括部分图案化导电层230(一些部分未绘示)。
图4为本发明的实施例的一种内埋式半导体封装件400的剖面示意图。内埋式半导体封装件400与图2所述的内埋式半导体封装件200相似,二者主要差异之处在于:半导体元件402为引线接合的半导体元件。部分位于半导体元件402下方的图案化导电层230可透过多条焊线404电性连接至芯片402。
于实施例中,电性连接至这些接垫254的半导体元件(未绘示)可透过包括内层电性连接层253、内层电性连接层225以及导通孔224的导电路径而电性连接至半导体元件402。导电路径可包括部分图案化导电层230、240(一些部分未绘示)。
于实施例中,半导体元件402可透过包括内层电性连接层263的导电路径而电性连接至这些接垫274。导电路径亦可包括部分图案化导电层230(一些部分未绘示)。
图5为本发明的实施例的一种内埋式半导体封装件500的剖面示意图。内埋式半导体封装件500与图2所述的内埋式半导体封装件200相似,二者主要差异之处在于:半导体元件502至少一部分配置于介电层260所定义的凹穴504内。于实施例中,粘着层213配置于凹穴504内。
半导体元件502配置于凹穴504内好处是在于较高的半导体元件502,其可支撑内埋式半导体封装件500且无需相对于内埋式半导体封装件200而增加内埋式半导体封装件500的整体厚度。于实施例中,半导体元件502具有高度506,其中高度506大于导通孔224的高度508与图案化导电层230的厚度509的总和。为了避免增加导通孔224的高度508,半导体元件502的至少一部分可配置于凹穴504内。
图7为本发明的实施例的一种内埋式半导体封装件700的剖面示意图。内埋式半导体封装件700与图2所述的内埋式半导体封装件200相似,二者主要差异之处在于:半导体元件202的至少一部分配置于延伸穿过介电层715的开口704中。且,无源元件203至少部分地配置于延伸穿过介电层715且暴露出介电层260的开口705内。(需注意的是,在此说明书中所采用的“半导体元件”亦可为任一有源元件、任一无源元件或上述的任意组合。)于实施例中,半导体元件202配置邻近介电层260。粘着层213可配置于半导体元件202与介电层260之间。于实施例中,无源电子元件203配置邻近介电层260。于实施例中,粘着层207配置于无源电子元件203与介电层260之间。除此之外,介电层715具有与先前所提及的介电层260相似的特征。
于此实施例中,单一介电层于工艺中可包括多个介电层。举例来说,介电层701包括介电层715与介电层260。位于介电层715中的开口704亦可称为位于介电层701中的凹穴706,其中凹穴706具有凹穴底部716。位于介电层715中的开口705亦可称为位于介电层701中的凹穴707,其中凹穴707具有凹穴底部717。半导体元件202配置邻近凹穴底部716,而无源电子元件203配置邻近凹穴底部717。每一凹穴底部716与每一凹穴底部717亦可具有介电层260的表面的至少一部分。
通过配置半导体元件202于凹穴706中,内埋式半导体封装件700可支撑较高的半导体元件202,而无须增加内埋式半导体封装件700相对于内埋式半导体封装件200的高度。于实施例中,此可通过部分配置半导体元件202于凹穴706中而达成。举例来说,半导体元件202亦可具有高于凹穴706的高度721的高度720,但此高度720小于高度721与介电层214的厚度722(在凹穴706上)的总和。
再者,由于凹穴706的设置,因此半导体元件202的表面一点也没有被暴露于内埋式半导体封装件700的外部表面。于实施例中,介电层214包覆半导体元件202。此不但可提供结构稳定度,亦可提供足够的保护来避免半导体元件202受到氧化、湿气以及其他环境条件的影响。具体来说,介电层214可实质上覆盖半导体元件202的上表面(有源面)206的至少一部分。介电层214亦可覆盖半导体元件202的侧表面208、210。半导体元件202的下表面(背表面)204可配置邻近凹穴716与/或介电层260。
内埋式半导体封装件700亦可包括延伸穿过介电层715且连接图案化导电层230至图案化导电层740的导通孔。图案化导电层230具有底表面231。于实施例中,半导体元件202的底表面204低于图案化导电层230的底表面231。图案化导电层740介于介电层715与介电层260之间。导通孔742延伸穿过介电层260且连接图案化导电层740至图案化导电层750。图案化导电层750介于介电层260与介电层270之间。图7中剩余的元件标号说明于图2中。
于实施例中,介电层214的厚度722介于约10微米(μm)至约150微米(μm)的范围内,例如从约10微米(μm)至约120微米(μm)、从约10微米(μm)至100微米(μm)、从约30微米(μm)至100微米(μm)以及从约50微米(μm)至100微米(μm)。
于实施例中,从凹穴716的侧表面736至半导体元件202的最邻近侧表面208之间的距离738是介于约10微米(μm)至约100微米(μm)的范围内,例如从约10微米(μm)至约50微米(μm)、从约30微米(μm)至50微米(μm)以及从约50微米(μm)至100微米(μm)。减少距离738的优点在于可降低封装胶体填入凹穴716内的空间所需的量,其中此凹穴716介于半导体元件202与侧表面735之间。于另一方面,距离738相对于精确度应大于最小公差,而使得凹穴716与半导体元件202于工艺中可以被配置。于其他实施例中,距离738可大于100微米(μm)。
图8为本发明的实施例的一种内埋式半导体封装件800的剖面示意图。内埋式半导体封装件800与图7所述的内埋式半导体封装件700相似,二者主要差异之处在于:半导体元件302为为倒装接合的半导体元件。图案化导电层830的一部分840透过开口704而被暴露出来,且亦可由凹穴706的凹穴底部716而被暴露出来。此外,图案化导电层830可具有与前述图案化导电层230相似的特征。半导体元件302的电性接点304可配置邻近部分840。于实施例中,部分840可透过熔融的导电凸块304而电性连接至半导体元件302,其中熔融的导电凸块304可由导电材料(例如焊料)所形成。
图9为本发明的实施例的一种内埋式半导体封装件900的剖面示意图。内埋式半导体封装件900与图7所述的内埋式半导体封装件700相似,二者主要差异之处在于:半导体元件402为引线接合的半导体元件。图案化导电层230的部分可透过多条焊线404电性连接至半导体元件402。
图10为本发明的实施例的一种内埋式半导体封装件1000的剖面示意图。内埋式半导体封装件1000与图7所述的内埋式半导体封装件700相似,二者主要差异之处在于:半导体元件1002至少部分地配置于双层凹穴1006内。再者,无源电子元件1003至少部分地配置于双层凹穴1007内。半导体元件1002具有与半导体元件202相似的特征,除了半导体元件1002的高度1010大于半导体元件202的高度210。双层凹穴1006具有与双层凹穴1007相似的特征,因此于此仅对双层凹穴1006作更进一步的说明。双层凹穴1006具有由介电层715所定义出的上部分1006a以及由介电层1060所定义出的下部分1006b。此外,介电层1060具有与前述所述的介电层260相似的特征。上部分1006a延伸穿过介电层715,且下部分1006b延伸穿过介电层1060,也就是说,双层凹穴1006延伸穿过二介电层。
双层凹穴1006的高度1021可大于单层凹穴706的高度721。通过配置半导体元件1002于双层凹穴1006内,内埋式半导体封装件700可支撑半导体元件1002,而无须增加(或甚至减少)内埋式半导体封装件1000相对于内埋式半导体封装件700的高度。于其他实施例中,凹穴亦可延伸穿过多于两层的介电层。
于实施例中,上部分1006a的宽度1008大于下部分1006b的宽度1012,相差的总合至少小于或等于约50微米(μm),例如从约10微米(μm)至约20微米(μm)、从约10微米(μm)至30微米(μm)以及从约10微米(μm)至50微米(μm)。
图6A至图6R绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。为了方便说明起见,以下将配合图2的内埋式半导体封装件200对内埋式半导体封装件的制作方法进行详细的说明。然而,这些制作过程可同样地被执行以形成其他内埋式半导体封装件,其可具有不同于内埋式半导体封装件200的初始结构,例如图3至图5所绘示的内埋式半导体封装件。这些制作过程亦可被执行以形成包括连接内埋式半导体封装件的阵列的装置条,其中每一装置条对应如图1至图5的内埋式半导体封装件。如图6Q所描述,连接内埋式半导体封装件的阵列可单体化以形成如图1至图5的单独的内埋式半导体封装件。
请先参考图6A,提供基底条600,绘示于图6A中的部分对应于图2中的基底264。多个图案化导电层602、604配置邻近基底条600。图6A中的部分图案化导电层602对应于图2中的图案化导电层230。基底条600定义出这些开口262。这些导电连接结构263延伸于这些图案化导电层602、604之间,且实质上填充这些开口262。每一图案化导电层602、604可具有从约10微米(μm)至约30微米(μm)之间的厚度,例如从15微米(μm)至约25微米(μm)。
接着,请参考图6B,可形成邻近图案化导电层602的光致抗蚀剂材料。光致抗蚀剂材料可为干膜光致抗蚀剂或其他型态的图案化层或介电层。可透过涂布、印刷或其他适当的方式来形成光致抗蚀剂层606。光致抗蚀剂层606预先决定或选择的部分可以经由曝光与显影,以产生多个暴露出图案化导电层602的开口607。光致抗蚀剂层606可以透过光掩模(未绘示)以光化学的方式来定义。曝光与显影相较于其他相近于光致抗蚀剂层606中制作开口的技术而言,可具有低成本与降低工艺时间的优势。所得到的这些开口可具有任何一种形态,包括圆柱形状,例如圆形圆柱形状、椭圆圆柱形状、方形圆柱形状或矩形圆柱形状、或非圆柱形状,例如圆锥形、漏斗形或其他一头逐渐变尖细的形状。此外,这些开口的侧边界可为曲线或具有粗糙的结构。
接着,请参考图6C,填入电性导电材料于光致抗蚀剂层606所定义的这些开口607内,以形成从图案化导电层602垂直延伸的这些导通孔224。这些导通孔224可利用一些涂布技术,例如化学气相沉积法(CVD)、无电电镀法(electroless plating)、电解电镀法(electrolytic plaitng)、电镀法(plating)、旋转法(spinning)、喷涂法(spraying)、溅镀法(sputting)或真空蒸镀法(vacuum deposition)。
接着,请参考图6D,剥离光致抗蚀剂层606以暴露出图案化导电层602。
接着,请参考图6E,半导体元件202配置邻近图案化导电层602。粘着层213可配置于半导体元件202与图案化导电层602之间。无源电子元件203配置邻近图案化导电层602。粘着层207可配置于无源电性元件203与图案化导电层602之间。
或者,请参考图6F,在基底条600中形成凹穴504。半导体元件502可至少部分地配置于凹穴504中。于实施例中,粘着层213配置于凹穴504内。
接着,请再参考图6E,提供介电层614,其中介电层614与一组第一开口614a是被预先形成,且第一开口614a的位置分别对应导通孔224、半导体元件202以及无源电子元件203。于实施例中,介电层614包括纤维强化的树脂材料,例如胶片(prepreg,PP),包括玻纤290以强化介电层614的强度。如图6E所示,玻纤290最初是沿着介电层614的一般水平平面延伸定向。如图6E所示的开口614a可完全延伸穿过介电层614,但开口614亦可部分地延伸穿过介电层614。
接着,请参考图6G,介电层614配置邻近基底条600,且覆盖半导体元件202、无源电子元件203以及这些导通孔224。介电层614亦可覆盖图案化导电层602。介电层614可分开导电片616从半导体元件202、无源电子元件203以及这些导通孔224。绘示于图6G中的部分介电层614对应于图2中的介电层214。于实施例中,玻纤290于后续介电层614的层压后被重新定向,随着部分邻近导通孔224、半导体元件202以及沿着导通孔224的垂直延伸方向伸出的无源电子元件203、半导体元件202以及无源元件203,且远离图案化导电层230。导电片616,例如铜箔,可配置邻近介电层614,举例来说,以形成覆盖半导体元件202、无源电子元件203以及这些导通孔224的树脂铜箔层。介电层614可具有单一树脂层或可具有由树脂所形成的第一子层以及由强化树脂所形成的第二子层,其中强化树脂例如具有玻璃纤维或克维拉纤维(Kevlar fiber)的强化树脂。
于其他实施例中,介电层614可由胶片材料所形成,且导电片616可配置邻近于介电层614。胶片材料可配置邻近于基底条600,且可预先形成以定义这些开口于半导体元件202、无源电子元件203以及这些导通孔224上的位置。此外,胶片材料可覆盖半导体元件202、无源电子元件203以及这些导通孔224。胶片材料可被形成一层胶层、或二层或多层胶层。或者,介电层614可包括胶片子层与树脂子层的复合层,以及导电片616可配置邻近介电层614。胶片子层可配置邻近基底条600,且可预先形成以定义这些开口于半导体元件202、无源电子元件203以及这些导通孔224上的位置。树脂子层可配置邻近胶片子层,且亦可配置邻近基底条600由胶片子层所定义出的这些开口内。
于其他实施例中,介电层614亦可由环氧封装胶体所形成,例如封装材料,且导电片616可配置邻近介电层614。
于实施例中,介电层614可压合于基底条600上。或者,介电层614可利用任何一种成形技术来形成,例如射出成形。一旦应用此技术,成形材料是硬的或是固体的,例如通过低于成形材料的熔化点的温度以形成介电层614。或者,介电层614可利用任何一种涂布技术来形成,例如印刷法、转法或喷涂法。
于实施例中,导电片616亦可在介电层614配置邻近于基底条600之前贴附于介电层614上。于实施例中,已贴附有导电片616的介电层614可配置邻近基底条600。
接着,请参考图6H,形成包括这些开口221、222、223的这些开口。这些开口221延伸穿过导电片616与介电层614,以暴露出每一导通孔224的上表面233。这些开口222延伸穿过导电片616与介电层614,以暴露出半导体元件202的这些电性接点212。这些开口223延伸穿过导电片616与介电层614,以暴露出无源电子元件203的这些电性接点215。这些开口221、222、223可由激光钻孔或其他适当已知的已知技术所形成。
接着,请参考图6I,这些开口221、222、223填入导电材料以形成导通孔,例如图2中的这些内层电性连接层225、226、227。这些内层电性连接层225、226、227可利用任何一种涂布技术,例如无电电镀与/或电解电镀法所形成。
接着,在图6J至图6L中说明减成法,以形成包括图2的图案化导电层240的图案化导电层。于图6J中,附加导电材料配置邻近这些内层电性连接层225、226、227,且邻近导电片616。此附加导电材料形成导电层618以电性连接至这些内层电性连接层225、226、227。
于图6K中,形成邻近导电层618的光致抗蚀剂层620。光致抗蚀剂层620已预先决定或选择的部分可曝光与显影以形成这些开口622。这些开口622暴露出导电层618。光致抗蚀剂层620(与这些开口622)与图6B的光致抗蚀剂层606(与这些开口607)具有相同特征与类似的形成方式。
于图6L中,形成暴露出介电层614的这些开口624于导电层618中,以形成图案化导电层640。图6L所示的部分图案化导电层640对应于图2的图案化导电层240。图案化以形成图案化导电层640的方式可采用任何一种方式,例如化学蚀刻法、激光钻孔法或机械钻孔法,而所形成的这些开口可为任何一种形态,例如圆柱形态,例如圆形圆柱形状、椭圆圆柱形状、方形圆柱形状或矩形圆柱形状、或非圆柱形状,例如圆锥形、漏斗形或其他一头逐渐变尖细的形状。此外,这些开口的侧边界可为曲线或具有粗糙的结构。
与图6J至图6L所说明的减层法两者择一,图6M至图6O中说明修改半加成法(modified semi-additive process,MSAP)过程以形成包括图2的图案化导电层240的图案化导电层。修改半加成法过程是用来形成相对于减成法具有微细间距以及较窄线路的图案化导电层。于图6M中,形成邻近导电片616的光致抗蚀剂层630。光致抗蚀剂层630的预先决定或选择的部分可曝光与显影以形成这些开口632。这些开口632暴露出导电片616。光致抗蚀剂层630(与这些开口632)与图6B的光致抗蚀剂层606(与这些开口607)具有相同特征与类似的形成方式。
于图6N中,附加导电材料配置邻近这些内层电性连接层225、226、227,且邻近导电片616。附加导电材料形成导电层634以电性连接至这些内层电性连接层225、226、227。导电片616与导电层634的结合具有厚度635。
于图6O中,移除图案化光致抗蚀剂层630。接着,移除部分导电层634,例如透过快速蚀刻法(flash etching),以形成图案化导电层640。由于快速蚀刻法,图案化导电层640的厚度641可从图6N的厚度635减少。
接着,在图6P中,介电层650配置邻近介电层614,且介电层670配置邻近基底条600。图6P中的部分这些介电层650、670分别对应图2中的这些介电层250、270。这些介电层650、670的形成方式可与上述图6G所述的介电层614的形成方式相同。这些延伸穿过这些介电层650、670的内层电性连接层,例如这些内层电性连接层253,可采用与上述图6C所述的这些导通孔224相同的形成方式。这些电性接点254、274的形成方式可采用与上述图6K与图6L所述的图案化导电层640相同的形成方式。
接着,请参考图6Q,介电层651配置邻近介电层650,且介电层671配置邻近介电层670。图6Q中的部分这些介电层651、671分别对应于图2中的这些介电层251、271。这些介电层651、671的形成方式可采用与上述图6G所述的介电层614相同的形成方式。这些表面处理层255、275的形成方式可采用与上述图6C所述的这些导通孔224相同的形成方式。之后,沿着多条虚线680、681进行单体化工艺,以得到单独的内埋式半导体封装件,例如图2的内埋式半导体封装件200。
接着,请参考图6R,第二半导体元件690以及无源电子元件692可电性连接至这些电性接点254。
图11A至图11S绘示为本发明的实施例的一种内埋式半导体封装件的制作方法。为了方便说明起见,以下将配合图7的内埋式半导体封装件700,其包括图2的内埋式半导体封装件200的观点,对内埋式半导体封装件的制作方法进行详细的说明。然而,这些制作过程可同样地被执行以形成其他内埋式半导体封装件,其可具有不同于内埋式半导体封装件700的初始结构,例如图8至图10所绘示的内埋式半导体封装件。这些制作过程亦可被执行以形成包括连接内埋式半导体封装件的阵列的装置条,其中每一装置条对应如图8至图10的内埋式半导体封装件。如图11R所描述,连接内埋式半导体封装件的阵列可单体化以形成如图8至图10的单独的内埋式半导体封装件。
请先参考图11A,提供承载器1100。于实施例中,承载器110包括核心层(未绘示)以及二承载导电层(未绘示),其中核心层介于两承载导电层之间,且两承载导电层贴附核心层。每一承载导电层可由金属、金属合金、具有金属或金属合金扩散于其内的金属基质或其他适当导电材料所形成。举例来说,每一承载导电层可包括由铜或含铜的合金所形成的金属铜箔。金属铜箔可具有介于约10微米(μm)至约30微米(μm)之间的厚度,例如从15微米(μm)至约25微米(μm)。
承载器1100具有上表面1102与下表面1104。导电层1105(导电片1105)配置邻近下表面1104。图11A至图11H绘示承载器1100对应下表面1104的单一侧的制作方法。可预期相似的制作方法可发生于制作承载器1100的相对两侧,包括承载器1100相对于上表面1102的一侧。以双侧制作为例,具有与导电片1105相似的特征的导电层(未绘示)可配置邻近上表面1102。
导电片1105可由金属、金属合金、具有金属或金属合金扩散于其内的金属基质或其他适当导电材料所形成。举例来说,导电片1105可包括由铜或含铜的合金所形成的可剥离金属铜箔(releasable metal foil)。导电片1105可透过离形层(release layer)(未绘示)贴附于承载器1100上。于实施例中,离形层可为粘着层,其可为有机或无机,例如胶带。胶带可为单面或双面粘着胶带,固定元件相对于彼此于适当间隔,且允许后续工艺操作可执行元件配置邻近承载器1100。导电片1105可具有介于约2微米(μm)至约10微米(μm)之间的厚度,例如从3微米(μm)至约5微米(μm)。
接着,请参考图11B,导电块1106以及导通孔741形成邻近导电片1105的下表面1107。导电块1106与导通孔741的形成过程相似于前述图6B至图6D的制作步骤。光致抗蚀剂材料形成邻近下表面1107。于光致抗蚀剂内的开口被形成,例如透过曝光与显影,其对应导电块1106与导通孔741的位置。电性连接材料应用于开口以形成导电块1106与导通孔741。导电块1106与导通孔741可作缓冲器。之后剥离光致抗蚀剂层以暴露出导电片1105。
接着,请参考图11C,介电层1115配置邻近导电片1105的下表面1107。图11C所示的介电层1115的部分对应于图7的介电层715。介电层1115可覆盖导电块1106的侧表面1108。介电层1110(导电片1110)可配置邻近介电层1115、导电块1106以及导通孔741。于实施例中,介电层1115可由树脂材料所构成。导电片1110,例如铜箔,可配置邻近介电层1115,举例来说,以形成树脂铜箔层。导电片1110可为金属,例如铜箔或含铜的合金。导电片1110可透过无电电镀法、溅镀法或其他已知的适当的方式来形成。介电层1115可具有单一树脂层或可具有由树脂所形成的第一子层以及由强化树脂所形成的第二子层,其中强化树脂例如具有玻璃纤维或克维拉纤维(Kevlar fiber)的强化树脂。
于其他实施例中,介电层1115可由胶片材料所形成,且导电片1110可配置邻近于介电层1115。胶片材料可配置邻近于导电片1105,且可预先形成以定义这些开口于导电块1106以及导通孔741上的位置。胶片材料可被形成一层胶层、或二层或多层胶层。或者,介电层1115可包括胶片子层与树脂子层的复合层,以及导电片1110可配置邻近介电层1115。胶片子层可配置邻近导电片1105,且可预先形成以定义这些开口于导电块1106以及这些导通孔741上的位置。树脂子层可配置邻近胶片子层,且亦可配置邻近导电片1105由胶片子层所定义出的这些开口内。
接着,请参考图11D,图案化导电层1140是由导电片1110所形成,且导通孔742形成邻近图案化导电层1140。图11D的图案化导电层1140的位置对应于图7的图案化导电层740。图案化导电层1140与导通孔742的形成过程相似于前述图6B至图6D的制作步骤。光致抗蚀剂材料形成邻近导电片1110,例如透过干膜层压。于光致抗蚀剂内的开口被形成,例如透过曝光与显影,其对应图案化导电层1140。电性连接材料应用于开口以形成对应图案化导电层1140的导电层。之后剥离光致抗蚀剂层。然后,再次形成邻近导电片1110的光致抗蚀剂材料。于光致抗蚀剂内的开口被形成,例如透过曝光与显影,其对应导通孔742。电性连接材料应用于开口以形成导通孔742。导通孔742可作缓冲器。之后剥离光致抗蚀剂层。然后,进行快速蚀刻以移除导电片1110残余的部分,以及形成图案化导电层1140。
图11E绘示实施例的一种形成对应图10的双层凹穴1006的导电块1112。导电块1112包括第一导电部1112a以及第二导电部1112b。第二导电部1112b的形成与如何形成导通孔742相似(请参考图11D的描述)。于实施例中,第一导电部1112a具有宽度1111,此宽度1111大于第二导电部1112b的宽度1117。第一导电部1112a的侧表面1113被介电层1115所覆盖。第二导电部1112b的侧表面1116被对应于图2与图7的介电层260的介电层所覆盖。
接着,请参考图11F,介电层1160配置邻近介电层1115且覆盖图案化导电层1140以及导通孔742。图11F的介电层1160的部分对应于图2与图7的介电层260。介电层1118(导电片1118)可配置邻近介电层1160与导通孔742。介电层1160与导电片1118具有相似的特征,且其形成方法分别与形成介电层1115与导电片1110的方法相似,请参考图11C的描述,在此不再赘述。
接着,请参考图11G,图案化导电层1150是由导电片1118所形成,且导通孔744形成邻近图案化导电层1150。图11G的图案化导电层1150的部分对应于图7的图案化导电层750。图案化导电层1150与导通孔744具有相似的特征,且其形成方法分别与形成图案化导电层1142及导通孔742的方法相似,请参考图11D的描述,在此不再赘述。
接着,请参考图11H,介电层1170配置邻近介电层1160,且覆盖图案化导电层1150与导通孔744。图11H的介电层1170的部分对应于图2与图7的介电层270。介电层1119(导电片1119)可配置邻近介电层1170与导通孔744。介电层1170与导电片1119具有相似的特征,且其形成方法分别与介电层1115与导电片1110的形成方法相似,请参考图11C的描述,在此不再赘述。
接着,请参考图11I,移除承载器1110,以暴露出导电片1105。
接着,请参考图11J,图案化导电层1130是由导电片1105所形成,且导通孔224形成邻近图案化导电层1130。图11J的图案化导电层1130的部分对应图2与图7的图案化导电层230。图案化导电层1130与导通孔224具有相似的特征,且其形成的方法分别与形成图案化导电层1142及导通孔742的方法相似,请参考图11D的描述,在此不再赘述。
接着,请参考图11K,光致抗蚀剂材料形成邻近介电层1115,且位于光致抗蚀剂内的开口被形成,透过相似于前述图6B的形成方法。位于光致抗蚀剂内的开口被形成,例如透过曝光与显影,以暴露出导电块1106。
接着,请参考图11L,移除导电块1106以形成延伸穿过介电层1115的开口704与705。每一开口704与705暴露出介电层1160。开口704亦可视为具有凹穴底部716的凹穴706。开口705亦可视为具有凹穴底部717的凹穴707。于实施例中,移除导电块1106的方法为化学蚀刻法。化学蚀刻的好处在于可透过相同的工艺步骤来同时移除导电块1106。于其他实施例中,替代蚀刻导电块1106的方法,凹穴706可透过激光与/或机械钻孔穿过介电层1115。这些钻孔工艺可多次消耗化学蚀刻,因为凹穴的形成每次都是利用这些方法。
接着,请参考图11M,半导体元件202配置邻近介电层1160(亦邻近凹穴底部716)。粘着层213可配置于半导体元件202与凹穴底部716之间。无源电子元件203配置邻近介电层1160(亦邻近凹穴底部717)。粘着层207可配置于无源电子元件203与凹穴底部717之间。
接着,请参考图11N,介电层1114配置邻近介电层1115,且覆盖半导体元件202、无源电子元件203以及导通孔224。介电层1114可分离导电片1120与半导体元件202、无源电子元件203以及导通孔224。图6G的介电层1114的部分对应于图2与图7的介电层214。介电层1114与导电片1120具有相似的特征,且其形成方法分别与形成介电层614及导电片616的方法相似,请参考图6G的描述,在此不再赘述。
接着,请参考图11O,形成包括这些开口221、222、223的这些开口。这些开口221延伸穿过导电片1120与介电层1114,以暴露出每一导通孔224的上表面233。这些开口222延伸穿过导电片1120与介电层1114,以暴露出半导体元件202的这些电性接点212。这些开口223延伸穿过导电片1120与介电层1114,以暴露出无源电子元件203的这些电性接点205。这些开口221、222、223可由激光钻孔或其他适当已知的已知技术所形成。
接着,请参考图11P,这些开口221、222、223填入导电材料以形成导通孔,例如图2与图7中的这些内层电性连接层225、226、227。这些内层电性连接层225、226、227可利用任何一种涂布技术,例如无电电镀与/或电解电镀法所形成。于实施例中,接着,进行减成法,以形成图案化导电层1140。减成法相似于前述图6J至图6L的描述,在此不再赘述。于其他实施例中,修改半加成法(modified semi-additive process,MSAP)过程以形成包括图2与图7的图案化导电层240的图案化导电层。修改半加成法相似于图6M至图6O,在此不再赘述。图11P的图案化导电层1140的部分对应图2与图7的图案化导电层240。
接着,请参考图11Q,介电层1150配置邻近介电层1114,且介电层1170配置邻近介电层1160。图11Q所示的介电层1150及1170的部分分别对应于图2与图7的介电层250及270。介电层1150及1170的形成方法相似于前述图6G所述的介电层614的形成方法。电性内连接延伸穿过介电层1150及1170,例如内部电性连接253,其形成方法相似于前述图11D所述的导通孔742的形成方法。电性接点254及274的形成方法相似于前述图11P所述的图案化导电层1140的形成方法。
接着,请参考图11R,介电层1151配置邻近介电层1150,且介电层1171配置邻近介电层1170。图11R的介电层1151及1171的部分分别对应于图2及图7的介电层251及271。介电层1151及1171的形成方法相似于前述图6G的介电层614的形成方法。表面处理层255及274的形成方法相似于前述图6C的导通孔224的形成方法。然后,沿着切割线1180及1181进行单体化工艺,以形成多个自独立的内埋式半导体封装件,例如图7的内埋式半导体封装件700。
接着,请参考图11S,第二半导体元件1190及无源电子元件1192可电性连接至电性接点254。
于图11至11S的制作步骤中,这些介电层与这些导电元件可形成于半导体元件202的上方与下方。因此,半导体元件202每有一个表面是暴露于内埋式半导体封装件700的外侧表面。于实施例中,介电层214覆盖半导体元件202。此可提供机械稳定度同时亦可保护半导体元件202以阻绝氧气、湿气或其他环境状态。
图12A至图12E绘示为本发明的实施例的一种内埋式半导体封装件1280(请参考图12E)的制作方法。为了方便说明起见,以下将配合图6A至图6R的制作步骤与不同之处于下述进行详细的说明。然而,这些制作过程可同样地被执行以形成其他内埋式半导体封装件,其可具有不同于内埋式半导体封装件1280的初始结构。这些制作过程亦可被执行以形成包括连接内埋式半导体封装件的阵列的装置条。
请先参考图12A,提供装置条1200,例如印刷电路板。装置条1200包括位于基底1200内的导电元件1201以及位于基底条1200的表面上的导电元件1202。导通孔1224从导电元件1202垂直延伸。于实施例中,导通孔1224具有与导通孔224相似的特征及相似的形成方法,请参考图6B至图6D的描述。
请参考图12B,介电层1214配置邻近基底条1200。介电层1214具有与介电层614相似的特征,请参考图6E的描述。介电层1214的配置方式亦相似于介电层614,请参考图6G,除了介电层1214在配置于半导体元件1202(请参考图12D)上之前是配置于基底条1200上。介电层1214具有凹穴1225,而半导体元件1202配置于凹穴1225内(请参考图12D)。于实施例中,介电层1214透过研磨与/或钻孔的方式来暴露出导通孔1224。
请参考图12C,光致抗蚀剂层1220,例如光成像焊料光致抗蚀剂(photo-imageable solder resist),形成邻近介电层1214。光致抗蚀剂层1220预定或选择的部分可曝光与显影而形成开口1222。开口1222暴露出导通孔1224。光致抗蚀剂层1220(以及开口1222)具有相似的特征,且其形成方法相似于图6B所描述的形成光致抗蚀剂层606(以及开口607)的方法。于实施例中,电性接点(例如焊球)可配置于开口1222内,且电性连接至导通孔1224。这些电性接点可提供电性导通至,举例来说,图案化导电层与/或其他配置于光致抗蚀剂层1220上的封装。
请参考图12D至图12E,半导体元件1202配置于位于介电层1214的凹穴1225内。接着,填充介电层1234于凹穴1225内。介电层1234可为环氧树脂、封装胶体、液态封装胶体或其他不同于胶片的适当材料。于实施例中,半导体元件1202可倒装接合至一或多个导电元件1202。或者,相似于半导体元件202(请参考图6E)的半导体元件配置邻近基底条1200。于此实施例中,半导体元件202的电性接点212被暴露出来,请参考图6H的描述。再者,在此实施例中,导电片616(请参考图6G)的形成以及配合图6H至6R的操作步骤可与图12E的操作步骤联想在一起。
于实施例中,凹穴可透过如图6F所描述的机械钻孔法的方式形成于基底条1200上。接着,半导体元件1202至少部分地配置于基底条1200的凹穴内。于实施例中,相似于粘着层213的粘着层可配置于凹穴内。
图13A至图13H绘示为本发明的实施例的一种内埋式半导体封装件1390(请参考图13H)的制作方法。为了方便说明起见,以下将配合图6A至图6R以及图11A至图11S的制作步骤与不同之处于下述进行详细的说明。然而,这些制作过程可同样地被执行以形成其他内埋式半导体封装件,其可具有不同于内埋式半导体封装件1390的初始结构。这些制作过程亦可被执行以形成包括连接内埋式半导体封装件的阵列的装置条。
请先参考图13A,提供导电层1105(先前描述于图11A中)。于实施例中,导电层1105(导电片1105)可包括由铜或含铜的合金所形成的可剥离金属铜箔。金属铜箔可具有介于约10微米(μm)至约30微米(μm)之间的厚度,例如从15微米(μm)至约25微米(μm)。导电片1105可配置邻近于承载器(未绘示),例如绘示于图11A的承载器1100。导电片1105可透过离形层(未绘示)贴附于承载器1100。于实施例中,离形层为粘着层,其为有机或无机,例如胶带。
图案化导电层1300可配置邻近导电片1105,且导通孔1302可从图案化导电层1300垂直延伸。图案化导电层1300可具有与前述图11D所描述的图案化导电层1140相似的特征。导通孔1302可具有与前述图11D所描述的图案化导电层742相似的特征。图案化导电层1300与导通孔1302的形成方法具有与前述图11D所描述的制作步骤相似的观点。光致抗蚀剂材料形成邻近导电片1105,例如透过干膜层压。于光致抗蚀剂内的开口被形成,例如透过曝光与显影,其对应图案化导电层1300。电性导电材料应用于开口内以形成对应图案化导电层1300的导电层。接着,剥离光致抗蚀剂层。然后,再次形成邻近导电片1105的光致抗蚀剂材料。于光致抗蚀剂内的开口被形成,例如透过曝光与显影,其对应导通孔1302。电性导电材料应用于开口内,以形成导通孔1302。导通孔1302可作缓冲器。之后,剥离光致抗蚀剂层。
于实施例中,在剥离光致抗蚀剂层,介电子层1304配置邻近导电片1105。介电子层1304具有与前述图11C所述的介电层1115相似的特征。于实施例中,介电子层1304可由树脂材料所形成。导电片1105可配置邻近介电子层1304以形成,举例来说,树脂铜箔层。介电子层1304可具有单一树脂层或可具有由树脂所形成的第一子层以及由强化树脂所形成的第二子层,其中强化树脂例如具有玻璃纤维或克维拉纤维(Kevlar fiber)的强化树脂。或者,介电层1304可由胶片材料所形成。胶片材料可预先形成以定义这些开口于这些导通孔1302上的位置。介电子层1304可包括胶片子层与树脂子层的复合层。于实施例中,在形成邻近导电片1105的介电子层1304之后,形成邻近介电子层1304的导电片1306。导电片1306具有与前述图11C的导电片1110相似的特征与相似的形成方法。导电片1306可为金属,例如铜或含铜的合金。导电片1306可透过无电电镀法、溅镀法或其他已知的方法来形成。
或者,导电片1306可在配置于邻近导电片1105的介电子层1304上之前贴附于介电子层1304上。于实施例中,已贴附有导电片1306的介电子层1304可配置邻近导电片1105。此步骤可与配置导电片1306于邻近的导通孔1302上同时进行。
接着,请参考图13B,导通孔1308与导电块1310形成邻近导电片1306。导通孔1308延伸至导通孔1302(请参考图13A)以形成导通孔1312。导通孔1312及导电块1310具有于前述图11B所述的导通孔741及导电块1106相似的特征与相似的形成方法。光致抗蚀剂材料形成邻近导电片1306。于光致抗蚀剂内的开口被形成,例如透过曝光与显影,其对应于导电块1310与导通孔1312的位置。电性连接材料应用于开口内,以形成导电块1310与导通孔1312。导电块1310与导通孔1312可做缓冲器。之后,剥离光致抗蚀剂层以暴露出导电片1306。
接着,请参考图13C,之后,透过快速蚀刻来移除导电片1306。具有与前述图11C所描述的介电层1115相似特征的附加介电子层配置邻近介电子层1304(请参考图13A),以形成介电层1314。导电块1310与导通孔1312可作缓冲器。接着,导电片1316可形成邻近介电层1314。导电片1316具有与前述图13A所述的导电片1306相似的特征与相似的形成方法。或者,导电片1316可于配置附加介电子层邻近于介电子层1304以形成介电层1314之前贴附于介电子层上。于实施例中,已贴附有导电片1316的附加介电子层可配置邻近介电层1304,以形成介电层1314。此步骤可与配置导电片1316于邻近的导通孔1312上同时进行。
接着,请参考图13D,图案化导电层1318配置邻近导电片1316。图案化导电层1318可具有与前述图13A的图案化导电层1300相似的特征与相似的形成方法。
接着,请参考图13E,导通孔1322形成邻近图案化导电层1318,且导电块1320形成邻近导电片1316。导电块1320延伸穿过导电块1310(请参考图13C)以形成导电块1321。导通孔1322与导电块1321具有与前述图13B的导通孔1312与导电块1310相似的特征与相似的形成方法。之后,透过快速蚀刻法来移除导电片1316。具有与前述图11C所述的介电层1115相似特征的附加介电子层配置邻近于介电层1314。导电块1321与导通孔1312可作缓冲器。之后,形成邻近介电子层1324的导电片1326。导电片1326具有与前述图13A的导电片1306相似的特征与相似的形成方法。或者,导电片1326可于配置介电层1324邻近介电层1314之前贴附于介电子层1324。于实施例中,已贴附有导电片1326的介电子层1324可配置邻近介电层1314。此步骤可与配置导电片1326于邻近的导通孔1322上同时进行。
或者,请参考图13F,导通孔1332形成邻近导电片1326,且导电块1330形成邻近导电片1326。导通孔1332延伸至导通孔1322(请参考图13E)以形成导通孔1333。导电块1330延伸至导电块1321(请参考图13E)以形成导电块1331。导通孔1333与导电块1331具有与前述图13B所述的导通孔1312与导电块1310相似的特征与相似的形成方法。接着,透过快速蚀刻来移除导电片1326。具有与前述图11C所述的介电层1115相似特征的附加介电层配置邻近介电子层1324(请参考图13E),以形成介电层1334。导电块1331与导通孔1333可作缓冲器。导电片1336可形成邻近于介电层1334。导电片1336可具有与前述图13A相似特征及相同制作方法。或者,导电片1336可于配置附加介电子层邻近于介电子层1324以形成介电层1334之前贴附于介电子层上。于实施例中,已贴附于导电片1336的附加介电子层可配置邻近于介电层1324,以形成介电层1334。此步骤可与配置导电片1336于邻近的导通孔1332上同时进行。
接着,图案化导电层1338配置邻近导电片1336。图案化导电层1338可具有与前述图13A的图案化导电层1300相同的特征与相似的形成方法。
接着,请参考图13G,可透过快速蚀刻来移除导电片1336。之后,形成邻近介电层1334的光致抗蚀剂材料层,且透过与前述图11K所描述的制作方法来形成位于光致抗蚀剂内的开口。光致抗蚀剂内的开口例如透过曝光与显影被形成,以暴露出导电块1331(请参考图13F)。移除导电块1331以形成延伸穿过介电层1334至介电层1314内的开口1340。开口1340可视为具有凹穴底部1342的凹穴1340。于实施例中,可透过化学蚀刻来移除导电块1331。此化学蚀刻的好处在于可透过相同的工艺步骤来同时移除导电块1331。于其他实施例中,替代蚀刻导电块1331的方法,凹穴1340可透过激光与/或机械钻孔穿过介电层1331。这些钻孔工艺可多次消耗化学蚀刻,因为凹穴的形成每次都是利用这些方法。
图13H绘示内埋式半导体封装件1390。芯片202配置于凹穴1340内。介电层1344形成邻近介电层1334。介电层1344具有与前述图11C的介电层1115相似的特征。图案化导电层1346可采用于前述图11N至图11P相似步骤的制作方法。于实施例中,相似于图6J至图6L的减成法被采用,故于此不再赘述。于其他实施例中,相似于图6M至图6O所述的修改半加成法(modified semi-additive process,MSAP)被采用,故于此不再赘述。
或者,图案化导电层1346亦可透过位于介电层1344内的开口1347来形成,接着,透过配置介电材料层于开口1347内。开口1347可透过机械钻孔或其他已知的适当方式来形成。导电层可透过溅镀法、无电电镀法或其他以的适当方式来配置于开口1347内。之后,图案化此导电层以形成图案化导电层1346。图案化导电层1346可具有与前述图13A的图案化导电层1300相似的特征与相同的形成方法。
接着,介电层1350与1352可分别配置邻近图案化导电层1346与1300。介电层1350与1352可为焊罩层。介电层1350及1352暴露出图案化导电层1346及1300的部分,以形成电性接点1354及1356于内埋式半导体封装件1390的外部周围。电性接点1354及1356可分别具有表面处理层1358及1360,且其可包括一或多镍子层与金子层。
图13A至图13H绘示形成延伸穿过多个于内埋式半导体封装件内的图案化导电层的凹穴。特别是,凹穴1340从图案化导电层1338延伸经过导电层1318。于实施例中,凹穴底部1342可配置于图案化导电层1318与图案化导电层1300之间,且位于介电层1314内。凹穴1342可配置于图案化导电层1300与图案化导电层1318之间,透过配置导电块1310与导通孔1308邻近导电片1306,而无形成邻近导电片1306的分离的图案化导电层。或者,凹穴底部1342可配置于图案化导电层的深度中,举例来说,透过形成邻近导电片1306的分离的图案化导电层。于实施例中,凹穴1340可延伸经过图案化导电层1318,透过形成图13D与图13E的导电块1321。凹穴1340可形成具有深度,此深度对应配置于以导电片1306(请参考图13B)及导电片1336(请参考图13F)的位置为基准的凹穴1340内芯片202。于绘示的实施例中,凹穴1340的深度大于介电层1334的厚度。
图14A至图14C绘示为本发明的实施例的一种内埋式半导体封装件1490(请参考图14C)的制作方法。为了方便说明起见,以下将配合图11A至图11S以及图13A至图11H的制作步骤与不同之处将于下述进行详细的说明。然而,这些制作过程可同样地被执行以形成其他内埋式半导体封装件,其可具有不同于内埋式半导体封装件1490的初始结构。这些制作过程亦可被执行以形成包括连接内埋式半导体封装件的阵列的装置条。
请先参考图14A,提供导电层1105(先前描述于图11A中)。于实施例中,导电块1105(导电片1105)可包括由铜或含铜的合金所形成的可掀离金属铜箔。导电片1105可配置邻近承载器(未绘示),例如图11A所绘示的承载器1100。导电片1105可透过离形层(未绘示)贴附于承载器1100上。
导通孔1406与导电块1404形成邻近导电片1105。导通孔1406与导电块1404具有与前述图11B的导通孔741与导电块1106相似的特征与相似的形成方法。形成邻近导电片1105的光致抗蚀剂材料。形成于光致抗蚀剂内的开口,例如透过曝光与显影,其对应导电块1404与导通孔1406的位置。电性导电材料应用于开口内以形成导电块1404与导通孔1406。导电块1404与导通孔1406可作缓冲器。之后,剥离光致抗蚀剂层以暴露出导电片1105。
接着,具有与图11C的介电层1115相似特征的介电层1402配置邻近导电片1105。之后,导电块1404与导通孔1406可作缓冲器。导电片1400可形成邻近介电层1402。导电片1400具有与导电片1105相似的特征及相似的形成方法。
接着,图案化导电层1410可配置邻近导电片1400。图案化导电层1410可具有与前述图11D的图案化导电层1140相似的特征。图案化导电层1410的形成过程相似于前述图13A所述的图案化导电层1300的形成方式。
于实施例中,接着,导电片1105可分离承载器且翻转以使图案化导电层1410可配置于承载器上。之后,图案化导电层1408配置邻近导电片1105。图案化导电层可具有与图案化导电层1410相似的特征与相似的形成方法。
或者,进行附加步骤于导电片1105分离承载器之前。举例来说,介电层1417、导通孔1422以及图案化导电层1414(请参考图14B)可形成邻近与/或图案化导电层1410的上方,相似于图11D、图11F及图11G的制作步骤。
如图14B所示,在导电片1105分离于承载器且翻转后,相似于图13E、图13F以及图13G的步骤可被执行,以得到结构1430。结构1430可包括凹穴1420,其延伸穿过介电层1416与1402,且暴露出介电层1417。凹穴1420可从图案化导电层1412延伸经过图案化导电层1408至图案化导电层1410。
请参考图14C,额外增加的工艺,类似图11M至11R,可得到内埋式半导体封装件1490。此导致半导体元件202配置于内埋式半导体封装件1490的内部,因此半导体元件202位于两内部图案化导电层之间:图案化导电层1412及图案化导电层1410。于实施例中,至少一介电层1417分离图案化导电层1410与邻近内埋式半导体封装件1490的外部周围的图案化导电层1414。于实施例中,至少一介电层1430、图案化导电层1431以及介电层1432分离图案化导电层1412与邻近内埋式半导体封装件1490的外部周围1441的图案化导电层1433。半导体装置透过内层电性连接层1435电性连接至图案化导电层1431。
虽然本发明已以实施例披露如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视权利要求所界定为准。此外,许多修改可使事件、方法或过程的特殊情况、材料或合成物来适应本发明的宗旨、精神和范围。这一类的修改亦被预期为可能在权利要求中的一些项中陈述。特别是,在此中被披露的方法描述了关于按特殊顺序进行的特殊操作,这些操作也许可被结合、被细分或者被重新调整而形成一个等同方法,此仍不脱离本发明所教示的范围内。因此,除非此文中明确地说明,否则顺序和编组操作非用以限定本发明。
Claims (12)
1.一种内埋式半导体封装件,包括:
半导体元件,具有电性接点;
上方图案化导电层;
介电层,介于该上方图案化导电层与该半导体元件之间,该介电层具有第一开口且暴露该电性接点;
第一内层电性连接层,从该电性接点延伸至该上方图案化导电层,其中该第一内层电性连接层填充于该第一开口;
下方图案化导电层,该介电层具有从该下方图案化导电层延伸至该上方图案化导电层的第二开口,该第二开口具有上部分及下部分,其中该上部分暴露出该上方图案化导电层,该下部分暴露出该下方图案化导电层;
导通孔,位于该第二开口的该下部分;以及
第二内层电性连接线,填充于该第二开口的该上部分;
其中该导通孔具有第一端与第二端,该第二端邻近该第二内层电性连接线,该第一端相对于该第二端,该导通孔的第二端至该上方图案化导电层的第一距离大于从该半导体元件的上表面至该上方图案化导电层的第二距离。
2.如权利要求1所述的内埋式半导体封装件,其中该上方图案化导电层透过导电路径电性连接至该下方图案化导电层,而该导电路径包括该导通孔以及该第二内层电性连接线。
3.如权利要求1所述的内埋式半导体封装件,其中该导通孔为电镀导电柱。
4.如权利要求1所述的内埋式半导体封装件,其中该介电层包括至少一胶层、树脂层以及环氧层。
5.如权利要求4所述的内埋式半导体封装件,其中该介电层包括玻纤,且该玻纤的部分定向远离该下方图案化导电层。
6.如权利要求1所述的内埋式半导体封装件,其中该半导体元件具有背表面,且该背表面配置邻近该下方图案化导电层。
7.如权利要求1所述的内埋式半导体封装件,其中该导通孔的上表面与该半导体元件的有源表面共平面。
8.一种内埋式半导体封装件的制作方法,包括:
提供第一图案化导电层以及半导体元件;
形成从该第一图案化导电层垂直延伸的导通孔;
配置该半导体元件,以使该半导体元件电性连接至该第一图案化导电层;
配置介电层,以覆盖该半导体元件、该第一图案化导电层以及该导通孔,配置导电片于邻近该介电层的上表面,该介电层分离该导电片与该半导体元件以及分离该导电片与该导通孔;
形成第一开口,该第一开口延伸穿过该导电片与该介电层,以暴露该导通孔的顶端;
形成第一内层电性连接层,连接该导通孔至该导电片,其中该第一内层电性连接层填充该第一开口;以及
从该导电片形成第二图案化导电层。
9.如权利要求8所述的内埋式半导体封装件的制作方法,还包括:
形成第二开口,该第二开口延伸穿过该导电片与该介电层,以暴露该半导体元件的电性接点;以及
形成第二内层电性连接层,连接该半导体元件的该电性接点至该导电片,其中该第二内层电性连接层填充该第二开口。
10.如权利要求8所述的内埋式半导体封装件的制作方法,其中形成该第一内层电性连接层与形成该第二图案化导电层,还包括:
配置导电材料的第一部分,以填充该第一开口;
通过配置邻近该导电片的该导电材料的第二部分来形成导电层;
形成图案化干膜,该图案化干膜邻近该导电层,该图案化干膜暴露部分该导电层;
通过移除被该图案化干膜所暴露的部分该导电层,以形成该第二图案化导电层;以及
于形成该第二图案化导电层之后,移除该图案化干膜。
11.如权利要求8所述的内埋式半导体封装件的制作方法,其中形成该第一内层电性连接层与形成该第二图案化导电层,还包括:
配置导电材料的第一部分,以填充该第一开口;
形成邻近该导电片的图案化干膜,该图案化干膜暴露部分该导电片;
通过配置邻近被该图案化干膜所暴露的部分该导电片的该导电材料的第二部分来形成导电层;
移除该图案化干膜;以及
于移除该图案化干膜之后,通过移除部分该导电层以形成该第二图案化导电层。
12.如权利要求8所述的内埋式半导体封装件的制作方法,还包括:
提供基底条;
形成邻近该基底条的该第一图案化导电层;
形成凹穴于该基底条内;以及
配置该半导体元件的至少一部分于该凹穴内。
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CN102214626A (zh) | 2011-10-12 |
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