KR910005446A - 반도체소자 제조방법 - Google Patents

반도체소자 제조방법 Download PDF

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Publication number
KR910005446A
KR910005446A KR1019890011609A KR890011609A KR910005446A KR 910005446 A KR910005446 A KR 910005446A KR 1019890011609 A KR1019890011609 A KR 1019890011609A KR 890011609 A KR890011609 A KR 890011609A KR 910005446 A KR910005446 A KR 910005446A
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South Korea
Prior art keywords
layer
ions
semiconductor device
mos
grown
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KR1019890011609A
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English (en)
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KR940010107B1 (ko
Inventor
정상기
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

반도체소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 따른 반도체소자의 개략단면도.

Claims (1)

  1. P형규소기판(11)상부에 N+매입층(12)을 형성한 후, 마스킹을 이용하여 P+이온을 주입하며, 이어서 N-에피텍셜층(13)을 성장시킨 다음 트렌치마스크를 정의함과 아울러, 측벽산화막을 형성하여 그 측벽산화막사이에 폴리(14)를 형성한 다음 필드산화막(15)을 성장시키고, 이후 엔모스가 형성될 부위와 엔피엔형바이폴라가 형성될 부위에 피웰(16)을 형성하고 나서 선택식각된 새로운 산화물층(17)을 통해 P+이온 및 N+이온 주입을 행하고 이어서 마스킹 및 에칭된 Sio2의 산화물층을 통하여 폴리게이트(18)를 성장시킨 다음 BPS층(19)을 증착시킴과 아울러 금속전극창을 열고 엔피엔 및 피엔피형 바이폴라, 엔모스 및 피모스의 각 단자를 인출하는 과정으로 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940011609A 1988-05-17 1989-04-28 액티브 매트릭스 패널 KR940010107B1 (ko)

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JP88-119919 1988-05-17
JP11991988A JP2653099B2 (ja) 1988-05-17 1988-05-17 アクティブマトリクスパネル，投写型表示装置及びビューファインダー

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KR910005446A true KR910005446A (ko) 1991-03-30
KR940010107B1 KR940010107B1 (ko) 1994-10-21

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US5811837A (en) 1998-09-22
US6486497B2 (en) 2002-11-26
DE68928806D1 (de) 1998-10-08
JPH11237643A (ja) 1999-08-31
SG63566A1 (en) 1999-03-30
US5591990A (en) 1997-01-07
US5648685A (en) 1997-07-15
US5677212A (en) 1997-10-14
EP0342925B1 (en) 1994-12-28
EP1227469A3 (en) 2002-11-13
US5341012B1 (en) 1997-02-04
US20030010990A1 (en) 2003-01-16
DE68928806T2 (de) 1999-02-04
US5904511A (en) 1999-05-18
EP0610969A3 (en) 1994-08-24
US5341012A (en) 1994-08-23
HK1014586A1 (en) 1999-09-30
HK101897A (en) 1997-08-15
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US5754158A (en) 1998-05-19
US5616936A (en) 1997-04-01
DE68929189T2 (de) 2000-12-14
US5780872A (en) 1998-07-14
EP0610969B1 (en) 1998-09-02
SG81859A1 (en) 2001-07-24
DE68929091T2 (de) 2000-02-03
DE68920200T2 (de) 1995-05-11
JPH01289917A (ja) 1989-11-21
US5656826A (en) 1997-08-12
US20020053673A1 (en) 2002-05-09
DE68920200D1 (de) 1995-02-09
US5583347A (en) 1996-12-10
US5714771A (en) 1998-02-03
KR890017560A (ko) 1989-12-16
EP1227469A2 (en) 2002-07-31
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EP0609919A2 (en) 1994-08-10
EP0806702A1 (en) 1997-11-12
EP0342925A3 (en) 1990-09-05
JPH11237647A (ja) 1999-08-31
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DE68929091D1 (de) 1999-11-25
KR940010107B1 (ko) 1994-10-21
US5250931A (en) 1993-10-05
HK1014585A1 (en) 1999-09-30
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US6700135B2 (en) 2004-03-02
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