JP6771616B2 - 集積回路素子内でキャパシタをデジタル処理で同調するときに用いられる方法及び装置 - Google Patents
集積回路素子内でキャパシタをデジタル処理で同調するときに用いられる方法及び装置 Download PDFInfo
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Description
本願明細書を通じて、示される好適な実施形態及び例は、例として考えられるべきであり、本発明を限定すると考えられるべきではない。
ここで、CmimはDTC500’により生成されうる最小キャパシタンスを有し、CmaxはDTC500’により生成されうる最大キャパシタンスを有し、「bits」は制御ワード内のビット数を表し、同調比率(本願明細書では「同調範囲」とも称される)はDTCが調整されうるキャパシタンスの範囲を有し、QminはDTC500’の最小許容Qファクタを有する。電子機器設計分野の当業者は、実際にはMIMキャパシタの「理想的でない」Q値が上述の式4で考慮される必要がありうることを理解するだろう。しかしながら、式4は「理想的な」式を有するので、この理想的でないQファクタはここでは考慮されない。
以下に示す式5bは、RF+端子がグランドに結合されている間にRF−端子を駆動しているときの、オン状態のQON、f、CMIM、RMIM、n、RG及びRONの数学的な関係を示す。この場合には、RGが事実上にCMIMに並列なので、Q値は劣化する。従って、RF+端子の代わりに、RF−端子がグランドに結合されることが望ましい。
電子工学設計分野の当業者により理解されるように、上述の式(つまり、式5a及び5b)は、システム仕様又は基準により要求される(例えば、WCDMA(登録商標)のような無線通信基準により要求される)所与のQファクタを満たすようにDTCを設計させる。所与のQファクタ(つまり、所与のQON値)及び所与の最大動作周波数(つまり、所与のfMAX)では、DTC設計者は、式5a及び5bに従ってユニット・セルのCMIM、RMIM、n、RG及びRON値を決定してもよい。
以下に示す式6bは、RF+端子がグランドに結合されている間にRF−端子を駆動しているときの、オフ状態のQOFF、f(周波数)、CMIM、RMIM、n、RG、RDS、COFF、及びRCOFFの数学的な関係を示す。
電子工学設計分野の当業者により理解されるように、上述の式(つまり、式6)は、仕様により要求される(例えば、WCDMA(登録商標)のような無線通信基準により要求される)所与のQファクタを満たすようにDTCを設計させる。所与のQファクタ(つまり、所与のQOFF値)及び所与の最小動作周波数(つまり、所与のfMIM)では、DTC設計者は、ユニット・セルのCMIM、RMIM、COFF、RCOFF、n、RDS及びRG値を選択してもよい。標準的に、RDSはRG/nに等しく設定される。ここで、nはスタック高さ(つまり、スタック内のFETの数)を有する。しかしながら、電子工学設計分野の当業者は、本開示の範囲又は精神から逸脱することなく、他の値がゲート抵抗器及びドレイン−ソース抵抗器のために選択されうることを理解するだろう。
ここで、neffは実効スタック高さを有し、nはスタック内のFETの数を有し、CMIMはMIMキャパシタ799のキャパシタンス値を有し、COFFはFET795のようなFETスタック797の単一のFETのオフ・キャパシタンスを有する。上述のように、図7Jに示された例である値が与えられるとき、実効スタック高さは8.8であるが、実際のスタック高さは6である。
表1
図8Aは、表1に示された設計特性に従い作成された1GHzのDTC800の例の概略図である。図8Aに示されるように、全ての有効ビットのサブ回路は2値で重み付けされる。上述のように、MIMキャパシタとスタックFETの両者は、LSBからMSBまで2値で重み付けされる。DTCは、上述のユニット・セル設計手法に従い設計される。図8Aは、各有効ビットのサブ回路(本願明細書では回路要素とも表される)の総オン抵抗値(RON)及びオフ・キャパシタンス(COFF)を示す。例えば、LSB有効ビットのサブ回路は、8.18オームのオン抵抗値(RON)及び0.0733pFのオフ・キャパシタンス(COFF)を有する。次の有効ビットのサブ回路は、4.09オームのオン抵抗値(RON)及び0.147pFのオフ・キャパシタンス(COFF)を有する。DTC800は、0.2pFの「キャパシタンス・ステップ」(Cstep)を生じる5ビットの制御ワードを用いる。キャパシタンス・ステップは、選択されたキャパシタンス・レベル(選択された制御ワード値)から次の有効ビットのキャパシタンス・レベル((例えば、制御ワードを「00000」から「00001」に変更することにより)最下位ビットにより増大された選択された制御ワード値)へ変更することにより達成されたDTCの総キャパシタンスの差分を有する。DTCの調整範囲又は同調比率(本願明細書では「Cmax/Cmim」として定められる)は、約4.41である(つまり、DTCは、制御ワードが00000のとき約1.81pHの総キャパシタンスを達成し、制御ワードが11111のとき約8.0pHの総キャパシタンスを達成する)。図8Aに示されるように、スタックされたFETは、6個のスタックされたFETを有する(つまり、n=6)。TINは0.4に等しい。ここで、TINは例である本実施形態で用いられるFETの「特色」を有する。示された実施形態では、この特定の例では、0.4μmのゲート長を有する厚い酸化物のINトランジスタが用いられる。しかしながら、当業者は、本発明の教示の精神及び範囲から逸脱することなく、FETの他の「特色」が用いられうることを理解するだろう。DTCのRONCOFF=600fF−Ωである。DTCの切り替え時間は、RG×CONに等しい。ここで、図8AのDTC800は2.9μsに等しい。
上述のデジタル同調キャパシタ(DTC)の方法及び装置は、有利なことに、広範な回路正方及びDTCの大きさの特性を最大限に利用するよう又は満足するよう設計されてよい。これらの設計特性及び「トレードオフ」を用い、DTCはシステム・プロバイダにより課される仕様及び要件を満たすようカスタマイズされ最適化されうる。
例えば、図11は、選択された最小Qファクタ値(Qmin)における、DTCの調整範囲対適用信号の周波数のグラフ1100を示す。図11に2つの曲線が示される。第1の曲線1102は、調整範囲が変化するときの最小Qファクタ50を有する第1のDTCの調整範囲を適用信号の周波数の関数として示す。第2の曲線1104は、調整範囲が変化するときの最小Qファクタ100を有する第2のDTCの調整範囲を適用信号の周波数の関数として示す。式1−6を参照して上述したように、最小Qファクタ値(Qmin)及び調整範囲(Cmax/Cmin)は、動作原理及び本発明の教示のDTCの設計により互いに強く関連する。本発明のDTCの最小Qファクタは、DTCのオン抵抗値RON及びDTCのオフ・キャパシタンスCOFF(つまり、RONCOFF)に依存する。図11の曲線1102及び1104は、RONCOFF=600fF−Ωとして描かれている。
式7は、プロセスのRONCOFF及びQ要件に基づく調整範囲の限界を示す。式3は、COFFとCMIMとの間の比を所要の同調比率仕様に基づきどのように選択するかを教示する。調整範囲の「大雑把な」設計特性は、次の表2に示される。
図4A、5A−5B、6、8A、8F、9A及び9Fを参照して上述したように、動作原理及び本発明のDTCの教示の設計技術により、DTCにより占有されるダイ面積は増大し、DTCに関連する調整範囲はQファクタ値の増大と共に減少する。この設計のトレードオフは、図12のグラフ1200に図式的に示される。 図12は、調整範囲及びダイ面積要件対所与の適用信号周波数における選択されたDTCの最小Qファクタ値(Qmin)のグラフ1200を示す(図12のグラフ1200では、曲線1202及び1204は適用信号の周波数が900MHzを有すると仮定して描かれている)。図12を再び参照すると、曲線1202は、DTCのQファクタ要件が増大するにつれ、調整範囲がどのように減少するかを示す。曲線1204は、DTCのQファクタ要件が増大するにつれ、DTCのダイ面積要件がどのように増大するかを示す。図12の曲線1202及び1204は、以下を想定して描かれている。つまり、RONCOFF=600fF−Ω;適用信号の周波数は900MHzであり;キャパシタンス制御ワードは5ビットであり;FETスタックは6であり(つまり、n=6);Cmax=8.2pFである。
図4A、5A−5B、6、8A、8F、9A及び9Fを参照して上述したように、動作原理及び本発明のDTCの教示の設計技術により、DTCのダイ面積要件はDTCの最大キャパシタンス(Cmax)(つまり、DTCにより達成可能な最大キャパシタンス)に比例する。図13を参照すると、曲線1302は、最大DTCキャパシタンス(Cmax)が増大するにつれ、FETダイ面積要件(つまり、DTCのFETのダイ面積要件)がどのように増加するかを示す。曲線1302は、FETダイ面積と6個のシャントFETのスタック(これにより、約+35dBmのDTC電力処理能力を提供する)を有するDTCのCmaxとの間の関係を示す。曲線1304は、FETダイ面積と5個のシャントFETのスタック(これにより、約+33.4dBmのDTC電力処理能力を提供する)を有するDTCのCmaxとの間の関係を示す。予想通り、低い電力処理要件(及び少ない数のスタックされたFET)を有するDTCは、高い電力処理要件(従ってより多い数のスタックされたFET)を有するDTCよりも、少ないダイ面積を占有する。曲線1302、1304は次を想定している。つまり、900MHzにおいてQ=50;5ビットのキャパシタンス制御ワード;及びDTCは7:1の調整範囲を有する。FET(IN 0.4)の面積は、1Ωの単一のFETに対して80μm×80μmを有すると想定する。
DTCのCmaxの低減 ― 幾つかの設計トレードオフ及び設計条件は、DTCにより占有される集積回路ダイ面積を削減するために利用されうる。例えば、図13を参照して上述したように、動作原理及び本発明のDTCの教示の設計技術により、DTCのダイ面積要件はDTCの最大キャパシタンス(Cmax)(つまり、DTCにより達成可能な最大キャパシタンス)に比例する。従って、DTCの最大キャパシタンス(Cmax)が減少できれば、DTCにより必要とされるダイ面積も削減されうる。従って、DTCを最小の可能なダイ面積に最適化するために、最小の最大キャパシタンスCmaxを必要とするチューナのトポロジを用いることが有用である。例えば、結合された共振器又はチューナのトポロジは有意に良好である。例として、選択されたDTCの最大キャパシタンスCmaxの仕様が9.4pFから6.0pFに減少された場合、本発明の教示に従い作成された選択されたDTCにより必要とされるダイ面積は、36%=[(1)−(6/9.4)]だけ削減される。
上述のように、DTCにより必要とされるICダイ面積は、DTCの同調比率がシステム仕様により課される同調比率を超えている場合には削減されうる。この削減は、固定MIMキャパシタ(CADD)をDTCに並列に結合することにより達成されうる。図14A及び14Bは、所与の適用信号周波数における、調整範囲及びダイ面積要件に対する選択された変更されていないDTC(図14Aのグラフ1400)及び変更されたDTC(図14Bのグラフ1400’、ここで選択されたDTCは、固定MIMキャパシタCADDをDTCに並列に結合することにより変更される)の最小Qファクタのグラフを示す示された例では、グラフ1400、1400’の曲線は、適用信号周波数が900MHzを有すると想定して描かれている。グラフ1400は、図12を参照して上述された曲線1200と同一である。図14Aを参照すると、曲線1402は、DTCのQファクタ要件が増大するにつれ、調整範囲がどのように減少するかを示す。曲線1404は、DTCのQファクタ要件が増大するにつれ、DTCのダイ面積要件がどのように増大するかを示す。図12の曲線1402及び1404は、次の条件を想定して描かれている。RONCOFF=600fF−Ω;適用信号の周波数は900MHzであり;キャパシタンス制御ワードは5ビットであり;FETスタックは6であり(つまり、n=6);Cmax=8.2pFである。図14Aに示されるように、及び詳細には曲線1404により示されるように、Qファクタ値80、キャパシタンス範囲1.7乃至8.0pF、従って調整範囲(又は同調比率)4.7:1を有する所与の変更されていないDTCでは、所与の変更されていないDTCにより必要とされるダイ面積は0.82mm2に等しい。
ここで、CADDは変更されたDTC1501に並列に結合された固定キャパシタのキャパシタンスを有し;Cminは変更されていないDTC(つまり図15AのDTC1500)の最小総キャパシタンスを有し;Cmaxは変更されていないDTC1500の最大総キャパシタンスを有し;Qminは変更されていないDTC1500の最小許容可能Qファクタ値を有し、TRは再設計された変更されたDTC1500’の総同調比率(又は調整範囲)(つまり、結合されたDTC−CADD回路1500’の総調整範囲)を有し;Cmin,2は変更されたDTC1501の最小総キャパシタンスを有し;Cmax,2は変更されたDTC1501の最大総キャパシタンスを有し;Qmin,2は変更されたDTC1501の最小許容可能Qファクタ値を有する。留意すべき点は、変更されたDTC1500’全体の最小許容可能QファクタQMIN−total(つまり、結合されたDTC−CADD回路1500’のQMIN)は、次に示す式12に従い決定されることである。
上述の理想的な式(式8−11)を用いて、DTC回路設計者は、変更されたDTC1501を、低減されたQファクタ値(つまり、変更されたDTC1501の低減された最小Qファクタ値Qmin,2は式11に従い計算される)及び低減された最大総キャパシタンス(Cmax)(つまり、変更されたDTC1501の低減された最大総キャパシタンスは式10に従い計算される)を有するように直ちに設計しうる。式8は、CADDのキャパシタンス値を計算するために用いられる。変更されたDTC1501の最小総キャパシタンスは、式9に従い計算される。変更されたDTC回路1501のみの同調比率’(つまり、CADDから分離されたDTCの同調比率)は、変更されていないDTC1500の同調比率と比較して増大される。しかしながら、結合された回路DTC−CADD回路1500’の同調比率TRは、(変更されていないDTC1500のTRと比較して)低減された同調比率にされうる。例えば、図15A及び15Bに示されるように、DTCのTRは4.70:1から3:1へ低減される。結合された回路DTC−CADD回路1500’のTRの値は、本例では3:1にされる。
従って、結果として生じる(システム仕様により課される最小許容可能Qファクタ値に基づく)DTCの同調比率が仕様により要求されるものよりも高い場合には、変更されたDTC1501は、DTC1501に並列に結合された固定MIMキャパシタ(CADD)を用いて設計されうる。変更されたDTC1500’全体(つまり、結合されたDTC1501とCADDキャパシタの回路)は、必要なシステム仕様を満たすが、有利なことに占有するICダイ面積が少ない。以上に記載され図15A及び15Bに示された例では、CADD=1.45pF、Cmin,2=1.13pF、Cmax,2=6.3pF、及びQmin,2=65.0である。DTCを実施するために必要なダイ面積は、0.82mm2から0.55mm2に(又は約33%だけ)削減される。本発明の教示の特徴は、DTCを設計仕様及びシステム規格により課される要件を効率的に満たすよう調整させる。設計トレードオフ及び上述の検討を利用することにより、貴重なダイ面積の節約が達成されるが、依然として本発明のDTCはシステム仕様及び規格により課される要件を満たしている。
仕様に準拠した調整可能な構成要素の利用可能性は、多帯域・マルチモードの携帯電話機のためのRFアーキテクチャに重大な影響を与えるだろう。本発明のDTCの方法及び装置は、限定でなく適応型インピーダンス整合、アンテナ帯域お世bいインピーダンスの調整、電力増幅器(PA)の出力整合の調整、RFフィルタ及び送受切り替え器の調整、調整可能なフィルタ及び再構成可能なフィルタ、アンテナ及びPAを含む多くの異なる環境及び用途で用いられうる。仕様は厳しく、また高電力処理(+35dBm)、高線形性(IMD3−105dBm)、低損失(Q>50−100)、高信頼性、3:1−8:1の調整範囲、高速切り替え(5μS)、低価格、量産可能などの要件を満たすことは困難である。調整可能な構成要素の一般的な要件は、UltraCMOSで実施されたDTCを、上述のDTCを実施するための優れた技術の候補にする端末のアンテナ・スイッチのための要件に必要に類似する。この特定の実施は、高電力処理及び線形性についてスタック・トランジスタの独自の能力に強く依存し、高いQのキャパシタを集積することができる。UltraCMOSの手法は、単に既存の一体に集積された単一ダイの固体の調整可能キャパシタであるように見え、全ての仕様を満たし、UltraCMOSの端末のアンテナ・スイッチと全て同一の利点を有する。有利なことに、上述のDTCは、MEMSの代替及びBSTの実施である完全に集積された素子に、高信頼性及び低価格で量産されうる。実績のある大容量のUltraCMOSスイッチ技術は、DTCを実施するために用いられうる。このプロセス技術は、シリアル又はパラレル・バス、デジタル不整合センサ、本発明のDTCを支援するために用いられうる制御アルゴリズムを、幾つかの完全に集積されたソリューションの実施形態に一体に集積させる。有利なことに、DTCは、インピーダンス・チューナの用途、アンテナ調整、PA出力整合の調整、及び多くの他の有用な用途に使用可能である。
[関連出願の相互参照]
本出願は、発明の譲受人に譲渡された米国仮出願番号61/067634、2008年2月出願、発明の名称「Method and Apparatus for Digitally Tuning a Capacitor in an Integrated Circuit Device」の優先権の利益を主張する。上記米国仮出願は参照されることによりその全体が本願明細書に組み込まれる。
402、404、406、408 キャパシタ
402’、404’、406’、408’ FET
410 グランド端子
412 負荷端子
416 制御ロジック・ブロック
420、422、424 信号線
426 制御ワードCAPword
502 キャパシタ
503 サブ回路
504 FET
506、510 RF端子
602 サブ回路
604、620、622 キャパシタ
606、608、610、612、614、616 FET
618、680 RF端子
700 ユニット・セル
702 スタック
704 MIMキャパシタ
705 抵抗器
706、708、710、712、714、716 FET
718、780 RF端子
Claims (20)
- 少なくとも1つの集積回路チップを含むモジュールであって、
i)前記少なくとも1つの集積回路チップは、前記モジュールに組み込まれ、
第1のノードと、
第2のノードと、
1又は複数の容量性要素、及び前記第1のノードと前記第2のノードとの間に結合される2個以上のスイッチ、の直列構成と、
を有し、
ii)前記2個以上のスイッチは、1個のスイッチにより耐えられる電圧より高い電圧に耐えるよう構成され、
iii)前記2個以上のスイッチの各々は、抵抗性要素を介して制御信号に接続可能な制御ノードを有し、
iv)前記制御信号は、前記2個以上のスイッチをイネーブル又はディスエーブルし、それにより、前記第1のノードと前記第2のノードとの間のキャパシタンスを調整するよう構成される、
モジュール。 - 前記1又は複数の容量性要素のうちの容量性要素は、前記2個以上のスイッチのうちの一番上のスイッチを前記第1のノードに接続し、前記一番上のスイッチは、前記第1のノードに最も近いスイッチであり且つ前記第2のノードから最も遠いスイッチである、請求項1に記載のモジュール。
- 前記2個以上のスイッチは、FETスイッチである、請求項1に記載のモジュール。
- 前記1又は複数の容量性要素のうちの前記容量性要素は、前記2個以上のFETスイッチのうちの一番上のFETスイッチのドレイン又はソースを前記第1のノードに接続する、請求項3に記載のモジュール。
- 前記容量性要素は、1又は複数のキャパシタを有する、請求項2乃至4のいずれか一項に記載のモジュール。
- 前記1又は複数のキャパシタは、MIMキャパシタを有する、請求項5に記載のモジュール。
- 前記第2のノードはグランドに結合される、請求項2乃至6のいずれか一項に記載のモジュール。
- 少なくとも1つの集積回路チップを含む通信装置であって、
i)前記少なくとも1つの集積回路チップは、前記通信装置に組み込まれ、
第1のノードと、
第2のノードと、
1又は複数の容量性要素、及び前記第1のノードと前記第2のノードとの間に結合される2個以上のスイッチ、の直列構成と、
を更に有し、
ii)前記2個以上のスイッチは、1個のスイッチにより耐えられる電圧より高い電圧に耐えるよう構成され、
iii)前記2個以上のスイッチの各々は、抵抗性要素を介して制御信号に接続可能な制御ノードを有し、
iv)前記制御信号は、前記2個以上のスイッチをイネーブル又はディスエーブルし、それにより、前記第1のノードと前記第2のノードとの間のキャパシタンスを調整するよう構成される、
通信装置。 - 前記1又は複数の容量性要素のうちの容量性要素は、前記2個以上のスイッチのうちの一番上のスイッチを前記第1のノードに接続し、前記一番上のスイッチは、前記第1のノードに最も近いスイッチであり且つ前記第2のノードから最も遠いスイッチである、請求項8に記載の通信装置。
- 前記2個以上のスイッチは、FETスイッチである、請求項8に記載の通信装置。
- 前記1又は複数の容量性要素のうちの前記容量性要素は、前記2個以上のFETスイッチのうちの一番上のFETスイッチのドレイン又はソースを前記第1のノードに接続する、請求項10に記載の通信装置。
- 前記容量性要素は、1又は複数のキャパシタを有する、請求項9乃至11のいずれか一項に記載の通信装置。
- 前記1又は複数のキャパシタは、MIMキャパシタを有する、請求項12に記載の通信装置。
- RFフロントエンドであって、少なくとも1つの集積回路チップと他のRFフロントエンドコンポーネントとを含み、
i)前記少なくとも1つの集積回路チップ及び他のRFフロントエンドコンポーネントは、前記RFフロントエンドに組み込まれ、前記少なくとも1つの集積回路チップは、
第1のノードと、
第2のノードと、
1又は複数の容量性要素、及び前記第1のノードと前記第2のノードとの間に結合される2個以上のスイッチ、の直列構成と、
を更に有し、
ii)前記2個以上のスイッチは、1個のスイッチにより耐えられる電圧より高い電圧に耐えるよう構成され、
iii)前記2個以上のスイッチの各々は、抵抗性要素を介して制御信号に接続可能な制御ノードを有し、
iv)前記制御信号は、前記2個以上のスイッチをイネーブル又はディスエーブルし、それにより、前記第1のノードと前記第2のノードとの間のキャパシタンスを調整するよう構成される、
RFフロントエンド。 - 前記1又は複数の容量性要素のうちの容量性要素は、前記2個以上のスイッチのうちの一番上のスイッチを前記第1のノードに接続し、前記一番上のスイッチは、前記第1のノードに最も近いスイッチであり且つ前記第2のノードから最も遠いスイッチである、請求項14に記載のRFフロントエンド。
- 前記2個以上のスイッチは、FETスイッチである、請求項14に記載のRFフロントエンド。
- 前記1又は複数の容量性要素のうちの前記容量性要素は、前記2個以上のFETスイッチのうちの一番上のFETスイッチのドレイン又はソースを前記第1のノードに接続する、請求項16に記載のRFフロントエンド。
- 前記容量性要素は、1又は複数のキャパシタを有する、請求項15乃至17のいずれか一項に記載のRFフロントエンド。
- 前記1又は複数のキャパシタは、MIMキャパシタを有する、請求項18に記載のRFフロントエンド。
- 前記第2のノードはグランドに結合される、請求項15乃至19のいずれか一項に記載のRFフロントエンド。
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