JP2010123938A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2010123938A JP2010123938A JP2009243798A JP2009243798A JP2010123938A JP 2010123938 A JP2010123938 A JP 2010123938A JP 2009243798 A JP2009243798 A JP 2009243798A JP 2009243798 A JP2009243798 A JP 2009243798A JP 2010123938 A JP2010123938 A JP 2010123938A
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
【解決手段】同一基板上に画素部と、画素部を駆動する駆動回路とを有し、駆動回路の少なくとも一部の回路を、上下をゲート電極で挟んだ酸化物半導体を用いた薄膜トランジスタで構成する。同一基板上に画素部及び駆動回路を設けることによって製造コストを低減する。
【選択図】図1
Description
図1(A)に駆動回路に用いる第1の薄膜トランジスタ430と、画素部に用いる第2の薄膜トランジスタ170とを同一基板上に設ける例を示す。なお、図1(A)は表示装置の断面図の一例である。
実施の形態1では駆動回路の薄膜トランジスタとして一つの薄膜トランジスタを説明したが、ここでは、2つのnチャネル型の薄膜トランジスタを用いて駆動回路のインバータ回路を構成する例を基に以下に説明する。図2(A)に示す薄膜トランジスタは、実施の形態1の図1(A)に示した薄膜トランジスタ430と同一であるため、同じ部分には同じ符号を用いて説明する。
本実施の形態では、表示装置について、ブロック図等を参照して説明する。
本実施の形態では、実施の形態1に示した第2の薄膜トランジスタ170を含む表示装置の作製工程について、図9乃至図16を用いて説明する。
本実施の形態では、半導体装置として電子ペーパーの例を示す。
本実施の形態では、半導体装置として発光表示装置の例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
本実施の形態では、半導体装置の一形態に相当する液晶表示パネルの上面及び断面について、図21(A1)、図21(A2)、図21(B)を用いて説明する。図21(A1)、図21(A2)は、第1の基板4001上に形成された実施の形態1で示したIn−Ga−Zn−O系非単結晶膜を半導体層として含む薄膜トランジスタ4010、4011、及び液晶素子4013を、第2の基板4006との間にシール材4005によって封止した、パネルの上面図であり、図21(B)は、図21(A1)、図21(A2)のM−Nにおける断面図に相当する。
開示した発明に係る半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
ここでは、配線と酸化物半導体層とが接する構成の薄膜トランジスタを有する表示装置の例を図26に示す。なお、図26において、図1(A)と同一の箇所には同じ符号を用いて説明する。
101 ゲート電極
102 ゲート絶縁層
103 酸化物半導体層
104a、104b n+層
105a ソース電極層
105b ドレイン電極層
107 保護絶縁層
108 容量配線
109 酸化物半導体膜
110 画素電極
111 酸化物半導体膜
120 接続電極
121 端子
122 端子
125 コンタクトホール
126 コンタクトホール
127 コンタクトホール
128 透明導電膜
129 透明導電膜
131 レジストマスク
132 導電膜
150 端子
151 端子
152 ゲート絶縁層
153 接続電極
154 保護絶縁膜
155 透明導電膜
156 電極
170 第2の薄膜トランジスタ
400 基板
401 第1のゲート電極
402 ゲート電極
403 第1のゲート絶縁層
404 コンタクトホール
405 酸化物半導体層
407 酸化物半導体層
409 配線
410 配線
411 配線
412 第2のゲート絶縁層
430 薄膜トランジスタ
431 薄膜トランジスタ
432 薄膜トランジスタ
433 薄膜トランジスタ
470 第2のゲート電極
471 電極
472 第1の電極
473 絶縁層
474 第2の電極
475 発光層
476 電極
581 薄膜トランジスタ
585 絶縁層
587 電極層
588 電極層
589 球形粒子
594 キャビティ
595 充填材
Claims (11)
- 絶縁表面上に第1のゲート電極と、
前記第1のゲート電極上方に第1の絶縁層と、
前記第1の絶縁層上方に酸化物半導体層と、
前記酸化物半導体層上方にソース電極またはドレイン電極と、
前記ソース電極または前記ドレイン電極を覆う第2の絶縁層と、
前記第2の絶縁層上方に第2のゲート電極とを有し、
前記酸化物半導体層は、前記ソース電極または前記ドレイン電極と重なる領域よりも膜厚の薄い領域を有し、
前記第2の絶縁層は、前記酸化物半導体層の膜厚の薄い領域と接することを特徴とする半導体装置。 - 請求項1において、前記第1のゲート電極の幅は、前記第2のゲート電極の幅よりも広い半導体装置。
- 請求項1において、前記第1のゲート電極の幅は、前記第2のゲート電極の幅よりも狭い半導体装置。
- 請求項1において、前記第1のゲート電極の幅は、前記酸化物半導体層の膜厚の薄い領域の幅よりも広く、前記第2のゲート電極の幅は、前記酸化物半導体層の膜厚の薄い領域の幅よりも狭い半導体装置。
- 画素部と駆動回路とを有し、
前記画素部は、少なくとも第1の酸化物半導体層を有する第1の薄膜トランジスタを有し、
前記駆動回路は、少なくとも第2の酸化物半導体層を有する第2の薄膜トランジスタと、第3の酸化物半導体層を有する第3の薄膜トランジスタとを有するEDMOS回路を有し、
前記第3の薄膜トランジスタは、前記第3の酸化物半導体層の下方に第1のゲート電極と、前記第3の酸化物半導体層の上方に第2のゲート電極とを有し、
前記第3の酸化物半導体層は、ソース電極またはドレイン電極と重なる領域よりも膜厚の薄い領域を有する半導体装置。 - 請求項5において、前記第1の薄膜トランジスタは画素電極と電気的に接続され、前記画素電極は、前記第2のゲート電極と同じ材料である半導体装置。
- 請求項5において、前記第1の薄膜トランジスタは画素電極と電気的に接続され、前記画素電極は、前記第2のゲート電極と異なる材料である半導体装置。
- 請求項5乃至7のいずれか一において、前記第3の酸化物半導体層は、第1の絶縁層を介して前記第1のゲート電極と重なり、且つ、第2の絶縁層を介して前記第2のゲート電極と重なり、前記第2の絶縁層は、前記酸化物半導体層の膜厚の薄い領域と接する半導体装置。
- 請求項5乃至8のいずれか一において、前記第1の酸化物半導体層、前記第2の酸化物半導体層、及び前記第3の酸化物半導体層は、インジウム、ガリウム、亜鉛から選ばれる少なくとも一を含むことを特徴とする半導体装置。
- 請求項1乃至9のいずれか一において、前記第1のゲート電極と前記第2のゲート電極は同電位である半導体装置。
- 請求項1乃至9のいずれか一において、前記第1のゲート電極と前記第2のゲート電極は異なる電位である半導体装置。
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