JP6736430B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6736430B2 JP6736430B2 JP2016172579A JP2016172579A JP6736430B2 JP 6736430 B2 JP6736430 B2 JP 6736430B2 JP 2016172579 A JP2016172579 A JP 2016172579A JP 2016172579 A JP2016172579 A JP 2016172579A JP 6736430 B2 JP6736430 B2 JP 6736430B2
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- Prior art keywords
- oxide semiconductor
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- semiconductor layer
- gate electrode
- electrode
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Description
図1〜図8を用いて、本発明の実施形態1に係る半導体装置10の概要について説明する。実施形態1の半導体装置10は、液晶表示装置(Liquid Crystal Display Device:LCD)、表示部に有機EL素子または量子ドット等の自発光素子(Organic Light−Emitting Diode:OLED)を利用した自発光表示装置、もしくは電子ペーパー等の反射型表示装置において、各々の表示装置の各画素や駆動回路に用いられる。
図1は、本発明の一実施形態に係る半導体装置の概要を示す平面図である。図2は、本発明の一実施形態に係る半導体装置の概要を示す断面図である。図1および図2に示すように、半導体装置10は、トランジスタ素子100および容量素子200を有する。トランジスタ素子100および容量素子200はいずれも基板105上に配置された下地層110の上方に配置されている。
基板105としては、ポリイミド基板が用いられる。基板105として、ポリイミド基板の他にもアクリル基板、シロキサン基板、またはフッ素樹脂基板などの樹脂を含む絶縁基板が用いられてもよい。基板105の耐熱性を向上させるために、上記の基板に不純物が導入されてもよい。特に、半導体装置10がトップエミッション型のディスプレイである場合、基板105が透明である必要はないため、基板105の透明度が悪化する不純物が用いられてもよい。一方、基板105が可撓性を有する必要がない場合は、基板105としてガラス基板、石英基板、およびサファイア基板などの透光性を有する絶縁基板が用いられてもよい。半導体装置10が表示装置ではない集積回路の場合は、シリコン基板、炭化シリコン基板、化合物半導体基板などの半導体基板、またはステンレス基板などの導電性基板のように、透光性を有さない基板が用いられてもよい。
図3は、本発明の一実施形態に係る半導体装置において、酸化物半導体層の第1領域および第2領域を示す平面図である。図3を用いて、本発明の実施形態1に係る半導体装置10の容量素子200における第1領域222および第2領域224の形状について説明する。図3において、第2領域224は斜線で描かれた領域である。図3は、図1で描かれている第2電極266および開口部256が省略されて描かれている。図3に示すように、第2領域224は第1領域222を連続して囲んでいる。換言すると、第2領域224は第1領域222の周囲を1周途切れずに囲んでいる。さらに換言すると、第2領域224は、D1方向において、第1領域222に対してそれぞれ反対方向、およびD1方向に直交するD2方向において、第1領域222に対してそれぞれ反対方向に設けられている。
図4〜図8を用いて、本発明の実施形態1に係る半導体装置10の製造方法について、断面図を参照しながら説明する。図4は、本発明の一実施形態に係る半導体装置の製造方法において、下地層を形成する工程を示す断面図である。図4に示すように、基板105上に下地層110を成膜する。
図9〜図12を用いて、本発明の実施形態2に係る半導体装置10Aの概要について説明する。なお、以下の実施形態で参照する図面において、実施形態1と同一部分または同様な機能を有する部分には同一の数字または同一の数字の後にアルファベットを追加した符号を付し、その繰り返しの説明は省略する。
図9は、本発明の一実施形態に係る半導体装置の概要を示す断面図である。図9に示す半導体装置10Aは図1に示す半導体装置10に類似しているが、半導体装置10Aは、ソース領域124Aおよびドレイン領域126Aの酸化物半導体層120Aが層間絶縁層150Aに接している点、ならびに第2領域224Aの酸化物半導体層220Aが層間絶縁層250Aに接している点において、半導体装置10とは相違する。半導体装置10Aにおいて、上記の酸化物半導体層120A、220Aが層間絶縁層150A、250Aと接することで、実施形態1で説明した不純物のドーピングとは異なる方法で酸化物半導体層120A、220Aを低抵抗化することができる。なお、本実施形態では、第2領域224Aの酸化物半導体層220Aに含まれる酸素欠損は、第1領域222の酸化物半導体層220に含まれる酸素欠損よりも多い。また、層間絶縁層150A、250AはSiNxを含む。
図10〜図12を用いて、本発明の実施形態2に係る半導体装置10Aの製造方法について、断面図を参照しながら説明する。図10は、本発明の一実施形態に係る半導体装置の製造方法において、酸化物半導体層、ゲート絶縁層、およびゲート電極を形成する工程を示す断面図である。図4および図5と同じ製造方法で下地層110Aおよび酸化物半導体層120A、220Aを形成する。酸化物半導体層120A、220Aの上方にゲート絶縁層130A、230Aおよびゲート電極140A、240Aを含む導電層を成膜し、フォトリソグラフィおよびエッチングによって図10に示すようなゲート電極140A、240Aおよびゲート絶縁層130A、230Aのパターンを形成する。つまり、ゲート電極140A、240Aおよびゲート絶縁層130A、230Aを一括エッチングし、酸化物半導体層120A、220Aをゲート電極140A、240Aおよびゲート絶縁層130A、230Aから露出する。
図13〜図16を用いて、本発明の実施形態3に係る表示装置の概要について説明する。表示装置は、実施形態1の半導体装置10または実施形態2の半導体装置10Aで説明したトランジスタ素子および容量素子を用いた画素回路である。なお、本実施形態に係る表示装置として示す画素回路はEL表示装置の画素回路である。ただし、上記の容量素子はEL表示装置の画素回路に限定されず、一対の電極に供給される電位の大小関係が反転しない回路に用いることができる。
図13は、本発明の一実施形態に係る半導体装置における容量素子を使用する回路構成の一例を示す図である。図13に示すサブ画素300Bを構成するトランジスタは全てnチャネル型トランジスタである。図13に示すように、サブ画素300Bは、発光素子DO、駆動トランジスタDRT、出力トランジスタBCT、リセットトランジスタRST、画素選択トランジスタSST、保持容量Cs、および補助容量Cadを含む。補助容量Cadに半導体装置10または10Aで説明した容量素子200または200Aが用いられる。駆動トランジスタDRT、出力トランジスタBCT、リセットトランジスタRST、および画素選択トランジスタSSTに半導体装置10または10Aで説明したトランジスタ素子100または100Aが用いられる。
図14は、本発明の一実施形態の変形例に係る半導体装置における容量素子を使用する回路構成の一例を示す図である。図14に示すサブ画素300Cは、図13のサブ画素300Bと類似しているが、駆動トランジスタDRTのゲート電極に初期化トランジスタISTを介して初期化電源線340Cが接続されている点において、サブ画素300Bとは相違する。初期化電源線340Cには初期化電位Viniが供給される。初期化トランジスタISTのゲート電極は、初期化制御信号線356Cに接続されている。初期化制御信号線356Cには初期化制御信号IGが供給される。
図15は、本発明の一実施形態の変形例に係る半導体装置における容量素子を使用する回路構成の一例を示す図である。図15に示すサブ画素300Dは、図13のサブ画素300Bと類似しているが、発光素子DOのアノード電極にリセットトランジスタRSTが接続されていない点、駆動トランジスタDRTと出力トランジスタBCTとの間にクロストークキャンセルトランジスタCCTが配置されている点、およびクロストークキャンセルトランジスタCCTと出力トランジスタBCTとの間にリセット電源線342Dが接続されている点において、サブ画素300Bとは相違する。クロストークキャンセルトランジスタCCTのゲート電極は、クロストークキャンセル制御信号線358Dに接続されている。クロストークキャンセル制御信号線358Dにはクロストークキャンセル制御信号CGが供給される。
図16は、本発明の一実施形態の変形例に係る半導体装置における容量素子を使用する回路構成の一例を示す図である。図16に示すサブ画素300Eは、図14のサブ画素300Cと類似しているが、発光素子DOのアノード電極にリセットトランジスタRSTが接続されていない点、駆動トランジスタDRTと出力トランジスタBCTとの間にクロストークキャンセルトランジスタCCTが配置されている点、およびクロストークキャンセルトランジスタCCTと出力トランジスタBCTとの間にリセット電源線342Eが接続されている点において、サブ画素300Cとは相違する。クロストークキャンセルトランジスタCCTのゲート電極は、クロストークキャンセル制御信号線358Eに接続されている。クロストークキャンセル制御信号線358Eにはクロストークキャンセル制御信号CGが供給される。
図17を用いて、本発明の実施形態4に係る半導体装置10Fの概要について説明する。半導体装置10Fでは、容量素子200Fにおける第1領域222Fおよび第2領域224Fの形状について説明する。
図17は、本発明の一実施形態に係る半導体装置において、酸化物半導体層の低抵抗領域を示す平面図である。図17において、第2領域224Fは斜線で描かれた領域である。図17は、図1で描かれている第2電極266および開口部256が省略されて描かれている。図17に示すように、第2領域224Fは第1領域222Fを連続して囲んでいる。さらに、第2領域224Fは、平面視において第1領域222Fの内側に突出した突出領域225Fを備えている。換言すると、第1領域222Fの一部にスリット(突出領域225Fに対応する領域)が設けられている。さらに換言すると、ゲート電極240Fは、平面視においてゲート電極240Fの内側に向かって延びる切り欠き領域(突出領域225Fに対応する領域)を備えている。なお、図17では、突出領域225FがD2方向に長手を有する形状である構成を例示したが、突出領域225FがD1方向に長手を有する構造であってもよい。
Claims (5)
- n型の酸化物半導体層と、
前記酸化物半導体層の上方に配置されたゲート電極と、
前記酸化物半導体層と前記ゲート電極との間のゲート絶縁層と、
前記酸化物半導体層に接続された第1端子と、
前記ゲート電極に接続された第2端子と、
前記酸化物半導体層、前記ゲート絶縁層、および前記ゲート電極を覆う絶縁層と、
を有し、
前記第2端子に印加される電位は、前記第1端子に印加される電位よりも高く、
前記酸化物半導体層は、
平面視において前記ゲート電極とオーバーラップする第1領域と、
平面視において前記ゲート電極から露出された第2領域と、
を備え、
前記第2領域の前記酸化物半導体層の抵抗は、前記第1領域の前記酸化物半導体層の抵抗よりも低く、
前記第2領域の前記酸化物半導体層に含まれる酸素欠損は、前記第1領域の前記酸化物半導体層に含まれる酸素欠損よりも多く、
前記第2領域の前記酸化物半導体層は、前記ゲート絶縁層から露出され、前記絶縁層と接する半導体装置。 - p型の酸化物半導体層と、
前記酸化物半導体層の上方に配置されたゲート電極と、
前記酸化物半導体層と前記ゲート電極との間のゲート絶縁層と、
前記酸化物半導体層に接続された第1端子と、
前記ゲート電極に接続された第2端子と、
前記酸化物半導体層、前記ゲート絶縁層、および前記ゲート電極を覆う絶縁層と、
を有し、
前記第2端子に印加される電位は、前記第1端子に印加される電位よりも低く、
前記酸化物半導体層は、
平面視において前記ゲート電極とオーバーラップする第1領域と、
平面視において前記ゲート電極から露出された第2領域と、
を備え、
前記第2領域の前記酸化物半導体層の抵抗は、前記第1領域の前記酸化物半導体層の抵抗よりも低く、
前記第2領域の前記酸化物半導体層に含まれる酸素欠損は、前記第1領域の前記酸化物半導体層に含まれる酸素欠損よりも多く、
前記第2領域の前記酸化物半導体層は、前記ゲート絶縁層から露出され、前記絶縁層と接する半導体装置。 - 前記絶縁層は窒化珪素を含む、請求項1又は2に記載の半導体装置。
- n型の酸化物半導体層と、
前記酸化物半導体層の上方に配置されたゲート電極と、
前記酸化物半導体層と前記ゲート電極との間のゲート絶縁層と、
前記酸化物半導体層に接続された第1端子と、
前記ゲート電極に接続された第2端子と、
を有し、
前記第2端子に印加される電位は、前記第1端子に印加される電位よりも高く、
前記酸化物半導体層は、
平面視において前記ゲート電極とオーバーラップする第1領域と、
平面視において前記ゲート電極から露出された第2領域と、
を備え、
前記第2領域の前記酸化物半導体層の抵抗は、前記第1領域の前記酸化物半導体層の抵抗よりも低く、
前記第2領域は、前記第1領域を連続して囲み、
前記第2領域は、平面視において前記第1領域の内側に突出した突出領域を備える半導体装置。 - p型の酸化物半導体層と、
前記酸化物半導体層の上方に配置されたゲート電極と、
前記酸化物半導体層と前記ゲート電極との間のゲート絶縁層と、
前記酸化物半導体層に接続された第1端子と、
前記ゲート電極に接続された第2端子と、
を有し、
前記第2端子に印加される電位は、前記第1端子に印加される電位よりも低く、
前記酸化物半導体層は、
平面視において前記ゲート電極とオーバーラップする第1領域と、
平面視において前記ゲート電極から露出された第2領域と、
を備え、
前記第2領域の前記酸化物半導体層の抵抗は、前記第1領域の前記酸化物半導体層の抵抗よりも低く、
前記第2領域は、前記第1領域を連続して囲み、
前記第2領域は、平面視において前記第1領域の内側に突出した突出領域を備える半導体装置。
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