TW201336038A - 具有導線搭接貫孔的堆疊封裝總成 - Google Patents

具有導線搭接貫孔的堆疊封裝總成 Download PDF

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Publication number
TW201336038A
TW201336038A TW101138311A TW101138311A TW201336038A TW 201336038 A TW201336038 A TW 201336038A TW 101138311 A TW101138311 A TW 101138311A TW 101138311 A TW101138311 A TW 101138311A TW 201336038 A TW201336038 A TW 201336038A
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Taiwan
Prior art keywords
wire
microelectronic
substrate
encapsulation layer
overlap
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TW101138311A
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English (en)
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TWI599016B (zh
Inventor
Ellis Chau
Reynaldo Co
Roseann Alatorre
Philip Damberg
Wei-Shun Wang
Se-Young Yang
zhi-jun Zhao
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Invensas Corp
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Publication of TW201336038A publication Critical patent/TW201336038A/zh
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Publication of TWI599016B publication Critical patent/TWI599016B/zh

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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Abstract

本發明揭示一種微電子封裝，其可包含導線搭接，該等導線搭接具有搭接至一基板上之各自導電元件之基部及與該等基部相對之端部。自該基板延伸之一介電囊封層覆蓋該等導線搭接之部分，使得該等導線搭接之該等覆蓋部分因該囊封層而彼此分離，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之部分界定。未囊封部分可佈置於若干位置處以呈具有一最小節距之一圖案，該最小節距大於相鄰導線搭接之基部之間之一第一最小節距。

Description

具有導線搭接貫孔的堆疊封裝總成
本發明係關於堆疊封裝總成，且更特定言之，本發明係關於具有導線搭接貫孔之堆疊封裝總成。
本申請案係美國專利申請案第13/404,408號、第13/404,458號及第13/405,108號之一接續案，該等申請案之全部在2012年2月24日被申請、名稱為「Package-On-Package Assembly with Wire Bond Vias」且主張2011年10月17日申請之美國臨時專利申請案第61/547,930號(該案之全文以引用方式併入本文中)之申請日之權利。
微電子裝置(諸如半導體晶片)通常需要至其他電子組件之諸多輸入及輸出連接。一半導體晶片或其他類似裝置之輸入及輸出接點大體上佈置成實質上覆蓋裝置之一表面之柵格狀圖案(通常被稱為一「區域陣列」)，或佈置成伸長列，該等列可平行及鄰近於裝置前表面之各邊緣延伸或沿前表面之中心線延伸。通常，裝置(諸如晶片)必須實體地安裝於一基板(諸如一印刷電路板)上，且裝置之接點必須電連接至該電路板之導電特徵。
半導體晶片通常在製造期間及在晶片於一外部基板(諸如一電路板或其他電路面板)上之安裝期間設置於促進晶片處置之封裝中。例如，諸多半導體晶片係設置於適合於表面安裝之封裝中。已針對各種應用而提出此一般類型之諸多封裝。最常見地，此等封裝包含一介電元件(通常被 稱為一「晶片載體」)，其中端子形成為該介電元件上之電鍍或蝕刻金屬結構。此等端子通常藉由沿該晶片載體本身延伸之特徵(諸如細小跡線)及延伸於晶片之接點與該等端子或跡線之間之精細引線或導線而連接至晶片本身之接點。在一表面安裝操作中，封裝被放置至一電路板上，使得封裝上之各端子與該電路板上之一對應接觸墊對準。焊料或其他搭接材料係設置於該等端子與該等接觸墊之間。可藉由加熱總成以便熔融或「回焊」焊料或否則活化搭接材料而將封裝永久地搭接在適當位置。
諸多封裝包含呈焊料球形式之焊料塊(直徑通常為約0.1毫米至約0.8毫米(5密耳至30密耳))，其等附接至封裝之端子。具有自其底面突出之一陣列之焊料球之一封裝通常被稱為一球柵格陣列或「BGA」封裝。被稱為平臺柵格陣列或「LGA」封裝之其他封裝藉由由焊料形成之薄層或平臺而牢固至基板。此類型之封裝可十分緊湊。通常被稱為「晶片級封裝」之某些封裝佔用電路板之一面積，該面積等於或僅略微大於併入至封裝中之裝置之面積。此係有利的，因為其減小總成之總尺寸且允許基板上之各種裝置之間使用較短互連，其繼而限制裝置之間之信號傳播時間因此促進總成之高速操作。
封裝半導體晶片通常被設置成「堆疊」配置，其中一封裝係例如設置於一電路板上且另一封裝係安裝於該第一封裝之頂部上。此等配置可容許諸多不同晶片安裝於一電路板上之一單一覆蓋區內且可藉由在封裝之間提供一較短互 連而進一步促進高速操作。通常，此互連距離僅略微大於晶片本身之厚度。對於待在一堆疊之晶片封裝內實現之互連，需要將用於機械及電連接之結構設置於各封裝(最上層封裝除外)之兩側上。此已例如藉由將接觸墊或接觸平臺設置於其上安裝晶片之基板之兩側上而完成，該等墊透過基板之導電貫孔或類似者而連接。焊料球或類似者已被用於橋接一較低基板之頂部上之接點至下一較高基板之底部上之接點之間之間隙。該等焊料球必須高於晶片之高度以連接該等接點。美國專利申請公開案第2010/0232129號(「'129公開案」)中提供堆疊晶片配置及互連結構之實例，該案之全文以引用方式併入本文中。
呈長形柱或銷形式之微接觸元件可用於將微電子封裝連接至電路板且用於微電子封裝中之其他連接。在一些例項中，已藉由蝕刻包含一或多個金屬層之一金屬結構以形成微接點而形成該等微接點。該蝕刻程序限制該等微接點之尺寸。習知蝕刻程序通常無法形成具有高度與最大寬度之一較大比率(本文中稱為「縱橫比」)之微接點。已難以或無法形成具有可觀高度及相鄰微接點之間之非常小節距或間隔之微接點陣列。再者，藉由習知蝕刻程序而形成之微接點之組態係受限制的。
儘管先前技術已具有上述全部優點，但仍可期望進一步改良微電子封裝之製造及測試。
一微電子封裝可包含導線搭接，其等具有搭接至一基板 上之各自導電元件之基部及與該等基部相對之端部。自該基板延伸之一介電囊封層覆蓋該等導線搭接之部分，使得該等導線搭接之覆蓋部分因該囊封層而彼此分離，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之部分界定。未囊封部分可佈置於若干位置處以呈具有一最小節距之一圖案，該最小節距大於相鄰導線搭接之基部之間之一第一最小節距。
本文中揭示各種封裝結構，其等併入充當自導電元件(例如一基板上之導電墊)向上延伸之垂直連接之導線搭接。此等導線搭接可用於製造堆疊封裝之電連接，其中一微電子封裝疊覆於一介電囊封層之一表面上。另外，本文中揭示用於製造一微電子封裝或一微電子總成之各種方法實施例。
根據本發明之一態樣之一微電子封裝可包含具有一第一區及一第二區之一基板，該基板具有一第一表面及該第一表面遠端處之一第二表面。一或多個微電子元件可疊覆於該第一區內之該第一表面上。導電元件可暴露於該基板之該第一表面及該第二表面之至少一者處，且該等導電元件可暴露於該第二區內。該等導電元件之部分或全部可與至少一微電子元件電連接。
導線搭接可界定邊緣表面且具有搭接至導電元件之各自者之基部。該等導線搭接之該等基部可包含沿導電元件延伸之該等邊緣表面之第一部分，且具有佈置成相對於該等第一部分成25°至90°之間之一角度之該等邊緣表面之各自 第二部分。該等導線搭接可具有位於該基板及該等基部遠端處之端部，例如位於與該等基部相對之位置處。
一介電囊封層可自第一或第二表面之至少一者延伸。該囊封層可覆蓋導線搭接之部分，使得導線搭接之覆蓋部分因該囊封層而彼此分離。該囊封層可疊覆於基板之第二區上且可疊覆於另一部分(諸如第一區)上。導線搭接之未囊封部分可由未被該囊封層覆蓋之導線搭接之部分界定。該等未囊封部分可包含端部。導電元件可佈置於若干位置處以呈具有複數個導電元件之各自相鄰導電元件之間之一第一最小節距之一圖案。該等未囊封部分可佈置於若干位置中以呈具有複數個導線搭接之相鄰導線搭接之各自端部之間之一第二最小節距之一圖案。在一實例中，該第二節距大於該第一節距。
在一實例中，邊緣表面之各自部分之所成角度可介於80°至90°之間。
在一實例中，導線搭接之至少一些未囊封部分之各者包含一球形部分。該球形部分可與此導線搭接之一圓柱形部分整合。在一實例中，各球形部分及各圓柱形部分可具有本質上由銅、銅合金或金組成之至少一核心。在一實例中，與球形部分整合之圓柱形部分突出超過囊封層之一表面。
在一實例中，導線搭接之至少若干者具有一原生金屬核心及一金屬防護層，該金屬防護層包含疊覆於該原生金屬上之與該原生金屬不同之一再生金屬。在一實例中，該原 生金屬可為銅且該金屬防護層可包含一層銀。
在一實例中，導電元件可為第一導電元件。微電子封裝可進一步包括與導線搭接之未囊封部分電連接之複數個第二導電元件，且該等第二導電元件可不接觸該第等一導電元件。在一實例中，可在形成囊封層之後藉由電鍍而形成與導線搭接之未囊封部分接觸之該等第二導電元件。
在一實例中，導線搭接之至少一者之一端部可自該導線搭接之基部沿平行於基板之第一表面之一方向位移等於以下之一者之至少一距離：導電元件之間之一最小節距；及100微米。導線搭接之一或多者可包含介於導線搭接之基部與導線搭接之未囊封部分之間之至少一彎曲部。該至少一導線搭接之該彎曲部可位於該導線搭接之基部及該導線搭接之未囊封部分之一遠端位置處。在一實例中，該彎曲部之一半徑可比該至少一導線搭接之一圓柱形部分之一直徑大12倍。在一實例中，該彎曲部之該半徑可比該至少一導線搭接之一圓柱形部分之一直徑小10倍。在一實例中，該至少一導線搭接之未囊封部分可沿相對於基板之第一表面成25°至90°內之一方向突出高於囊封層。
在一實例中，導電元件之部分或全部可經非阻焊界定。
在一實例中，球形搭接可接合及疊覆至導線搭接之基部之部分上。
在一實例中，至少一微電子元件可包含疊覆於第一區內之第一表面上之第一及第二微電子元件。導電元件之部分或全部可與該第一微電子元件連接，且導電元件之部分或 全部可與該第二微電子元件連接。該第一微電子元件及該第二微電子元件可在微電子封裝內彼此電連接。
根據本發明之一態樣，囊封層可具有一主表面及相對於該主表面傾斜之一對準表面。一導線搭接之至少一未囊封部分可定位於該主表面上，其中該對準表面接近於位於該未囊封部分之一鄰近位置處之該主表面。以此方式，該對準表面可經組態以引導佈置於該對準表面上方之一導電突出部朝向該導線搭接之該未囊封部分。在一實例中，該突出部可包含一搭接金屬(諸如附接至一電路元件之一焊料球)及其他可能組態。
在一實例中，囊封層可界定其之一角隅區，囊封層進一步包含定位於該角隅區內且定位成比主表面更遠離基板之至少一次表面。對準表面可延伸於次表面與主表面之間。在一實例中，主表面可為疊覆於基板之第一區上之一第一主表面。囊封層可進一步界定疊覆於第二區上且定位成比主表面更靠近基板之一第二主表面。對準表面可延伸於該等第一與第二主表面之間。
根據本發明之一態樣之一微電子總成可包含：一第一微電子封裝，其具有如先前所描述之一對準表面；及一第二微電子封裝，其具有一前表面及位於該前表面上之端子。複數個導電突出部將導線搭接之未囊封部分之至少若干者與該等端子之各自者連接。在此總成中，該等導電突出部之至少一者可定位成與該對準表面之一部分接觸。在一實例中，該等導電突出部包含焊料球。
如上所闡釋，在一微電子封裝之一變體中，球形搭接可設置於導電元件之至少若干者頂上，導線搭接之邊緣表面(其等界定導線搭接之基部)可形成及接合至導電元件頂上之此等球形搭接上。
根據本發明之一態樣，可提供包含如先前所闡釋之一第一微電子封裝之一微電子總成，該第一微電子封裝具有暴露於與第一表面相對之基板之一第二表面處之複數個端子，且該第一微電子封裝具有沿基板之第一與第二表面之間之一方向延伸之周邊邊緣。一第二微電子封裝可具有：一基板，其具有位於其上之接點；及一第二微電子元件，其與該等接點電連接。該第二微電子封裝可具有暴露於此基板之一表面處之端子，該等端子透過該等接點而與該第二微電子元件電連接。該第二微電子元件之該等端子可面向導線搭接之各自未囊封部分且與該等未囊封部分電連接。
一電路面板可具有一第一表面及暴露於該電路面板之該表面處之面板接點。第一微電子封裝可疊覆於該電路面板上且具有接合至該電路面板之該等面板接點之端子。一單塊底部填充材料可疊覆於第一微電子封裝之周邊邊緣之至少一者上且佈置於將第一微電子封裝之端子與電路面板之面板接點之間之接合點包圍之空間內。該底部填充材料可佈置於將第二微電子封裝與第一微電子封裝之端子之間之接合點包圍之空間內。
在根據一特定實例之一微電子封裝中，囊封層可界定： 一第一表面部分，其位於一區中之第一表面上方之一第一高度處，該區疊覆於基板之第一區上；及一第二表面部分，其位於一區中之第一表面上方之一第二高度處，該區疊覆於基板之第二區上。該第二高度可小於該第一高度。在一實例中，微電子元件可具有位於第一表面上方之一第三高度處之一前表面。該第二高度可小於該第三高度。
在根據一特定實例之一微電子封裝中，導線搭接可具有接合至第一導電元件之各自者之球形搭接基部，而非具有搭接(例如接合)至基板之導電元件之邊緣表面。導線搭接之端部表面可在比基部之一直徑小3倍之一距離處位於基板及基部之遠端處。各導線搭接可界定延伸於該導線搭接之基部與端部表面之間之一邊緣表面。在一實例中，球形搭接基部可包含：第一球形搭接，其等接合至各自導電元件；及第二球形搭接，其等經由自該等第一球形搭接之頂面延伸之位置而接合至該等第一球形搭接。導線搭接可延伸於該等端部表面與該等第二球形搭接之間。
在根據一特定實例之一微電子封裝中，兩個或兩個以上導線搭接可接合(例如搭接)至基板之複數個導電元件之一個別導電元件。在該微電子封裝之實例中，此等導線搭接可具有搭接至該個別導電元件之球形搭接或搭接至該個別導電元件之邊緣表面，或可由使用諸如本文中所描述技術之方法之一組合形成。
在根據一實例之一微電子封裝中，可形成包含一主表面及相對於該主表面成角度之一對準表面之囊封層。導線搭 接之至少一未囊封部分可暴露於該主表面處，且該對準表面可自該主表面延伸，例如，在接近於未囊封部分之一位置處與該主表面相交，使得該對準表面經組態以引導佈置於該對準表面上方之一導電突出部朝向導線搭接之未囊封部分。在一實例中，可形成囊封層以界定該囊封層之一角隅區且進一步包含定位於該角隅區內之至少一次表面。該次表面可定位於比該主表面更遠離基板之位置處。該對準表面可延伸於該次表面與該主表面之間。
在一實例中，囊封層之主表面可為疊覆於基板之第一區上之一第一主表面。可形成囊封層以便界定疊覆於第二區上且定位成比主表面更靠近基板之一第二主表面。對準表面可延伸於次表面與主表面之間。
根據本發明之一態樣之製造一微電子總成之一方法可包含使一第二微電子封裝與一第一微電子封裝對準，如本文中所描述。該第二微電子封裝可包含一基板，其界定具有接點(例如暴露於其上之接觸墊)之一第一表面。在一些情況中，該等接點可包含與其等接合之導電塊。該第二微電子封裝可藉由將該等導電塊之至少一者移動成與至少一導線搭接之對準表面與至少端部表面兩者接觸而與該第一微電子封裝對準。可執行該等導電塊之加熱或否則固化以形成電連接，例如該第二微電子封裝之接點與該等導線搭接之未囊封部分之間之接合點。
根據本發明之一態樣，用於製造一微電子總成之一方法可包含使一第二微電子封裝與具有諸如本文中所描述之一 結構之一第一微電子封裝對準，其中囊封層之一表面沿一橫向方向延伸超過該第二微電子封裝之對立表面之一邊緣。此方法可包含例如在將該第二微電子封裝定位於該第一微電子封裝之囊封層頂上之後或之前將一底部填充材料沈積至施配區上。接著，該底部填充材料可流入至界定於該第二微電子封裝之基板之囊封層與第一表面之間之一空間中。沈積於該施配區上之一定數量之該底部填充材料可流入至該等第一及第二微電子封裝之對立表面之間之空間中。
在一實例中，第二微電子封裝可包含四個邊緣表面，且施配區可由橫向地延伸超過全部四個邊緣表面以包圍第二微電子封裝之囊封層之一部分界定。
在一實例中，第二微電子封裝可包含四個邊緣表面，且施配區可由橫向地延伸超過該等邊緣表面之兩個相鄰者之囊封層之一部分界定。
在一實例中，第二微電子封裝可包含四個邊緣表面，且施配區可由橫向地延伸超過一單一邊緣表面之囊封層之一部分界定。
根據本發明之一態樣之製造一微電子總成之一方法可包含定位第一及第二微電子封裝，其中複數個導電塊例如介於各自封裝之端子(諸如該第一微電子封裝之端子，其等由導線搭接之未囊封部分界定或具有接觸未囊封部分之第二導電元件)之間。可圍繞該等第一及第二微電子封裝之邊緣表面組裝一柔性邊框。可例如藉由加熱、回焊或否則 固化導電塊以接合各自第一接觸墊與第二接觸墊而執行一接合步驟。
在根據一實例之製造一微電子封裝之一方法中，可自一搭接工具之一毛細管向外供給具有一預定長度之一金屬導線。該毛細管之一表面可在一成形單元之第一及第二表面上移動以將該金屬導線段塑形成具有沿順著該毛細管之一外壁之一方向向上突出之一第一部分。該搭接工具可用於將該金屬導線之一第二部分搭接至與暴露於一基板之一第一表面處之一導電元件接合之一球形搭接。該金屬導線之該第二部分可經定位以沿該導電元件延伸。在一實例中，該第一部分可定位成與該第二部分成25°至90°之間之一角度。
在根據一實例之製造一微電子總成之一方法中，可形成一單塊底部填充材料以包圍諸如上文所描述之一第一微電子封裝之暴露部分。可形成該單塊底部填充材料以便填充將該第一微電子封裝之端子與此封裝下方之一電路面板之間之接合點包圍之空間。形成該單塊底部填充材料之步驟亦可填充將佈置於該第一微電子封裝上方之一第二微電子封裝之端子之間之接合點包圍之空間，此等端子面向及接合至該第一微電子封裝之導線搭接之各自未囊封部分。
製造一微電子封裝之一方法可包含在一在製(in-process)單元上之一介電囊封層之一表面上形成一犧牲材料層。該在製單元可包含具有端部表面及基部(其等位於該等端部表面遠端處且定位於囊封層內)之導線搭接，各導線搭接 界定向遠處延伸於該基部與該端部表面之間之一邊緣表面。囊封層可覆蓋該等導線搭接之部分，使得該等導線搭接之未囊封部分由該端部表面及其邊緣表面之一部分(其未被囊封層覆蓋)界定。該犧牲材料層可覆蓋未被囊封層覆蓋之該等導線搭接之部分。可使該犧牲材料層之一部分及該等導線搭接之部分平坦化，使得未被囊封層覆蓋之該等導線搭接之該等部分達到一實質上相等之預定高度。該方法可包含自囊封層移除該犧牲材料層之一剩餘部分。
可使用具有導線搭接之一在製單元來執行根據一實例之製造一微電子封裝之一方法，該等導線搭接接合至該微電子封裝之一基板之導電元件及與該基板連接之一微電子元件之一表面上之若干位置處之導電元件。例如，該等導線搭接可連接至該微電子元件之一後表面。在形成覆蓋該等導線搭接之至少部分之一囊封層之後，該方法可包含同時移除該囊封層之一部分及該等導線搭接之部分，使得該等導線搭接被分段成接合至該基板之導電元件之連接貫孔及接合至該微電子元件之該表面之熱貫孔。該等連接貫孔與該等熱貫孔兩者可具有位於基部遠端處之端部表面，例如，該等基部在該移除步驟之後暴露於該囊封層之表面處。該移除步驟可進一步使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之端部表面之至少一部分界定。
根據本發明之一態樣之製造一微電子封裝之一方法可包含在一在製單元上形成複數個導線搭接，該在製單元包含 具有一第一表面及該第一表面遠端處之一第二表面之一基板。一微電子元件可安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處，該等導電元件之至少若干者係電連接至該微電子元件。該等導線搭接可具有接合至該等導電元件之基部及位於該等基部遠端處之端部表面。各導線搭接可界定延伸於該基部與該端部表面之間之一邊緣表面。在一實例中，至少兩個導線搭接可形成於該等導電元件之一個別導電元件上。一介電囊封層可形成於該在製單元上，其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分。該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定。
根據本發明之一態樣之製造一微電子封裝之一方法可包含在一在製單元上形成一犧牲結構，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板。一微電子元件可安裝至該基板之該第一表面。複數個導電元件可暴露於該第一表面處，且該等導電元件之至少若干者可電連接至該微電子元件。該犧牲結構可於其內具有使該等導電元件之至少一者暴露之一開口。該犧牲結構可界定鄰近於該開口且位於該基板之該第一表面遠端處之一表面。該方法可包含：形成複數個導線搭接，該等導線搭接可具有接合至該等導電元件之基部及位於該等基部遠端處之端部表面，各導線搭接界定延伸於該基部與該端部表面之間之一邊緣表面；及在位於該等開口外部且鄰近於該犧 牲結構之該表面之位置處切斷該等導線搭接。其後，可移除該犧牲結構，且該方法可進一步包含在在製單元上形成一介電囊封層。可形成該囊封層以便至少部分覆蓋該第一表面及該等導線搭接之部分。一導線搭接之一未囊封部分可由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定。
根據本發明之一態樣之製造一微電子封裝之一方法可包含自一搭接工具之一毛細管向外供給具有一預定長度之一金屬導線段。該毛細管之表面可在一成形單元之第一及第二表面上移動以將該金屬導線段塑形成具有沿順著該毛細管之一外壁之一方向向上突出之一第一部分。該搭接工具可用於將該金屬導線之一第二部分搭接至暴露於一基板之一第一表面處之一導電元件。該金屬導線之該第二部分可經定位以沿該導電元件延伸，其中該第一部分定位成與該第二部分成25°至90°之間之一角度。可重複步驟(a)至步驟(c)以將複數個金屬導線搭接至該基板之複數個導電元件。可形成一介電囊封層以疊覆於該基板之該表面上。可形成該囊封層以便至少部分覆蓋該基板之該表面及該等導線搭接之部分。一導線搭接之一未囊封部分可由未被該囊封層覆蓋之該導線搭接之一端部表面或一邊緣表面之至少一者之一部分界定。
在一實例中，導線搭接之一第一者可經調適以承載一第一信號電位，且導線搭接之一第二者經調適以同時承載不同於該第一信號電位之一第二信號電位。
在一實例中，方法可包含安裝一微電子元件及使該微電子元件與基板電互連，方法使該微電子元件與導線搭接之至少若干者電互連。
在一實例中，基板可為一電路面板。在一實例中，基板可為一引線框，且方法可包含安裝一微電子元件及使該微電子元件與該引線框電互連，該微電子元件可與導線搭接之至少若干者電互連。
在一實例中，基板可為一第一微電子元件。方法可包含安裝一第二微電子元件及使該第二微電子元件與第一微電子元件電互連。方法可包含透過第一微電子元件而使該第二微電子元件與導線搭接之至少若干者電互連。
在一實例中，金屬導線段可為一第一金屬導線段。方法可包含在形成向上突出部分之後：(i)向外供給與該第一金屬導線段整合之一第二金屬導線段；及(ii)在成形單元之一第三表面上移動毛細管之表面以將該第二金屬導線段塑形成具有沿毛細管之外壁向上突出之一第二部分。在一實例中，該第二部分可藉由金屬導線之一第三部分而連接至第一向上突出部分。
在此實例中，可形成一初始囊封層，接著，可使該初始囊封層之至少一部分凹陷以形成囊封層且界定導線搭接之未囊封部分。在一實例中，該凹陷步驟包含雷射燒蝕該初始囊封層。在一實例中，該凹陷步驟包含濕性擦蝕該初始囊封層。
在一實例中，方法可包含用囊封劑與一模板之間之一暫 時薄膜模製囊封層。導線搭接可延伸至該暫時薄膜中。可移除該暫時薄膜以暴露導線搭接之未囊封部分。
在一實例中，方法可包含將暫時薄膜之一連續片材之一部分施加至模板。方法可接著在由模板至少部分界定之一空腔中形成囊封層。接著，可用暫時薄膜之該連續片材之另一部分替換暫時薄膜之當前部分。
在一實例中，在形成囊封層之後，方法可包含形成接觸導線搭接之未囊封部分之第二導電元件。
在一實例中，形成第二導電元件之步驟可包含將一導電材料沈積至導線搭接之未囊封部分上。
在一實例中，形成第二導電元件之步驟可包含將一金屬層電鍍至導線搭接之未囊封部分上。
在一實例中，形成第二導電元件之步驟可包含將導電膏沈積至導線搭接之未囊封部分上。
在一實例中，沈積導電材料之步驟可包含以下之至少一者：將導電材料施配、模板印刷、網版印刷或噴塗至導線搭接之未囊封部分上。
在一實例中，毛細管之一外壁可實質上垂直。可執行在成形單元之第二表面上移動毛細管之表面之步驟，使得金屬導線段之第一部分相對於第二部分成約80°至90°之間之角度。
在一實例中，兩個或兩個以上導線搭接可形成於導電元件之至少一者上。
在一實例中，毛細管可界定：一開口，透過該開口而供 給金屬導線段；及一前壁，其自該開口周圍延伸至由外壁界定之一邊緣。前表面可界定鄰近於該邊緣之一凸起部分。在步驟(b)期間，可在接近第一部分之一位置處將該凸起部分壓入至金屬導線中。
在一實例中，可形成包含一主表面及相對於該主表面傾斜之一對準表面之囊封層。導線搭接之至少一未囊封部分可定位於該主表面上，其中該對準表面在接近該未囊封部分之一位置處與該主表面相交。在此情況中，該對準表面可經組態以引導佈置於該對準表面上方之一導電突出部朝向導線搭接之該未囊封部分。
在一實例中，可形成囊封層以界定該囊封層之一角隅區且進一步包含定位於該角隅區內且定位成比主表面更遠離基板之至少一次表面，對準表面延伸於次表面與主表面之間。
在一實例中，囊封層之主表面可為疊覆於基板之第一區上之一第一主表面，進一步形成囊封層以界定疊覆於第二區上且定位成比主表面更靠近基板之一第二主表面。對準表面可延伸於次表面與主表面之間。
在一實例中，可形成一球形搭接以在將第二部分搭接至導電元件之後於金屬導線之第二部分上延伸。
根據本發明之一態樣之一方法可包含使一第二微電子封裝與根據本發明之一態樣而製造之一第一微電子封裝對準。該第二微電子封裝可包含界定一第一表面之一基板，其中接觸墊暴露於該第一表面上且導電塊與該等接觸墊接 合。該第二微電子封裝可藉由將焊料球之至少一者移動成與至少一導線搭接之對準表面與至少端部表面兩者接觸而與該第一微電子封裝對準。可加熱、回焊或否則固化該等導電塊以使該等導電塊與導線搭接之未囊封部分之各自者接合。
根據本發明之一態樣之一方法可包含將一第一微電子封裝定位於一第二微電子封裝上，該第一微電子封裝包含具有一第一表面(其具有暴露於其上之端子)之一基板，該等端子包含遠離該第一表面而突出之接合元件。
第二微電子封裝可包含具有一第一區及一第二區之一基板，該基板具有一第一表面及該第一表面遠端處之一第二表面。至少一微電子元件可疊覆於該第一區內之該第一表面上。導電元件可暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等導電元件之至少若干者係電連接至該至少一微電子元件。界定邊緣表面之導線搭接可具有接合至該等導電元件之各自者之基部。該等基部可包含沿該等導電元件延伸之該等邊緣表面之第一部分，其中該等邊緣表面之各自第二部分相對於該等第一部分成25°至90°之間之一角度。該等導線搭接可進一步具有位於該基板及該等基部遠端處之端部。一介電囊封層可自該等第一或第二表面之至少一者延伸且覆蓋該等導線搭接之部分，使得該等導線搭接之覆蓋部分因該囊封層而彼此分離，該囊封層至少疊覆於該基板之該第二區上。該等導線搭接之未囊封部分可由未被該囊封層覆蓋之該等導線搭 接之部分界定。未囊封部分可包含該等端部。可例如加熱、固化或回焊接合元件以與第二微電子封裝之未囊封導線搭接部分接合。
在一實例中，方法可進一步包含形成一底部填充材料之一步驟，該底部填充材料填充界定於第一微電子封裝及第二微電子封裝之對立表面之間之一空間且包圍第一微電子元件之端子與第二微電子封裝之未囊封導線搭接部分之間之導電突出部。
根據本發明之一態樣之一微電子封裝可包含具有一第一區及一第二區之一基板，該基板具有一第一表面及該第一表面遠端處之一第二表面。一微電子元件可疊覆於諸如該第一區內之該第一表面上。導電元件可暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處。該等導電元件之至少若干者可電連接至該至少一微電子元件。導線搭接界定邊緣表面且具有搭接至該等導電元件之各自者之基部。該等基部可包含沿該等導電元件延伸之該等邊緣表面之第一部分，其中該等邊緣表面之各自第二部分相對於該等第一部分成例如25°至90°之間之一角度。該等導線搭接可進一步具有位於該基板及該等基部遠端處之端部。一介電囊封層可自該等第一或第二表面之至少一者延伸且覆蓋該等導線搭接之部分。該等導線搭接之該等覆蓋部分可因該囊封層而彼此分離。該囊封層可疊覆於該基板之該第二區上且亦可疊覆於該基板之該第一區或另一區上。該等導線搭接之未囊封部分可由未被該囊封層覆蓋之 該等導線搭接之部分界定。該等未囊封部分可包含該等導線搭接之該等端，例如位於該等導電元件遠端處之該等導線搭接之該等端部。
在一實例中，導線搭接之一邊緣表面之一第一部分與一第二部分之間之角度可介於45°至90°之間。在一實例中，導線搭接之一第一者經調適(例如經組態)以承載一第一信號電位，且導線搭接之一第二者經調適(例如經組態)以同時承載不同於該第一信號電位之一第二信號電位。
各導線搭接可具有延伸於其之基部與端部之間之一邊緣表面。導線搭接之未囊封部分可由未被囊封層覆蓋之導線搭接之端部及鄰近於該等端部之邊緣表面之部分界定。
導線搭接之至少若干者之端部可包含漸縮尖端。在一實例中，該等漸縮尖端可具有沿一徑向方向自導線搭接之圓柱形部分之軸偏移之質心。
在一實例中，未囊封部分可具有位於其上之搭接工具標記。
在一實例中，導線搭接之未囊封部分之至少若干者之各者包含一球形部分。各球形部分可與此導線搭接之一圓柱形部分整合。各球形部分及各圓柱形部分具有本質上由銅、銅合金或金組成之至少一核心。
在一實例中，球形部分可具有比與其整合之圓柱形部分之直徑更大之直徑。在此實例或其他實例中，可由囊封層完全覆蓋與球形部分整合之圓柱形部分。在一實例中，可由囊封層部分覆蓋球形部分。
在一實例中，一抗氧化層可接觸導線搭接之未囊封部分之至少若干者。
在一實例中，導線搭接之至少若干者具有一原生金屬核心及一金屬防護層，該金屬防護層包含疊覆於該原生金屬上之與該原生金屬不同之一再生金屬。在一實例中，該金屬防護層可包含鈀。
在一實例中，導線搭接之至少若干者可由一原生金屬形成，其中一層鎳疊覆於該原生金屬上且一層金或銀疊覆於該鎳層上。在一實例中，該原生金屬可為金或銅之一者。
在一實例中，導電元件可為第一導電元件，且微電子封裝進一步包括與導線搭接之未囊封部分電連接之複數個第二導電元件。可佈置該等第二導電元件，使得其等不接觸該等第一導電元件。
在一實例中，第二導電元件可包含本質上由一單一金屬組成之一單塊金屬層。在一實例中，該單一金屬可為鎳、金、銅、鈀或銀之一者。
在一實例中，第二導電元件可包含接觸導線搭接之未囊封部分之一導電膏。
在一實例中，導線搭接之至少一者之一端部自該導線搭接之基部沿平行於基板之第一表面之一方向位移等於以下之一者之至少一距離：複數個導電元件之相鄰導電元件之間之一最小節距；及100微米。
在一實例中，導線搭接之至少一者包含該導線搭接之基部與該導線搭接之未囊封部分之間之至少一彎曲部。
在一實例中，至少一導線搭接之彎曲部可位於該導線搭接之基部及該導線搭接之未囊封部分之遠端處。
在一實例中，至少一導線搭接之未囊封部分可疊覆於微電子元件之一主表面上。
在一實例中，導線搭接之基部可佈置於若干位置處以呈具有複數個導線搭接之各自相鄰基部之間之一第一最小節距之一第一圖案，且導線搭接之未囊封部分可佈置於若干位置處以呈具有複數個導線搭接之導線搭接之各自相鄰未囊封部分之間之一第二最小節距之一第二圖案，該第二最小節距大於該第一節距。
在一實例中，至少一微電子元件可包含疊覆於第一區內之第一表面上之第一及第二微電子元件，且其中導電元件之至少若干者與該第一微電子元件連接。在一實例中，至少一些導電元件可與該第二微電子元件連接。在一特定實例中，該第一微電子元件與該第二微電子元件在微電子封裝內彼此電連接。
在一實例中，第一導電元件之至少一者可具有與其接合之至少兩個導線搭接。
根據本發明之一態樣之一微電子總成可包含一第一微電子封裝。該第一微電子封裝可包含具有一第一區及一第二區之一基板，該基板具有一第一表面及該第一表面遠端處之一第二表面。至少一微電子元件可疊覆於該第一區內之該第一表面上。導電元件可暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處。該等導電元件之 至少若干者可電連接至該至少一微電子元件。界定邊緣表面之導線搭接可具有搭接至該等導電元件之各自者之基部。該等基部可包含沿該等導電元件延伸之該等邊緣表面之第一部分，且該等邊緣表面之各自第二部分沿相對於該等第一部分之一角度(例如介於25°至90°之間)延伸。該等導線搭接可具有位於該基板及該等基部遠端處之端部。一介電囊封層可自該等第一或第二表面之至少一者延伸且覆蓋該等導線搭接之部分，使得該等導線搭接之覆蓋部分因該囊封層而彼此分離。該囊封層可至少疊覆於該基板之該第二區上。該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之部分界定。該等囊封部分可包含該等端部。
本發明之此態樣可包含一第二微電子封裝，其包含一第二微電子元件及與該第二微電子元件電連接且暴露於該第二微電子封裝之一表面處之端子。複數個導電突出部可使導線搭接之未囊封部分之至少若干者與該第二微電子封裝之該等端子之各自者電連接。
在一實例中，第一微電子封裝之囊封層可具有一主表面及遠離該主表面而向上傾斜之一對準表面。導線搭接之至少一未囊封部分可定位於該主表面上，且該對準表面可延伸至與該主表面及導線搭接之該至少一未囊封部分接近之一位置。在此情況中，與導線搭接之該至少一未囊封部分連接之一導電突出部可接觸該對準表面。
在一實例中，一底部填充材料可佈置於界定於第一微電 子封裝及第二微電子封裝之對立表面之間及複數個導電突出部之各自相鄰導電突出部之間之一空間內。
現轉至圖式，其中類似元件符號用於指示類似特徵，圖1中展示根據本發明之一實施例之一微電子總成10。圖1之實施例為呈一封裝微電子元件形式之一微電子總成，諸如用在電腦或其他電子應用中之一半導體晶片總成。
圖1之微電子總成10包含具有一第一表面14及一第二表面16之一基板12。基板12通常呈實質上平坦之一介電元件形式。該介電元件可呈片狀且較薄。在特定實施例中，該介電元件可包含一或多層之有機介電材料或複合介電材料，諸如(但不限於)聚醯亞胺、聚四氟乙烯(「PTEE」)、環氧樹脂、環氧玻璃、FR-4、BT樹脂、熱塑性塑膠或熱固性塑膠材料。基板可為具有用於進一步與一電路面板(例如一電路板)電互連之端子之一封裝基板。替代地，基板可為一電路面板或電路板。在基板之一實例中，基板可為一雙列記憶體模組(「DIMM」)之一模組板。在又一變體中，基板可為一微電子元件，諸如可為或可包含具體實現複數個主動裝置(例如呈一積體電路或其他者形式)之一半導體晶片。
第一表面14與第二表面16較佳地實質上彼此平行且隔開達垂直於表面14、16之一距離以界定基板12之厚度。較佳地，在本申請案中，基板12之厚度在大體上可接受之一厚度範圍內。在一實施例中，第一表面14與第二表面16之間 之距離介於約25微米至500微米之間。為此論述之目的，第一表面14可描述為被定位於第二表面16之相對或遠端處。僅為繪示之目的，使此一描述以及本文中所使用元件之相對位置之任何其他描述(其意指此等元件之一垂直或水平位置)與圖式內之元件之位置對應，且該等描述不具限制性。
在一較佳實施例中，基板12被視為分成一第一區18及一第二區20。第一區18位於第二區20內且包含基板12之一中央部分並自該中央部分向外延伸。第二區20實質上包圍第一區18且自第一區18向外延伸至基板12之外邊緣。在此實施例中，基板本身沒有特定特色在實體上劃分這兩個區；然而，為本文中論述之目的，相對於其上所應用或其內所含之處理或特徵而區分該等區。
一微電子元件22可安裝至第一區18內之基板12之第一表面14。微電子元件22可為一半導體晶片或另一類似裝置。在圖1之實施例中，微電子元件22以所謂之一習知或「面向上」方式安裝至第一表面14。在此一實施例中，引線24可用於將微電子元件22電連接至暴露於第一表面14處之複數個導電元件28之若干者。引線24亦可接合至基板12內之跡線(圖中未展示)或其他導電特徵(其等接著連接至導電元件28)。
導電元件28包含暴露於基板12之第一表面14處之各自「接點」或接觸墊30。如本描述中所使用，當一導電元件被描述為「暴露於」具有介電結構之另一元件之表面處 時，其指示：該導電結構可用於與一理論點接觸，該理論點自該介電結構外部、沿垂直於該介電結構之表面之一方向移動朝向該介電結構之表面。因此，暴露於一介電結構之一表面處之一端子或其他導電結構：可自此表面突出；可與此表面齊平；或可相對於此表面凹陷且透過該介電質中之一孔或凹陷部而暴露。導電元件28可為平坦薄元件，其中接觸墊30係暴露於基板12之第一表面14處。在一實施例中，導電元件28可實質上呈圓形且可彼此互連或藉由跡線(圖中未展示)與微電子元件22互連。導電元件28可至少形成於基板12之第二區20內。另外，在某些實施例中，導電元件28亦可形成於第一區18內。此一配置在將微電子元件122(圖3)安裝至基板112(呈所謂之一「覆晶」組態)時尤其有用，其中微電子元件122上之接點可藉由定位於微電子元件122下方之焊料凸塊126或類似者而連接至第一區118內之導電元件128。在一實施例中，導電元件28由一固體金屬材料(諸如此一應用可接受之銅、金、鎳或其他材料，其包含各種合金(其包含銅、金、鎳或以上各者之組合之一或多者))形成。
導電元件28之至少若干者可與暴露於基板12之第二表面16處之對應第二導電元件40(諸如導電墊)互連。可使用形成於基板12中之貫孔41來完成此一互連，貫孔41可用具有與導電元件28及40相同之材料之導電金屬作襯裡或填充。基板12上之跡線可視情況進一步使導電元件40互連。
微電子總成10進一步包含複數個導線搭接32，其等諸如 經由導電元件28之接觸墊30而接合至導電元件28之至少若干者。導線搭接32沿其邊緣表面37之一部分搭接至導電元件28。此搭接之實例包含縫合式搭接、楔形搭接及類似者。如下更詳細所描述，一導線搭接工具可用於將自該導線搭接工具之一毛細管延伸之一段導線縫合搭接至一導電元件28，同時自該毛細管之一導線供應端切斷該導線之縫合搭接端。導線搭接經由其各自「基部」34而縫合搭接至導電元件28。在下文中，此縫合搭接式導線搭接32之「基部」34意指與導電元件28形成一接合點之導線搭接之部分。替代地，可使用球形搭接來將導線搭接接合至導電元件之至少若干者，共同待審的共同讓與之美國專利申請案中展示及描述該等球形搭接之實例，該案之全文以引用方式併入本文中。
如本文中所描述，各種形式之邊緣搭接之併入可容許導電元件28成為非阻焊界定(「NSMD」)型導電元件。在使用導電元件之其他類型連接(例如焊料球或類似者)之封裝中，導電元件經阻焊界定。即，導電元件係暴露於一阻焊材料層中所形成之開口中。在此一配置中，該阻焊層可部分疊覆於導電元件上或可沿其一邊緣接觸導電元件。相比而言，一NSMD導電元件為不與一阻焊層接觸之導電元件。例如，導電元件可暴露於不具有一阻焊層之一基板之一表面上，或若存在一阻焊層，則該表面上之該阻焊層可具有一開口及與導電元件隔離之邊緣。亦可形成呈非圓形形狀之此等NSMD導電元件。阻焊界定墊通常可在意欲被 用於經由一焊料塊(其在此一表面上形成一大體上呈圓形之輪廓)而搭接至一元件時呈圓形。當例如使用待附接至一導電元件之一邊緣搭接時，搭接輪廓本身不呈圓形以可容許一非圓形導電元件。此等非圓形導電元件可例如呈橢圓形、矩形或具有含圓角之一矩形形狀。該等非圓形導電元件可經進一步組態以使待接納搭接之邊緣搭接之方向較長，同時使導線搭接32之寬度方向較短。此可容許基板12之水平面處之一更精細節距。在一實例中，導電元件28可在兩個方向上比基部34之所欲尺寸更大約10%至25%之間。此可容許基部34之定位精度變動及搭接程序之變動。
在一些實施例中，可呈一縫合搭接形式之一邊緣搭接式導線搭接(如上所描述)可與一球形搭接組合。如圖23A中所展示，一球形搭接1372可形成於一導電元件1328上，且一導線搭接1332可具有沿邊緣表面1337之一部分縫合搭接至球形搭接1372之一基部1334。在另一實例中，球形搭接之大體尺寸及佈局可如1372'處所展示。在圖23B所展示之另一變體中，可諸如藉由縫合搭接而沿導電元件1328邊緣搭接一導線搭接1332，如上所描述。接著，一球形搭接1373可形成於導線搭接1332之基部1334之頂部上。在一實例中，球形搭接之尺寸及佈局可如1373'處所展示。導線搭接32之各者可延伸至位於此導線搭接之基部34及基板12遠端處之一自由端36。導線搭接32之端部36以自由為特徵，此係因為其等無需電連接或否則接合至微電子總成10內之微電子元件22或任何其他導電特徵(其等接著連接至微電 子元件22)。換言之，自由端36可直接或間接地(諸如透過本文中所論述之一焊料球或其他特徵)電子連接至總成10外部之一導電特徵。端部36藉由例如囊封層42而固持在一預定位置中或否則接合或電連接至另一導電特徵之事實不意謂端部36不「自由」(如本文中所描述)，只要任何此類特徵不電連接至微電子元件22。相反地，基部34係不自由的，此係因為其直接或間接地電連接至微電子元件22，如本文中所描述。如圖1中所展示，導線搭接32之基部34通常在其等與各自導電元件28之縫合搭接(或其他邊緣搭接)接合點處彎曲。各導線搭接具有延伸於此導線搭接之基部34與此導線搭接之端部36之間之一邊緣表面37。基部34之特定尺寸及形狀可根據用於形成導線搭接32之材料類型、導線搭接32與導電元件28之間之連接之所要強度或用於形成導線搭接32之特定程序而變動。替代實施例係可行的，其中導線搭接32係另外或替代地接合至暴露於基板12之第二表面16上之導電元件40以自導電元件40向遠處延伸。
在圖40所展示之一替代配置中，基部2734可實質上呈圓形形狀以自界定於基部2734與端部2736之間之導線搭接2732之一邊緣表面2737向外延伸。基部2734之特定尺寸及形狀可根據用於形成導線搭接2732之材料類型、導線搭接2732與導電元件2728之間之連接之所要強度或用於形成導線搭接2732之特定程序而變動。Otremba之美國專利第7,391,121號及美國專利申請公開案第2005/0095835號(其描述可被視為一導線搭接形式之一楔形搭接程序)中描述 形成導線搭接2732之例示性方法，該兩個案之全文以引用方式併入本文中。替代實施例係可行的，其中導線搭接2732係另外或替代地接合至暴露於基板2712之第二表面2716上之導電元件2740以自導電元件2740向遠處延伸。發明者Reynaldo Co及Laura Mirkarimi之名稱為「METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE」之共同擁有的共同待審之美國申請案第13/405,125號中展示及描述球形搭接式導線搭接之實例，該案之全文以引用方式併入本文中。
在一特定實例中，導線搭接32之一第一者可經調適(即，經構造、經配置或電耦合至基板上之其他電路)以承載一第一信號電位，且導線搭接32之一第二者可經同樣調適以同時承載不同於該第一信號電位之一第二信號電位。因此，當給一微電子封裝(如圖1及圖2中所見)供能時，該等第一及第二導線搭接可同時承載第一及第二不同信號電位。
導線搭接32可由一導電材料(諸如銅、銅合金或金)製成。另外，導線搭接32可由材料之組合製成，諸如由一導電材料(諸如銅或鋁)之一核心製成，例如，其中一塗層施加於該核心上。該塗層可具有一第二導電材料，諸如鋁、鎳或類似者。替代地，該塗層可具有一絕緣材料，諸如一絕緣護套。
在特定實施例中，導線搭接可具有一原生金屬核心及一 金屬防護層，該金屬防護層包含疊覆於該原生金屬上之與該原生金屬不同之一再生金屬。例如，導線搭接可具有銅、銅合金或金之一原生金屬核心且該金屬防護層可包含鈀。鈀可避免一核心金屬(諸如銅)之氧化，且可充當一擴散障壁以避免導線搭接之未囊封部分39與如下進一步所描述之另一組件之間之焊料接合點中擴散一焊接可溶金屬(諸如金)。因此，在一實施例中，導線搭接可由可透過導線搭接工具之毛細管而供給之塗覆鈀之銅導線或塗覆鈀之金導線形成。
在一實施例中，用於形成導線搭接32之導線可具有約15微米至150微米之間之一厚度，即，沿與導線之長度成橫向之一維度。一般而言，使用此項技術中已知之專用設備來形成一導電元件(諸如導電元件28)、一接觸墊、跡線或類似者上之一導線搭接。導線搭接32之自由端36具有一端部表面38。端部表面38可形成由複數個導線搭接32之各自端部表面38形成之一陣列中之一接點之至少一部分。圖2展示由端部表面38形成之此一陣列之接點之一例示性圖案。可形成呈一區域陣列組態之此一陣列，可使用本文中所描述之結構來實施該組態之變動。此一陣列可用於將微電子總成10電及機械地連接至另一微電子結構，諸如連接至一印刷電路板(「PCB」)或其他封裝微電子元件(圖6中展示其等之一實例)。在此一堆疊配置中，導線搭接32及導電元件28與40可承載通過其等之多個電子信號，該等電子信號各具有一不同信號電位以容許一單一堆疊中之不同 微電子元件處理不同信號。焊料塊52可用於將此一堆疊中之微電子總成互連(諸如藉由將端部表面38電及機械地附接至導電元件40)。
微電子總成10進一步包含由一介電材料形成之一囊封層42。在圖1之實施例中，囊封層42係形成於未以其他方式被微電子元件22覆蓋或佔用之基板12之第一表面14之部分上，或形成於導電元件28上。類似地，囊封層42係形成於未以其他方式被導線搭接32覆蓋之導電元件28(其包含其之接觸墊30)之部分上。囊封層42亦可實質上覆蓋微電子元件22、導線搭接32(其包含基部34及其端部表面37之至少一部分)。導線搭接32之一部分可保持不被囊封層42覆蓋(該部分亦可被稱為未囊封部分39)以藉此使導線搭接可用於電連接至位於囊封層42外部之一特徵或元件。在一實施例中，導線搭接32之端部表面38保持不被囊封層42之主表面44內之囊封層42覆蓋。其他實施例係可行的，其中：除使端部表面38保持不被囊封層42覆蓋以外，邊緣表面37之一部分亦未被囊封層42覆蓋；或作為使端部表面38保持不被囊封層42覆蓋之一替代，邊緣表面37之一部分未被囊封層42覆蓋。換言之，除導線搭接32之一部分(諸如端部表面38、邊緣表面37或以上兩者之組合)以外，囊封層42可覆蓋第一表面14及其上方之微電子總成10之全部。在圖式所展示之實施例中，一表面(諸如囊封層42之主表面44)可與基板12之第一表面14隔開達足以覆蓋微電子元件22之一距離。相應地，使導線搭接32之端部38與表面44齊平之 微電子總成10之實施例將包含比微電子元件22更高之導線搭接32及用於覆晶連接之任何下伏焊料凸塊。然而，其他組態可用於囊封層42。例如，囊封層可具有含不同高度之多個表面。在此一組態中，其內定位端部38之表面44可比其下方定位微電子元件22之一向上對向表面更高或更低。
囊封層42用來保護微電子總成10內之其他元件，尤其是導線搭接32。此容許一更穩固結構，其不會因測試而損壞或不會在運輸或組裝至其他微電子結構期間受損。囊封層42可由具有絕緣性之一介電材料(諸如美國專利申請公開案第2010/0232129號中所描述之材料，該案以引用方式併入本文中)形成。
圖3展示微電子總成110之一實施例，其具有含端部136之導線搭接132，端部136未直接定位於導線搭接132之各自基部134上方。即，將基板112之第一表面114視為沿兩個橫向方向延伸以便實質上界定一平面，端部136或導線搭接132之至少一者自基部134之一對應橫向位置沿此等橫向方向之至少一方向位移。如圖3中所展示，導線搭接132可實質上筆直地沿其縱向軸(如同圖1之實施例)，其中該縱向軸相對於基板112之第一表面114成一角度146。雖然圖3之橫截面圖僅展示透過與第一表面114垂直之一第一平面之角度146，但導線搭接132亦可在與該第一平面與第一表面114兩者垂直之另一平面中相對於第一表面114成角度。此一角度可實質上等於或不同於角度146。即，端部136相對於基部134之位移可沿兩個橫向方向且位移量可為沿該 等方向之各者之相同或不同距離。
在一實施例中，導線搭接132之不同者可沿不同方向位移且位移量可為遍及總成110之不同數量。此一配置容許總成110具有一陣列，該陣列經組態以位於與基板12之水平面不同之表面144之水平面上。例如，一陣列可覆蓋一較小總面積或具有比基板112之第一表面114處之節距更小之表面144上之一節距。此外，一些導線搭接132可具有端部138，其等係定位於微電子元件122上方以接納具有不同尺寸之封裝微電子元件之一堆疊配置。在另一實例中，導線搭接132可經組態使得一導線搭接之端部實質上定位於一第二導線搭接之基部上方，其中該第二導線搭接之端部係定位於其他位置處。此一配置可被稱為相較於一對應接觸陣列在第二表面116上之位置而改變一接點端部表面136在一陣列之接點內之相對位置。在圖8所展示之另一實例中，導線搭接132可經組態使得一導線搭接132A之端部136A實質上定位於另一導線搭接132B之基部134B上方，該導線搭接132B之端部138B係定位於其他位置處。此一配置可被稱為相較於一對應接點陣列在第二表面116上之位置而改變一接點端部表面136在一陣列之接點內之相對位置。在此一陣列內，可根據微電子總成之應用或其他要求而視情況改變或變動接點端部表面之相對位置。圖4展示一微電子總成210之另一實施例，其具有含端部236之導線搭接232，端部236位於相對於基部234而橫向位移之位置中。在圖4之實施例中，導線搭接232藉由於其內包含一 彎曲部分248而實現此橫向位移。彎曲部分248可在導線搭接形成程序期間之一額外步驟中形成且可例如在導線部分被拉出達所要長度時出現。可使用可用導線搭接設備(其可包含使用一單一機器)來實施此步驟。
彎曲部分248可根據需要呈各種形狀以實現導線搭接232之端部236之所要位置。例如，彎曲部分248可形成為各種形狀之S形曲線(諸如圖4中所展示)或更平滑之S形曲線(諸如圖5A中所展示)。另外，彎曲部分248可定位成更靠近端部236而非基部234，或反之亦然。彎曲部分248亦可呈螺旋形或環形形式，或可為沿多個方向或具有不同形狀或特性之複合曲線。
在圖26所展示之另一實例中，導線搭接132可經配置使得基部134係配置成具有一節距之一第一圖案。導線搭接132可經組態使得包含端部表面138之其未囊封部分139可佈置於若干位置處以呈具有暴露於囊封層之表面144處之導線搭接132之相鄰未囊封部分139之間之一最小節距之一圖案，該最小節距大於複數個基部134之相鄰基部之間之最小節距且相應地大於與基部接合之導電元件128之間之最小節距。為此，導線搭接可包含沿相對於與導電元件正交之一方向之一或多個角度延伸之部分，諸如圖26中所展示。在另一實例中，導線搭接可經彎曲(如例如圖4中所展示)使得端部238自基部234沿一或多個橫向方向位移，如上所論述。如圖26中進一步所展示，導電元件128及端部138可配置於各自列或行中，且一些位置處(諸如一列之端 部中)之端部表面138自與端部表面138接合之基板上之各自導電元件之橫向位移可大於其他位置處之未囊封部分自與該等未囊封部分連接之各自導電元件之橫向位移。為此，導線搭接132可例如相對於基板112之表面116成不同角度146A、146B。
圖5A展示一微電子封裝310之另一例示性實施例，其具有呈各種形狀以導致基部334與端部336之間之各種相對橫向位移之導線搭接332之一組合。一些導線搭接332A實質上呈筆直狀，其中端部336A定位於其各自基部334A上方；而其他導線搭接332B包含導致端部336B與基部334B之間之一略微相對橫向位移之一細微彎曲部分348B。此外，一些導線搭接332C包含具有一彎曲形狀之彎曲部分348C，其等導致端部336C自相對基部334C之橫向位移距離大於端部336B自基部334B之橫向位移距離。圖5A亦展示一對例示性導線搭接332Ci與332Cii，其等具有定位於一基板級陣列之相同列中之基部334Ci與334Cii及定位於一對應表面級陣列之不同各列中之端部336Ci與336Cii。在一些情況中，導線搭接332Ci、332Cii中之彎曲部之半徑可較大，使得導線搭接中之曲線可似乎呈連續狀。在其他情況中，彎曲部之半徑可相對較小，且導線搭接可甚至具有介於導線搭接之彎曲部之間之筆直部分或相對筆直部分。再者，在一些情況中，導線搭接之未囊封部分可自其基部位移達基板之接點328之間之至少一最小節距。在其他情況中，導線搭接之未囊封部分可自其基部位移達至少200微 米。
圖中展示一導線搭接332D之另一變體，其經組態以使其之一側面347未被囊封層342覆蓋。在所展示實施例中，自由端336D未被覆蓋，然而，邊緣表面337D之一部分可另外或替代地不被囊封層342覆蓋。此一組態可用於使微電子總成310接地(藉由電連接至一適當特徵)或用於機械或電連接至橫向佈置至微電子總成310之其他特徵。另外，圖5A展示囊封層342之一區，其已經蝕除、經模製或否則經形成以界定定位成比主表面344更靠近基板312之一凹陷表面345。一或多個導線搭接(諸如導線搭接332A)可在沿凹陷表面345之一區內未被覆蓋。在圖5A所展示之例示性實施例中，端部表面338A及邊緣表面337A之一部分未被囊封層342覆蓋。此一組態可容許焊料沿邊緣表面337A吸芯(wick)且接合至端部表面338而提供諸如藉由一焊料球或類似者而至另一導電元件之一連接。可使一導線搭接之一部分未被沿凹陷表面345之囊封層342覆蓋之其他組態係可行的，其等包含以下組態：其中端部表面與凹陷表面345或相對於囊封層342之任何其他表面之本文中所展示之其他組態實質上齊平。類似地，使導線搭接332D之一部分未被沿側面347之囊封層342覆蓋之其他組態可類似於相對於囊封層之主表面之變體之本文中其他位置處所論述之組態。
圖5A進一步展示具有呈一例示性配置之兩個微電子元件322及350之一微電子總成310，其中微電子元件350係面向上地堆疊於微電子元件322上。在此配置中，引線324係用 於將微電子元件322電連接至基板312上之導電特徵。各種引線係用於將微電子元件350電連接至微電子總成310之各種其他特徵。例如，引線380將微電子元件350電連接至基板312之導電特徵，且引線382將微電子元件350電連接至微電子元件322。此外，可在結構上與導線搭接332之各者類似之導線搭接384係用於在與微電子元件350電連接之囊封層342之表面344上形成一接觸表面386。此可用於自囊封層342上方將另一微電子總成之一特徵直接電連接至微電子元件350。亦可包含連接至微電子元件322之此一引線，其包含在存在此一微電子元件且該微電子元件上未貼附一第二微電子元件350時連接至微電子元件322。一開口(圖中未展示)可形成於囊封層342中，該開口自囊封層342之表面344沿例如引線380而延伸至一點，藉此提供通路至引線380以使位於表面344外部之一元件電連接至引線380。一類似開口可形成於其他引線或導線搭接332之任何者上，諸如形成於遠離導線搭接332C之端部336C之一點處之導線搭接332C上。在此一實施例中，端部336C可定位於表面344下方，其中該開口僅提供用於電連接至端部336C之通路。
圖27A至圖27C中展示具有多個微電子元件之微電子封裝之額外配置。此等配置可與例如圖5A中所展示之導線搭接配置及以下進一步所論述之圖6之堆疊封裝配置一起使用。具體言之，圖27A展示一配置，其中一下微電子元件1622係覆晶搭接至基板1612之表面1614上之導電元件 1628。第二微電子元件1650可疊覆於第一微電子元件1622上且諸如透過導線搭接1688而面向上地連接至基板上之額外導電元件1628。圖27B展示一配置，其中一第一微電子元件1722係面向上地安裝於表面1714上且透過導線搭接1788而連接至導電元件1728。第二微電子元件1750可具有暴露於其之一表面處之接點，該等接點面向及接合至背向基板之第一微電子元件1722之一表面處之對應接點(透過第二微電子元件1750之一組接點1726，其等面向及接合至第一微電子元件1722之前表面上之對應接點)。與第二微電子元件之對應接點接合之第一微電子元件1722之此等接點可接著透過第一微電子元件1722之電路圖案而連接且藉由導線搭接1788而連接至基板1712上之導電元件1728。
圖27C展示一實例，其中第一及第二微電子元件1822、1850沿順著基板1812之一表面1814之一方向彼此分離。該等微電子元件(及額外微電子元件)之任一者或兩者可安裝於本文中所描述之面向上或覆晶組態中。此外，用在此一配置中之該等微電子元件之任何者可透過此等微電子元件之一或兩者上或基板上或以上兩者上之電路圖案而彼此連接，該等電路圖案電連接與該等微電子元件電連接之各自導電元件1828。
圖5B進一步繪示根據上述實施例之一變體之一結構，其中一第二導電元件43可形成為與暴露於囊封層42之一表面44處或在表面44上方突出之一導線搭接之一未囊封部分39接觸，第二導電元件不接觸第一導電元件28(圖1)。如圖 5B中所見，在一實施例中，第二導電元件可包含延伸至囊封層之一表面44上之一接觸墊45，其可提供用於與一組件之一搭接金屬或搭接材料接合之一表面給第二導電元件。
替代地，如圖5C中所見，第二導電元件48可為選擇性形成於一導線搭接之未囊封部分39上之一金屬防護層。無論何種情況，在一實例中，可諸如藉由電鍍而由以下各者形成第二導電元件43或48：一層鎳，其接觸導線搭接之未囊封部分且疊覆於導線搭接之一核心上；及一層金或銀，其疊覆於該鎳層上。在另一實例中，第二導電元件可為本質上由一單一金屬組成之一單塊金屬層。在一實例中，該單一金屬層可為鎳、金、銅、鈀或銀。在另一實例中，第二導電元件43或48可包含與導線搭接之未囊封部分39接觸之一導電膏或由該導電膏形成。例如，模板印刷、施配、網版印刷、受控噴塗(例如類似於噴墨印刷之一程序)或傳遞模製可用於形成導線搭接之未囊封部分39上之第二導電元件43或48。
圖5D進一步繪示可由一金屬或其他導電材料(如以上針對導電元件43、48所描述)形成之一第二導電元件43D，其中第二導電元件43D至少部分形成於延伸至囊封層42之一外表面44中之一開口49內。在一實例中，可藉由在固化或部分固化囊封層之後移除囊封層之一部分而形成開口49以便同時暴露開口49下方之導線搭接之一部分，該部分接著變為導線搭接之未囊封部分。例如，可藉由雷射燒蝕、蝕刻而形成開口49。在另一實例中，可在形成囊封層之前將 一可溶材料預置於開口之位置處，接著，可在形成囊封層之後移除該預置材料以形成開口。
如圖24A至圖24B中所見，在另一實例中，多個導線搭接1432可具有與一單一導電元件1428接合之基部。此一群組之導線搭接1432可用於使囊封層1442上之額外連接點與導電元件1428電連接。在例如約等於導電元件1428本身之尺寸之一區或近似等於一搭接塊之所欲尺寸之另一區中，共同接合之導線搭接1432之暴露部分1439可一起群組於囊封層1442之表面1444上以與導線搭接1432之群組形成一外部連接。如圖所展示，此等導線搭接1432可球形搭接(圖24A)或邊緣搭接(圖24B)於導電元件1428上(如上所描述)，或可搭接至導電元件(如以上參考圖23A或圖23B或圖23A與圖23B兩者所描述)。
如圖25A及圖25B中所展示，球形搭接式導線搭接1532可形成為導電元件1528之至少若干者上之接線柱凸塊。如本文中所描述，一接線柱凸塊為一球形搭接式導線搭接，其中延伸於基部1534與端部表面1538之間之導線段具有至多達球形搭接式基部1534之直徑之300%之一長度。如同其他實施例，端部表面1538可未被囊封層1542囊封且接線柱凸塊之邊緣表面1537之一部分可視情況未被囊封層1542囊封。如圖25B中所展示，此一接線柱凸塊1532A可形成於另一接線柱凸塊1532B之頂部上以本質上形成由兩個球形搭接構成之一導線搭接1532之一基部1534，其中一導線段自基部1534一直延伸至囊封層1542之表面1544。此等導 線搭接1532可具有比(例如)本發明中其他位置處所描述之導線搭接更小之一高度。相應地，囊封層可包含：一主表面1544，其位於例如疊覆於微電子元件1522上之一區中；及一次表面1545，其位於基板1512之表面1514上方之一間隔高度處，該間隔高度小於主表面1544之間隔高度。此等配置亦可用於形成對準特徵且減小一封裝(其採用本文中所揭示之接線柱凸塊類型導線搭接及其他類型導線搭接)之總高度，同時接納可使導線搭接1532之未囊封部分1539與另一微電子封裝1588上之接點1543連接之導電塊1552。
圖6展示微電子總成410與488之一堆疊封裝。在此一配置中，焊料塊452將總成410之端部表面438電及機械地連接至總成488之導電元件440。該堆疊封裝可包含額外總成且可最終附接至一PCB 490或類似者上之接點492以用在一電子裝置中。在此一堆疊配置中，導線搭接432及導電元件440可承載通過其等之多個電子信號，該等電子信號各具有一不同信號電位以容許一單一堆疊中之不同微電子元件(諸如微電子元件422或微電子元件489)處理不同信號。在圖6之例示性組態中，導線搭接432組態有一彎曲部分448，使得導線搭接432之端部436之至少若干者延伸至疊覆於微電子元件422之一主表面424上之一區中。此一區可由微電子元件422之外周邊界定且自該外周邊向上延伸。自面向圖6中之基板412之第一表面414之一視圖展示此一組態之一實例，其中導線搭接432疊覆於微電子元件422之一後主表面上，微電子元件422使其之一前表面425覆晶搭 接至基板412。在另一組態(圖5A)中，微電子元件322可面向上地安裝至基板312，其中前表面325背向基板312且至少一導線搭接332疊覆於微電子元件322之前表面上。在一實施例中，此導線搭接332未與微電子元件322電連接。搭接至基板312之一導線搭接332亦可疊覆於微電子元件350之前表面或後表面上。圖7中所展示之微電子總成410之實施例使得導電元件428係配置成形成一第一陣列之一圖案，其中導電元件428係配置成包圍微電子元件422之列及行且可具有個別導電元件428之間之一預定節距。導線搭接432係接合至導電元件428，使得導線搭接432之各自基部434沿著由導電元件428佈陣之該第一陣列之該圖案行進。然而，導線搭接432經組態使得導線搭接432之各自端部436可配置成根據一第二陣列組態之一不同圖案。在所展示實施例中，第二陣列之節距可不同於第一陣列之節距，且在一些情況中，第二陣列之節距小於第一陣列之節距。然而，其他實施例係可行的，其中第二陣列之節距大於第一陣列之節距，或其中導電元件428未定位成一預定陣列，但導線搭接432之端部436係定位成一預定陣列。此外，導電元件428可組態成定位於整個基板412內之數組陣列，且導線搭接432可經組態使得端部436呈不同陣列組或一單一陣列。
圖6進一步展示沿微電子元件422之一表面延伸之一絕緣層421。可在形成導線搭接之前由一介電質或其他電絕緣材料形成絕緣層421。絕緣層421可保護微電子元件免於與 在其上延伸之導線搭接432之任何者接觸。特定言之，絕緣層421可避免導線搭接之間之電短路及一導線搭接與微電子元件422之間之短路。以此方式，絕緣層421可有助於避免由一導線搭接432與微電子元件422之間之一非所欲電接觸引起之故障或可能損害。
在其中例如微電子總成488及微電子元件422之相對尺寸並非不允許之某些例項中，圖6及圖7中所展示之導線搭接組態可容許微電子總成410連接至另一微電子總成(諸如微電子總成488)。在圖6之實施例中，微電子總成488經定尺寸使得接觸墊440之若干者呈一區內之一陣列，該區小於微電子元件422之前表面424或後表面426之面積。在具有實質上垂直導電特徵(諸如取代導線搭接432之支柱)之一微電子總成中，無法實現導電元件428與接觸墊440之間之直接連接。然而，如圖6中所展示，具有經適當組態之彎曲部分448之導線搭接432可在適當位置中具有端部436以形成微電子總成410與微電子總成488之間之所需電子連接。此一配置可用於形成一堆疊封裝，其中微電子總成410例如為具有一預定接觸墊陣列之一DRAM晶片或類似者，且其中微電子元件422為經組態以控制該DRAM晶片之一邏輯晶片。此可容許一單一類型之DRAM晶片與具有不同尺寸之若干不同邏輯晶片一起使用，該等邏輯晶片包含大於該DRAM晶片之晶片，此係因為導線搭接432可具有定位於與該DRAM晶片形成所要連接之任何位置處之端部436。在一替代實施例中，微電子封裝410可安裝於印刷電 路板490上呈另一組態，其中導線搭接432之未囊封表面436係電連接至電路板490之接觸墊492。此外，在此一實施例中，另一微電子封裝(諸如封裝488之一修改版本)可藉由接合至接觸墊440之焊料球452而安裝於封裝410上。
圖9及圖10展示一微電子總成510之另一實施例，其中導線搭接532係形成於一引線框結構上。美國專利第7,176,506號及第6,765,287號中展示及描述引線框結構之實例，該等專利之全文以引用方式併入本文中。一般而言，一引線框為由一導電金屬(諸如銅)片形成之一結構，其係圖案化成包含複數個引線之區段且可進一步包含一腳座(paddle)及一框架。該框架係用於在總成之製造期間牢固該等引線及該腳座(若被使用)。在一實施例中，一微電子元件(諸如一晶粒或晶片)可面向上地接合至該腳座且電連接至該等引線(使用導線搭接)。替代地，該微電子元件可直接安裝至可在該微電子元件下方延伸之該等引線上。在此一實施例中，該微電子元件上之接點可藉由焊料球或類似者而電連接至各自引線。接著，該等引線可用於形成至各種其他導電結構之電連接以承載抵達及來自該微電子元件之一電子信號電位。當該結構之組裝(其可包含在該結構上形成一囊封層)完全時，可自該引線框之該等引線及腳座移除該框架之暫時元件以便形成個別引線。為本發明之目的，個別引線513及腳座515被視為共同形成一基板512之區段部分，基板512包含與其一體成型之部分中之導電元件528。此外，在此實施例中，腳座515被視為位於基 板512之第一區518內，且引線513被視為位於第二區520內。導線搭接524(亦如圖10之正視圖中所展示)將承載於腳座515上之微電子元件522連接至引線513之導電元件528。導線搭接532可使其基部534進一步接合至引線513上之額外導電元件528。囊封層542係形成至總成510上以使表面544內之若干位置處之導線搭接532之端部538不被覆蓋。導線搭接532可在與參考本文中其他實施例而描述之部分對應之結構中具有未被囊封層542覆蓋之導線搭接532之額外或替代部分。
圖11進一步繪示用於機械地加固一封裝610A之導線搭接632與安裝於封裝610A上之另一封裝610B之焊料塊652之間之接合點之一底部填充材料620之用法。如圖11中所展示，雖然底部填充材料620僅需佈置於封裝610A、610B之對立表面642、644之間，但底部填充材料620可接觸封裝610A之邊緣表面且可接觸其上安裝封裝610A之電路面板690之一第一表面692。此外，沿封裝610A、610B之邊緣表面延伸之底部填充材料620之部分可在存在之條件下佈置成相對於其上佈置該等封裝之電路面板之一主表面成0°至90°之間之一角度，且可自鄰近於電路面板之一較大厚度漸縮至電路面板上方之一高度處且鄰近於該等封裝之一或多者之一較小厚度。
可在用於形成一底部填充材料層(及尤其是佈置於封裝1910A及1910B之對立表面(諸如封裝1910A之表面1944與封裝1910B之表面1916)之間之該底部填充材料層之一部 分)之一技術中實施圖28A至圖28D中所展示之一封裝配置。如圖28A中所展示，封裝1910A可延伸超過封裝1910B之一邊緣表面1947，使得(例如)囊封層1942之表面1944具有暴露於封裝1910B外部之一部分。此一區可用作為一施配區1949，藉此一裝置可自相對於施配區1949之一垂直位置將呈一易流動狀態之一底部填充材料沈積於施配區上。在此一配置中，施配區1949可經定尺寸使得底部填充材料可成塊沈積於表面上且不會自表面之邊緣溢出，同時達到足以在封裝1910B下方流動之一容積，其中可藉由毛細管而將該底部填充材料汲取至封裝1910A及1910B之對立表面之間之區(其包含封裝1910A與1910B之間之任何接合點周圍，諸如焊料塊或類似者)中。當底部填充材料被汲取至對立表面之間時，額外材料可沈積於施配配區上，使得不會自封裝1910A之邊緣明顯溢出之一連續流被實現。如圖28B中所展示，施配區1949可包圍封裝1910B且在封裝1910B之各側上具有沿遠離封裝1910B之一周邊邊緣之一正交方向之約1毫米(1 mm)之一尺寸D。此一配置可容許施配於封裝1910B之一側上或依序或同時施配於封裝1910B之一個以上側上。圖28C中展示替代配置，其中施配區1949僅沿封裝1910B之兩個相鄰側延伸且具有沿遠離第二封裝之一周邊邊緣之一正交方向之約1毫米之一尺寸D'，且圖28D中展示替代配置，其中施配區1949沿封裝1910B之一單一側延伸且可具有沿遠離封裝之邊緣周邊之一正交方向之例如1.5毫米至2毫米之一尺寸D"。
在其中微電子封裝2010A與2010B具有沿一水平斷面之類似尺寸之一配置中，一柔性邊框2099可用於藉由例如將第二封裝之端子與包括導線搭接2032之未囊封部分2039之元件接合(例如通過加熱或固化導電塊2052，例如回焊焊料塊)而在附接期間將封裝2010A與2010B牢固在一起以將封裝2010A與2010B接合在一起。圖29中展示此一配置，其中封裝2010B經由例如與封裝2010B上之端子2043接合之導電塊2052(例如焊料塊)而組裝於封裝2010A上。該等封裝可經對準使得焊料塊2052與封裝2010A之導線搭接2032之未囊封部分2039對準或與與導線搭接2032之端部表面2038接合之第二導電元件對準，如上所描述。接著，邊框2099可圍繞封裝2010A及2010B而組裝以在使第二封裝之端子與第一封裝之導線搭接2032或第二導電元件接合之一加熱程序期間維持此對準。例如，一加熱程序可用於回焊焊料塊2052以搭接第二封裝之端子與導線搭接2032或第二導電元件。邊框2099亦可沿封裝2010B之表面2044之部分及封裝2010A之表面2016向內延伸以在回焊之前及回焊期間維持封裝之間之接觸。邊框2099可為一彈性柔軟材料(諸如橡膠、TPE、PTFE(聚四氟乙烯)、聚矽氧或類似者)且可使其尺寸小於組裝封裝之尺寸，使得適當位置中之一壓縮力藉由邊框而施加。邊框2099亦可在一底部填充材料之施加期間處於適當位置，且可包含一開口以適應穿過該開口之此一施加。可在封裝組裝之後移除柔性邊框2099。
另外或替代地，圖30A至圖30F中展示微電子封裝2110A 及2110B之總成，一下封裝2110A可包含至少一對準表面2151。圖30A中展示此之一實例，其中在封裝2110B之角隅附近對準表面2151被包含於囊封層2142中。對準表面相對於主表面而傾斜且在自主表面2144之某一位置處界定相對於主表面2144之約0°至高達90°(含90°)之間之一角度，對準表面之延伸位置接近主表面2144及各自次表面2145，在基板2112上方，次表面2145比主表面2144更遠離基板2112。次表面2145可佈置於封裝2110A之角隅鄰近處且可部分延伸於封裝2110A之相交側之間。如圖30B中所展示，對準表面亦可形成與封裝2110A之相交側相對之內部角隅且可被包含於沿封裝2110A之全部角隅(例如4個角隅)之類似形式中。如圖30C中所繪示，對準表面2151可定位成與對應導線搭接2132之未囊封部分相隔一適當距離之位置處，使得當具有突出部(例如導電突出部，諸如接合至第二封裝2110B之導電塊或焊料球)之一第二封裝2110B係堆疊於封裝2110A之頂部上時，對準表面2151將引導焊料球進入適當位置以疊覆於與對準表面2151對應之導線搭接2132之未囊封部分上。接著，焊料球可經回焊以與封裝2110A之導線搭接2132之未囊封部分接合。
圖31A至圖31C中展示採用對準表面2251之另一配置，其中對準表面2251延伸於一凸起內表面2244與一下部外表面2245之間。在此一配置中，內表面2244可疊覆於微電子元件2222上且可相應地在基板2212上方被間隔。外表面2245可沿基板2212之一厚度方向更靠近基板2212且可垂直 定位於基板2212之表面2214與微電子元件2222之表面2223之間。導線搭接2232之一或多個未囊封部分可相對於對準表面2251而定位以實現焊料球2252或其他導電突出部之對準，如參考圖30A至圖30C所描述。如上所描述，此一分階配置可與或可不與所描述之對準功能一起使用以實現一總體較低之總成高度(考量某一搭接塊尺寸)。此外，一凸起內表面2244之併入可導致封裝2210A之電阻增大至引起扭曲。
圖12係展示一第一組件610A之導線搭接632與一第二組件(諸如一微電子封裝610B)之對應焊料塊652之間之例示性接合點之一照片影像。在圖12中，元件符號620指示其中可佈置一底部填充材料。
圖13A、圖13B、圖13C、圖13D、圖13E及圖13F繪示導線搭接32(如以上參考圖1所描述)之結構之一些可能變體。例如，如圖13A中所見，一導線搭接732A可具有一向上延伸部分736，其終止於具有與部分736之半徑相同之半徑之一端部738A。
圖13B繪示一變體，其中端部738B為相對於部分736而漸縮之尖端。另外，如圖13C中所見，一導線搭接732B之一漸縮端738B可具有沿一徑向方向741自與其整合之導線搭接之一圓柱形部分之一軸偏移之一質心740。此形狀可為由形成導線搭接之一程序所致之一搭接工具標記，如下進一步所描述。替代地，一搭接工具標記(非如738B處所展示)可存在於導線搭接之未囊封部分上。如圖13A中進一 步所見，一導線搭接之未囊封部分739可沿相對於其上佈置導電元件728之基板之表面730成25°至90°內之一角度750突出遠離基板712。
圖13D繪示：一導線搭接732D之一未囊封部分可包含一球形部分738D。封裝上之全部導線搭接之若干者可具有此結構。如圖13D中所見，球形部分738D可與導線搭接732D之一圓柱形部分736整合，其中球形部分及導線搭接之圓柱形部分之至少一核心本質上由銅、銅合金或金組成。如下進一步所描述，可在將導線搭接縫合搭接至基板之一導電元件728之前藉由在一預塑形程序期間熔融暴露於搭接工具之毛細管之一開口處之導線之一部分而形成球形部分。如圖13D中所見，球形部分738D之直徑744可大於與其整合之圓柱形導線搭接部分736之直徑746。在諸如圖13D所展示之一特定實施例中，與球形部分738D整合之一導線搭接732D之圓柱形部分可突出超過封裝之囊封層751之一表面752。替代地，如圖13E中所見，一導線搭接732D之圓柱形部分可被囊封層完全覆蓋。在此情況中，如圖13E中所見，導線搭接732D之球形部分738D可在一些情況中被囊封層751部分覆蓋。
圖13F進一步繪示一導線搭接732F，其具有：一原生金屬核心731；及一金屬防護層733，其位於原生金屬核心731上，金屬防護層733包含疊覆於該原生金屬上之一再生金屬，諸如鍍鈀之銅導線或鍍鈀之金導線(如上所描述)。在另一實例中，一非金屬材料之一抗氧化層(諸如一市售 「有機保焊劑(OSP)」)可形成於一導線搭接之非囊封部分上以避免氧化囊封部分，直至該導線搭接之非囊封部分係接合至另一組件之一對應接點。
圖14繪示可使如本文中所描述之導線搭接32(圖1)經塑形且接著縫合搭接至一基板上之導電元件28之一方法。如該方法之階段A處所見，自一搭接工具之一毛細管804向外供給一金屬導線(諸如金或銅導線或複合導線，如以上參考圖1所描述)之一區段800，即，具有一預定長度802之一整合部分。為確保自毛細管向外供給一預定長度之金屬導線，初始導線長度可歸零或否則藉由搭接工具在開始向外供給用於處理之導線之前縫合搭接導線(其接著自毛細管延伸)而設定為一已知長度。此時，區段可沿與毛細管之一表面806垂直之一筆直方向801延伸。接著，如階段B處所見，沿例如平行於一成形單元810之一第一表面812之至少一第一方向814移動毛細管804之表面806以將金屬導線段800彎曲成遠離垂直方向。成形單元810可為一經特別設計之工具，其具有適合表面以有助於在將金屬導線段搭接至基板之導電元件之前形成(即，塑形)金屬導線段。
如階段B處所見，在預成形程序期間，區段800之一部分可接著沿平行於表面812之一方向延伸。其後，如階段C處所見，在一第二表面816上移動毛細管，其接著導致段800之至少一部分沿順著毛細管之一外壁820之一方向818上向上突出。在以此方式預先形成金屬導線段800之後，使搭接工具之毛細管移動遠離成形單元810且移動朝向基板之 導電元件28(圖1)，其中毛細管接著將鄰近於毛細管開口808及毛細管表面806之金屬導線段之一部分822縫合搭接至導電元件。因此，毛細管開口808遠端處之金屬導線段800之一端部838變為導電元件28遠端處之導線搭接之一端部38(圖1)。
圖15進一步繪示根據本發明之一實施例之一方法中之在一成形單元810之表面上移動毛細管之一實例。如該方法中所見，成形單元810可具有一第一凹陷部830，其中在成形程序之階段A處自毛細管之開口808向外供給區段800時佈置毛細管804。凹陷部可包含一通道或凹槽832，其可有助於在階段B處將區段800引導至一表面812上。成形單元可進一步包含用於在程序之階段B處引導區段800之一通道834或凹槽。如圖15中進一步所展示，成形單元可包含具有一內表面816之另一凹陷部840，毛細管在程序之階段C中抵著內表面816而移動以導致金屬導線段沿抵著毛細管之外壁820之一方向818彎曲。在一實例中，凹陷部840可呈三角形形狀，如圖15中所見。
在一實施例中，可使用圖14中所展示之毛細管之一變體，其併入一垂直或接近垂直之側壁2820。如圖35中所展示，毛細管2804之側壁2820可實質上垂直，換言之，平行於導線段2800或垂直於毛細管2804之表面2806。此可容許形成遠離基板之第一表面之表面之一導線搭接(圖1中之32)，該導線搭接比由毛細管(諸如圖14中所展示之毛細管)之外部處之一側壁實現之導線搭接更接近於垂直(即，更 接近90°角)，該側壁界定具有實質上小於90°之一量測值之一角度。例如，可使用一成形工具2810來實現佈置成與第一部分成之一角度之一導線搭接，該第一部分延伸於相對於第一導線部分2822之25°至90°之間、或約45°至90°之間或約80°至90°之間。
在另一變體中，一毛細管3804可包含突出超過其表面3806之一表面3808。可例如在側壁3820之邊緣上包含此表面3808。在用於形成一導線搭接(例如圖1中之32)之方法中，可在導線段之成形期間(例如，當毛細管沿順著一成形表面3816(其沿遠離表面3812之一方向延伸)之一方向移動時)使毛細管3804緊貼著導線段3800之第一部分3822。在此實例中，表面3808在彎曲部附近之一位置處壓入至第一部分3822中，剩餘導線段3800自該位置延伸。此可導致導線段3800變形，使得其可緊貼著毛細管3804之壁3820且在移除毛細管3804之後移動至一略微更垂直位置。在其他例項中，來自表面3808之變形可使得可在移除毛細管時實質上保持導線段3800之一部分。
圖16係一照片影像，其展示：根據本文中所描述之方法之一或多者而形成之導線搭接932可具有自其等各自基部934偏移之端部938。在一實例中，一導線搭接之一端部938可自其各自基部位移，使得端部938沿平行於基板之表面之一方向位移超過與端部938連接之導電元件之一周邊。在另一實例中，一導線搭接之一端部938可自其各自基部934位移，使得端部938沿平行於基板之表面之一方向 位移超過與端部938連接之導電元件之一周邊933。
圖17繪示可用於形成導線搭接332Cii(圖5A)之上述預成形程序之一變體，導線搭接332Cii具有一彎曲部且具有沿一橫向方向1014A自部分1022(其等將縫合搭接至導電元件作為導線搭接之基部1034)位移之端部1038。
如圖17中所見，程序之前三個階段A、B及C可與以上參考圖14而描述之階段相同。接著，參考程序中之階段D及E，由可與成形單元整合之一工具夾緊毛細管804之表面806鄰近處之導線搭接之一部分1022A。可因毛細管在成形單元上移動而主動或被動地執行該夾緊。在一實例中，可藉由將其上具有一防滑表面之一板按壓至金屬導線段800上以阻止導線金屬段移動而執行該夾緊。
當圖17所展示之階段D處以此方式夾緊金屬導線段800時，毛細管工具沿順著成形單元1010之一第三表面1018之一方向1016移動且向外供給與沿表面1018移動之距離相等之一定長度之導線。其後，在階段E處，沿成形單元之一第三表面1024向下移動毛細管以導致導線之一部分沿毛細管804之一外表面1020向上彎曲。以此方式，導線之一向上突出部分1026可藉由金屬導線之一第三部分1048而連接至另一向上突出部分1036。
如圖40中所展示，用於形成具有球形搭接式導線搭接2732之一微電子封裝2710之一方法包含各種步驟，如圖41至圖44中所繪示。圖41展示一步驟處之微電子總成2710'，其中微電子元件2722已電及機械地連接至第一區2718內之 基板2712之第一表面2714上。微電子元件2722在圖41中展示為藉由焊料塊2726安裝於基板2712上呈一覆晶配置。替代地，可代以使用面向上之搭接，如以上圖40中所見。在圖41所展示之方法步驟之實施例中，可在微電子元件2722與基板2712之間設置一介電底填層2766。
圖42展示微電子總成2710"，其具有施加於暴露於基板2712之第一表面2714上之導電元件2728之接觸墊2730上之導線搭接2732。如所論述，可藉由加熱一導線段之一端部以軟化該端部而施加導線搭接2732，使得導線搭接2732在被按壓至導電元件2728以形成基部2734時形成至導電元件2728之一沈積搭接。接著，遠離導電元件2728而拉出導線，且若期望，則在切割或否則切斷導線以形成導線搭接2732之端部2736及端部表面2738之前將導線處理成一特定形狀。替代地，可藉由楔形搭接而形成由例如一鋁導線製成之導線搭接2732。藉由加熱導線之端部鄰近處之導線之一部分且用施加至該部分之壓力沿導電元件2728拖拉該部分而形成楔形搭接。美國專利第7,391,121號中進一步描述此一程序，該專利之全文以引用方式併入本文中。
在圖43中，囊封層2742已藉由施加於基板之第一表面2714上而添加至微電子總成2710'''，囊封層2742自第一表面2714向上延伸且沿導線搭接2732之邊緣表面2737向上延伸。囊封層2742亦覆蓋底部填充層2766。可藉由將一樹脂沈積於圖42中所展示之微電子總成2710"上而形成囊封層2742。此可藉由將總成2710'放置於一經適當組態之模具中 而完成，該模具具有可接納總成2710'之呈囊封層2742之所要形狀之一空腔。可在美國專利申請公開案第2010/0232129號中展示及描述此一模具及用該模具形成一囊封層之方法，該案之全文以引用方式併入本文中。替代地，可由一至少部分柔性材料預先製成呈所要形狀之囊封層2742。在此組態中，介電材料之柔軟性容許囊封層2742被按壓至導線搭接2732及微電子元件2722上之適當位置中。在此一步驟中，導線搭接2732穿入至其內形成各自孔之柔性材料中，囊封層2742沿導線搭接2732接觸邊緣表面2737。此外，微電子元件2722可使柔性材料變形，使得柔性材料內可接納微電子元件2722。可壓縮柔性介電材料以暴露外表面2744上之端部表面2738。替代地，可自囊封層移除任何過度柔性介電材料以形成其上未覆蓋導線搭接2732之端部表面2738之一表面2744，或可在表面2763內之一位置處形成未覆蓋端部表面2738之空腔2764。
在圖43所展示之實施例中，形成囊封層，使得囊封層之表面2744最初位於導線搭接2732之端部表面2738上方。為暴露端部表面2738，可移除位於端部表面2738上方之囊封層2742之部分以暴露實質上與端部表面2738齊平之一新表面2744'，如圖44中所展示。替代地，可形成其中端部表面2738未被囊封層2742覆蓋之空腔(圖中未展示)。在另一替代例中，可形成囊封層2742，使得表面2744實質上已與端部表面2738齊平或使得表面2744係定位於端部表面2738下方。若需要，則可藉由磨削、乾式蝕刻、雷射蝕刻、濕式 蝕刻、研磨或類似者而實現囊封層2742之一部分之移除。若期望，則亦可在相同或額外步驟中移除導線搭接2732之端部2738之一部分以實現實質上與表面2744齊平之實質上平坦端部表面2738。若期望，則亦可在此一步驟之後形成空腔或亦可施加接線柱凸塊。接著，所得微電子總成2710可貼附於一PCB上或否則併入至另一總成(例如一堆疊封裝，如圖6中所展示)中。
在形成導線段且將其搭接至一導電元件以形成尤其是以上所論述球形搭接類型之一導線搭接之後，該導線搭接(例如圖1中之32)接著與毛細管(諸如圖32A中之804)內之導線之一剩餘部分分離。此可在導線搭接32之基部34之任何遠端位置處完成且較佳在與基部34相隔一距離以至少足以界定導線搭接32之所要高度之一位置處完成。可由佈置於毛細管804內或佈置於毛細管804外部之一機構(介於表面806與導線搭接32之基部34之間)實施此離開。在一方法中，可藉由在所要離開點處有效焊穿導線段800而分離導線段800，其可藉由施加一火花或火焰至導線段800而完成。為實現導線搭接高度之更大精度，可對導線段800實施不同形式之切割。如本文中所描述，切割可用於描述可在一所要位置處削弱導線之一部分切割，或完全切斷導線以將導線搭接32與剩餘導線段800完全分離。
在圖32所展示之一實例中，一切割刀片805可整合至諸如毛細管804內之搭接頭總成中。如圖所展示，毛細管804之側壁820中可包含一開口807，切割刀片805可延伸穿過 該開口。切割刀片805可自毛細管804之內部移入及移出，使得其可交替地容許導線800自由地穿過毛細管804或接合導線800。相應地，可拉出導線800，且形成導線搭接32並將其搭接至一導電元件28，其中切割刀片805位於毛細管內部外之一位置中。在搭接形成之後，可使用整合至搭接頭總成中之一夾具803來夾緊導線段800以牢固導線之位置。接著，切割刀片805可移入至導線段中以完全切割導線或部分切割或削弱導線。一完全切割可在可使毛細管804移動遠離導線搭接32以例如形成另一導線搭接之點處形成導線搭接32之端部表面38。類似地，若導線段800因切割刀片805而削弱，則搭接頭單元與仍由導線夾具803固持之導線之移動可導致由在部分切割之削弱區處折斷導線800引起之分離。
可由氣體或使用一偏心凸輪之一伺服馬達致動切割刀片805之移動。在其他實例中，可由一彈簧或一隔膜致動切割刀片805之移動。用於切割刀片805之致動之觸發信號可基於自球形搭接之形成起開始倒計之一時間延遲，或可藉由將毛細管804移動至導線搭接基部34上方之一預定高度而致動。此一信號可鏈結至其他軟體，該軟體操作搭接機器使得可在任何後續搭接形成之前重新設定切割刀片805之位置。切割機構亦可包含在與刀片805並列之一位置處之一第二刀片(圖中未展示)(其中導線介於該等刀片之間)，以便藉由第一及第二刀片之一或多者相對於第一及第二刀片之另一者之移動而諸如在一實例中自導線之相對 側切割導線。
在另一實例中，一雷射809可與搭接頭單元組裝且經定位以切割導線。如圖33中所展示，一雷射頭809可諸如藉由安裝至毛細管804或包含毛細管804之搭接頭單元上之另一點而定位於毛細管804之外部。可在一所要時間(諸如，以上參考圖32中之切割刀片805而論述之時間)致動雷射以切割導線800以在基部34上方之一所要高度處形成導線搭接32之端部表面38。在其他實施方案中，可定位雷射809以導引切割光束穿過或進入毛細管804本身，且可內置至搭接頭單元。在一實例中，可使用二氧化碳雷射，或作為一替代例，可已使用Nd：YAG或Cu水蒸氣雷射。
在另一實施例中，一模板單元824(如圖34A至圖34C中所展示)可用於使導線搭接32與剩餘導線段800分離。如圖34A中所展示，模板824可為一結構，其具有界定導線搭接32之所要高度處或該高度附近之一上表面826之一主體。模板824可經組態以接觸基板12之導電元件28或任何部分或導電元件28之間之與模板824連接之封裝結構。模板包含可與導線搭接32之所要位置(諸如位於導電元件28上)對應之複數個孔828。孔828可經定尺寸以於其內接受搭接頭單元之毛細管804，使得毛細管可在孔中延伸至相對於導電元件28之一位置以將導線800搭接至導電元件28以諸如藉由球形搭接或類似者而形成基部34。在一實例中，模板可具有透過其而暴露導電元件之個別者之孔。在另一實例中，模板之一單一孔可暴露複數個導電元件。例如，一孔 可為模板中之一通道形開口或凹口，一列或一行之導電元件透過該孔而暴露於模板之一頂面826處。
接著，毛細管804可自孔828向外垂直移動，同時拉出導線段達一所要長度。在自孔828取出之後，導線段可(諸如)藉由夾具803而被夾緊於搭接頭單元內，且毛細管804可沿一橫向方向(諸如平行於模板824之表面826)移動以將導線段800移動成與由孔828之表面與模板824之外表面826之相交點界定之模板824之一邊緣829接觸。此移動可導致導線搭接32與仍固持於毛細管804內之導線段800之一剩餘部分分離。可重複此程序以在所要位置中形成所要數目之導線搭接32。在一實施方案中，可在導線分離之前垂直移動毛細管，使得剩餘導線段突出超過毛細管804之表面806達足以形成一後續球形搭接之一距離802。圖34B展示模板824之一變體，其中孔828可經漸縮使得其等具有自表面826處之一第一直徑增大至表面826遠處之一更大直徑之一直徑。如圖34C中所展示，在另一變體中，可形成具有一外框架821之模板，外框架821具有足以使表面826與基板12隔開達所要距離之一厚度。框架821可至少部分包圍經組態以定位於基板12鄰近處之一空腔823，其中模板824之一厚度延伸於表面826與敞開區823之間，使得包含孔828之模板824之部分在定位於基板12上時與基板12隔開。
圖18、圖19及圖20繪示可在藉由模製而形成囊封層以使導線搭接之未囊封部分39(圖1)突出超過囊封層42之一表面44時使用之一技術。因此，如圖18中所見，可使用一薄膜 輔助模製技術，藉由該技術而將一暫時薄膜1102放置於一模具之一板1110與一空腔1112(其中可接合包含基板之一子總成、接合至該基板之導線搭接1132及諸如一微電子元件之一組件)之間。圖18進一步展示可佈置於第一板1110相對處之模具之一第二板1111。
接著，如圖19至圖20中所見，當模板1110、1111係接合在一起時，導線搭接1132之端部1138可突入至暫時薄膜1102中。當一模製化合物在空腔1112中流動以形成囊封層1142時，該模製化合物不接觸導線搭接之端部1138，此係因為端部1138已被暫時薄膜1102覆蓋。在此步驟之後，自囊封層1142移除模板1110、1111，此時可自模具表面1144移除暫時薄膜1102以接著使導線搭接1132之端部1138突出超過囊封層之表面1144。
薄膜輔助模製技術非常適用於大規模生產。例如，在程序之一實例中，可將暫時薄膜之一連續片材之一部分施加至模板。接著，可在由模板至少部分界定之一空腔1112中形成囊封層。接著，自動構件可用暫時薄膜之該連續片材之另一部分替換模板1110上之暫時薄膜1102之一當前部分。
在薄膜輔助模製技術之一變體中，並非使用如上所描述之一可移除薄膜，而是可在形成囊封層之前將一水溶性薄膜放置於模板1110之一內表面上。當移除模板時，可藉由洗去該水溶性薄膜而移除該水溶性薄膜以便使導線搭接之端部突出超過囊封層之表面1144，如上所描述。
在圖18及圖19之方法之一實例中，導線搭接1132在囊封層1142之表面1144上方之高度可變動於導線搭接1132之間，如圖37A中所展示。圖37B至圖37D中展示用於進一步處理封裝1110使得導線搭接1132突出高於表面1142達實質上均勻高度之一方法，且該方法利用一犧牲材料層1178，可形成犧牲材料層1178以藉由將犧牲材料層1178施加於表面1144上而覆蓋導線搭接1132之未囊封部分。接著，犧牲層1178可經平坦化以將導線搭接1132之高度降低至所要高度，其可藉由研磨、磨削或拋光或類似者而完成。亦如圖中所繪示，犧牲層1178之平坦化可藉由導線搭接1132之高度降低至使導線搭接1132變為暴露於犧牲層1178之表面處之一點而開始。接著，平坦化程序亦可與犧牲層1178同時地使導線搭接1132平坦化，使得導線搭接1132之高度隨犧牲層1178之高度連續降低而降低。可在導線搭接1132達到所要高度之後停止平坦化。應注意，在此一程序中，可首先形成導線搭接1132，使得導線搭接1132之高度(雖然非均勻)全部大於目標均勻高度。在平坦化使導線搭接1132降低至所要高度之後，可諸如藉由蝕刻或類似者而移除犧牲層1178。犧牲層1178可由可容許藉由蝕刻(其使用不會明顯影響囊封材料之一蝕刻劑)而移除之一材料形成。在一實例中，犧牲層1178可由一水溶性塑膠材料製成。
圖21及圖22繪示另一方法，可藉由該方法而形成突出超過囊封層之一表面之導線搭接之未囊封部分。因此，在圖21所見之實例中，導線搭接1232最初可與囊封層1242之一 表面1244齊平或甚至可不暴露於囊封層1242之一表面1244處。接著，如圖22中所展示，可移除囊封層(例如一模製囊封層)之一部分以導致端部1238突出超過經修改之囊封層表面1246。因此，在一實例中，雷射燒蝕可用於使囊封層均勻地凹陷以形成一平坦凹陷表面1246。替代地，可在鄰接個別導線搭接之囊封層之區中選擇性執行雷射燒蝕。
可用於選擇性移除囊封層之至少部分至導線搭接之其他技術中包含「濕式擦蝕」技術。在濕式擦蝕中，導引由一液體介質承載之一串流之磨蝕粒子朝向一目標以自該目標之表面移除材料。該串流之粒子有時可與一化學蝕刻劑組合，該化學蝕刻劑可選擇性促進或加速移除材料至其他結構，諸如在濕式擦蝕之後仍將保留之導線搭接。
在圖38A及圖38B所展示之實例中，在圖21及圖22所展示之方法之一變體中，可形成導線搭接環1232'，其使一端部具有位於導電元件1228上之基部1234A及使另一端部1234B附接至微電子元件1222之一表面。為將導線搭接環1232'附接至微電子元件1222，可諸如藉由濺鍍、化學氣相沈積、電鍍或類似者而使微電子元件1222之表面金屬化。基部1234A可經球形搭接(如圖所展示)或經邊緣搭接，端部1234B亦可接合至微電子元件1222。如圖38A中進一步所展示，介電囊封層1242可形成於基板1212上以覆蓋導線搭接環1232'。接著，可諸如藉由磨削、研磨、拋光或類似者而使囊封層1242平坦化以降低囊封層1242之高度且將導線搭接環1232'分成：連接導線搭接1232A，其可用於至少 接合至待與導電元件1228電連接之導線搭接環1232'之端部表面1238；及散熱搭接1232B，其係接合至微電子元件1222。散熱搭接可使得其等不電連接至微電子元件1222之電路之任何者，但經定位以將熱自微電子元件1222向遠處熱傳導至囊封層1242之表面1244。額外處理方法可應用於所得封裝1210'，如本文其他位置中所描述。
圖39A至圖39C中展示用於形成具有一預定高度之導線搭接2632之另一方法。在此一方法中，一犧牲囊封層2678可形成於基板2612之表面2614(其至少位於基板2612之第二區2620中)上。犧牲層2678亦可形成於基板2612之第一區2618上以通過與以上參考圖1而描述之囊封層類似之一方式覆蓋微電子元件2622。犧牲層2678包含至少一開口2679且在一些實施例中包含複數個開口2679以暴露導電元件2628。可在犧牲層2678之模製期間或在模製之後藉由蝕刻、鑽孔或類似者而形成開口2679。在一實施例中，可形成一較大開口2679以暴露全部導電元件2628，而在其他實施例中，可形成複數個較大開口2679以暴露各自群組之導電元件2628。在另外實施例中，可形成與個別導電元件2628對應之開口2679。形成具有位於導線搭接2632之一所要高度處之一表面2677之犧牲層2678，使得可藉由將導線搭接2632之基部2634搭接至導電元件2628且接著將導線拉出至到達犧牲層2678之表面2677而形成導線搭接2632。接著，導線接合可自開口橫向拉出以疊覆於犧牲層2678之表面2677上。可移動搭接成形儀器之毛細管(諸如圖14中所 展示之毛細管804)以將導線段按壓成與表面2677接觸，使得表面2677與毛細管之間之導線上之壓力導致導線在表面2677上被切斷，如圖39A中所展示。
接著，可藉由蝕刻或另一類似程序而移除犧牲層2678。在一實例中，犧牲層2678可由一水溶性塑膠材料形成，使得其可藉由暴露於水而移除且不影響在製單元2610"之其他組件。在另一實施例中，犧牲層2678可由一可光成像材料(諸如一光阻劑)製成，使得其可藉由暴露於一光源而移除。犧牲層2678'之一部分可保持於微電子元件2622與基板2612(其可充當包圍焊料球2652之一底部填充)材料之表面2614之間。在移除犧牲層2678之後，可在在製單元中形成一囊封層2642以形成封裝2610。囊封層2642可類似於上述囊封層且可實質上覆蓋基板2612之表面2614及微電子元件2622。囊封層2642可進一步支撐及分離導線搭接2632。在圖39C所展示之封裝2610中，導線搭接包含其邊緣表面2637之部分，該等部分係暴露於囊封劑2642之表面2644處且實質上平行於表面2644而延伸。在其他實施例中，可使導線搭接2632及囊封層2642平坦化以形成一表面2644，其中導線搭接具有暴露於表面2644上及與表面2644實質上齊平之端部表面。
可以除如上具體所描述方式以外之方式組合本發明之上述實施例及變體。本發明意欲涵蓋落在本發明之範疇及精神內之全部此等變體。
10‧‧‧微電子總成
12‧‧‧基板
14‧‧‧第一表面
16‧‧‧第二表面
18‧‧‧第一區
20‧‧‧第二區
22‧‧‧微電子元件
24‧‧‧引線
28‧‧‧導電元件
30‧‧‧接觸墊
32‧‧‧導線搭接
34‧‧‧基部
36‧‧‧自由端/端部
37‧‧‧邊緣表面
38‧‧‧端部表面/端部
39‧‧‧未囊封部分
40‧‧‧導電元件
41‧‧‧貫孔
42‧‧‧囊封層
43‧‧‧第二導電元件
43D‧‧‧第二導電元件
44‧‧‧主表面
45‧‧‧接觸墊
48‧‧‧第二導電元件
49‧‧‧開口
110‧‧‧微電子總成
112‧‧‧基板
114‧‧‧第一表面
116‧‧‧第二表面
118‧‧‧第二區
122‧‧‧微電子元件
126‧‧‧焊料凸塊
128‧‧‧導電元件
132‧‧‧導線搭接
132A‧‧‧導線搭接
132B‧‧‧導線搭接
134‧‧‧基部
134B‧‧‧基部
136‧‧‧端部/端部表面
138‧‧‧端部
144‧‧‧表面
146‧‧‧角度
210‧‧‧微電子總成
232‧‧‧導線搭接
234‧‧‧基部
236‧‧‧端部
238‧‧‧端部
248‧‧‧彎曲部
310‧‧‧微電子封裝
312‧‧‧基板
322‧‧‧微電子元件
324‧‧‧引線
332A‧‧‧導線搭接
332B‧‧‧導線搭接
332Ci‧‧‧導線搭接
332Cii‧‧‧導線搭接
332D‧‧‧導線搭接
334A‧‧‧基部
334B‧‧‧基部
334Ci‧‧‧基部
334Cii‧‧‧基部
336‧‧‧端部
336B‧‧‧端部
336Ci‧‧‧端部
336Cii‧‧‧端部
336D‧‧‧自由端
337A‧‧‧邊緣表面
337D‧‧‧邊緣表面
338‧‧‧端部表面
342‧‧‧囊封層
344‧‧‧主表面
345‧‧‧凹陷表面
348C‧‧‧彎曲部分
350‧‧‧微電子元件
382‧‧‧引線
384‧‧‧導線搭接
386‧‧‧接觸表面
410‧‧‧微電子總成/微電子封裝
412‧‧‧基板
421‧‧‧絕緣層
422‧‧‧微電子元件
426‧‧‧後表面
428‧‧‧導電元件
432‧‧‧導線搭接
434‧‧‧基部
436‧‧‧未囊封表面
438‧‧‧端部表面
440‧‧‧導電元件/接觸墊
448‧‧‧彎曲部分
452‧‧‧焊料塊/焊料球
488‧‧‧微電子總成
489‧‧‧微電子元件
490‧‧‧印刷電路板(PCB)
492‧‧‧接點/接觸墊
512‧‧‧基板
513‧‧‧引線
515‧‧‧腳座
518‧‧‧第一區
520‧‧‧第二區
522‧‧‧微電子元件
524‧‧‧導線搭接
528‧‧‧導電元件
532‧‧‧導線搭接
534‧‧‧基部
538‧‧‧端部
610A‧‧‧封裝/第一組件
610B‧‧‧封裝/微電子封裝
620‧‧‧底部填充材料
632‧‧‧導線搭接
642‧‧‧對立表面
644‧‧‧對立表面
652‧‧‧焊料塊
690‧‧‧電路面板
692‧‧‧第一表面
712‧‧‧基板
728‧‧‧導電元件
730‧‧‧表面
732A‧‧‧導線搭接
732B‧‧‧導線搭接
732D‧‧‧導線搭接
736‧‧‧向上延伸部分/圓柱形導線搭接部分
738A‧‧‧端部
738B‧‧‧端部
738D‧‧‧球形部分
739‧‧‧未囊封部分
740‧‧‧質心
741‧‧‧徑向方向
744‧‧‧直徑
746‧‧‧直徑
750‧‧‧角度
751‧‧‧囊封層
752‧‧‧表面
800‧‧‧金屬導線段/導線
801‧‧‧方向
802‧‧‧長度
803‧‧‧夾具
804‧‧‧毛細管
805‧‧‧切割刀片
806‧‧‧表面
807‧‧‧開口
808‧‧‧毛細管開口
809‧‧‧雷射頭/雷射
810‧‧‧成形單元
812‧‧‧第一表面
814‧‧‧第一方向
816‧‧‧第二表面/內表面
818‧‧‧方向
820‧‧‧外壁
821‧‧‧框架
822‧‧‧部分
823‧‧‧空腔/敞開區
824‧‧‧模板單元/模板
826‧‧‧上表面/頂面/外表面
828‧‧‧孔
829‧‧‧邊緣
830‧‧‧凹陷部
832‧‧‧凹槽
834‧‧‧通道
838‧‧‧端部
840‧‧‧凹陷部
932‧‧‧導線搭接
933‧‧‧周邊
934‧‧‧基部
938‧‧‧端部
1010‧‧‧成形單元
1014A‧‧‧橫向方向
1016‧‧‧方向
1018‧‧‧第三表面
1020‧‧‧外表面
1022‧‧‧部分
1022A‧‧‧部分
1024‧‧‧第三表面
1026‧‧‧向上突出部分
1036‧‧‧向上突出部分
1038‧‧‧端部
1102‧‧‧暫時薄膜
1110‧‧‧第一板/模板
1111‧‧‧第二板/模板
1112‧‧‧空腔
1132‧‧‧導線搭接
1138‧‧‧端部
1142‧‧‧囊封層
1144‧‧‧模具表面
1178‧‧‧犧牲材料層/犧牲層
1212‧‧‧基板
1222‧‧‧微電子元件
1232‧‧‧導線搭接
1232'‧‧‧導線搭接環
1232B‧‧‧散熱搭接
1234A‧‧‧基部
1234B‧‧‧端部
1242‧‧‧囊封層
1244‧‧‧表面
1246‧‧‧囊封層表面/平坦凹陷表面
1328‧‧‧導電元件
1332‧‧‧導線搭接
1334‧‧‧基部
1372‧‧‧球形搭接
1372'‧‧‧球形搭接
1373'‧‧‧球形搭接
1428‧‧‧導電元件
1432‧‧‧導線搭接
1439‧‧‧暴露部分
1444‧‧‧表面
1522‧‧‧微電子元件
1532‧‧‧導線搭接
1534‧‧‧基部
1538‧‧‧端部表面
1539‧‧‧未囊封部分
1552‧‧‧導電塊
1622‧‧‧第一微電子元件
1628‧‧‧導電元件
1650‧‧‧第二微電子元件
1688‧‧‧導線搭接
1722‧‧‧第一微電子元件
1728‧‧‧導電元件
1750‧‧‧第二微電子元件
1788‧‧‧導線搭接
1822‧‧‧第一微電子元件
1828‧‧‧導電元件
1850‧‧‧第二微電子元件
1910A‧‧‧封裝
1910B‧‧‧封裝
1916‧‧‧表面
1942‧‧‧囊封層
1944‧‧‧表面
1947‧‧‧邊緣表面
1949‧‧‧施配區
2010A‧‧‧微電子封裝
2010B‧‧‧微電子封裝
2016‧‧‧表面
2032‧‧‧導線搭接
2039‧‧‧未囊封部分
2043‧‧‧端子
2044‧‧‧表面
2052‧‧‧導電塊/焊料塊
2099‧‧‧柔性邊框
2110A‧‧‧封裝
2110B‧‧‧封裝
2112‧‧‧基板
2132‧‧‧導線搭接
2142‧‧‧囊封層
2144‧‧‧主表面
2145‧‧‧次表面
2151‧‧‧對準表面
2210A‧‧‧封裝
2212‧‧‧基板
2232‧‧‧導線搭接
2244‧‧‧凸起內表面
2245‧‧‧下部外表面
2251‧‧‧對準表面
2252‧‧‧焊料球
2612‧‧‧基板
2614‧‧‧表面
2622‧‧‧微電子元件
2628‧‧‧導電元件
2632‧‧‧導線搭接
2634‧‧‧基部
2642‧‧‧囊封層/囊封劑
2644‧‧‧表面
2652‧‧‧焊料球
2677‧‧‧表面
2678‧‧‧犧牲囊封層/犧牲層
2679‧‧‧開口
2710‧‧‧微電子封裝/微電子總成
2710'‧‧‧微電子總成
2710"‧‧‧微電子總成
2710'''‧‧‧微電子總成
2712‧‧‧基板
2714‧‧‧第一表面
2716‧‧‧第二表面
2718‧‧‧第一區
2722‧‧‧微電子元件
2726‧‧‧焊料塊
2728‧‧‧導電元件
2730‧‧‧接觸墊
2732‧‧‧導線搭接
2734‧‧‧基部
2736‧‧‧端部
2737‧‧‧邊緣表面
2738‧‧‧端部表面
2740‧‧‧導電元件
2742‧‧‧囊封層
2744‧‧‧表面
2766‧‧‧介電底部填充層
2800‧‧‧導線段
2804‧‧‧毛細管
2806‧‧‧表面
2810‧‧‧成形工具
2820‧‧‧側壁
2822‧‧‧第一導線部分
3800‧‧‧導線段
3804‧‧‧毛細管
3806‧‧‧表面
3808‧‧‧表面
3812‧‧‧表面
3816‧‧‧成形表面
3820‧‧‧側壁
3822‧‧‧第一部分
圖1係描繪根據本發明之一實施例之一微電子封裝之截面圖。
圖2展示圖1之微電子封裝之一俯視平面圖。
圖3係描繪根據圖1中所展示實施例之一變體之一微電子封裝之一截面圖。
圖4係描繪根據圖1中所展示實施例之一變體之一微電子封裝之一截面圖。
圖5A係描繪根據圖1中所展示實施例之一變體之一微電子封裝之一截面圖。
圖5B係描繪根據本發明之一實施例之形成於一導線搭接之一未囊封部分上之一導電元件之一局部截面圖。
圖5C係描繪根據圖5B中所展示實施例之一變體之形成於一導線搭接之一未囊封部分上之一導電元件之一局部截面圖。
圖5D係描繪根據圖5B中所展示實施例之一變體之形成於一導線搭接之一未囊封部分上之一導電元件之一局部截面圖。
圖6係繪示一微電子總成之一截面圖，該微電子總成包含根據前述實施例之一或多者之一微電子封裝以及一額外微電子封裝及與該額外微電子封裝電連接之一電路面板。
圖7係繪示根據本發明之一實施例之一微電子封裝之一俯視正視圖。
圖8係進一步繪示根據本發明之一實施例之一微電子封裝之一局部俯視正視圖。
圖9係繪示根據本發明之一實施例之包含一引線框型基板之一微電子封裝之一俯視正視圖。
圖10係圖9中所展示之微電子封裝之一對應截面圖。
圖11係根據圖6中所展示實施例之一變體之一微電子總成之一截面圖，該微電子總成包含電連接在一起且經由一底填材料加固之複數個微電子封裝。
圖12係表示一總成之一照片影像，該總成具有介於一第一組件之導線搭接與附接至該第一組件之一第二組件之焊料塊之間之搭接。
圖13A係繪示根據本發明之一實施例之一微電子封裝中之一導線搭接貫孔之一局部截面圖。
圖13B係繪示根據本發明之一實施例之一微電子封裝中之一導線搭接貫孔之一局部截面圖。
圖13C係繪示根據圖13B中所展示實施例之一微電子封裝中之一導線搭接貫孔之一放大局部截面圖。
圖13D係繪示根據本發明之一實施例之一微電子封裝中之一導線搭接貫孔之一局部截面圖。
圖13E係繪示根據圖13D中所展示實施例之一微電子封裝中之一導線搭接貫孔之一放大局部截面圖。
圖13F係繪示根據本發明之一實施例之一微電子封裝中之一導線搭接貫孔之一局部截面圖。
圖14繪示根據本發明之一實施例之在將一金屬導線段搭接至一導電元件之前形成該導線段之一方法中之階段。
圖15進一步繪示如圖14中所描繪之一方法及適合於用在 此方法中之一成形單元。
圖16係繪示根據本發明之一實施例而形成之導線搭接之一俯視正視圖。
圖17繪示根據本發明之一實施例之在將一金屬導線段搭接至一導電元件之前形成該導線段之一方法中之階段。
圖18及圖19係繪示根據本發明之一實施例之形成一微電子封裝之一囊封層之一方法中之一階段及該階段後之另一階段之截面圖。
圖20係進一步繪示與圖19對應之階段之一放大截面圖。
圖21係繪示根據本發明之一實施例之製造一微電子封裝之一囊封層之一階段之一截面圖。
圖22係繪示圖21中所展示之階段後之製造一微電子封裝之一囊封層之一階段之一截面圖。
圖23A及圖23B係繪示根據另一實施例之導線搭接之局部截面圖。
圖24A及圖24B係根據另一實施例之一微電子封裝之截面圖。
圖25A及圖25B係根據另一實施例之一微電子封裝之截面圖。
圖26展示根據另一實施例之一微電子封裝之一截面圖。
圖27A至圖27C係展示根據另外實施例之微電子封裝之實施例之實例之截面圖。
圖28A至圖28D展示根據本發明之一實施例之在形成一微電子總成之步驟期間之微電子封裝之各種實施例。
圖29展示根據本發明之一實施例之在形成一微電子總成之步驟期間之微電子封裝之另一實施例。
圖30A至圖30C展示根據本發明之另一實施例之在形成一微電子總成之步驟期間之微電子封裝之實施例。
圖31A至圖31C展示根據本發明之另一實施例之在形成一微電子總成之步驟期間之微電子封裝之實施例。
圖32A及圖32B展示根據本發明之另一實施例之可用於在一方法之各種階段中形成各種導線搭接貫孔之一機器之一部分。
圖33展示根據本發明之另一實施例之可用於在一方法中形成各種導線搭接貫孔之一機器之一部分。
圖34A至圖34C展示根據本發明之一實施例之可用在製造導線搭接之一方法中之一儀器之各種形式。
圖35展示根據本發明之一另一實施例之可用於在一方法中形成各種導線搭接貫孔之一機器之一部分。
圖36展示根據本發明之一另一實施例之可用於在一方法中形成各種導線搭接貫孔之一機器之一部分。
圖37A至圖37D展示繪示根據本發明之一實施例之製造一微電子封裝之階段之截面圖。
圖38A及圖38B展示繪示根據本發明之另一實施例之製造一微電子封裝之階段之截面圖。
圖39A至圖39C展示繪示根據本發明之另一實施例之製造一微電子封裝之階段之截面圖。
圖40展示根據本發明之一實施例之一微電子封裝。
圖41至圖44展示根據本發明之一實施例之在製造一微電子封裝之各種步驟期間之該微電子封裝。
10‧‧‧微電子總成
12‧‧‧基板
14‧‧‧第一表面
16‧‧‧第二表面
18‧‧‧第一區
20‧‧‧第二區
22‧‧‧微電子元件
24‧‧‧引線
28‧‧‧導電元件
30‧‧‧接觸墊
32‧‧‧導線搭接
34‧‧‧基部
36‧‧‧自由端/端部
37‧‧‧邊緣表面
38‧‧‧端部表面/端部
39‧‧‧未囊封部分
40‧‧‧導電元件
41‧‧‧貫孔
42‧‧‧囊封層
44‧‧‧主表面

Claims (44)

  1. 一種微電子封裝，其包括：一基板，其具有一第一區及一第二區，該基板具有一第一表面及該第一表面遠端處之一第二表面；至少一微電子元件，其疊覆於該第一區內之該第一表面上；導電元件，其等暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等導電元件之至少若干者係電連接至該至少一微電子元件；導線搭接，其等界定邊緣表面且具有與該等導電元件之各自者搭接之基部，該等基部包含沿該等導電元件延伸之該等邊緣表面之第一部分，其中該等邊緣表面之各自第二部分相對於該等第一部分成25°至90°之間之一角度，該等導線搭接進一步具有位於該基板及該等基部遠端處之端部；及一介電囊封層，其自該等第一或第二表面之至少一者延伸且覆蓋該等導線搭接之部分，使得該等導線搭接之覆蓋部分因該囊封層而彼此分離，該囊封層至少疊覆於該基板之該第二區上，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之部分界定，該等未囊封部分包含該等端部，其中該等導電元件係佈置於若干位置處以呈具有該複數個導電元件之各自相鄰導電元件之間之一第一最小節距之一圖案，且其中該等未囊封部分係佈置於若干位置處以呈具有該複數個導線搭接 之相鄰導線搭接之各自端部之間之一第二最小節距之一圖案，該第二節距大於該第一節距。
  2. 如請求項1之微電子封裝，其中該角度介於80°至90°之間。
  3. 如請求項1之微電子封裝，其中該等導線搭接之該等未囊封部分之至少若干者之各者包含一球形部分，各球形部分與此導線搭接之一圓柱形部分整合，各球形部分及各圓柱形部分具有本質上由銅、銅合金或金組成之至少一核心。
  4. 如請求項3之微電子封裝，其中與該等球形部分整合之該等圓柱形部分突出超過該囊封層之一表面。
  5. 如請求項1之微電子封裝，其中該等導線搭接之至少若干者具有一原生金屬核心及一金屬防護層，該金屬防護層包含疊覆於該原生金屬上之與該原生金屬不同之一再生金屬。
  6. 如請求項5之微電子封裝，其中該原生金屬為銅且該金屬防護層包含一層銀。
  7. 如請求項1之微電子封裝，其中該等導電元件為第一導電元件，該微電子封裝進一步包括與該等導線搭接之該等未囊封部分電連接之複數個第二導電元件，其中該等第二導電元件不接觸該第等一導電元件。
  8. 如請求項7之微電子封裝，其中在形成該囊封層之後藉由電鍍而形成與該等導線搭接之該等未囊封部分接觸之該等第二導電元件。
  9. 如請求項1之微電子封裝，其中該等導線搭接之至少一者之一端部沿平行於該基板之該第一表面之一方向自該導線搭接之基部位移達等於以下之一者之至少一距離：該等導電元件之一最小節距；及100微米，其中該等導線搭接之至少一者包含該導線搭接之該基部與該導線搭接之該未囊封部分之間之至少一彎曲部，且其中該至少一導線搭接之該彎曲部位於該導線搭接之該基部及該導線搭接之該未囊封部分之遠端處。
  10. 如請求項9之微電子封裝，其中該彎曲部之一半徑比該至少一導線搭接之一圓柱形部分之一直徑大12倍。
  11. 如請求項9之微電子封裝，其中該彎曲部之該半徑比該至少一導線搭接之一圓柱形部分之一直徑小10倍。
  12. 如請求項9之微電子封裝，其中該至少一導線搭接之該未囊封部分沿相對於該基板之該第一表面成25°至90°內之一方向突出高於該囊封層。
  13. 如請求項1之微電子封裝，其中該等導電元件經非阻焊界定。
  14. 如請求項1之微電子封裝，其進一步包括與該等導線搭接之該等基部之部分接合且疊覆於該等部分上之球形搭接。
  15. 如請求項1之微電子封裝，其中該至少一微電子元件包含疊覆於該第一區內之該第一表面上之第一及第二微電子元件，其中該等導電元件之至少若干者與該第一微電子元件連接，且其中至少一些導電元件與該第二微電子 元件連接，且其中該第一微電子元件與該等第二微電子元件在該微電子封裝內彼此電連接。
  16. 一種微電子封裝，其包括：一基板，其具有一第一區及一第二區，該基板具有一第一表面及該第一表面遠端處之一第二表面；至少一微電子元件，其疊覆於該第一區內之該第一表面上；第一導電元件，其等暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等第一導電元件之至少若干者係電連接至該至少一微電子元件；導線搭接，其等具有與該等第一導電元件之各自者接合之基部及位於該基板及該等基部遠端處之端部表面，各導線搭接界定延伸於該導線搭接之該基部與該端部表面之間之一邊緣表面；一介電囊封層，其自該等第一或第二表面之至少一者延伸且填充該等導線搭接之間之空間，使得該等導線搭接因該囊封層而彼此分離，該囊封層至少疊覆於該基板之該第二區上，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之該等端部表面之至少部分界定，該囊封層包含一主表面及相對於該主表面傾斜之一對準表面，該導線搭接之至少一未囊封部分係定位於該主表面上且該對準表面係接近於該未囊封部分之一鄰近位置處之該主表面，使得該對準表面經組態以引導佈置於 該對準表面上方之一導電突出部朝向該導線搭接之該未囊封部分。
  17. 如請求項16之微電子封裝，其中該突出部包含一搭接金屬。
  18. 如請求項17之微電子封裝，其中該搭接金屬包含附接至一電路元件之一焊料球。
  19. 如請求項16之微電子封裝，其中該囊封層界定其之一角隅區，該囊封層進一步包含定位於該角隅區內且定位成比該主表面更遠離該基板之至少一次表面，該對準表面延伸於該次表面與該主表面之間。
  20. 如請求項16之微電子封裝，其中該主表面為疊覆於該基板之該第一區上之一第一主表面，該囊封層進一步界定疊覆於該第二區上之且定位成比該主表面更靠近該基板之一第二主表面，該對準表面延伸於該等第一與第二主表面之間。
  21. 一種微電子總成，其包括：一第一微電子封裝，其如請求項16所闡釋；一第二微電子封裝，其界定一前表面，該前表面具有位於其上之端子；及複數個導電突出部，其等將該等導線搭接之該等未囊封部分之至少若干者與該等端子之各自者連接；其中該等導電突出部之至少一者係定位成與該對準表面之一部分接觸。
  22. 如請求項21之微電子總成，其中該等導電突出部包含焊 料球。
  23. 一種微電子封裝，其包括：一基板，其具有一第一區及一第二區，該基板具有一第一表面及該第一表面遠端處之一第二表面；至少一微電子元件，其疊覆於該第一區內之該第一表面上；導電元件，其等暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等導電元件之至少若干者係電連接至該至少一微電子元件；球形搭接，其等接合至該等導電元件之至少若干者；導線搭接，其等界定邊緣表面且具有搭接至該等至少一些導電元件頂上之該等球形搭接之基部，該等基部包含在該等導電元件上延伸之該等邊緣表面之第一部分，其中該等邊緣表面之各自第二部分相對於該等第一部分成25°至90°之間之一角度，該等導線搭接進一步具有位於該基板及該等基部遠端處之端部；及一介電囊封層，其自該等第一或第二表面之至少一者延伸且覆蓋該等導線搭接之部分，使得該等導線搭接之覆蓋部分因該囊封層而彼此分離，該囊封層至少疊覆於該基板之該第二區上，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之部分界定，該等未囊封部分包含該等端部。
  24. 一種微電子總成，其包括：一第一微電子封裝，其如請求項1所闡釋且進一步包 含暴露於該基板之第二表面處之複數個端子及沿該基板之第一與第二表面之間之一方向延伸之周邊邊緣；一第二微電子封裝，其包含：一基板，其具有位於其上之接點；一第二微電子元件，其與該等接點電連接；及端子，其等暴露於該基板之一表面處且透過該等接點而與該第二微電子元件電連接，該第二微電子封裝之該等端子面向該等導線搭接之各自未囊封部分且與該等導線搭接之該等各自未囊封部分電連接；一電路面板，其包含一第一表面及暴露於該電路面板之該表面處之面板接點，該第一微電子封裝疊覆於該電路面板上且具有與該電路面板之該等面板接點接合之該第一微電子封裝之該等端子；及一單塊底部填充材料，其疊覆於該第一微電子封裝之該等周邊邊緣之至少一者上且佈置於將該第一微電子封裝之該等端子與該電路面板之該等面板接點之間之接合點包圍之空間內，且佈置於將該第二微電子封裝與該第一微電子封裝之該等端子之間之接合點包圍之空間內。
  25. 一種微電子封裝，其包括：一基板，其具有一第一區及一第二區，該基板具有一第一表面及該第一表面遠端處之一第二表面；至少一微電子元件，其疊覆於該第一區內之該第一表面上；第一導電元件，其等暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等第一導電元 件之至少若干者係電連接至該至少一微電子元件；導線搭接，其等具有與該等第一導電元件之各自者接合之基部及位於該基板及該等基部遠端處之端部表面，各導線搭接界定延伸於該導線搭接之該基部與該端部表面之間之一邊緣表面；一介電囊封層，其自該第一表面延伸且填充該等導線搭接之間之空間，使得該等導線搭接因該囊封層而彼此分離，該囊封層界定：一第一表面部分，其位於一區中之該第一表面上方之一第一高度處，該區疊覆於該基板之該第一區上；及一第二表面部分，其位於一區中之該第一表面上方之一第二高度處，該區疊覆於該基板之該第二區上，其中該第二高度小於該第一高度，且其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之該等端部表面之至少部分界定。
  26. 如請求項25之微電子封裝，其中該微電子元件界定位於該第一表面上方之一第三高度處之一前表面，且其中該第二高度遠小於該第三高度。
  27. 一種微電子封裝，其包括：一基板，其具有一第一區及一第二區，該基板具有一第一表面及該第一表面遠端處之一第二表面；至少一微電子元件，其疊覆於該第一區內之該第一表面上；第一導電元件，其等暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等第一導電元 件之至少若干者係電連接至該至少一微電子元件；導線搭接，其等具有與該等第一導電元件之各自者接合之球形搭接基部及位於該基板及該等基部遠端處比該基部之一直徑小3倍之一距離之端部表面，各導線搭接界定延伸於該導線搭接之該基部與該端部表面之間之一邊緣表面；一介電囊封層，其自該第一表面延伸且填充該等導線搭接之間之空間，使得該等導線搭接因該囊封層而彼此分離，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之該等端部表面之至少部分界定。
  28. 如請求項27之微電子封裝，其中球形搭接基部包含接合至該等各自導電元件之第一球形搭接及接合至該等第一球形搭接之第二球形搭接，該等端部表面延伸於該等第一球形搭接與該等第二球形搭接之間。
  29. 一種微電子封裝，其包括：一基板，其具有一第一區及一第二區，該基板具有一第一表面及該第一表面遠端處之一第二表面；至少一微電子元件，其疊覆於該第一區內之該第一表面上；第一導電元件，其等暴露於該第二區內之該基板之該第一表面及該第二表面之至少一者處，該等第一導電元件之至少若干者係電連接至該至少一微電子元件；導線搭接，其等具有與該等第一導電元件之至少若干者接合之基部及位於該基板及該等基部遠端處之端部表 面，各導線搭接界定延伸於該導線搭接之該基部與該端部表面之間之一邊緣表面，其中該等導線搭接之至少兩者係接合至該複數個第一導電元件之一個別第一導電元件；一介電囊封層，其自該等第一或第二表面之至少一者延伸且填充該等導線搭接之間之空間，使得該等導線搭接因該囊封層而彼此分離，該囊封層至少疊覆於該基板之該第二區上，其中該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之該等端部表面之至少部分界定。
  30. 一種製造一微電子封裝之方法，其包括：在一在製單元上形成一介電囊封層，該在製單元包含一基板具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件等暴露於該第一表面處，該等導電元件之至少若干者係電連接至該微電子元件，且導線搭接具有與該等導電元件接合之基部及位於該等基部遠端處之端部表面，各導線搭接界定向遠處延伸於該基部與該端部表面之間之一邊緣表面；其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定，該囊封層經進一步形成以包含一主表面及相對於該主表面成角度之一對準表 面，該導線搭接之至少一未囊封部分係定位於該主表面上且該對準表面在接近該未囊封部分之一位置處與該主表面相交，使得該對準表面經組態以引導佈置於該對準表面上方之一導電突出部朝向該導線搭接之該未囊封部分。
  31. 如請求項30之方法，其中囊封層經進一步形成以界定該囊封層之一角隅區且進一步包含定位於該角隅區內且定位成比該主表面更遠離該基板之至少一次表面，該對準表面延伸於該次表面與該主表面之間。
  32. 如請求項30之方法，其中該囊封層之該主表面為疊覆於該基板之該第一區上之一第一主表面，該囊封層經進一步形成以界定疊覆於該第二區上且定位成比該主表面更靠近該基板之一第二主表面，該對準表面延伸於該次表面與該主表面之間。
  33. 一種製造一微電子總成之方法，其包括：使一第二微電子封裝與根據請求項30之方法而製造之一第一微電子封裝對準，該第二微電子封裝包含界定一第一表面之一基板，其中具有接觸墊暴露於該第一表面上且導電塊與該等接觸墊接合，其中該第二微電子封裝藉由將諸焊料球之至少一者移動成與對準表面與至少一導線搭接之至少端部表面兩者接觸而與該第一微電子封裝對準；及回焊該等導電塊以使該等導電塊與該等導線搭接之未囊封部分之各自者接合。
  34. 一種製造一微電子總成之方法，其包括：使一第二微電子封裝與根據包含以下步驟之一方法而製造之一第一微電子封裝對準：在一在製單元上形成一介電囊封層，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處，該等導電元件之至少若干者係電連接至該微電子元件，且導線搭接具有與該等導電元件接合之基部及位於該等基部遠端處之端部表面，各導線搭接界定向遠處延伸於該基部與該端部表面之間之一邊緣表面，其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定；該第二微電子封裝包含界定一第一表面之一基板，其中接觸墊暴露於該第一表面上且相對於該第一微電子封裝而定尺寸使得其可被對準以便使施配區由橫向地延伸超過該第二微電子封裝之一邊緣表面之該囊封層之一部分界定；及將一底部填充材料沈積至該施配區上使得該底部填充材料流入至該囊封層與該第二微電子封裝之該基板之該第一表面之間所界定之一空間中且該施配區上之一定數量之該底部填充材料可流入至該等第一及第二微電子封裝之對立表面之間之該空間中。
  35. 如請求項34之方法，其中該第二微電子封裝包含四個邊緣表面，且其中該施配區由橫向地延伸超過全部四個邊緣表面以包圍該第二微電子封裝之該囊封層之一部分界定。
  36. 如請求項34之方法，其中該第二微電子封裝包含四個邊緣表面，且其中該施配區由橫向地延伸超過該等邊緣表面之兩個相鄰者之該囊封層之一部分界定。
  37. 如請求項34之方法，其中該第二微電子封裝包含四個邊緣表面，且其中該施配區由橫向地延伸超過一單一邊緣表面之該囊封層之一部分界定。
  38. 一種製造一微電子總成之方法，其包括：將複數個導電塊定位於一第一微電子封裝與一第二微電子封裝之間，該第二微電子封裝包含界定一第一表面之一基板，其中第二接觸墊暴露於該第一表面上，其中該等導電塊係進一步定位於各自第一接觸墊與第二接觸墊之間，且該第一微電子封裝藉由包含以下步驟之一方法而製造：在一在製單元上形成一介電囊封層，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處且複數個端子暴露於該第二表面處，該等導電元件之至少若干者係電連接至該微電子元件，且導線搭接具有與該等導電元件接合之基部及位於該等基部遠端處之端部表面，各導線搭接界 定向遠處延伸於該基部與該端部表面之間之一邊緣表面，其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定；在該等第一及第二微電子封裝之邊緣表面周圍組裝一柔性邊框；及回焊該等導電塊以接合該等各自第一接觸墊及第二接觸墊。
  39. 一種製造一微電子封裝之方法，其包括：a)自一搭接工具之一毛細管向外供給具有一預定長度之一金屬導線段；b)在一成形單元之第一及第二表面上移動該毛細管之表面以將該金屬導線段塑形成具有沿順著該毛細管之一外壁之一方向向上突出之一第一部分；及c)使用該搭接工具來將該金屬導線之一第二部分搭接至接合於暴露於一基板之一第一表面處之一導電元件上之一球形搭接，該金屬導線之該第二部分經定位以沿該導電元件延伸，其中該第一部分定位成相對於該第二部分成25°至90°之間之一角度；d)重複步驟(a)至(c)以將複數個金屬導線搭接至該基板之該複數個導電元件；及e)接著形成疊覆於該基板之該表面上之一介電囊封層，其中該囊封層經形成以便至少部分覆蓋該基板之該 表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之一端部表面或一邊緣表面之至少一者之一部分界定。
  40. 一種製造一微電子總成之方法，其包括：接合一第一微電子封裝與一第二微電子封裝，該第二微電子封裝包含具有一第一表面之一基板，該第一表面與該囊封層隔開且面向該囊封層，且該第一微電子封裝藉由包含以下步驟之一方法而製造：在一在製單元上形成一介電囊封層，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處且複數個端子暴露於該第二表面處，該等導電元件之至少若干者係電連接至與該微電子元件，且導線搭接具有與該等導電元件接合之基部及位於該等基部遠端處之端部表面，各導線搭接界定向遠處延伸於該基部與該端部表面之間之一邊緣表面，其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定；接合該第一微電子封裝與一電路面板，該電路面板具有與該基板之該第二表面隔開且面向該第二表面之一表面，該第一微電子封裝及電路面板係接合於該第一微電子封裝之該等端子與暴露於該電路面板之該表面上之接 觸墊之間；及形成一單塊底部填充材料，該單塊底部填充材料包圍該第一微電子封裝之暴露部分且填充將該第一微電子封裝之該等端子與該電路面板之間之接合點及該第二微電子封裝及該第一微電子封裝之間之該等端子之間之接合點包圍之空間。
  41. 一種製造一微電子封裝之方法，其包括：在一在製單元上之一介電囊封層之一表面上形成一犧牲材料層，該在製單元進一步包含具有端部表面及基部之導線搭接，該等基部位於該等端部遠端處且定位於該囊封層內，各導線搭接界定向遠處延伸於該基部與該端部表面之間之一邊緣表面，其中該囊封層覆蓋該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面及該邊緣表面之一部分界定，且其中該犧牲材料層覆蓋未被該囊封層覆蓋之該等導線搭接之該等部分；使該犧牲材料層之一部分及該等導線搭接之部分平坦化，使得未被該囊封層覆蓋之該等導線搭接之該等部分達到一預定之實質上均勻高度；及移除該犧牲材料層之任何剩餘部分。
  42. 一種製造一微電子封裝之方法，其包括：在一在製單元上形成複數個導線搭接，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複 數個導電元件暴露於該第一表面處，該等導電元件之至少若干者係電連接至該微電子元件，該等導線搭接具有與該等導電元件接合之第一基部及與該微電子元件之一後表面接合之第二基部，各導線搭接界定延伸於該第一基部與該第二基部之間之一邊緣表面；在該在製單元上形成一介電囊封層，其中該囊封層經形成以便覆蓋該第一表面及該等導線搭接；同時移除該囊封層之一部分及該等導線搭接之部分，使得該等導線搭接被分成包含該等第一基部之連接貫孔及包含該等第二基部之熱貫孔，該等連接貫孔與該等熱貫孔兩者具有位於該等基部遠端處之端部表面，該移除步驟進一步使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該等導線搭接之該等端部表面之至少一部分界定。
  43. 一種製造一微電子封裝之方法，其包括：在一在製單元上形成複數個導線搭接，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處，該等導電元件之至少若干者係電連接至該微電子元件，該等導線搭接具有與該等導電元件接合之基部及位於該等基部遠端處之端部表面，各導線搭接界定延伸於該基部與該端部表面之間之一邊緣表面，其中至少兩個導線搭接係形成於該等導電元件之至少一者上；及 在該在製單元上形成一介電囊封層，其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定。
  44. 一種製造一微電子封裝之方法，其包括：在一在製單元上形成一犧牲結構，該在製單元包含具有一第一表面及該第一表面遠端處之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處，該等導電元件之至少若干者係電連接至該微電子元件，該犧牲結構具有暴露於該等導電元件之至少一者處之位於其內之一開口，該犧牲結構界定位於該開口鄰近處及該基板之該第一表面遠端處之一表面；形成複數個導線搭接，其包含自一搭接工具之一毛細管向外供給具有一預定長度之一金屬導線段，該等導線搭接具有與該等導電元件接合之基部及位於該等基部遠端處之端部表面，各導線搭接界定延伸於該基部與該端部表面之間之一邊緣表面；及在該等開口外部及該犧牲結構之該表面鄰近處之位置處切斷該等導線搭接；移除該犧牲結構；及在該在製單元上形成一介電囊封層，其中該囊封層經形成以便至少部分覆蓋該第一表面及該等導線搭接之部分，使得該等導線搭接之未囊封部分由未被該囊封層覆 蓋之該導線搭接之該端部表面或該邊緣表面之至少一者之一部分界定。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI712123B (zh) * 2015-10-22 2020-12-01 美商艾馬克科技公司 半導體裝置及其製造方法
US12100655B2 (en) 2022-05-17 2024-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits having signal lines formed with double patterning

Families Citing this family (136)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5592055B2 (ja) 2004-11-03 2014-09-17 テッセラ，インコーポレイテッド 積層パッケージングの改良
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US9123614B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Methods and applications of non-planar imaging arrays
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
US9941195B2 (en) 2009-11-10 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical metal insulator metal capacitor
FR2959350B1 (fr) * 2010-04-26 2012-08-31 Commissariat Energie Atomique Procede de fabrication d?un dispositif microelectronique et dispositif microelectronique ainsi fabrique
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9721872B1 (en) * 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
KR101681269B1 (ko) * 2011-08-16 2016-12-01 인텔 코포레이션 오프셋 인터포저들, 상기 오프셋 인터포저들을 포함하는 장치들, 및 상기 오프셋 인터포저들의 구축 방법들
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9196588B2 (en) * 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) * 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
TWI471989B (zh) 2012-05-18 2015-02-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8955388B2 (en) * 2012-05-31 2015-02-17 Freescale Semiconductor, Inc. Mold compound compatibility test system and methods thereof
US9226402B2 (en) 2012-06-11 2015-12-29 Mc10, Inc. Strain isolation structures for stretchable electronics
US9295842B2 (en) 2012-07-05 2016-03-29 Mc10, Inc. Catheter or guidewire device including flow sensing and use thereof
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9136213B2 (en) 2012-08-02 2015-09-15 Infineon Technologies Ag Integrated system and method of making the integrated system
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
KR20140019535A (ko) * 2012-08-06 2014-02-17 엘지이노텍 주식회사 카메라 모듈 및 그를 구비한 전자장치
TWI495066B (zh) * 2012-08-31 2015-08-01 Chipmos Technologies Inc 晶圓級封裝結構及其製造方法
JP2016500869A (ja) 2012-10-09 2016-01-14 エムシー１０ インコーポレイテッドＭｃ１０，Ｉｎｃ． 衣類と一体化されたコンフォーマル電子回路
US9171794B2 (en) 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
TWI570864B (zh) * 2013-02-01 2017-02-11 英帆薩斯公司 具有焊線通孔的微電子封裝、其之製造方法以及用於其之硬化層
US9237648B2 (en) 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
US9016552B2 (en) * 2013-03-15 2015-04-28 Sanmina Corporation Method for forming interposers and stacked memory devices
US9706647B2 (en) 2013-05-14 2017-07-11 Mc10, Inc. Conformal electronics including nested serpentine interconnects
US9660154B2 (en) * 2013-05-20 2017-05-23 Koninklijke Philips N.V. Chip scale light emitting device package with dome
DE102013211405B4 (de) 2013-06-18 2020-06-04 Infineon Technologies Ag Verfahren zur herstellung eines halbleitermoduls
US9508635B2 (en) 2013-06-27 2016-11-29 STATS ChipPAC Pte. Ltd. Methods of forming conductive jumper traces
US9406533B2 (en) 2013-06-27 2016-08-02 STATS ChipPAC Pte. Ltd. Methods of forming conductive and insulating layers
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
CA2920485A1 (en) 2013-08-05 2015-02-12 Mc10, Inc. Flexible temperature sensor including conformable electronics
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
DE102013217349B4 (de) 2013-08-30 2024-06-13 Robert Bosch Gmbh Mikromechanische Sensoranordnung und entsprechendes Herstellungsverfahren
US20150076714A1 (en) * 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
CA2925387A1 (en) 2013-10-07 2015-04-16 Mc10, Inc. Conformal sensor systems for sensing and analysis
DE102013220880B4 (de) * 2013-10-15 2016-08-18 Infineon Technologies Ag Elektronisches Halbleitergehäuse mit einer elektrisch isolierenden, thermischen Schnittstellenstruktur auf einer Diskontinuität einer Verkapselungsstruktur sowie ein Herstellungsverfahren dafür und eine elektronische Anordung dies aufweisend
KR102365120B1 (ko) 2013-11-22 2022-02-18 메디데이타 솔루션즈, 인코포레이티드 심장 활동 감지 및 분석용 등각 센서 시스템
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9691693B2 (en) 2013-12-04 2017-06-27 Invensas Corporation Carrier-less silicon interposer using photo patterned polymer as substrate
US9693469B2 (en) 2013-12-19 2017-06-27 The Charles Stark Draper Laboratory, Inc. Electronic module subassemblies
EP3092661A4 (en) 2014-01-06 2017-09-27 Mc10, Inc. Encapsulated conformal electronic systems and devices, and methods of making and using the same
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
KR20160129007A (ko) 2014-03-04 2016-11-08 엠씨10, 인크 전자 디바이스를 위한 다부분 유연성 봉지 하우징
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9209110B2 (en) * 2014-05-07 2015-12-08 Qualcomm Incorporated Integrated device comprising wires as vias in an encapsulation layer
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
CA2957044A1 (en) * 2014-09-22 2016-03-31 Mc10, Inc. Methods and apparatuses for shaping and looping bonding wires that serve as stretchable and bendable interconnects
USD781270S1 (en) 2014-10-15 2017-03-14 Mc10, Inc. Electronic device having antenna
CN104326441B (zh) * 2014-11-05 2016-03-23 中国科学院电子学研究所 Soi片过孔内金属焊盘的制作方法
US9735084B2 (en) * 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
CN104538377A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种基于载体的扇出封装结构及其制备方法
CN104505384A (zh) * 2014-12-30 2015-04-08 华天科技（西安）有限公司 一种键合线埋入扇入型封装件及其制备方法
KR101651905B1 (ko) * 2015-02-17 2016-09-09 (주)파트론 칩 패키지와 베젤부의 결합구조물
EP3258837A4 (en) 2015-02-20 2018-10-10 Mc10, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation
US9888579B2 (en) * 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
CN104835747A (zh) * 2015-04-02 2015-08-12 苏州晶方半导体科技股份有限公司 一种芯片封装方法
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
JP6392171B2 (ja) * 2015-05-28 2018-09-19 新光電気工業株式会社 半導体装置及びその製造方法
WO2017015000A1 (en) 2015-07-17 2017-01-26 Mc10, Inc. Conductive stiffener, method of making a conductive stiffener, and conductive adhesive and encapsulation layers
TWI620296B (zh) * 2015-08-14 2018-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
WO2017031129A1 (en) 2015-08-19 2017-02-23 Mc10, Inc. Wearable heat flux devices and methods of use
KR102357937B1 (ko) * 2015-08-26 2022-02-04 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
KR102372349B1 (ko) 2015-08-26 2022-03-11 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US10096958B2 (en) * 2015-09-24 2018-10-09 Spire Manufacturing Inc. Interface apparatus for semiconductor testing and method of manufacturing same
WO2017059215A1 (en) 2015-10-01 2017-04-06 Mc10, Inc. Method and system for interacting with a virtual environment
US10532211B2 (en) 2015-10-05 2020-01-14 Mc10, Inc. Method and system for neuromodulation and stimulation
US10490528B2 (en) * 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) * 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
DE102015118664B4 (de) * 2015-10-30 2024-06-27 Infineon Technologies Ag Verfahren zur herstellung eines leistungshalbleitermoduls
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9666560B1 (en) 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
US10083894B2 (en) * 2015-12-17 2018-09-25 International Business Machines Corporation Integrated die paddle structures for bottom terminated components
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
CN105514057B (zh) * 2016-01-15 2017-03-29 气派科技股份有限公司 高密度集成电路封装结构以及集成电路
US20200066676A1 (en) * 2016-02-05 2020-02-27 Hewlett Packard Enterprise Development Lp Dual in-line memory module
WO2017147052A1 (en) 2016-02-22 2017-08-31 Mc10, Inc. System, devices, and method for on-body data and power transmission
CN108781313B (zh) 2016-02-22 2022-04-08 美谛达解决方案公司 用以贴身获取传感器信息的耦接的集线器和传感器节点的系统、装置和方法
US11154235B2 (en) 2016-04-19 2021-10-26 Medidata Solutions, Inc. Method and system for measuring perspiration
TWI590349B (zh) * 2016-04-27 2017-07-01 南茂科技股份有限公司 晶片封裝體及晶片封裝製程
CN105972018B (zh) * 2016-06-21 2019-06-21 新沂市承翔电子有限公司 一种智能工业点胶控制方法
CN105972017B (zh) * 2016-06-21 2019-01-18 黄伟 一种自动控制点胶方法
CN105952749B (zh) * 2016-06-21 2019-03-08 浙江东吴宏伟网络技术有限公司 一种指纹识别模块点胶方法
US9991233B2 (en) * 2016-07-22 2018-06-05 Invensas Corporation Package-on-package devices with same level WLP components and methods therefor
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10447347B2 (en) 2016-08-12 2019-10-15 Mc10, Inc. Wireless charger and high speed data off-loader
US10631410B2 (en) 2016-09-24 2020-04-21 Apple Inc. Stacked printed circuit board packages
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN106876363A (zh) * 2017-03-13 2017-06-20 江苏长电科技股份有限公司 3d连接的扇出型封装结构及其工艺方法
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US10707635B2 (en) * 2017-05-15 2020-07-07 Current Lighting Solutions, Llc Method for providing a wire connection to a printed circuit board
IT201700055983A1 (it) 2017-05-23 2018-11-23 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti
US20190206827A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Semiconductor package with externally accessible wirebonds
US10672693B2 (en) 2018-04-03 2020-06-02 Intel Corporation Integrated circuit structures in package substrates
CN108878382A (zh) * 2018-06-01 2018-11-23 江苏长电科技股份有限公司 一种具有电磁屏蔽的封装结构及其工艺方法
US10593647B2 (en) * 2018-06-27 2020-03-17 Powertech Technology Inc. Package structure and manufacturing method thereof
US10854476B2 (en) * 2018-08-06 2020-12-01 Sj Semiconductor (Jiangyin) Corporation Semiconductor vertical wire bonding structure and method
US20200083132A1 (en) 2018-09-07 2020-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US11437322B2 (en) 2018-09-07 2022-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10872866B2 (en) * 2018-10-08 2020-12-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US11239400B1 (en) * 2020-01-08 2022-02-01 Facebook Technologies, Llc Curved pillar interconnects
TWI767243B (zh) * 2020-05-29 2022-06-11 矽品精密工業股份有限公司 電子封裝件
KR20220000087A (ko) * 2020-06-25 2022-01-03 삼성전기주식회사 전자 소자 모듈
JP2022033633A (ja) 2020-08-17 2022-03-02 キオクシア株式会社 半導体装置
JP2022112923A (ja) 2021-01-22 2022-08-03 キオクシア株式会社 半導体装置およびその製造方法
CN113345860B (zh) * 2021-06-03 2022-09-09 长江存储科技有限责任公司 芯片封装结构及其制造方法
US20230115846A1 (en) * 2021-10-13 2023-04-13 Skyworks Solutions, Inc. Electronic Package and Method for Manufacturing an Electronic Package
US20230197585A1 (en) * 2021-12-20 2023-06-22 Infineon Technologies Ag Semiconductor package interconnect and power connection by metallized structures on package body
JP2023122330A (ja) * 2022-02-22 2023-09-01 キオクシア株式会社 半導体装置およびその製造方法
TWI822634B (zh) * 2022-07-20 2023-11-11 強茂股份有限公司 晶圓級晶片尺寸封裝方法
TWI830388B (zh) * 2022-09-19 2024-01-21 大陸商芯愛科技（南京）有限公司 電子封裝件之製法及其承載結構

Family Cites Families (818)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2230663A (en) 1940-01-18 1941-02-04 Alden Milton Electric contact and wire assembly mechanism
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3430835A (en) 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5150661A (zh) * 1974-10-30 1976-05-04 Hitachi Ltd
US4072816A (en) 1976-12-13 1978-02-07 International Business Machines Corporation Integrated circuit package
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4213556A (en) 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) * 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS59189069U (ja) 1983-06-02 1984-12-14 昭和アルミニウム株式会社 冷却装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4667267A (en) 1985-01-22 1987-05-19 Rogers Corporation Decoupling capacitor for pin grid array package
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
JPS61269345A (ja) 1985-05-24 1986-11-28 Hitachi Ltd 半導体装置
JP2608701B2 (ja) 1985-09-19 1997-05-14 三菱電機株式会社 保護装置の点検回路
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPH07122787B2 (ja) 1986-09-30 1995-12-25 カシオ計算機株式会社 連綿文字作成装置
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
JPS6412769A (en) 1987-07-07 1989-01-17 Sony Corp Correction circuit for image distortion
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
AU637874B2 (en) 1990-01-23 1993-06-10 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
CA2034703A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
US5238173A (en) 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
US7368924B2 (en) * 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
JPH06333931A (ja) 1993-05-20 1994-12-02 Nippondenso Co Ltd 半導体装置における微細電極の製造方法
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6741085B1 (en) 1993-11-16 2004-05-25 Formfactor, Inc. Contact carriers (tiles) for populating larger substrates with spring contacts
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US5578869A (en) 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5679954A (en) 1994-11-14 1997-10-21 Soloman; Sabrie Non-destructive identification of tablet and tablet dissolution by means of infared spectroscopy
KR20030096425A (ko) * 1994-11-15 2003-12-31 폼팩터, 인크. 인터포저
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
JP2833522B2 (ja) 1995-04-27 1998-12-09 日本電気株式会社 半導体装置
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH1012769A (ja) 1996-06-24 1998-01-16 Ricoh Co Ltd 半導体装置およびその製造方法
JP3537447B2 (ja) 1996-10-29 2004-06-14 トル‐シ・テクノロジーズ・インコーポレイテッド 集積回路及びその製造方法
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) * 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US5736785A (en) 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (ja) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd キャプスタンモータ
WO1999009595A1 (en) 1997-08-19 1999-02-25 Hitachi, Ltd. Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP3262531B2 (ja) * 1997-10-02 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 曲げられたフライング・リード・ワイヤ・ボンデイング・プロセス
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) * 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) * 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) * 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
US6255126B1 (en) 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
US6926796B1 (en) 1999-01-29 2005-08-09 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
JP2000323516A (ja) 1999-05-14 2000-11-24 Fujitsu Ltd 配線基板の製造方法及び配線基板及び半導体装置
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6238949B1 (en) 1999-06-18 2001-05-29 National Semiconductor Corporation Method and apparatus for forming a plastic chip on chip package module
JP4367730B2 (ja) 1999-06-25 2009-11-18 株式会社エンプラス Ｉｃソケット及び該ｉｃソケットのバネ手段
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP5333337B2 (ja) 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US6319764B1 (en) 1999-08-25 2001-11-20 Micron Technology, Inc. Method of forming haze-free BST films
EP2081419B1 (en) 1999-09-02 2013-08-07 Ibiden Co., Ltd. Printed circuit board and method of manufacturing printed circuit board
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001319992A (ja) 2000-02-28 2001-11-16 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
US6581276B2 (en) 2000-04-04 2003-06-24 Amerasia International Technology, Inc. Fine-pitch flexible connector, and method for making same
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6395199B1 (en) 2000-06-07 2002-05-28 Graftech Inc. Process for providing increased conductivity to a material
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
JP2002050871A (ja) 2000-08-02 2002-02-15 Casio Comput Co Ltd ビルドアップ回路基板およびその製造方法
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP2002076250A (ja) 2000-08-29 2002-03-15 Nec Corp 半導体装置
US6614103B1 (en) 2000-09-01 2003-09-02 General Electric Company Plastic packaging of LED arrays
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6538336B1 (en) 2000-11-14 2003-03-25 Rambus Inc. Wirebond assembly for high-speed integrated circuits
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6472743B2 (en) 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
KR100401020B1 (ko) 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
EP1387412B1 (en) 2001-04-12 2009-03-11 Matsushita Electric Works, Ltd. Light source device using led, and method of producing same
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6486545B1 (en) 2001-07-26 2002-11-26 Amkor Technology, Inc. Pre-drilled ball grid array package
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
JP3895952B2 (ja) 2001-08-06 2007-03-22 日本電気株式会社 半透過型液晶表示装置及びその製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
WO2003019654A1 (en) 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
SG117395A1 (en) 2001-08-29 2005-12-29 Micron Technology Inc Wire bonded microelectronic device assemblies and methods of manufacturing same
US6864166B1 (en) 2001-08-29 2005-03-08 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
US6787926B2 (en) 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6476506B1 (en) 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2005506690A (ja) 2001-10-09 2005-03-03 テッセラ，インコーポレイテッド 積層パッケージ
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
JP2003197668A (ja) 2001-12-10 2003-07-11 Senmao Koochii Kofun Yugenkoshi 半導体パッケージ用のボンディングワイヤ及びその製造方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW548816B (en) 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
DE10209922A1 (de) 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
JP2003318327A (ja) 2002-04-22 2003-11-07 Mitsui Chemicals Inc プリント配線板および積層パッケージ
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
JP4601892B2 (ja) 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US7943436B2 (en) 2002-07-29 2011-05-17 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
AU2003265417A1 (en) 2002-08-16 2004-03-03 Tessera, Inc. Microelectronic packages with self-aligning features
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US20040041757A1 (en) 2002-09-04 2004-03-04 Ming-Hsiang Yang Light emitting diode display module with high heat-dispersion and the substrate thereof
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
EP1556894A4 (en) 2002-09-30 2009-01-14 Advanced Interconnect Tech Ltd THERMALLY IMPROVED SEALING FOR SINGLE-LOCKING ASSEMBLY
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
KR20050074961A (ko) 2002-10-08 2005-07-19 치팩, 인코포레이티드 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
US20050176233A1 (en) 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
JP2004200316A (ja) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd 半導体装置
US20050161814A1 (en) 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
JP2006518944A (ja) 2003-02-25 2006-08-17 テッセラ，インコーポレイテッド バンプを有するボールグリッドアレー
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP2004327855A (ja) 2003-04-25 2004-11-18 Nec Electronics Corp 半導体装置およびその製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
JP2005093551A (ja) 2003-09-12 2005-04-07 Genusion:Kk 半導体装置のパッケージ構造およびパッケージ化方法
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
JP3999720B2 (ja) 2003-09-16 2007-10-31 沖電気工業株式会社 半導体装置およびその製造方法
US7061096B2 (en) * 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
WO2005031863A1 (en) 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
US8970049B2 (en) 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
JP3917133B2 (ja) 2003-12-26 2007-05-23 株式会社東芝 インターフェイスモジュール付ｌｓｉパッケージ及びそれに用いるインターポーザ、インターフェイスモジュール、接続モニタ回路、信号処理ｌｓｉ
US6917098B1 (en) * 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
WO2005065207A2 (en) 2003-12-30 2005-07-21 Tessera, Inc. Microelectronic packages and methods therefor
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP3956965B2 (ja) 2004-09-07 2007-08-08 日立エーアイシー株式会社 チップ部品型発光装置及びそのための配線基板
US7290448B2 (en) 2004-09-10 2007-11-06 Yamaha Corporation Physical quantity sensor, lead frame, and manufacturing method therefor
CN1755929B (zh) 2004-09-28 2010-08-18 飞思卡尔半导体（中国）有限公司 形成半导体封装及其结构的方法
US7595548B2 (en) 2004-10-08 2009-09-29 Yamaha Corporation Physical quantity sensor and manufacturing method therefor
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP4671802B2 (ja) 2004-10-18 2011-04-20 富士通株式会社 めっき方法、半導体装置の製造方法及び回路基板の製造方法
US20060087013A1 (en) 2004-10-21 2006-04-27 Etron Technology, Inc. Stacked multiple integrated circuit die package assembly
EP2014406A3 (de) 2004-11-02 2010-06-02 HID Global GmbH Verlegevorrichtung, Kontaktiervorrichtung, Zustellsystem, Verlege- und Kontaktiereinheit Herstellungsanlage, Verfahren zur herstellung und eine Transpondereinheit
JP5592055B2 (ja) 2004-11-03 2014-09-17 テッセラ，インコーポレイテッド 積層パッケージングの改良
TW200631111A (en) 2004-11-04 2006-09-01 Koninkl Philips Electronics Nv Nanotube-based circuit connection approach
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
JP4917257B2 (ja) 2004-11-12 2012-04-18 浜松ホトニクス株式会社 レーザ加工方法
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
US7301770B2 (en) 2004-12-10 2007-11-27 International Business Machines Corporation Cooling apparatus, cooled electronic module, and methods of fabrication thereof employing thermally conductive, wire-bonded pin fins
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
KR100843137B1 (ko) 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100867038B1 (ko) 2005-03-02 2008-11-04 삼성전기주식회사 커패시터 내장형 인쇄회로기판 및 그 제조방법
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US20060216868A1 (en) 2005-03-25 2006-09-28 Advanced Semiconductor Engineering Inc. Package structure and fabrication thereof
US7582963B2 (en) 2005-03-29 2009-09-01 Texas Instruments Incorporated Vertically integrated system-in-a-package
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7528474B2 (en) 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
US20100078795A1 (en) 2005-07-01 2010-04-01 Koninklijke Philips Electronics, N.V. Electronic device
TWI294757B (en) 2005-07-06 2008-03-11 Delta Electronics Inc Circuit board with a through hole wire, and forming method thereof
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
JP4787559B2 (ja) 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7355289B2 (en) 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US20070080360A1 (en) 2005-10-06 2007-04-12 Url Mirsky Microelectronic interconnect substrate and packaging techniques
KR101241650B1 (ko) 2005-10-19 2013-03-08 엘지이노텍 주식회사 엘이디 패키지
US8810031B2 (en) 2005-10-26 2014-08-19 Industrial Technology Research Institute Wafer-to-wafer stack with supporting pedestal
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
EP1946364A1 (en) 2005-11-01 2008-07-23 Koninklijke Philips Electronics N.V. Methods of packaging a semiconductor die and package formed by the methods
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7378726B2 (en) 2005-12-28 2008-05-27 Intel Corporation Stacked packages with interconnecting pins
JP4530984B2 (ja) 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
WO2007083351A1 (ja) 2006-01-17 2007-07-26 Spansion Llc 半導体装置およびその製造方法
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007201254A (ja) 2006-01-27 2007-08-09 Ibiden Co Ltd 半導体素子内蔵基板、半導体素子内蔵型多層回路基板
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
TWI295115B (en) 2006-02-13 2008-03-21 Ind Tech Res Inst Encapsulation and methods thereof
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7876180B2 (en) 2006-03-09 2011-01-25 Kyocera Corporation Waveguide forming apparatus, dielectric waveguide forming apparatus, pin structure, and high frequency circuit
JP4949719B2 (ja) 2006-04-07 2012-06-13 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
JP4821849B2 (ja) 2006-04-10 2011-11-24 株式会社村田製作所 複合基板及び複合基板の製造方法
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
DE102006022360B4 (de) 2006-05-12 2009-07-09 Infineon Technologies Ag Abschirmvorrichtung
US7910385B2 (en) 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
US7780064B2 (en) * 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US7967062B2 (en) * 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
US20070290325A1 (en) * 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
WO2008014633A1 (en) 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
JP2008016688A (ja) 2006-07-07 2008-01-24 Elpida Memory Inc 半導体装置の製造方法
US7612638B2 (en) 2006-07-14 2009-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Waveguides in integrated circuits
SG139573A1 (en) 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
JP5132101B2 (ja) 2006-07-27 2013-01-30 新光電気工業株式会社 スタックパッケージ構造体及びその製造に用いる単体パッケージと、それらの製造方法
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
KR100809696B1 (ko) 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US20080042265A1 (en) 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
US7560360B2 (en) 2006-08-30 2009-07-14 International Business Machines Corporation Methods for enhancing trench capacitance and trench capacitor
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
US7683460B2 (en) 2006-09-22 2010-03-23 Infineon Technologies Ag Module with a shielding and/or heat dissipating element
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
US7659617B2 (en) 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
US7537962B2 (en) 2006-12-22 2009-05-26 Stats Chippac Ltd. Method of fabricating a shielded stacked integrated circuit package system
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
KR100757345B1 (ko) * 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20090008796A1 (en) 2006-12-29 2009-01-08 United Test And Assembly Center Ltd. Copper on organic solderability preservative (osp) interconnect
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR100827667B1 (ko) 2007-01-16 2008-05-07 삼성전자주식회사 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
KR101057368B1 (ko) 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
WO2008108970A2 (en) 2007-03-05 2008-09-12 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
US20080217708A1 (en) 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
JP5010316B2 (ja) 2007-03-16 2012-08-29 日本電気株式会社 金属ポストを有する配線基板、半導体装置
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
US8183684B2 (en) 2007-03-23 2012-05-22 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
TWI335070B (en) 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8198716B2 (en) 2007-03-26 2012-06-12 Intel Corporation Die backside wire bond technology for single or stacked die package
US20100103634A1 (en) 2007-03-30 2010-04-29 Takuo Funaya Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
US20080246126A1 (en) 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US7800916B2 (en) 2007-04-09 2010-09-21 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080280393A1 (en) 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
TWI371809B (en) 2007-06-04 2012-09-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
US7872335B2 (en) 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
TW200908819A (en) 2007-06-15 2009-02-16 Ngk Spark Plug Co Wiring substrate with reinforcing member
US7576415B2 (en) 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR101329355B1 (ko) 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
KR101365621B1 (ko) 2007-09-04 2014-02-24 서울반도체 주식회사 열 방출 슬러그들을 갖는 발광 다이오드 패키지
JP2009064966A (ja) 2007-09-06 2009-03-26 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法ならびに半導体装置
US7808439B2 (en) 2007-09-07 2010-10-05 University Of Tennessee Reserch Foundation Substrate integrated waveguide antenna array
US9330945B2 (en) 2007-09-18 2016-05-03 Stats Chippac Ltd. Integrated circuit package system with multi-chip module
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR100902128B1 (ko) 2007-09-28 2009-06-09 삼성전기주식회사 방열 인쇄회로기판 및 반도체 칩 패키지
CN101874296B (zh) 2007-09-28 2015-08-26 泰塞拉公司 利用成对凸柱进行倒装芯片互连
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
KR101572600B1 (ko) 2007-10-10 2015-11-27 테세라, 인코포레이티드 다층 배선 요소와 마이크로전자 요소가 실장된 어셈블리
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
FR2923081B1 (fr) 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
GB0721957D0 (en) 2007-11-08 2007-12-19 Photonstar Led Ltd Ultra high thermal performance packaging for optoelectronics devices
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
CA2706092C (en) 2007-11-19 2014-08-19 Nexxus Lighting, Inc. Apparatus and methods for thermal management of light emitting diodes
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) * 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US7696631B2 (en) 2007-12-10 2010-04-13 International Business Machines Corporation Wire bonding personalization and discrete component attachment on wirebond pads
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US7706144B2 (en) 2007-12-17 2010-04-27 Lynch Thomas W Heat dissipation system and related method
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US20090166873A1 (en) 2007-12-27 2009-07-02 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor device package and method of the same
JP4989614B2 (ja) 2007-12-28 2012-08-01 サムソン エルイーディー カンパニーリミテッド． 高出力ｌｅｄパッケージの製造方法
US8048720B2 (en) 2008-01-30 2011-11-01 Kulicke And Soffa Industries, Inc. Wire loop and method of forming the wire loop
US20090194829A1 (en) 2008-01-31 2009-08-06 Shine Chung MEMS Packaging Including Integrated Circuit Dies
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
US8018065B2 (en) 2008-02-28 2011-09-13 Atmel Corporation Wafer-level integrated circuit package with top and bottom side electrical connections
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US8525214B2 (en) 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
JP5195903B2 (ja) 2008-03-31 2013-05-15 株式会社村田製作所 電子部品モジュール及び該電子部品モジュールの製造方法
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
CN102067310B (zh) 2008-06-16 2013-08-21 泰塞拉公司 带有边缘触头的晶片级芯片规模封装的堆叠及其制造方法
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
DE102008048420A1 (de) 2008-06-27 2010-01-28 Qimonda Ag Chip-Anordnung und Verfahren zum Herstellen einer Chip-Anordnung
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
SG158823A1 (en) 2008-07-18 2010-02-26 United Test & Assembly Ct Ltd Packaging structural member
EP2752872B1 (en) 2008-07-31 2018-06-27 Skyworks Solutions, Inc. Semiconductor package with integrated interference shielding and method of manufacture thereof
US8923004B2 (en) 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US7800810B2 (en) 2008-08-06 2010-09-21 Spatial Photonics, Inc. Packaging and testing of multiple MEMS devices on a wafer
TW201007924A (en) 2008-08-07 2010-02-16 Advanced Semiconductor Eng Chip package structure
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8237257B2 (en) 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
US8569892B2 (en) 2008-10-10 2013-10-29 Nec Corporation Semiconductor device and manufacturing method thereof
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) * 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
KR101015651B1 (ko) 2008-12-05 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
JP2010135671A (ja) 2008-12-08 2010-06-17 Panasonic Corp 半導体装置及びその製造方法
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US8115283B1 (en) 2009-07-14 2012-02-14 Amkor Technology, Inc. Reversible top/bottom MEMS package
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
JP5471605B2 (ja) 2009-03-04 2014-04-16 日本電気株式会社 半導体装置及びその製造方法
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
DE102009001461A1 (de) 2009-03-11 2010-09-16 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US20110068478A1 (en) 2009-03-26 2011-03-24 Reza Argenty Pagaila Integrated circuit packaging system with package stacking and method of manufacture thereof
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US8053814B2 (en) 2009-04-08 2011-11-08 International Business Machines Corporation On-chip embedded thermal antenna for chip cooling
JP2010251483A (ja) 2009-04-14 2010-11-04 Renesas Electronics Corp 半導体装置およびその製造方法
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) * 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20120153444A1 (en) 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US8183678B2 (en) 2009-08-04 2012-05-22 Amkor Technology Korea, Inc. Semiconductor device having an interposer
US20110209908A1 (en) 2009-08-06 2011-09-01 Advanced Chip Engineering Technology Inc. Conductor package structure and method of the same
KR101124102B1 (ko) 2009-08-24 2012-03-21 삼성전기주식회사 발광 소자 패키지용 기판 및 이를 포함하는 발광 소자 패키지
EP2290686A3 (en) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Method to perform electrical testing and assembly of electronic devices
US7923304B2 (en) * 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TW201123387A (en) 2009-12-25 2011-07-01 xiang-hua Wang Thermal-electric separated metal PCB with a chip carrier.
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
TWI395312B (zh) 2010-01-20 2013-05-01 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
JP5550369B2 (ja) 2010-02-03 2014-07-16 新日鉄住金マテリアルズ株式会社 半導体用銅ボンディングワイヤとその接合構造
JP2011166051A (ja) * 2010-02-15 2011-08-25 Panasonic Corp 半導体装置及び半導体装置の製造方法
US7990711B1 (en) 2010-02-24 2011-08-02 International Business Machines Corporation Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8558392B2 (en) 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8288854B2 (en) 2010-05-19 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for making the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US20120001336A1 (en) 2010-07-02 2012-01-05 Texas Instruments Incorporated Corrosion-resistant copper-to-aluminum bonds
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
JP5713598B2 (ja) 2010-07-20 2015-05-07 新光電気工業株式会社 ソケット及びその製造方法
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8076184B1 (en) 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8354297B2 (en) 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US8080445B1 (en) 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US8349735B2 (en) 2010-09-22 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive TSV with insulating annular ring
US8415704B2 (en) 2010-09-22 2013-04-09 Ut-Battelle, Llc Close-packed array of light emitting devices
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
JP5616739B2 (ja) 2010-10-01 2014-10-29 新日鉄住金マテリアルズ株式会社 複層銅ボンディングワイヤの接合構造
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
CN102024782B (zh) 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
JP5591653B2 (ja) 2010-10-27 2014-09-17 東和精工株式会社 ラベル剥離機
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
JPWO2012067177A1 (ja) 2010-11-17 2014-05-12 株式会社フジクラ 配線板及びその製造方法
KR20120056052A (ko) 2010-11-24 2012-06-01 삼성전자주식회사 반도체 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
US8772817B2 (en) 2010-12-22 2014-07-08 Cree, Inc. Electronic device submounts including substrates with thermally conductive vias
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8766436B2 (en) 2011-03-01 2014-07-01 Lsi Corporation Moisture barrier for a wire bond
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8841765B2 (en) 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US9508622B2 (en) 2011-04-28 2016-11-29 Freescale Semiconductor, Inc. Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8633059B2 (en) 2011-05-11 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8669646B2 (en) 2011-05-31 2014-03-11 Broadcom Corporation Apparatus and method for grounding an IC package lid for EMI reduction
US9128123B2 (en) 2011-06-03 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US9117811B2 (en) 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
US9006031B2 (en) 2011-06-23 2015-04-14 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
KR20130007049A (ko) 2011-06-28 2013-01-18 삼성전자주식회사 쓰루 실리콘 비아를 이용한 패키지 온 패키지
US8476770B2 (en) 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US8988895B2 (en) 2011-08-23 2015-03-24 Tessera, Inc. Interconnection elements with encased interconnects
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
KR101900423B1 (ko) 2011-09-19 2018-09-21 삼성전자주식회사 반도체 메모리 장치
EP2769409A1 (en) 2011-10-03 2014-08-27 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20130087915A1 (en) 2011-10-10 2013-04-11 Conexant Systems, Inc. Copper Stud Bump Wafer Level Package
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US9196588B2 (en) 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US8916781B2 (en) 2011-11-15 2014-12-23 Invensas Corporation Cavities containing multi-wiring structures and devices
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
TWI464031B (zh) 2011-12-14 2014-12-11 Univ Yuan Ze 抑制柯肯達爾孔洞形成於銲料與銅銲墊之間的方法
KR101924388B1 (ko) 2011-12-30 2018-12-04 삼성전자주식회사 재배선 구조를 갖는 반도체 패키지
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
KR20130090143A (ko) 2012-02-03 2013-08-13 삼성전자주식회사 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법
US8742576B2 (en) 2012-02-15 2014-06-03 Oracle International Corporation Maintaining alignment in a multi-chip module using a compressible structure
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
DE102012203293B4 (de) 2012-03-02 2021-12-02 Robert Bosch Gmbh Halbleitermodul mit integriertem Wellenleiter für Radarsignale
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
KR20130111780A (ko) 2012-04-02 2013-10-11 삼성전자주식회사 Ｅｍｉ 차폐부를 갖는 반도체 장치
US9405064B2 (en) 2012-04-04 2016-08-02 Texas Instruments Incorporated Microstrip line of different widths, ground planes of different distances
US8922005B2 (en) 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8978247B2 (en) 2012-05-22 2015-03-17 Invensas Corporation TSV fabrication using a removable handling structure
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US20130323409A1 (en) 2012-05-31 2013-12-05 Skyworks Solutions, Inc. Systems and methods for controlling electromagnetic interference for integrated circuit modules
US8948712B2 (en) 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8742597B2 (en) 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US8642393B1 (en) 2012-08-08 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of forming same
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US8963339B2 (en) 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9418971B2 (en) 2012-11-08 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure including a thermal isolation material and method of forming the same
US9412661B2 (en) 2012-11-21 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming package-on-package structure
US9401338B2 (en) 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US20140175657A1 (en) 2012-12-21 2014-06-26 Mihir A. Oka Methods to improve laser mark contrast on die backside film in embedded die packages
US8729714B1 (en) 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
US8907500B2 (en) 2013-02-04 2014-12-09 Invensas Corporation Multi-die wirebond packages with elongated windows
US20140225248A1 (en) 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
US9209081B2 (en) 2013-02-21 2015-12-08 Freescale Semiconductor, Inc. Semiconductor grid array package
US20140239479A1 (en) 2013-02-26 2014-08-28 Paul R Start Microelectronic package including an encapsulated heat spreader
US20140239490A1 (en) 2013-02-26 2014-08-28 Unimicron Technology Corporation Packaging substrate and fabrication method thereof
US9461025B2 (en) 2013-03-12 2016-10-04 Taiwan Semiconductor Manfacturing Company, Ltd. Electric magnetic shielding structure in packages
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9419667B2 (en) 2013-04-16 2016-08-16 Skyworks Solutions, Inc. Apparatus and methods related to conformal coating implemented with surface mount devices
KR20140126598A (ko) 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
RU2602746C2 (ru) 2013-06-28 2016-11-20 ИНТЕЛ АйПи КОРПОРЕЙШН Микроэлектромеханическая система (mems) на специализированной интегральной схеме (asic)
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
KR102161173B1 (ko) 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9012263B1 (en) 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
US9379078B2 (en) 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
KR101631934B1 (ko) 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR20150091932A (ko) 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9196586B2 (en) 2014-02-13 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including an embedded surface mount device and method of forming the same
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9437459B2 (en) 2014-05-01 2016-09-06 Freescale Semiconductor, Inc. Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure
US20150340305A1 (en) 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US10325876B2 (en) 2014-06-25 2019-06-18 Nxp Usa, Inc. Surface finish for wirebonding
JP6471162B2 (ja) 2014-07-15 2019-02-13 富士フイルム株式会社 検知システムおよび検知方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
KR101640341B1 (ko) 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9653428B1 (en) 2015-04-14 2017-05-16 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI712123B (zh) * 2015-10-22 2020-12-01 美商艾馬克科技公司 半導體裝置及其製造方法
US12100655B2 (en) 2022-05-17 2024-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits having signal lines formed with double patterning

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US11735563B2 (en) 2023-08-22
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