JP2009237573A - El表示装置 - Google Patents
El表示装置 Download PDFInfo
- Publication number
- JP2009237573A JP2009237573A JP2009107627A JP2009107627A JP2009237573A JP 2009237573 A JP2009237573 A JP 2009237573A JP 2009107627 A JP2009107627 A JP 2009107627A JP 2009107627 A JP2009107627 A JP 2009107627A JP 2009237573 A JP2009237573 A JP 2009237573A
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- Prior art keywords
- region
- film
- tft
- insulating film
- gate
- Prior art date
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- Granted
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Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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Abstract
【解決手段】第1のチャネル形成領域と、第1のソース領域及び第1のドレイン領域と、ゲート絶縁膜と、第1のゲート電極とを備えた第1のTFTと、第2のチャネル形成領域と、第2のソース領域及び第2のドレイン領域と、ゲート絶縁膜と、第2のゲート電極とを備えた第2のTFTと、第1のTFT及び第2のTFT上に設けられた第1の絶縁膜と、第1のソース領域及び第1のドレイン領域の一方と接続されたソース配線と、第1のソース領域及び第1のドレイン領域の他方と接続し、且つ第2のゲート電極に接続された第1のドレイン配線と、第1の絶縁膜上に設けられ、第2のソース領域及び第2のドレイン領域の一方に接続された第2のドレイン配線と、第1の絶縁膜上に設けられ、第2のソース領域及び第2のドレイン領域の他方に接続された電流供給線と、を有する。
【選択図】図26
Description
で構成された回路を有する半導体装置およびその作製方法に関する。特に本発明は、画素部(画素マトリクス回路)とその周辺に設けられる駆動回路(ドライバー回路)を同一基板上に設けた液晶表示装置やEL(エレクトロルミネッセンス)表示装置に代表される電気光学装置(電子装置ともいう)、および電気光学装置を搭載した電気器具(電子機器ともいう)に関する。
電圧が印加されるが、駆動回路のTFTは基本的に逆バイアス電圧が印加されて動作されることはない。また、前者の動作速度は後者の1/100以下で良い。
この低濃度不純物領域112は、後にCMOS回路のnチャネル型TFTに、ゲート絶縁膜を介してゲート配線と重なるLDD領域(本明細書中ではこのLDD領域をLov領域と呼ぶ。なお、ovとはoverlapの意味である。)を形成するための不純物領域である。なお、ここで形成された低濃度不純物領域に含まれるn型を付与する不純物元素の濃度を(n-)で表すこととする。従って、本明細書中では低濃度不純物領域112をn-領域と言い換えることができる。
このときゲート配線130はn-領域112とゲート絶縁膜107を介して重なるように形成した。
)
)
を行っても良い。(図8(B))
これは上記回路群の場合、ソース領域とドレイン領域の機能が変わらず、キャリア(電子)の移動する方向が一定だからである。但し、必要に応じてチャネル形成領域の両側にLov領域を配置することもできる。
さらに、本実施例のように画素TFT上に形成される遮光膜を保持容量の一方の電極とすることで、アクティブマトリクス型液晶表示装置の画像表示部の開口率を向上させることができた。
の結晶性を改善するための工程について説明する。まず、実施例8〜10のいずれかの工程に従って活性層を形成する。但し、本実施例ではTFTを形成する基板として800〜1150℃の温度に耐えうる基板を用いる材料を用いる必要がある。そのような基板としては、石英基板、金属基板、シリコン基板、セラミックス基板(セラミックスガラス基板も含む)が挙げられる。
によってスピン密度の差となって現れる。現状では本実施例の作製工程に従って作製された結晶質珪素膜のスピン密度は少なくとも 5×1017spins/cm3以下(好ましくは 3×1017spins/cm3以下)であることが判明している。ただし、この測定値は現存する測定装置の検出限界に近いので、実際のスピン密度はさらに低いと予想される。
本実施例の活性層を用いたTFTは、MOSFETに匹敵する電気特性を示した。本出願人が試作したTFT(但し、活性層の膜厚は30nm、ゲート絶縁膜の膜厚は100nm)からは次に示す様なデータが得られている。
(2)TFTの動作速度の指標となる電界効果移動度(μFE)が、Nチャネル型TFTで 200〜650cm2/Vs (代表的には 300〜500cm2/Vs )、Pチャネル型TFTで100〜300cm2/Vs(代表的には 150〜200cm2/Vs)と大きい。
(3)TFTの駆動電圧の指標となるしきい値電圧(Vth)が、Nチャネル型TFTで-0.5〜1.5 V、Pチャネル型TFTで-1.5〜0.5 Vと小さい。
の工程でnチャネル型TFTのp++領域の端部にもリンが添加されるようにすれば、実施例12のゲッタリング工程を行うことが可能である。
の工程(pチャネル型TFTのゲート配線とp++領域の形成工程)を行わずに、図7(B)と同様にnチャネル型TFTのゲート配線およびその他の接続配線を形成する。なお、図21(A)では図7(B)と同一の符号を用いている。但し、pチャネル型TFTとなる領域に関しては、レジストマスク2101を形成して、後にpチャネル型TFTのゲート配線となる導電膜2102を残す。
しかし、本発明の効果は残りの18通り全てにおいて得られるため、どの順序で不純物領域を形成するのであっても良い。
、負電源2(−9.6V)とし、ゲート線駆動回路のシフトレジスタの電源を正電源(9.6V)、負電源1(−2.4V)、負電源2(−11.0V)として85℃大気中の環境で動作させている。
即ち、駆動回路と画素部を同じ電源電圧で動作させることが可能となり、液晶表示装置全体の低消費電力化を図ることができる。
これらの有機EL材料や無機材料は公知の材料を用いることができる。
本発明は液晶表示装置2502に用いることができ、本願発明の半導体回路はCPUやメモリ等に用いることができる。
に示した光源光学系は光源を2つ用いたが、一つでも良いし、三つ以上としてもよい。また、光源光学系の光路のどこかに、光学レンズ、偏光機能を有するフィルム、位相差を調節するフィルムもしくはIRフィルム等を設けてもよい。
602a、602b 下地膜
603〜606 活性層
607 ゲート絶縁膜
612〜614 n-領域
615 第1の導電膜
616 第2の導電膜
618 第3の導電膜
626、639、640、641 ゲート配線
625、627 接続配線
631、632 p++領域
647〜653 n+領域または(n++n-)領域
654〜657 n--領域
663 保護絶縁膜
664 層間絶縁膜
665〜668 ソース配線
669〜672 ドレイン配線
673、674 接続配線
675 パッシベーション膜
676 第2の層間絶縁膜
677 遮光膜
678 酸化物
679〜681 画素電極
682 保持容量
701、704、708、713、714 チャネル形成領域
702、705、709、715 ソース領域
703、706、710、716 ドレイン領域
707、711a、712a Lov領域
711b、712b、717〜720 Loff領域
721 n+領域
Claims (5)
- 基板上に複数の画素を有し、前記複数の画素はそれぞれ、
前記基板上に第1のチャネル形成領域と、第1のソース領域及び第1のドレイン領域と、前記第1のチャネル形成領域、前記第1のソース領域及び前記第1のドレイン領域上に設けられたゲート絶縁膜と、前記ゲート絶縁膜上に設けられた第1のゲート電極とを備えたスイッチング用TFTと、
前記基板上に第2のチャネル形成領域と、第2のソース領域及び第2のドレイン領域と、前記第2のチャネル形成領域、前記第2のソース領域及び前記第2のドレイン領域上に設けられたゲート絶縁膜と、前記ゲート絶縁膜上に設けられた第2のゲート電極とを備えた電流制御用TFTと、
前記スイッチング用TFT及び前記電流制御用TFT上に設けられた第1の絶縁膜と、
前記スイッチング用TFTの前記第1のソース領域及び前記第1のドレイン領域の一方と接続されたソース配線と、
前記スイッチング用TFTの前記第1のソース領域及び前記第1のドレイン領域の他方と接続し、且つ前記電流制御用TFTの前記第2のゲート電極に接続された第1のドレイン配線と、
前記第1の絶縁膜上に設けられ、前記電流制御用TFTの前記第2のソース領域及び前記第2のドレイン領域の一方に接続された第2のドレイン配線と、
前記第1の絶縁膜上に設けられ、前記電流制御用TFTの前記第2のソース領域及び前記第2のドレイン領域の他方に接続された電流供給線と、
前記ソース配線、前記第1のドレイン配線、前記第2のドレイン配線及び前記電流供給線上に設けられた第2の絶縁膜と、
前記第2の絶縁膜上の設けられ、前記第2のドレイン配線と接続した第1の電極と、
前記第1の電極上に設けられたEL層と、
前記EL層上に設けられた第2の電極と、
前記電流供給線に電気的に接続された半導体層と、前記ゲート絶縁膜と、前記電流制御用TFTの前記第2のゲート電極からなる保持容量と、を有し、
前記保持容量は、前記電流供給線と重畳することを特徴とするEL表示装置。 - 請求項1に記載の第1のゲート電極は、トリプルゲートであることを特徴とするEL表示装置。
- 請求項1または2において、前記スイッチング用TFTは、低濃度不純物領域を有することを特徴とするEL表示装置。
- 請求項3に記載の低濃度不純物領域は、前記ゲート絶縁膜を介して前記第1のゲート電極と重畳しないことを特徴とするEL表示装置。
- 請求項1乃至4のいずれか一に記載の電流制御用TFTは、低濃度不純物領域が設けられていないことを特徴とするEL表示装置。
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