CN106575666B - 超结金属氧化物半导体场效应晶体管 - Google Patents
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Abstract
用于超结MOSFET的边缘终端。根据本发明的实施例,超结金属氧化物半导体场效应晶体管(MOSFET)包括核心超结区,所述核心超结区包括耦连至超结MOSFET的源端的多个平行的核心板。超结MOSFET还包括围绕核心超结区的终端区,所述终端区包括多个分离的浮置的终端部分,所述终端部分被配置为对核心超结区施加击穿而不对终端区施加击穿。每个终端部分具有比核心板的长度尺寸更小的长度尺寸。
Description
相关申请
本申请要求于2014年8月19日递交的、代理机构案号为VISH-8822.pro、序列号为62/039,346、帕塔纳亚克(Pattanayak)的题为“具有板的SJMOSFET的新边缘终端(New EdgeTermination for SJMOSFETs with Plates)”的美国临时专利申请的优先权,该申请特此通过引用全部并入本文中。
领域
本技术的实施例涉及集成电路设计和制造领域。更具体地,本技术的实施例涉及用于超结(super-junction)MOSFET的终端(termination)的系统和方法。
背景
超结金属氧化物半导体场效应晶体管(MOSFET)包括由N型和P型区组成的漂移区。超结MOSFET主要依赖于维持漂移区中N区和P区之间的一定的电荷关系。总之,漂移区中的板型结构在体积上显示了较小的制造变化,因此与柱型结构(例如,采用圆形或椭圆形横截面)相比总电荷变化较小。因此,与柱型结构相比,在漂移区中包括板型结构的器件通常呈现出对期望的电荷关系的改进的控制。出于此原因,对于超结MOSFET的漂移区来说,板型结构相比柱型结构是优选的。
然而,板型区域在感测方面具有方向性不对称性,其在一个方向上板是浮置的,而在另一垂直维度上,它们呈现(assume)出源极电势处于非常低的电流。此特征要求终端方案的开发受到电荷平衡要求的约束。
发明内容
因此,需要用于超结MOSFET的边缘终端的系统和方法。存在对超结MOSFET的边缘终端的具有在减小的距离上的增大的击穿电压的额外需要。还需要用于超结MOSFET的边缘终端的系统和方法,所述超结MOSFET包括在漂移区中的板型结构。还存在对用于超结MOSFET的边缘终端的系统和方法的又一需要,所述系统和方法与已有的集成电路设计、制造和测试的系统和方法兼容且是其补充。本技术的实施例提供这些优点。
根据本技术的实施例,超结金属氧化物半导体场效应晶体管(MOSFET)包括核心超结区,其包括耦连至所述超结MOSFET的源端的多个平行的核心板。超结MOSFET还包括终端区,其围绕所述核心超结区,包括多个分离的浮置的终端部分,所述终端部分被配置为对所述核心超结区施加击穿且不对所述终端区施加击穿。每个终端部分具有比所述核心板的长度尺寸更小的长度尺寸。
根据本技术的另一实施例,超结金属氧化物半导体场效应晶体管(MOSFET)包括形成于第一导电类型的衬底中、在所述MOSFET的有源区下面的核心区。所述核心区包括:多个第二导电类型的平行的核心板,所述核心板耦连至所述MOSFET的源端,所述板的每一个具有板宽度。所述核心板与宽度大约为所述板宽度的所述第一导电性的区域相交替。所述MOSFET还包括围绕所述核心区的终端区。所述终端区包括形成于所述衬底中的所述第二导电类型的多个分离的浮置的终端部分,所述终端部分彼此由所述第一导电类型的区域分离开。所述终端部分的每一个具有比所述核心板的长度尺寸更小的长度尺寸。所述终端区被配置为具有比所述核心区更高的击穿电压。
根据本技术的又一实施例,垂直沟槽MOSFET包括第一导电性的衬底,和下到所述衬底表面以下的多个栅极沟槽。每个栅极沟槽包括所述MOSFET的一个或多个栅极。例如,沟槽可包括有源栅和可选地屏蔽栅,其可耦连至源极。垂直沟槽MOSFET还包括位于所述栅极沟槽之间的台面上的MOSFET的源极区和体区以及在所述栅极沟槽下面并在所述源极区和体区下面的漂移区。所述漂移区包括多个第二导电性的核心板,与所述第一导电性的区域相交替,其中所述核心板被耦连至所述MOSFET的所述源极区。垂直沟槽MOSFET还包括围绕所述漂移区的终端区,与所述漂移区处于大约相同的深度。所述终端区包括形成于所述衬底中的所述第二导电性的多个分离的浮置的终端部分,所述终端部分彼此由所述第一导电类型的区域分离开。在所述终端区之上没有所述MOSFET的栅极,并且所述终端部分的每一个具有不大于所述核心板的长度尺寸的长度尺寸。
附图的简要说明
随附的附图,其并入并形成本说明书的一部分,与说明书一起例示了该技术的实施例,用于解释该技术的原理。除非另有注释,否则附图并未按比例绘制。
图1例示了根据本技术的实施例的、超结MOSFET的示例性边缘终端的平面图。
图2例示了根据本技术的实施例的终端部分的示例性设计。
图3例示了根据本技术的实施例的、超结MOSFET的示例性边缘终端的平面图。
具体实施方式
现在详细参考该技术的多个实施例,其示例在随附的附图中例示。虽然该技术将结合这些实施例进行描述,但应理解,它们并不意图被限制为这些实施例。相反,该技术意图覆盖替代、修改和等同物,其可包括在如由附属的权利要求所限定的该技术的精神和范围内。而且,在该技术的下面的详细描述中,详细阐述了多个具体细节,以便提供对该技术的详尽的理解。然而,本领域普通技术人员将认识到,该技术可在没有这些具体细节的情况下被实践。在其他例子中,公知的方法、程序、部件和电路未被详细描述,以不对本技术的方面多余地遮蔽。
符号和术语
附图并未按比例绘制,且仅仅结构的某些部分以及形成那些结构的多个层可在图中示出。而且,制造工艺和操作可随本文所讨论的工艺和操作一起执行;即在本文所示出和描述的操作之前、之间和/或之后可具有多个工艺操作。重要的是,根据本技术的实施例可连同这些其他(可能是常规的)工艺和操作一起被实现,而不严重扰乱它们。一般来说,根据本技术的实施例可替代和/或补充常规工艺的部分而不严重影响外围工艺和操作。
如本文所使用的,字母“n”指的是n型掺杂,而字母“p”指的是p型掺杂。加号“+”或减号“-”分别用于表示该掺杂浓度相对高或相对低。
术语“沟道”在本文中以可接受方式被使用。即,电流在FET的沟道内从源极连接移动到漏极连接。沟道可由n型或p型半导体材料组成;因此,FET指的是n沟道或p沟道器件。附图中的一些在n沟道器件的上下文中讨论,更具体地为n沟道垂直MOSFET;然而,根据本技术的实施例并不如此限制。即,本文描述的特征可用于p沟道器件。对n沟道器件的讨论可通过用p型掺杂和材料替代相应的n型掺杂和材料而容易映射到p沟道器件,反之亦可。此外,根据本技术的实施例很好地适于平面栅超结MOSFET。
术语“沟槽”已得到半导体领域内的两种不同的但相关的意思。通常,当涉及工艺时,例如刻蚀,术语沟槽用于意指或指的是材料的空隙,例如,孔或沟。通常,这种孔的长度比它的宽度或深度大得多。然而,当涉及半导体结构或器件时,术语沟槽用于意指或指的是布置在衬底表面下方的、具有不同于衬底的复杂组合物并且通常邻近场效应晶体管(FET)的沟道的固体垂直对准结构。该结构包括例如FET的栅极。因此,沟槽半导体器件通常包括台式结构(其并不是沟槽)和部分,例如两个邻近结构的“沟槽”的一半。
要理解,虽然通常被称为“沟槽”的半导体结构可通过刻蚀沟槽并且然后填充沟槽来形成,但本文中关于本技术的实施例的结构术语的使用并不暗指且不限制于该工艺。
用于超结MOSFET的边缘终端
超结MOSFET中的边缘终端的一个功能是以不给源极金属施加高于空气的电离电势的方式逐渐降低从源极电势到漏极电势的电势。源极到漏极的电势可以是大约600伏特或更大。
图1例示了根据本技术的实施例的、超结MOSFET 100的示例性边缘终端的平面图。图1的闭合形状指示p型材料,例如,n型外延层中的p型材料。应理解,p型区之间和周围的区域通常是n型材料。终端区110包括围绕核心区120的终端板112和多个终端部分(segment)114。p型终端板112和终端部分114是浮置的。在一些实施例中,具有比示例性的三行终端板112和终端部分114更多或更少的终端板和终端部分。
核心区120通常在有源器件(例如MOSFET)下方,且通常比终端区110的面积大得多。核心区120中的p型核心板122通常耦连至源极电极,例如,它们处于源极电势。例如,通常具有比所例示的更多的核心板122。核心板122、终端板112和终端部分114具有大致相同的垂直深度和垂直广度(extent),例如,在垂直于图1的平面的平面中。
终端部分114优选地是正方形的,例如,它们的宽度等于它们的长度,虽然并未要求如此。终端板112应是矩形的,例如它们的长度大于它们的宽度。总之,终端板112应是与核心区120内的p板122相同的长度并且平行对准核心区120内的p板122。部分114和板112的宽度不一定相同。
终端板112和终端部分114的数目和它们的间距由期望的超结MOSFET的源极到漏极电势来确定。在硅中,1μm的间距中可支持大约10伏特。对于600伏特器件,由p型结构彼此之间的间隙(终端板112和/或终端部分114之间的n型材料)所耗费的总间距大约应为40μm,例如支持大约400伏特。应理解的是,间距不必是规则(regular)的。假设p型结构的宽度为每个5μm,支持大约50伏特,则需要8个这种部分来支持400伏特。因此,对于所描述类型的800伏特的边缘终端,边缘终端的宽度可以低至80μm。根据传统领域,对于600伏特边缘终端,商业可用的产品需要大约230μm。
根据本技术的实施例,终端板112和终端部分114和中间部分间距应以这种方式被设计,所述方式中设置电荷平衡条件以便所有部分大多被耗尽并且边缘终端的击穿电压稍微高于核心区的击穿电压。这将改进器件的非钳位感应开关(UIS)能力。
然而,边缘部分完全被耗尽并不是必须的。部分的耗尽层应彼此融合并支持水平和垂直维度(在图1的视图中)两者的电压。围绕核心区的部分可设计为不同于核心板,以便边缘的击穿电压稍微高于核心的击穿电压,例如向核心区施加击穿并且不向终端区施加击穿。
根据本技术的实施例,部分间距和宽度可根据下面的关系式1进行设计:
δQn~2δQp (关系式1)
其中,δQn是终端部分之间的间隙中的电荷,并且δQp是P板部分中的附加电荷,由于相对于核心板的宽度做了其更大的宽度。
根据本技术的实施例,超结MOSFET可有利地具有电荷不平衡,例如,在终端区中,p型材料的电荷不等于n型材料的电荷。例如,Qp≠Qn。根据本技术的实施例,对于用n型材料形成的n沟道MOSFET,例如,n型外延层,n型材料的电荷可稍微大于p型材料的电荷,例如,Qp<Qn。终端击穿电压应高于核心击穿电压,这些两个区域之间具有不同的电荷不平衡性。
图2例示了根据本技术的实施例的、例如与图1的终端部分114相对应的终端部分的示例性设计200。图2并未按比例绘制。图2例示了例如与图1的核心板122相对应的核心板的部分222。核心板部分222具有宽度尺寸224。应理解,可以不例示核心板部分222的完整水平长度。
图2还例示了例如与图1的终端部分114相对应的多个终端部分214。终端部分214比核心板222宽。增加的宽度提供与核心板具有相同宽度(224)的终端部分相比增加的电荷2δQp(220)。终端部分214彼此之间间隔距离210,其提供δQn的电荷(210)。因此,满足关系式1的条件。
应理解,尺寸210和220根据该区域可用的电荷进行例示。实际的物理尺寸是n型和p型材料两者的掺杂浓度以及核心板222的宽度的函数。如之前呈现的,终端部分214的数目和它们的间距210是终端区中期望的击穿电压的函数。
以此新颖的方式,满足电荷平衡条件,以便所有终端部分214大部分被耗尽并且边缘终端的击穿电压稍微高于核心区域的击穿电压,因此改进了器件的非钳位感应开关(UIS)能力。
图3例示了根据本技术的实施例的、超结MOSFET 300的示例性边缘终端310的平面图。图3的闭合形状指示p型材料,例如,n型外延层中的p型材料。应理解,p型区之间和周围的区域通常是n型材料。与图1相反,终端区310包括所有部分区,例如,终端区中没有板区。终端区310包括围绕核心区320的多个终端部分314。p型终端部分314是浮置的。在一些实施例中,可能有比示例性的3行终端部分314更多或更少的终端部分。
核心区320通常在有源器件(例如,MOSFET)下方,且通常比终端区310的面积大得多。核心区120中的p型核心板322通常耦连至源极电极,例如,它们处于源极电势。例如,通常将具有比所例示的多得多的核心板322。
终端部分314优选地是正方形的,例如,它们的宽度等于它们的长度,虽然并未要求如此。终端部分314和核心板322的宽度并不一定相同。终端部分314和/或核心板322的角可以是如所例示的圆形,以增加击穿电压。应理解,这种圆形并非如此极端以将部分的形状减小至柱形的圆形。例如,圆形角的半径应比横跨部分的对角线距离的一半小得多。此外,在一些实施例中,角终端部分(例如角终端部分350)可设计为不同于将电荷与场分布关联起来的静电考虑所要求的边缘单元。例如,角终端部分350可被缩放,以使终端部分314的阵列包括圆形的“角”,如由终端区310的角中的虚线所指示的。
终端板312的数目、它们的宽度和它们的间距都由期望的超结MOSFET的源极到漏极电势来确定,如之前关于图1和图2所呈现的。
以此新颖的方式,多个分离浮置的终端部分被配置为远离终端区在核心超结区施加击穿。因此,核心超结区将在终端区之前被击穿,从而为期望的漏源电压提供有效的终端。
根据本技术的实施例提供了用于具有自对准体接触的沟槽金属氧化物半导体场效应晶体管(MOSFET)的系统和方法。此外,根据本技术的实施例提供了具有自对准体接触的、用于沟槽MOSFET的系统和方法,所述自对准体接触在体接触注入和栅极沟槽之间具有增加的分离。而且,根据本技术的实施例提供了具有自对准体接触的、用于沟槽MOSFET的系统和方法,所述自对准体接触具有更精细的例如更小的栅间间距尺寸的改进的性能。而且,根据本技术的实施例提供了具有自对准体接触的、用于沟槽MOSFET的系统和方法,所述自对准接触与已有的集成电路设计、制造和测试的系统和方法兼容并且是其补充。
因此描述了本技术的多个实施例。虽然本技术已用特定实施例进行了描述,但应理解,该技术不应被解释为由这种实施例进行限制,而是根据下面的权利要求进行解释。
广泛来说,此文至少公开了用于超结MOSFET的边缘终端。根据本发明的实施例,超结金属氧化物半导体场效应晶体管(MOSFET)包括核心超结区,其包括耦连至超结MOSFET的源端的多个平行的核心板。超结MOSFET还包括围绕核心超结区的终端区,其包括配置为对核心超结区施加击穿而不对终端区施加击穿的多个分离浮置的终端部分。每个终端部分的长度尺寸小于核心板的长度尺寸。
本文描述的所有元件、部分和步骤优选地被包括。应理解,任何这些元件、部分和步骤都可由其他元件、部分和步骤替代或由于对于本领域技术人员来说是明显的而被全部删除。
概念:
此文公开了至少下面的概念。
概念1:一种超结金属氧化物半导体场效应晶体管(MOSFET),包括:
核心超结区,所述核心超结区包括耦连至所述超结MOSFET的源端的多个平行的核心板;以及
终端区,所述终端区围绕所述核心超结区,所述终端区包括多个分离的浮置的终端部分,所述终端部分被配置为远离所述终端区在所述核心超结区内施加击穿,
其中,所述终端部分的每一个具有比所述核心板的长度尺寸更小的长度尺寸。
概念2:如概念1所述的超结MOSFET,包括沟槽栅极。
概念3:如概念1或2所述的超结MOSFET,包括平面栅极。
概念4:如概念1到3所述的超结MOSFET,其中所述终端区的电荷平衡在所述终端部分的载流子类型中更少富集。
概念5:如概念1到4所述的超结MOSFET,其中所述终端部分比所述核心板宽。
概念6:如概念5所述的超结MOSFET,其中由于所述终端部分的宽度相比所述核心板的宽度增加而导致的所述终端部分增加的电荷大致等于所述终端部分之间的材料中相反电荷的量值。
概念7:如概念1到6所述的超结MOSFET,其中所述终端区在宽度尺寸为80微米时达到800伏特的击穿电压。
概念8:一种金属氧化物半导体场效应晶体管(MOSFET),包括:
核心区,所述核心区形成于第一导电类型的衬底中、在所述MOSFET的有源区下面,所述核心区包括:
多个第二导电类型的平行的核心板,所述核心板耦连至所述MOSFET的源端,所述板的每一个具有板宽度;
所述核心板与宽度大约为所述板宽度的所述第一导电性的区域相交替;
终端区,所述终端区围绕所述核心区,包括:
形成于所述衬底中的多个所述第二导电类型的分离的浮置终端部分,所述终端部分彼此由所述第一导电类型的区域分离开,
其中,所述终端部分的每一个具有比所述核心板的长度尺寸更小的长度尺寸,以及
其中,所述终端区被配置为具有比所述核心区更高的击穿电压。
概念9:如概念8所述的MOSFET,其中所述核心板在所述MOSFET的栅极的水平面之下。
概念10:如概念8或9所述的MOSFET,其中所述核心板的垂直深度和垂直广度与所述终端部分的垂直深度和垂直广度大致相同。
概念11:如概念8到10所述的MOSFET,其中所述终端部分比所述核心板宽。
概念12:如概念11所述的MOSFET,其中一个所述终端部分的电荷大约等于将所述终端部分与邻近的终端部分分离开的区域中的电荷的量值。
概念13:如概念8到12所述的MOSFET,其中在所述终端区中第一导电性的电荷多于所述第二导电性的电荷。
概念14:一种垂直沟槽MOSFET,包括:
第一导电性的衬底;
多个栅极沟槽,多个栅极沟槽下到所述衬底表面下方以下,
其中,每个栅极沟槽包括所述MOSFET的一个或多个栅极;
所述MOSFET的源极区和体区位于所述栅极沟槽之间的台面上;
漂移区,所述漂移区在所述栅极沟槽下面并在所述源极区和体区下面,所述漂移区包括:
多个第二导电性的核心板,与所述第一导电性的区域相交替,其中所述核心板被耦连至所述MOSFET的所述源极区;
终端区,所述终端区围绕所述漂移区,与所述漂移区处于大约相同的深度,所述终端区包括:
形成于所述衬底中的所述第二导电性的多个分离的浮置终端部分,所述终端部分彼此由所述第一导电性的区域分离开,
其中,在所述终端区之上没有所述MOSFET的栅极,以及
其中,所述终端部分的每一个具有不大于所述核心板的长度尺寸的长度尺寸。
概念15:如概念14所述的MOSFET,其中所述终端部分比所述核心板宽。
概念16:如概念14或15所述的MOSFET,其中一个所述终端部分的电荷大约等于将所述终端部分与邻近的终端部分分离开的区域中的电荷的量值。
概念17:如概念14到16所述的MOSFET,其中在所述终端区中第一导电性的电荷多于所述第二导电性的电荷。
概念18:如概念14到17所述的MOSFET,其中所述终端部分具有半径比它们的对角线尺寸小得多的圆角。
概念19:如概念14到18所述的MOSFET,其中在所述终端区的角处的终端部分的广度被减小以接近所述终端区的圆角。
概念20:一种超结金属氧化物半导体场效应晶体管(MOSFET),包括:核心超结区,所述核心超结区包括耦连至所述超结MOSFET的源端的多个平行的核心板;所述超结MOSFET还包括围绕所述核心超结区的终端区,其包括多个分离浮置的终端部分,所述终端部分被配置为向所述核心超结区施加击穿并且不向所述终端区施加击穿;每个终端部分具有比所述核心板的长度尺寸更小的长度尺寸。
Claims (19)
1.一种超结金属氧化物半导体场效应晶体管MOSFET,包括:
核心超结区,所述核心超结区包括耦连至所述超结MOSFET的源端的多个平行的核心板;以及
终端区,所述终端区围绕所述核心超结区,所述终端区包括多个分离的终端部分,所述终端部分被配置为远离所述终端区在所述核心超结区内施加击穿,
其中,所述终端区中的所有所述终端部分都是浮置的,
其中,所述终端部分彼此之间的间距以这种方式被设计,所述方式中设置电荷平衡条件以便所有终端部分大多被耗尽并且所述终端部分的击穿电压稍微高于所述核心超结区的击穿电压,以及
其中,所述终端部分的每一个具有比所述核心板的长度尺寸更小的长度尺寸。
2.如权利要求1所述的超结MOSFET,包括沟槽栅极。
3.如权利要求1所述的超结MOSFET,包括平面栅极。
4.如权利要求1所述的超结MOSFET,其中所述终端区的电荷平衡在所述终端部分的载流子类型中更少富集。
5.如权利要求1所述的超结MOSFET,其中所述终端部分比所述核心板宽。
6.如权利要求5所述的超结MOSFET,其中由于所述终端部分的宽度相比所述核心板的宽度增加而导致的所述终端部分增加的电荷等于所述终端部分之间的材料中相反电荷的量值。
7.如权利要求1所述的超结MOSFET,其中所述终端区在宽度尺寸为80微米时达到800伏特的击穿电压。
8.一种金属氧化物半导体场效应晶体管MOSFET,包括:
核心区,所述核心区形成于第一导电类型的衬底中、在所述MOSFET的有源区下面,所述核心区包括:
多个第二导电类型的平行的核心板,所述核心板耦连至所述MOSFET的源端,所述核心板的每一个具有板宽度;
所述核心板与宽度为所述板宽度的所述第一导电类型的区域相交替;
终端区,所述终端区围绕所述核心区,包括:
形成于所述衬底中的多个所述第二导电类型的分离的浮置的终端部分,所述终端部分彼此由所述第一导电类型的区域分离开,
其中,所述终端部分的每一个具有比所述核心板的长度尺寸更小的长度尺寸,
其中,所述终端部分彼此之间的间距以这种方式被设计,所述方式中设置电荷平衡条件以便所有终端部分大多被耗尽并且所述终端部分的击穿电压稍微高于所述核心区的击穿电压,以及
其中,所述终端区被配置为具有比所述核心区更高的击穿电压。
9.如权利要求8所述的MOSFET,其中所述核心板在所述MOSFET的栅极的水平面之下。
10.如权利要求8所述的MOSFET,其中所述核心板的垂直深度和垂直广度与所述终端部分的垂直深度和垂直广度相同。
11.如权利要求8所述的MOSFET,其中所述终端部分比所述核心板宽。
12.如权利要求11所述的MOSFET,其中一个所述终端部分的电荷等于将所述终端部分与邻近的终端部分分离开的区域中的电荷的量值。
13.如权利要求8所述的MOSFET,其中在所述终端区中第一导电类型的电荷多于所述第二导电类型的电荷。
14.一种垂直沟槽MOSFET,包括:
第一导电性的衬底;
多个栅极沟槽,所述多个栅极沟槽下到所述衬底表面以下,
其中,每个栅极沟槽包括所述垂直沟槽MOSFET的一个或多个栅极;
所述垂直沟槽MOSFET的源极区和体区位于所述栅极沟槽之间的台面上;
漂移区,所述漂移区在所述栅极沟槽下面并在所述源极区和体区下面,所述漂移区包括:
多个第二导电性的核心板,与所述第一导电性的区域相交替,其中所述核心板被耦连至所述垂直沟槽MOSFET的所述源极区;
终端区,所述终端区围绕所述漂移区,与所述漂移区处于相同的深度,所述终端区包括:
形成于所述衬底中的所述第二导电性的多个分离的浮置的终端部分,所述终端部分彼此由所述第一导电性的区域分离开,
其中,在所述终端区之上没有所述垂直沟槽MOSFET的栅极,
其中,所述终端部分彼此之间的间距以这种方式被设计,所述方式中设置电荷平衡条件以便所有终端部分大多被耗尽并且所述终端部分的击穿电压稍微高于所述核心板的击穿电压,以及
其中,所述终端部分的每一个具有不大于所述核心板的长度尺寸的长度尺寸。
15.如权利要求14所述的垂直沟槽MOSFET,其中所述终端部分比所述核心板宽。
16.如权利要求14所述的垂直沟槽MOSFET,其中一个所述终端部分的电荷等于将所述终端部分与邻近的终端部分分离开的区域中的电荷的量值。
17.如权利要求14所述的垂直沟槽MOSFET,其中在所述终端区中第一导电性的电荷多于所述第二导电性的电荷。
18.如权利要求14所述的垂直沟槽MOSFET,其中所述终端部分具有半径比它们的对角线尺寸小得多的圆角。
19.如权利要求14所述的垂直沟槽MOSFET,其中在所述终端区的角处的终端部分的广度被减小以接近所述终端区的圆角。
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WO2016028944A1 (en) | 2016-02-25 |
US10340377B2 (en) | 2019-07-02 |
EP3183754A1 (en) | 2017-06-28 |
KR20170042596A (ko) | 2017-04-19 |
CN106575666A (zh) | 2017-04-19 |
KR102098996B1 (ko) | 2020-04-08 |
US9882044B2 (en) | 2018-01-30 |
EP3183754A4 (en) | 2018-05-02 |
US20170250247A1 (en) | 2017-08-31 |
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