CN203800053U - 半导体器件及包括该半导体器件的集成装置 - Google Patents

半导体器件及包括该半导体器件的集成装置 Download PDF

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CN203800053U
CN203800053U CN201320675145.2U CN201320675145U CN203800053U CN 203800053 U CN203800053 U CN 203800053U CN 201320675145 U CN201320675145 U CN 201320675145U CN 203800053 U CN203800053 U CN 203800053U
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semiconductor device
integrating
resilient coating
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U.瓦尔
A.维尔梅罗特
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Infineon Technologies Austria AG
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Abstract

本实用新型提供一种半导体器件及包括该半导体器件的集成装置。该半导体器件包括：衬底；在所述衬底上的缓冲层；补偿区，所述补偿区包括位于所述缓冲层上的p区和n区；以及位于所述补偿区上的晶体管单元，所述晶体管单元包括源区、体区、栅电极、以及至少在栅电极和体区之间形成的栅极电介质。所述栅极电介质具有在12nm到50nm的范围内的厚度。

Description

半导体器件及包括该半导体器件的集成装置
技术领域
本实用新型涉及半导体器件及包括该半导体器件的集成装置，尤其涉及一种具有逻辑电平阈值电压的超结器件及包括该超结器件的集成装置。 
背景技术
超结器件采用的想法是通过在通态电流路径的区域附近添加相反极性的电荷来补偿剩余电荷以实现非常地的特定RDSon值。一般用于垂直器件的结构采用垂直的n掺杂柱和p掺杂柱，通过沟槽刻蚀和再填充来形成所述n掺杂柱和p掺杂柱，或者通过多次外延布置来形成所述n掺杂柱和p掺杂柱。 
这种非常低的特定RDSon值使得能够实现非常小的器件面积（标准MOSFET的w/r），形成非常快速的开关器件（低电容CGD, CGS, CDS）。快速开关是例如开关模式电源中的非常低的开关损耗的基础，近年来开关模式电源已经明显提高了效率。 
为了具有充足的抗噪性，现有的超结器件的栅极阈值电压在3.5V到5V的范围内，达到完全导通时栅极电压为大约10V到12V。 
这阻碍了进一步的效率改善，因为开关速度和由此的开关损耗与完全导通所需的电压摆幅密切相关。 
现有解决方案采用Vth > 3.5V，其缺点是： 
- 比较低栅极阈值电压的开关损耗高；
- 较高的驱动损耗；具有较低栅极阈值电压的器件可以被相同的驱动电流驱动得更快得多或者在较小的驱动功率下以相同的速度被驱动；
- 现有的功率器件不能直接利用TTL或CMOS级驱动；它们需要升压器/电平移动器级。
图2a示出了现有的PFC（Power Factor Correction，功率因子校正）级20，其使用具有正常电平阈值电压（例如Vth=3V-5V）的功率MOSFET 22。该解决方案需要在控制器24之后产生PWM用于电压/电流控制另一升压器级26，该升压器级26在适当的电流电平下产生在10V-15V的范围内的栅极电压用于功率MOSFET 22。尽管使用了该另一升压器级26，该解决方案通常需要另一电压域（例如20V-30V）来供给升压器26并且支持驱动功率MOSFET 22。然而，这意味着在附加的器件成本、面积和较高损耗方面要付出更多。 
类似的例子在图3a中示出。图3a示出了反激拓扑结构（Flyback topology）30，其使用具有正常电平阈值电压（例如，Vth=3-5V）的现有功率MOSFET 32。该解决方案需要在控制器34之后产生PWM用于电压/电流控制另一升压器级36，该升压器级36在适当的电流电平下产生在10V-15V的范围内的栅极电压用于功率MOSFET 32。尽管使用了该另一升压器级36，该解决方案通常需要另一电压域（例如20V-30V）来供给升压器36并且支持驱动功率MOSFET 32。然而，这意味着在附加的器件成本、面积和较高损耗方面要付出更多。 
因此，需要一种具有较低逻辑电平阈值电压同时还具有充足的抗噪性的结构。 
发明内容
本实用新型提出了实施1.2V-2V的逻辑电平Vth（优选为1.6V）用于超结MOSFET。这里，Vth是超结MOSFET的栅极阈值电压。对于这些器件，然后在VGS=4.5V下评定RDSon。然而，这些器件还应该能够承受得住大约10V的VGS电压以处理电压尖刺而不会产生栅极氧化物退化。该实施方式可以通过使用在12 nm到50 nm的范围内的适当厚度的栅极氧化物和经调整的沟道区掺杂水平来完成。 
为了改善可能得到的低抗噪性，还提出了将栅极驱动器和/或控制器级与功率MOSFET非常近地集成以最小化栅极环路。该集成可以单片地、逐个芯片地（chip-by-chip）或者以芯片上芯片(chip-on-chip)的形式来实现。 
这些措施通过降低开关损耗以及驱动损耗将会带来明显的效率改善。该方法还提供了设计优势，因为设计工程师不必要关心信号完整性并且通过更加集成化的方案获得了板上空间。 
因此，根据本实用新型的一个方面，提供一种半导体器件，其包括： 
衬底；
在所述衬底上的缓冲层；
补偿区，所述补偿区包括位于所述缓冲层上的p区和n区；以及
位于所述补偿区上的晶体管单元，所述晶体管单元包括源区、体区、栅电极、以及至少在栅电极和体区之间形成的栅极电介质，
其特征在于，所述栅极电介质具有在12 nm到50 nm的范围内的厚度。
在一些实施例中，所述半导体器件具有在1V-2V范围内的栅极阈值电压。 
在一些实施例中，所述半导体器件具有在1.2V-2V范围内的栅极阈值电压。 
在一些实施例中，所述半导体器件具有1.6V的栅极阈值电压。 
在一些实施例中，所述缓冲层具有比所述n区低的掺杂浓度。 
在一些实施例中，所述缓冲层具有朝向衬底增加的掺杂浓度。 
在一些实施例中，所述缓冲层包括所述衬底上的第一子层和第一子层上的第二子层，并且第二子层的掺杂高于第一子层的掺杂。 
在一些实施例中，所述缓冲层包括所述衬底上的第一部分和第一部分上的第二部分，并且第一部分具有朝向衬底增加的掺杂浓度。 
在一些实施例中，所述半导体器件是超结器件。 
根据本实用新型的另一个方面，提供一种集成装置，其包括： 
如上所述的半导体器件中的任何一个；和
与所述半导体器件集成在一起用于控制所述半导体器件的操作的控制器，
其中所述半导体器件直接被所述控制器驱动。
在一些实施例中，所述控制器与所述半导体器件单片地、逐个芯片地或者以芯片上芯片的形式集成。 
在一些实施例中，所述集成装置采用反激式拓扑结构。 
在一些实施例中，所述集成装置采用LLC拓扑结构。 
在一些实施例中，所述集成装置采用TTF拓扑结构。 
在一些实施例中，所述集成装置采用ZVS拓扑结构。 
在一些实施例中，所述集成装置采用PFC拓扑结构。 
附图说明
本实用新型的这些和其它特征和优点将通过以下参考附图的详细描述而变得明显，在附图中： 
图1示意性地示出根据本实用新型的超结晶体管的三个非限制性实例的截面图。
图2a示出了使用具有正常电平阈值电压的功率MOSFET的现有PFC级。 
图2b示出了根据本实用新型的一个实施例的使用具有逻辑电平阈值电压的超结MOSFET的PFC级。 
图3a示出了使用具有正常电平阈值电压的功率MOSFET的现有反激式变换器。 
图3b示出了根据本实用新型的一个实施例的使用具有逻辑电平阈值电压的超结MOSFET的反激式变换器。 
具体实施方式
现在将参考示出本实用新型的实施例的附图在下文中更全面地描述本实用新型的实施例。然而，本实用新型可以以许多不同的形式来具体实施并且不应该被解释为受限于本文所阐述的实施例。更确切地说，提供这些实施例是为了使该公开内容更彻底和完整，并且将向本领域技术人员全面地传达本实用新型的范围。遍及全文，相似的数字指代相似的元件。此外，附图中示出的各个层和区只是示意性的并且没有必要按比例绘制。因此本实用新型不限于附图中示出的相对大小、间距和对准。另外，正如本领域技术人员所认识的，本文提到的形成于衬底或其它层上的层可以指直接形成在衬底或其它层上的层，也可以指在衬底或其它层上形成的一个或多个居间层上的层。而且，术语“第一导电类型”和“第二导电类型”指的是相反的导电类型，例如N或P型，然而，这里所描述和示出的每个实施例也包括其互补实施例。 
在本文中所使用的术语仅仅为了描述特定实施例的目的并且不意图限制本实用新型。如本文所使用的那样，单数形式“一”、“一个”和“该”意图也包括复数形式，除非上下文以其它方式明确指示。还将理解，当在本文使用术语“包括”和/或“包含”时，其指定所叙述的特征、整体、步骤、操作、元件和/或部件的存在，但是不排除一个或多个其它特征、整体、步骤、操作、元件、部件和/或其组群的存在或添加。 
除非以其它方式限定，本文所使用的所有术语（包括技术和科学术语）具有与如本实用新型所属领域的技术人员通常理解的含义相同的含义。还将理解本文所使用的术语应该被解释为具有与它们在该说明书的背景以及相关领域中的含义一致的含义，并且将不会以理想化或过分形式的方式解释，除非在本文中明确如此限定。 
附图通过在掺杂类型“n”或“p”旁边指示“-”或“+”来说明相对掺杂浓度。例如，“n-”表示低于“n”掺杂区域的掺杂浓度的掺杂浓度，而“n+”掺杂区域具有比“n“掺杂区域高的掺杂浓度。相同的相对掺杂浓度的掺杂区域没有必要具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可以具有相同或不同的绝对掺杂浓度。 
图1示意性地示出根据本实用新型的超结晶体管的三个非限制性实例的截面图。示出了多种用于实现补偿区和可选缓冲区的可能性，其中p表示单元间距，w表示栅电极尺寸。这些实例并非限制性的，其可以以任何方式结合成不同的方案。为简单起见，仅一部分有源区，即，承载垂直负载电流的区域的截面被示出。而晶体管的其它部分，如边缘终止系统，划片区或者栅极连接并未在图1中明确示出。所示出的器件具有半导体本体，其具有补偿区，所述补偿区包括p区（p柱）130和n区（n柱）134，其中所述补偿，即在垂直方向上p柱和n柱之间的掺杂的差，既可以是均匀的也可以是可变的。 
所述补偿区被连接至MOS晶体管单元，MOS晶体管单元包括源区118，体区138和控制栅极114。在所示出的实例中，所述栅极被构建成位于所述半导体本体顶部的平面栅电极。然而，所述栅极也能够在刻蚀进所述半导体本体中的沟槽中实现。 
绝缘结构140，例如氧化物，将所述栅极114与所述体区138，所述源区118，所述n区（n柱）134以及金属化层110电隔离。并且，所述绝缘结构140在所述栅极114下面的那部分可用作栅极绝缘层。 
所述晶体管的漏极128连接至高掺杂的衬底124。可选缓冲层126可以位于所述衬底和所述补偿区之间。所述缓冲层具有与衬底相同的导电类型，但具有比该衬底更低浓度的掺杂。在垂直方向上所述缓冲层的掺杂可以是变化的。例如，图1中部所示的截面描绘了所述缓冲层中逐步变化的掺杂水平。例如，所述缓冲层可以包括多个子层，如第一子层（缓冲层1）和第二子层（缓冲层2），并且所述第二子层的掺杂可以高于所述第一子层的掺杂。又例如，图1右部所示的截面描绘了所述n区（n柱）134的掺杂沿着自所述绝缘结构140至所述缓冲层126的方向逐步增加和/或逐渐增加。根据一个实施例（图1中未示出），n区（n柱）的掺杂和/或p区（p柱）的掺杂可以沿着自所述绝缘结构140至所述缓冲层126的方向具有一个或多个局部掺杂最大量及一个或多个局部掺杂最小量。 
各源极接触通过所述金属化层110电相连，所述金属化层在芯片的顶面构建公共源极焊盘。各个单元栅极114通过多晶硅相连以在顶面构建与金属化部的公共栅极接触。并且因此，具有相同或不同的金属化部的两个电极（一个用于源极，另一个用于栅极）被设置在器件顶面并且借助例如硅氧化物或硅氮化物钝化层或者借助二者彼此隔离。所述漏极接触构建在器件的后部并且被超结器件的金属化部128覆盖。 
图2b示出根据本实用新型的一个实施例的使用具有逻辑电平阈值电压的超结MOSFET 222的PFC（功率因子校正）级200（在该图中，逻辑电平=LL）。 
与图2a的现有PFC级20相比，根据本实用新型的一个实施例的超结MOSFET 222具有在1-2V范围内的逻辑电平阈值电压，优选在1.2-2V范围内，更优选为1.6V。在这种情况下，PFC级200可以提供直接从控制器224的输出到超结MOSFET 222的容易的控制。在一个实施例中，PFC级200可以提供在3V到5V范围内的栅极电压用于超结MOSFET 222。根据本实用新型，在1-2V范围内的逻辑电平阈值电压可以通过使用超结MOSFET的适当厚度（例如在12 nm到50 nm的范围内）的栅极氧化物和经调整的沟道区掺杂水平来实现。因此，在本实施例中，由于超级MOSFET 222可以直接被控制器224驱动，因此可以省略如在图2a的现有PFC级20中使用的另一升压器级并由此可以省略另一电压域，从而可以节省器件成本和面积，可以降低器件开关损耗，并且可以改善器件的开关速度。 
类似的例子在图3b中示出，图3b示出了根据本实用新型的一个实施例的使用具有逻辑电平阈值电压的超结MOSFET 332的反激式变换器300（在该图中，逻辑电平=LL）。 
与图3a的现有反激式拓扑结构30相比，根据本实用新型的一个实施例的超结MOSFET 332具有在1-2V范围内的逻辑电平阈值电压，优选在1.2-2V范围内，更优选为1.6V。在这种情况下，反激式变换器300可以提供直接从控制器334的输出到超结MOSFET 332的容易的控制。在一个实施例中，反激式变换器300可以提供在3V到5V范围内的栅极电压用于超结MOSFET 332。根据本实用新型，在1-2V范围内的逻辑电平阈值电压可以通过使用超结MOSFET的适当厚度（例如在12 nm到50 nm的范围内）的栅极氧化物和经调整的沟道区掺杂水平来实现。因此，在本实施例中，由于超级MOSFET 332可以直接被控制器334驱动，因此可以省略如在图3a的现有反激式变换器30中使用的另一升压器级并由此可以省略另一电压域，从而可以节省器件成本和面积，可以降低器件开关损耗，并且可以改善器件的开关速度。 
这些例子并不是限制性的，并且还可以适用于其他AC/DC和DC/DC功率变换拓扑结构，例如LLC（其指的是由两个电感器和一个电容器构成的谐振环结构）拓扑结构, TTF（Two Transistor Forward，双晶体管正激）拓扑结构和ZVS（Zero Voltage Switching，零电压变换）拓扑结构。 
另一方面，根据本实用新型，为了改善可能得到的低抗噪性，栅极驱动器和/或控制器级可以与功率MOSFET非常近地集成以最小化栅极环路。该集成可以单片地、逐个芯片地或者以芯片上芯片的形式来实现。这些措施通过降低开关损耗以及驱动损耗将会带来明显的效率改善。该方法还提供了设计优势，因为设计工程师在更多集成方案的情况下或许不会留意信号完整性和增益板空间。 
尽管上文已经通过示例性实施例详细描述了本实用新型及其优点，但是本领域技术人员应当理解，在不脱离由所附权利要求限定的本实用新型的精神和范围的情况下，可以对本实用新型进行多种替换和变型。 
参考标记说明： 
110： 源极/金属
114：栅极
130：p柱
134：n柱
126：缓冲层
126-1： 缓冲层1
126-2：缓冲层2
124：衬底
128： 漏极/金属。

Claims (16)

1.一种半导体器件，包括：
衬底；
在所述衬底上的缓冲层；
补偿区，所述补偿区包括位于所述缓冲层上的p区和n区；以及
位于所述补偿区上的晶体管单元，所述晶体管单元包括源区、体区、栅电极、以及至少在栅电极和体区之间形成的栅极电介质，
其特征在于，所述栅极电介质具有在12 nm到50 nm的范围内的厚度。
2.根据权利要求1所述的半导体器件，其特征在于，所述半导体器件具有在1V-2V范围内的栅极阈值电压。
3.根据权利要求2所述的半导体器件，其特征在于，所述半导体器件具有在1.2V-2V范围内的栅极阈值电压。
4.根据权利要求1所述的半导体器件，其特征在于，所述半导体器件具有1.6V的栅极阈值电压。
5.根据权利要求1所述的半导体器件，其特征在于，所述缓冲层具有比所述n区低的掺杂浓度。
6.根据权利要求1所述的半导体器件，其特征在于，所述缓冲层具有朝向衬底增加的掺杂浓度。
7.根据权利要求1所述的半导体器件，其特征在于，所述缓冲层包括所述衬底上的第一子层和第一子层上的第二子层，并且第二子层的掺杂高于第一子层的掺杂。
8.根据权利要求1所述的半导体器件，其特征在于，所述缓冲层包括所述衬底上的第一部分和第一部分上的第二部分，并且第一部分具有朝向衬底增加的掺杂浓度。
9.根据权利要求1所述的半导体器件，其特征在于，所述半导体器件是超结器件。
10.一种集成装置，包括：
根据权利要求1-9中的任一项所述的半导体器件；和
与所述半导体器件集成在一起用于控制所述半导体器件的操作的控制器，
其中所述半导体器件直接被所述控制器驱动。
11.根据权利要求10所述的集成装置，其特征在于，所述控制器与所述半导体器件单片地、逐个芯片地或者以芯片上芯片的形式集成。
12.根据权利要求10或11所述的集成装置，其特征在于，所述集成装置采用反激式拓扑结构。
13.根据权利要求10或11所述的集成装置，其特征在于，所述集成装置采用LLC拓扑结构。
14.根据权利要求10或11所述的集成装置，其特征在于，所述集成装置采用TTF拓扑结构。
15.根据权利要求10或11所述的集成装置，其特征在于，所述集成装置采用ZVS拓扑结构。
16.根据权利要求10或11所述的集成装置，其特征在于，所述集成装置采用PFC拓扑结构。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110912411A (zh) * 2019-12-02 2020-03-24 刘业瑞 非对称异型上、下管有源钳位反激变换器

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
EP3183754A4 (en) 2014-08-19 2018-05-02 Vishay-Siliconix Super-junction metal oxide semiconductor field effect transistor
DE102017126853B4 (de) 2017-11-15 2019-11-21 Infineon Technologies Dresden Gmbh Halbleitervorrichtung mit Puffergebiet
CN116741812A (zh) * 2023-08-11 2023-09-12 深圳天狼芯半导体有限公司 一种基于n-bal提高电流密度的超结肖特基二极管及制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
DE10340131B4 (de) * 2003-08-28 2005-12-01 Infineon Technologies Ag Halbleiterleistungsbauteil mit Ladungskompensationsstruktur und monolithisch integrierter Schaltung, sowie Verfahren zu dessen Herstellung
US20090166729A1 (en) * 2007-12-27 2009-07-02 Infineon Technologies Austria Ag Power semiconductor having a lightly doped drift and buffer layer
US9013004B2 (en) * 2009-02-27 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Quasi-vertical structure having a sidewall implantation for high voltage MOS device
JP6024075B2 (ja) * 2010-07-30 2016-11-09 住友電気工業株式会社 半導体装置およびその製造方法
JP5777455B2 (ja) * 2011-09-08 2015-09-09 株式会社東芝 半導体装置および半導体装置の製造方法
US8648643B2 (en) * 2012-02-24 2014-02-11 Transphorm Inc. Semiconductor power modules and devices
JP5481605B2 (ja) * 2012-03-23 2014-04-23 パナソニック株式会社 半導体素子
JP2014038899A (ja) * 2012-08-13 2014-02-27 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
US8853743B2 (en) * 2012-11-16 2014-10-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Pseudomorphic high electron mobility transistor comprising doped low temperature buffer layer
US9564330B2 (en) * 2013-08-01 2017-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Normally-off enhancement-mode MISFET
US9245991B2 (en) * 2013-08-12 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing
CN203983264U (zh) * 2013-10-30 2014-12-03 英飞凌科技奥地利有限公司 半导体器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110912411A (zh) * 2019-12-02 2020-03-24 刘业瑞 非对称异型上、下管有源钳位反激变换器

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