CN203910808U - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN203910808U
CN203910808U CN201320675405.6U CN201320675405U CN203910808U CN 203910808 U CN203910808 U CN 203910808U CN 201320675405 U CN201320675405 U CN 201320675405U CN 203910808 U CN203910808 U CN 203910808U
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semiconductor device
gate electrode
interconnection
gate
grid
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A.毛德
U.瓦尔
W.凯因德尔
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Infineon Technologies Austria AG
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Abstract

本实用新型提供一种半导体器件，其包括：补偿区，其包括p区和n区；位于所述补偿区上的包括栅电极的多个晶体管单元；一个或多个用于电连接栅电极的互连，其中所述栅电极具有比所述单元的节距的1/2小的宽度。

Description

半导体器件
技术领域
本实用新型涉及一种半导体器件,尤其涉及一种超结器件。
背景技术
为了快速开关超结晶体管，期望的是具有低的栅极电荷。这将减少开关损耗，驱动损耗并且能够有助于驱动概念。例如，在驱动器之后用来给开关晶体管的栅极提供高峰值电流的升压器可以被省略。因此，可以节约开发成本，板的空间，冷却努力和额外的器件。
另一方面，超结晶体管的减小的栅极电荷减少所述晶体管开启和关断的延时。由于延时时间减少了控制回路中的相位裕量,具有较低延时的超结晶体管改善控制回路的稳定性。
很明显，小的栅极电荷对于超结晶体管是有益的。
超结晶体管的栅极电荷由栅源电容和栅漏电容主宰。因此，可以通过分别减小源极与栅极以及栅极与漏极之间的重叠区域来减小栅极电荷。此目标可以通过最小化所述超结器件的栅电极面积而实现。
减小的栅电极面积的主要缺点为栅电极的串联电阻由于其越小的横截面而升高。因此，超结晶体管的开关将变得不均匀。例如，与所述超结晶体管的栅极连接相邻的芯片区域的一部分已经对栅极电压的改变做出响应而与栅极连接（栅极焊盘）距离较远的芯片区域的部分仍然保持在它们以前的状态。这样延迟的并且非均匀的开关可能导致开关损耗变大，导致不稳定的开关甚至是导致振荡。
然而，通过增加电极的厚度，所述栅电极的横截面可能没有充分地增加，因为其在生产期间会在超结器件上导致增加的拓扑。这里，最大的电极厚度不能被超过以维持超结晶体管的可制造性。
需要这样一种结构，其能够通过同时提供栅电极的小的面积和小的内部栅极分布电阻器使得超结晶体管具有小的栅极电荷。
发明内容
本实用新型的目的在于解决以上问题中的一个或多个。
根据本实用新型的一个方面，提供一种半导体器件，其包括：
补偿区，其包括p区和n区；
位于所述补偿区上的包括栅电极的多个晶体管单元，
一个或多个用于电连接栅电极的互连，
其中所述栅电极具有比所述单元的节距的1/2小的宽度。
优选地，所述栅电极的宽度比所述单元的节距的1/3小。
优选地，所述栅电极包括多晶硅。
优选地，所述互连包括多晶硅。
优选地，至少一个所述互连与仅两个相邻的栅电极连接。
优选地，至少一个所述互连与多于两个栅电极连接。
优选地，所述半导体器件包括至少第一布线层和第二布线层。
优选地，所述第一布线层包括所述互连和所述栅电极。
优选地，所述第二布线层包括栅极条和栅极指中的至少一个和源极金属化部。
优选地，所述栅极条和栅极指中的至少一个通过栅极接触电连接至至少一个所述互连。
优选地，所述晶体管单元进一步包括源极区和本体区，并且所述源极金属化部通过插塞/源接触孔电连接至所述源极区和本体区。
优选地，所述晶体管单元为条形。
优选地，所述互连位于所述晶体管单元的端部。
优选地，所述栅电极连接至所述晶体管单元端部处的栅极环或连接至所述晶体管单元的互连处的栅极指。
优选地，所述互连以规则的距离布置在有源区中。
优选地，所述栅电极彼此相互平行。
优选地，所述栅电极具有平面结构。
优选地，所述栅电极至少部分地位于沟槽中。
优选地，所述互连被实施为桥。
优选地，所述互连至少部分地位于沟槽中。
优选地，所述半导体器件进一步包括衬底和位于所述衬底和所述补偿区之间的缓冲层。
优选地，所述缓冲层其下部的掺杂浓度大于其上部的掺杂浓度。
优选地，所述n区其下部的掺杂浓度大于其上部的掺杂浓度。
优选地，所述晶体管单元进一步包括位于所述互连下方的本体区。
优选地，所述半导体器件是超结器件。
附图说明
包括以下附图来进一步理解实施例，所述附图被结合到说明书中并构成说明书的一部分。附图用于解释实施例且附图及其相应描述用于解释实施例的原理。将容易理解认识到其它的实施例及其意在的优点，因为通过参考以下详细描述它们将变得更好理解。附图中的元素彼此之间并非按比例绘制。相同的附图标记代表同样的部件。
图1A、图1B和图1C，示出了超结晶体管的一部分的三个非限制性示例的示意性截面图。
图2A和图2B，为超结器件的顶视图，其示出多个布线层。
图3为与栅电极平行的超结晶体管的截面图，其中本体区(在此示出为硅连接的下扩散)形成多晶硅栅极和漏极之间的屏蔽。
图4A和图4B，示出了根据实施例的具有沟槽栅极结构的超结晶体管的顶视图和截面图。
具体实施方式
在以下详细描述中，将参考附图，其构成说明书的一部分。说明书通过本实用新型得以实施的具体实施例来进行描述。因此，方向性术语，例如“顶部”，“底部”， “前”，“后”，“前面”，“后面”等参考所描述的附图的定向而使用。由于实施例的部件可以以许多不同的定向被定位，方向性术语仅用于示例性目的，而并非限制。应当理解的是在不脱离本实用新型的范围的情况下，可以使用其他实施例并可以进行结构或逻辑上的改变。因此，以下详细的描述并不以限制意义理解，该实用新型的范围由所附的权利要求限定。
应当理解的是这里所描述的各个示例性实施例的特征除非特别说明外均可彼此结合。
如说明书中所应用的，术语“耦合”和/或“电耦合”并非意指元件必须直接耦合在一起；“耦合”或“电耦合”的元件之间可以具有中间元件。
图1A、图1B和图1C，示出了超结晶体管的三个非限制性示例的示意性截面图。示出了多种用于实现补偿区和可选缓冲区的可能性。这些示例并非限制性的，其可以以任何方式结合成不同的方案。为简单起见, 仅一部分有源区，即，承载垂直负载电流的区域的截面被示出。而晶体管的其它部分，如边缘终止系统，划片区或者栅极连接并未在图1A-1C中明确示出。所示出的器件具有半导体本体，其具有补偿区，所述补偿区包括p区（p柱）130和n区（n柱）134,其中所述补偿，即，在垂直方向上p柱和n柱之间的掺杂的差既可以是均匀的也可以是可变的。
所述补偿区被连接至MOS晶体管单元，MOS晶体管单元包括源极118，本体区138和控制栅极114。在所示出的示例中，所述栅极被构建成位于所述半导体本体顶部的平面栅电极。然而，所述栅极也能够在刻蚀进所述半导体本体中的沟槽中实现。
绝缘结构140，例如氧化物，将所述栅极114与所述本体区138，所述源极118，所述n区（n柱）134以及金属化层110电隔离。并且所述绝缘结构140的一部分可用作栅极绝缘层。
所述晶体管的漏极128连接至高掺杂的衬底124。可选缓冲层126可以位于所述衬底和所述补偿区中间。所述缓冲层具有与所述衬底相同的导电类型，但具有比衬底较低浓度的掺杂。在垂直方向上所述缓冲层的掺杂可以是变化的。例如，图1B的截面示出所述缓冲层中逐步变化的掺杂水平。例如，所述缓冲层可以包括多个子层，如第一子层（缓冲层1）和第二子层（缓冲层2）,并且所述第二子层的掺杂可以高于所述第一子层的掺杂。又例如，图1C的截面示出所述n区（n柱）134的掺杂沿着自所述绝缘结构140至所述缓冲层126的方向逐步增加和/或逐渐增加。根据一实施例（图1A-1C中未示出），n区（n柱）的掺杂和/或p区（p柱）的掺杂可以沿着自所述绝缘结构140至所述缓冲层126的方向具有一个或多个局部掺杂最大量及一个或多个局部掺杂最小量。
源极接触通过所述金属化层110电连接，所述金属化层在芯片的顶面构建公共源极焊盘。各个单元栅极114通过多晶硅而被连接以在顶面构建与金属化部的栅极接触。并且因此，具有相同或不同的金属化部的两个电极（一个用于源极，另一个用于栅极）被设置在器件顶面并且通过例如，硅氧化物或硅氮化物钝化层或者二者彼此隔离。所述漏极接触构建在所述器件的后部并且被超结器件的金属化部128覆盖。
在超结晶体管中，由于用于n沟槽MOSFET的适合的功函数和其可制造性，栅电极的优选材料为n掺杂的多晶硅。然而，多晶硅的串联电阻被掺杂材料（例如，磷）的溶解度限制，因此，对于500nm厚的层来说，薄层电阻不能小于大约10 Ω。
同时，具有条形单元的超结晶体管通常在基本平行的电极间没有连接。因此，仅仅举几个可能性，由于漏极的内部反馈，单元间的一些小的（非预期的）结构差别或者芯片中的温度梯度，所述超结晶体管的平行单元的栅极电势可能会不同。所述栅电极可以仅在其端部与金属栅极条相连接。本文中的栅极条是高导电线，例如由一些金属制成，这些金属能够实现在所述栅电极和栅极焊盘之间的低欧姆连接。
随着超结晶体管的芯片面积增加，产生了非均匀开关的问题。
本发明公开的结构对于大于20mm2，或大于35mm2，或大于50mm2的较大的芯片面积而言更为重要。
根据本实用新型，对于最适宜的栅极电荷来说，优选地图1A-1C所示的所述栅电极的宽度w不超过所述单元的节距p的大约50%。在一个实施例中，所述栅电极的宽度w小于所述单元的节距p的1/2。在另一个实施例中，所述栅电极的宽度w小于所述单元的节距p的1/3。
此外，为了提供均匀的栅极电压分布并因此提供均匀的单元开关特性， 两个相邻栅电极结构间的电连接可以被使用和/或所述栅电极结构和所述栅极指间的电连接可以被使用。
图2A和图2B，为超结晶体管的顶视图，其示出多个布线层。在半导体层220（其例如包括上述的晶体管单元）上布置第一布线层，其包括基本平行的栅电极114（沿着水平方向延伸），在所述基本平行的栅电极114之间的一个或多个互连221（沿着垂直方向延伸）。在所述第一布线层上布置第二布线层，其包括源极金属化部110以及栅极条225和栅极指中的至少一个。所述栅极条和栅极指中的至少一个通过栅极接触227连接至所述互连221和/或栅电极114。所述源极金属化部110通过插塞/源接触孔228连接至所述源极118和本体区138。两个相邻栅电极114之间的互连221使得所述超结晶体管的栅电极电势一致。图2A示出了直互连221。图2B示出了级联互连221。所述互连221和栅电极114例如可以由多晶硅形成。
如图2A-2B所示，所述超结晶体管在基本平行的电极114间可以具有一个或多个互连221。这些互连例如能够被用来实现所述超结晶体管的栅极电势的更加均匀的分配，并且因此用来实现更加均匀的单元开关行为。
可选地，这些互连可以在条形单元的端部和/或仍以规则的距离布置在有源区中。在单元区域的末端还可以提供由栅电极至环绕的栅极环的可选连接。可替换地或附加地，能够提供至少一个栅极指，在有源区中与单元相交。优选地，所述栅电极连接至所述晶体管单元的交叉点处的至少一个栅极指。在这些交叉点处，所述源电极和所述源极接触的接触孔可以被省略（图2A-2B中未示出）。
当然，所述源极和本体连接之间的接触孔和所述源极金属化部不必是连续的，而是在如图2A-2B所示的互连221处断续的，以防止栅极和源极之间的电流短路。
然而，为了保持低栅极电荷这一目标，所述漏电极和附加互连之间的耦合应被最小化。在一个实施例中，如图3所示，所述超结晶体管的p本体区138应位于由绝缘结构142围绕的附加互连221下方。接着，所述本体区138在栅极电势上形成在所述漏极和所述附加互连之间的屏蔽。
根据另一个实施例，不存在与所述多晶硅互连221相邻的源极区118（例如掩蔽注入）和/或提供额外的p掺杂来防止出现额外的反型沟道（图3中未示出）。
在图3所示的实施例中，示出了通过p柱130的横截面。当然，在与图3所示的横截面相比垂直的横截面中，所述本体区不必被覆盖以留出导电沟道。参照图1A-1C示出这样的横截面。
在另一个实施例中，所述超结晶体管也可以采用在沟槽中具有栅电极的单元结构构建。图4A和图4B，示出了超结晶体管（左侧）的条形沟槽单元结构的顶视图和点A-A’的截面图（右侧）。如图4A-4B所示，所述栅电极114至少部分地位于沟槽中。
根据一个实施例，连接相邻栅电极的多晶硅桥223可以被实现为所述半导体表面上方的多晶硅线。
根据另一个实施例，所述多晶硅桥被实现在连接相邻栅极沟槽的沟槽中（未在图4A-4B中示出）。
尽管在此描述和图示了特定的实施例，本领域普通技术人员能够理解在不脱离本实用新型的范围的情况下，多种可替换和/或等同的实施方式可以用来替换所示出并描述的特定实施例。本申请旨在覆盖任何对此处讨论的特定实施例的调整或改变。因此，本实用新型旨在仅由权利要求及其等价物限制。

Claims (25)

1.一种半导体器件，其特征在于包括：
补偿区，其包括p区和n区；
位于所述补偿区上的包括栅电极的多个晶体管单元；
一个或多个用于电连接栅电极的互连，
其中所述栅电极具有比所述单元的节距的1/2小的宽度。
2.根据权利要求1所述的半导体器件, 其特征在于所述栅电极的宽度比所述单元的节距的1/3小。
3.根据权利要求1所述的半导体器件, 其特征在于所述栅电极包括多晶硅。
4.根据权利要求1所述的半导体器件, 其特征在于所述互连包括多晶硅。
5.根据权利要求1所述的半导体器件, 其特征在于至少一个所述互连与仅两个相邻的栅电极连接。
6.根据权利要求1所述的半导体器件, 其特征在于至少一个所述互连与多于两个栅电极连接。
7.根据权利要求1所述的半导体器件, 其特征在于所述半导体器件包括至少第一布线层和第二布线层。
8.根据权利要求7所述的半导体器件, 其特征在于所述第一布线层包括所述互连和所述栅电极。
9.根据权利要求8所述的半导体器件, 其特征在于所述第二布线层包括栅极条和栅极指中的至少一个和源极金属化部。
10.根据权利要求9所述的半导体器件, 其特征在于所述栅极条和栅极指中的至少一个通过栅极接触电连接至至少一个所述互连。
11.根据权利要求9所述的半导体器件, 其特征在于所述晶体管单元进一步包括源极区和本体区，并且所述源极金属化部通过插塞/源接触孔电连接至所述源极区和本体区。
12.根据权利要求1所述的半导体器件, 其特征在于所述晶体管单元为条形。
13.根据权利要求12所述的半导体器件, 其特征在于所述互连位于所述晶体管单元的端部。
14.根据权利要求12所述的半导体器件, 其特征在于所述栅电极连接至所述晶体管单元端部处的栅极环或连接至所述晶体管单元的互连处的栅极指。
15.根据权利要求1所述的半导体器件, 其特征在于所述互连以规则的距离布置在有源区中。
16.根据权利要求1所述的半导体器件, 其特征在于所述栅电极彼此相互平行。
17.根据权利要求1所述的半导体器件, 其特征在于所述栅电极具有平面结构。
18.根据权利要求1所述的半导体器件, 其特征在于所述栅电极至少部分地位于沟槽中。
19.根据权利要求18所述的半导体器件, 其特征在于所述互连被实施为桥。
20.根据权利要求18所述的半导体器件, 其特征在于所述互连至少部分地位于沟槽中。
21.根据权利要求1所述的半导体器件, 其特征在于进一步包括衬底和位于所述衬底和所述补偿区之间的缓冲层。
22.根据权利要求21所述的半导体器件, 其特征在于所述缓冲层其下部的掺杂浓度大于其上部的掺杂浓度。
23.根据权利要求1所述的半导体器件, 其特征在于所述n区其下部的掺杂浓度大于其上部的掺杂浓度。
24.根据权利要求1所述的半导体器件, 其特征在于所述晶体管单元进一步包括位于所述互连下方的本体区。
25.根据权利要求1所述的半导体器件, 其特征在于所述半导体器件是超结器件。
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