CN101630681B - 具有单片集成的rc缓冲器的功率器件 - Google Patents

具有单片集成的rc缓冲器的功率器件 Download PDF

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CN101630681B
CN101630681B CN2009101515362A CN200910151536A CN101630681B CN 101630681 B CN101630681 B CN 101630681B CN 2009101515362 A CN2009101515362 A CN 2009101515362A CN 200910151536 A CN200910151536 A CN 200910151536A CN 101630681 B CN101630681 B CN 101630681B
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乔恩·格拉迪施
阿瑟·布莱克
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Fairchild Semiconductor Corp
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Abstract

一种半导体结构，包括功率晶体管，与RC缓冲器单片集成在一个芯管中。该功率晶体管包括在硅区中延伸的体区，通过栅电极与体区绝缘的栅电极，在体区中延伸的源区，源区和体区为相反的导电类型，并且源极内连线与源区相接触。RC缓冲器包括通过缓冲器电介质与硅区绝缘的缓冲器电极，使得缓冲器电极和硅区形成具有预定值的缓冲器电容器。缓冲器电极以在缓冲器电容器和源极内连线之间的预定值的缓冲器电阻器的方式连接至源极内连线。缓冲器电容器和缓冲器电阻器配置为在功率晶体管切换状态时基本上使输出振铃衰减。

Description

具有单片集成的RC缓冲器的功率器件
相关申请的交叉参考
本申请要求于2008年6月30日提交的第61/077,070号美国临时申请的权益，其公开内容通过引证整体结合于此作为参考。
背景技术
RC缓冲器是切换电路的基础部件。其大体上用来控制切换期间产生的EMI和过度的高峰电压压力。例如，RC缓冲器是许多同步降压稳压器中的标准设计元件。在这种应用中，不受控的振铃可超出标准FET击穿电压。
图1示出了包括高边FET(HS_FET)110和低边FET(LS_FET)108的DrMOS(驱动MOS)的电路模型。示出了LS_FET的寄生元件。HS FET_110具有相似的寄生效应。电感器代表与结合线和封装插脚相关联的电感。在这种应用中，切换时间期间输出处的振铃可以导致从电路发出的EMI噪声、高频率振铃、以及过度的电压过冲。在这种具体的实例中，LS_FET 108被估计为25V VDSS。整个LS_FET 108上的高峰VDSS振铃电压(在VSWH节点测量为24.5V)几乎在FET的额定限制。
输出振铃特性由来自封装的电感加上板电感的和以及FET寄生电容确定。该结合产生了具有非常小的衰减的LC谐振。在诸如DrMOS的冲击波形因数电路中，在HS_FET导通处HF振铃接近150MHz，且在HS_FET截止处接近300MHz是常见的。由于过度的额定EMI该HF噪声可以导致电路失去标准。
为了控制输出振铃，典型地在PCB上增加外部RC缓冲器104。缓冲器104包括作为离散组件而连接至PCB的RC组件。增加RC缓冲器104来通过FET将振铃电流分流离开内路径106并提供衰减。然而，在典型的FET电路中，由于内部和外部寄生阻抗的混合，分流器仅有限地有效。在大多数情况中，振铃电压对器件高峰标准电压仍相对截止。因此，外部缓冲器性能限制了将RC缓冲器紧紧地连接至整个FET输出电容上的能力。这尤其涉及到电路中的快速切换动作，诸如同步降压稳压器或发动机驱动器。典型的解决方案是将HS FET的导通减慢，但是这将导致减少的电路效率的损失，并且将不减少高边振铃。
因此，需要一种用于在切换功率晶体管时使输出振铃衰减的低成本且有效的技术。
发明内容
根据本发明的一个实施例，半导体结构包括与RC缓冲器(snubber)单片地集成在一个芯管(die)中的功率晶体管。功率晶体管包括在硅区中延伸的体区，通过栅极电介质与体区绝缘的栅电极，在体区域中延伸的源区，源区和体区为相反的导电类型，以及与源区接触的源极内连线(interconnect)。RC缓冲器包括缓冲器电极，通过缓冲器电介质与硅区绝缘，使得缓冲器电极和硅区形成具有预定值的缓冲器电容器。缓冲器电极以使在缓冲器电容器和源极内连线之间形成预定值的缓冲器电阻器的方式连接至源极内连线。缓冲器电容器和缓冲器电阻器配置为在功率晶体管切换状态时基本上使输出振铃衰减。
在一个实施例中，半导体还包括多个栅极沟槽和多个缓冲器沟槽，其中每个栅极沟槽包括一个栅电极，每个缓冲器沟槽包括一个缓冲器电极。
在另一个实施例中，缓冲器沟槽和栅极沟槽沿行彼此平行地延伸，该结构还包括用于使源极内连线和缓冲器电极彼此接触的至少两列接触点。
在另一个实施例中，每个栅极沟槽包括在栅电极下方的屏蔽电极。
在另一个实施例中，缓冲器沟槽比栅极沟槽延伸得更深。
在另一个实施例中，缓冲器沟槽和栅极沟槽延伸至相同的深度，沿每个栅极沟槽底部延伸的电介质层比沿每个缓冲器沟槽底部延伸的电介质层厚。
在另一个实施例中，缓冲器沟槽和栅极沟槽沿平行的行延伸，并且缓冲器沟槽的行散布在栅极沟槽的行之中。
在另一个实施例中，在芯管的与RC缓冲器完全分开的部分中形成功率晶体管。
在另一个实施例中，在芯管的有源区中形成功率晶体管，并且在电连接至栅电极的栅极衬垫(gate pad)下方延伸的区域中形成RC缓冲器。
在另一个实施例中，栅电极和缓冲器电极在硅区的顶部表面之上横向延伸并且与硅区的顶部表面绝缘。
在另一个实施例中，缓冲器电阻在0.5到2.0欧姆的范围中。
在另一个实施例中，缓冲器电阻器具有与
Figure G2009101515362D00041
成比例的值，其中C表示功率晶体管截止时的输出电容，且L包括其中容纳了半导体结构的封装的寄生电感。
在另一个实施例中，缓冲器电容器具有比功率晶体管截止时的输出电容更大的值。
根据本发明的另一实施例，一种多芯片模块，包括高边开关，具有单片集成在第一芯管中的高边功率晶体管和高边RC缓冲器，其中高边功率晶体管包括高边漏极内连线、高边源极内连线、和高边栅极内连线，并且高边RC缓冲器包括在高边漏极内连线和高边源极内连线之间串联连接的高边缓冲器电容器和高边缓冲器电阻器，从而在高边开关变换状态时基本上使输出振铃衰减。多芯片模块还包括低边开关，具有单片集成在第二芯管中的低边功率晶体管和低边RC缓冲器，高边开关和低边开关串联连接，其中低边功率晶体管包括低边漏极内连线、低边源极内连线、和低边栅极内连线，并且低边RC缓冲器包括在低边漏极内连线和低边源极内连线之间串联连接的低边缓冲器电容器和低边缓冲器电阻器，从而在低边开关变换状态时基本上使输出振铃衰减。
在一个实施例中，高边功率晶体管还包括：体区，在漏区中延伸，高边漏极内连线与漏区相接触；栅电极，通过栅极电介质与体区绝缘，高边栅极内连线与栅电极相接触；以及源区，在体区中延伸，源区和体区为相反的导电类型，高边源极内连线与源区相接触。高边RC缓冲器还包括缓冲器电极，通过缓冲器电介质与漏区绝缘，使得缓冲器电极和漏区形成高边缓冲器电容器，缓冲器电极以形成高边缓冲器电阻器的方式连接至高边源极内连线。
在另一个实施例中，低边功率晶体管还包括：体区，在漏区中延伸，低边漏极内连线与漏区相接触；栅电极，通过栅极电介质与体区绝缘，低边栅极内连线与栅电极相接触；以及源区，在体区中延伸，源区和体区为相反的导电类型，低边源极内连线与源区相接触。低边RC缓冲器还包括缓冲器电极，通过缓冲器电介质与漏区绝缘，使得缓冲器电极与漏区形成低边缓冲器电容器，缓冲器电极以形成低边缓冲器电阻器的方式连接至低边源极内连线。
下面的的详细描述和附图提供了本发明特性和优点的更好理解。
附图说明
图1示出了具有外部提供的RC缓冲器的DrMOS的电路表示；
图2示出了根据本发明一个实施例的DrMOS的电路表示，其中RC缓冲器单片集成在LS_FET中；
图3A示出了根据本发明的一个优选实施例与RC缓冲器单片集成的同步FET(Sync FET)的截面图；
图3B示出了图3A中的Sync FET的电路表示；
图4A示出了图3A中的Sync FET的一个变化，其中肖特沟槽更深地延伸到硅区；
图4B示出了图4A中Sync FET的电路表示；
图5示出了图3A实施例的另一个变化；
图6示出了根据本发明另一个实施例具有集成的RC缓冲器的屏蔽栅极FET；
图7是示出了其中FET区和RC缓冲器均形成在芯管的单独区域中的一个变化的截面图；
图8示出了其中用作电荷平衡结构的沟槽有利地用来实现RC缓冲器的实施例；
图9示出了与RC缓冲器单片集成的横向MOSFET；
图10示出了与RC缓冲器单片集成的另一个横向MOSFET；
图11示出了具有单片集成的RC缓冲器的沟槽MOS肖特基势垒(TMBS)整流器；
图12示出了其中功率器件与RC缓冲器单片集成的芯管的简化俯视图；以及
图13A和13B示出了具有单片集成的RC缓冲器(左边图)的FET和没有RC缓冲器(右边图)的FET的测量结果。
具体实施方式
根据本发明的实施例，RC缓冲器与功率晶体管单片集成在一个单一的芯管中。在一个实施例中，功率晶体管包括漏极内连线、源极内连线以及栅极内连线。RC缓冲器包括在漏极内连线和源极内连线之间串联连接的缓冲器电阻器和缓冲器电容器。缓冲器电容器和缓冲器电阻器被设计为具有预先选择的值，以使功率晶体管切换状态时发生的输出振铃衰减。
图2示出了根据本发明一个实施例，其中RC缓冲器单片集成在LS_FET中的DrMOS的电路表示。虽然没有示出，但RC缓冲器也可以以相似的方式集成在HS_FET中。块202表示容纳多芯管DrMOS的封装。低边FET LS_FET 208与其RC缓冲器一起被单片形成在一个芯管中，并且高边FET HS_FET 210与其RC缓冲器一起被单片形成在一个单独的芯管中。示出了包括输出电容C_DS_LS、栅极到源极电容C_GS_LS和栅极到漏极电容C_GD_LS的LS_FET 208的寄生元件。连接至LS_FET 208的电感器代表与栅极、源极和漏极结合线相关联的电感。LS_FET 208的RC缓冲器包括LS_FET的漏极和源极之间串联连接的R缓冲器218和C缓冲器220。如所见，RC缓冲器的单片集成能够在LS_FET 208的整个输出电容C_DS_LS上直接连接RC缓冲器。因此单片RC缓冲器有利地绕过所有显著的寄生封装电感，并且还消除了对弥补外部缓冲器的离散的R和C组件的需要。这对其中存在已知LC的应用和环境是非常有用的，诸如作为已知LC的MCM(多芯片模块)允许精细调节RC缓冲器以更有效地抑制输出振铃。在另一个实施例中，低边FET LS_FET 208及其RC缓冲器以及高边FET HS_FET 210及其RC缓冲器都单片形成在单一的芯管中。
图3A示出了根据本发明的一个实施例具有单片集成的RC缓冲器的同步FET(Sync FET)的截面图。图3B示出了具有其输入(CGD、CGS、RG)和输出(CDS)寄生元件的图3A中的Sync FET的电路表示。图3A中的Sync FET可以用作图2中的低边FET和/或高边FET。在图3A中，最左端的沟槽305表示FET沟槽且右边的两个沟槽307表示肖特沟槽。更多的这种沟槽典型地存在于形成Sync FET的芯管中。FET沟槽305和肖特沟槽307被电介质层520所衬，并且之后用诸如多晶硅的导电电极填充。导电电极在FET沟槽305中形成栅电极306并且在肖特沟槽307中形成缓冲器电极304。
沟槽305和307延伸到n型硅区302之中，该n型硅区延伸到衬底300之上。硅区302可以是在衬底300之上形成的外延层。P型体区308延伸到相邻的FET沟槽305之间的硅区302之中。如所见，体区从相邻的肖特沟槽307之间的台地区域省略，因此能够在源极内连线312和硅区302之间形成肖特接触316。源极内连线312包括用于形成与硅区302的肖特接触的合适的已知材料。源区318在体区308中延伸并且与每个FET沟槽305侧面接触。重体区310在相邻的源区318之间的体区308中延伸。顶侧源极内连线312与源区318和重体区310接触，但是通过电介质罩314与栅电极306和缓冲器电极304绝缘。未示出的后部漏极内连线(例如包括金属)与衬底300的后部接触。
在图3A中，每个缓冲器电极304和n型硅区302以及在它们之间延伸的电介质层320形成分布的缓冲器电容器309的部分。不同于其中Sync FET直接连接于(tied to)源极内连线312的传统SyncFET，肖特沟槽307中的缓冲器电极304以形成具有期望电阻值的缓冲器电阻器311的方式在第三维上连接至源极内连线312。因此设计肖特沟槽307以及电介质层520和缓冲器电极304(例如，通过选择合适数量的缓冲器沟槽、缓冲器沟槽宽度/深度和多晶硅缓冲器电极的掺杂浓度、以及多晶硅缓冲器电极连接到源极内连线312的位置及方式)以确保得到的RC缓冲器在切换期间适当地使输出振铃衰减。
可以通过使用空沟槽(dummy trench)代替肖特沟槽307而在传统沟槽栅极FET(即，没有肖特区)中实现RC缓冲器。空沟槽将具有与肖特沟槽307相似的结构，除了空沟槽之间的台地表面要与源极内连线312绝缘。
图4A示出了图3A中的Sync FET的一个变化，其中肖特沟槽407比FET沟槽405更深地延伸到硅区402之中。在其他方面图4A中的Sync FET与图3A中的Sync FET相似，因此不再描述图4A中的Sync FET的结构特征。图4B示出了具有其输入(CGD、CGS、RG)和输出(CDS)寄生元件的图4A中的Sync FET的电路表示。肖特沟槽407的深度可以被调整为所需要的值以获得期望的RC缓冲器电容和电阻值。与图3A的实施例相似，栅电极406和缓冲器电极404可以被凹入到各个沟槽中。同样，可以通过使用与肖特沟槽407具有相似结构的空沟槽并通过消除源极内连线412和台地表面之间的接触来获得Sync FET的沟槽栅极FET变化。
图5示出了图3A实施例的另一个变化，其中FET和肖特沟槽505、507两者均深入延伸到硅区502之中，但是沿FET沟槽505的底部形成比衬于肖特沟槽507的电介质520更厚的电介质522。在其他方面图4A中的Sync FET与图3A中的Sync FET相似，因此不再描述图4A中的Sync FET的结构特征。该实施例有利地使得能够调整FET和肖特沟槽的深度来获得期望的RC缓冲器的RC值，而不需要形成不同深度的FET和肖特沟槽。根据期望的沟槽深度，沿FET沟槽505的底部形成更薄或更厚的电介质材料。此外，沿FET沟槽505底部的厚底部电介质522有助于最小化栅极到漏极电容。再次将导电电极504、506凹入到沟槽中，并且可以使用空沟槽替代肖特沟槽。
图6示出了根据本发明另一实施例具有集成的RC缓冲器的屏蔽栅极FET。传统的屏蔽栅极FET结构(图6的左侧)与肖特结构和RC缓冲器(图6的右侧)结合。图6中的Sync FET的FET部分与图3A中的相似，除了所有的沟槽更深地延伸到硅区502中并且屏蔽电极621被沉积在每个FET沟槽605中的栅电极606之下。屏蔽电极621通过屏蔽电介质622与硅区602绝缘，该屏蔽电介质比衬于FET沟槽605的上部侧壁的栅极电介质620厚。肖特沟槽607包括通过缓冲器电介质层622与相邻的硅区602绝缘的缓冲器电极604。缓冲器电介质层622可以与屏蔽电介质层622在FET沟槽605中的形成在同一时间形成，并且因此具有与屏蔽电介质层相同的物理特性。缓冲器电介质层622可以与屏蔽电介质的形成在不同的处理阶段形成，以获得提供期望的缓冲器电容值的缓冲器电介质厚度(例如，缓冲器电介质可以与栅极电介质层620在同一时间形成)。同样，缓冲器电极604可以与屏蔽电极621的形成或栅电极606的形成在同一时间形成。同样，肖特沟槽607(或空沟槽)和肖特电极以及其中的电介质可以被设计以获得期望的缓冲器RC值。
如图7所示，由于这里描述了多种实施例，RC缓冲器被分配在整个有源区(即，形成有源单元处)，芯管的单独部分704可以被仅分配给RC缓冲器。这是有利的，在于FET和RC缓冲器可以独立于彼此设计从而在设计FET和RC缓冲器时最小化竞争利益的潜在不利冲击。在一个替换中，RC缓冲器可以有利地形成在栅极衬垫区域下方，或有源单元不会延伸至其的其他相似区域，因此，最小化了硅消耗。
图8示出了作为电荷平衡结构的沟槽也有利地用来实现RC缓冲器的实施例。如所示，中央FET沟槽809被两个更深的电荷平衡沟槽807包围。在外部电荷平衡沟槽中的缓冲器电极804(例如包括多晶硅)可以以获得期望的缓冲器阻抗的方式沿第三维方式连接于源极内连线。利用之前的实施例，缓冲器电介质822可以与栅极电介质820在同一时间形成或者取决于期望的缓冲器电容值和期望的电荷平衡特性在过程的不同阶段形成。源区818、体区808、重体区810和源极内连线以与之前的实施例相似的方式相对于FET沟槽805配置。
图9示出了与RC缓冲器单片集成的横向MOSFET。如所见，横向延伸的缓冲器电极904(例如包括掺杂的或未掺杂的多晶硅)被包括在两个相邻的横向延伸的栅电极906(例如，包括掺杂的或未掺杂的多晶硅)之间。具有下面的电介质层920的缓冲器电极904利用LDD区924和漏极沉降(sinker)区926形成缓冲器电容器909。此外，缓冲器电极904以获得期望缓冲器阻抗的方式沿第三维连接至源极内连线912。示出的源极内连线912在相邻的电极904、906之间向下延伸以从漏极屏蔽栅电极906。在另一个实施例中，源极内连线912没有在相邻电极904、906之间向下延伸。体区908在硅区908中延伸，并且源区918在体区908中延伸并与栅电极906重叠。重体区910在与源区918相邻的体区908中延伸。N型LDD区924在体区908中延伸并且与栅电极906重叠。高掺杂漏沉降926从LDD区垂直向下延伸到衬底900之中。栅极和缓冲器电极906、904通过栅极电介质层920与下面的区域绝缘，并且通过电介质层922与源极内连线912绝缘。
图10示出了与RC缓冲器单片集成的另一个横向MOSFET。在该实施例中，用作影响漏区中的电场的两个中间电极1004(例如包括掺杂的或未掺杂的多晶硅)也被用作实现RC缓冲器。这两个缓冲器电极1004以获得期望缓冲器阻抗1011的方式连接于源极内连线1012，并且还在整个电介质层1020上利用LDD和沉降区1024、1026形成期望的缓冲器电容1009。尽管图10示出了放置在栅电极1006之间的两个缓冲器电极，根据期望的缓冲器RC值还可以包括更多的缓冲器电极。不同于图9中的横向MOSFET，图10中的体区1008没有达到LDD区1024。
图11示出了具有单片集成的RC缓冲器的沟槽MOS肖特基势垒(TMBS)整流器。沟槽1107延伸到硅区1102之中，并且包括衬于沟槽侧壁的电介质层1120和在沟槽1107中放置的凹入的缓冲器电极。顶侧内连线1112沿相邻沟槽之间的台地表面形成与硅区1102的肖特接触。顶侧内连线1112包括用于形成具有硅区1102的肖特基势垒的合适的已知材料。设计缓冲器沟槽1107和这里的材料从而获得期望的缓冲器RC值的考虑与之前的实施例相似，因此这里不再重复。
用于选择单片集成的RC缓冲器的电阻和电容值的设计因素
在这里描述的所有实施例以及其等价物中，可以使用下列标准确定用于缓冲器电容器和缓冲器电阻器的合适值。
电阻：对于典型的离散缓冲器网络(即没有单片集成)的情况，缓冲器电路相对复杂(至少第四个等级)。但是对于单片集成的缓冲器RC的情况，电路减少到理想的串联RLC第二等级网络。因此，传统的第二等级网络设计标准可以用于指导。为了使第二等级网络有效衰减，缓冲器R的衰减阻抗值必须是
Figure G2009101515362D00121
的比例。在该等式中，C表示当截止时FET的输出电容(例如，MOSFET中的Coss，或IGBT中的Coes)，并且L是PCB寄生效应和器件寄生效应两者之和。对于给定的封装类型，结合的总的电感将在整个电源设计上被公平地相容。这允许选择示出整个设计范围上有效性能的R的固定值。根据这些实施例的详细的仿真示出了典型的同步降压传动系中，对于低电压应用(例如小于50V)，0.5到2欧姆的R值将产生基本上改进的缓冲。对于更高的电压应用，更高的R值提供更好的缓冲效应。因此可见，缓冲器电极连接于源极(发射极)内连线的方式需要被仔细考虑和设计以获得期望的阻抗值。
电容：为了获得有效的缓冲，缓冲器臂需要具有比FET更低的阻抗。因此，缓冲器电容值需要在截止时大于FET的输出电容(例如MOSFET中的Coss，或IGBT中的Coes)。在一些实施例中，获得有效的缓冲，其中缓冲器电容值比FET的输出电容在截止时大2到5倍。
图12示出了芯管的简化的俯视布局示图，其中功率器件与RC缓冲器单片集成。通过芯管有源区横向延伸的行1204包括单元(例如包括FET沟槽)的行和散布在单元的行之间的缓冲器电极(例如放置在缓冲器沟槽中或台地区域之上)的行。相对于单元的行的数量的缓冲器电极的行的数量部分地由目标缓冲器电容值来确定。即，如果期望较大的缓冲器电容值，则使用更大数量的缓冲器电极行，反之亦然。
在图12中，接触区1206垂直延伸通过有源区。其中接触区1206与横向延伸的缓冲器电极的行相交，在未示出的顶侧内连线(例如，MOSFET的情况中的源极内连线)和缓冲器电极之间形成接触。接触区1206的至少两列可以是将缓冲器电阻减小到可以使输出振铃衰减的一个值所必须的。当然，根据期望的缓冲器电阻可以使用多于两列的接触区。大体上，为了获得更低的缓冲器电阻，可以使用更大数量的接触区1206的列。图12仅为多个可能布局结构中的一个，其中可以利用多种结构特征以获得期望的缓冲器RC值。
单片集成的RC缓冲器和FET与传统离散的解决方案相比示出了振铃的显著减少。图13A和13B示出了具有单片集成的RC缓冲器(左边图)的FET的测量结果和没有RC缓冲器(右边图)的FET的测量结果。输出振铃上的RC缓冲器冲击对HS_FET和LS_FET(传统的离散缓冲器技术，仅减小低边振铃)两者可以清楚地观察到。因此，不仅是RC缓冲器的单片实现提供了与传统离散解决方案相比的很大改进的振铃特性，其还消除了对于外部离散的电容器和电阻器的需要并因此降低了成本。
本发明不限于这里描述的具体结构，并且可以在多个其他FET和IGBT结构中实现本发明。具体地，RC缓冲器可以被实现在其中电极(除了栅电极)用来影响漏区的电特性(例如改进电荷平衡和/或晶体管导通电阻(Rdson))的任意功率晶体管结构中。这些电极可以被修改或配置以获得如上所述的期望的缓冲器电阻器和电容器值。因此，本发明的范围不应参考上述描述来确定，而应参考所附权利要求及其等价物的全部范围来确定。

Claims (20)

1.一种半导体结构，包括：
功率晶体管，包括：
体区，在硅区中延伸；
栅电极，通过栅极电介质与所述体区绝缘；
源区，在所述体区中延伸，所述源区与所述体区为相反的导电类型；
源极内连线，与所述源区相接触；
RC缓冲器，与所述功率晶体管单片集成在一个芯管中，所述RC缓冲器包括：
缓冲器电极，通过缓冲器电介质与所述硅区绝缘，使得所述缓冲器电极和所述硅区形成具有预定值的缓冲器电容器，所述缓冲器电极连接至所述源极内连线，以在所述缓冲器电容器和所述源极内连线之间形成预定值的缓冲器电阻器，所述RC缓冲器配置为在所述功率晶体管切换状态时基本上使输出振铃衰减。
2.根据权利要求1所述的半导体结构，其中所述功率晶体管包括多个栅极沟槽，其中每个所述栅极沟槽包括一个栅电极；
所述RC缓冲器包括多个缓冲器沟槽，其中每个所述缓冲器沟槽包括一个缓冲器电极。
3.根据权利要求1所述的半导体结构，其中，所述RC缓冲器包括缓冲器沟槽，并且所述功率晶体管包括栅极沟槽，所述缓冲器沟槽和所述栅极沟槽平行排列，
所述半导体结构还包括：
与所述源极内连线和所述缓冲器电极接触的至少两列接触点。
4.根据权利要求1所述的半导体结构，其中，所述功率晶体管包括多个栅极沟槽，所述多个栅极沟槽中的每个栅极沟槽包括在所述栅电极下方的屏蔽电极，其中所述栅电极被包括在所述多个栅极沟槽中的每个栅极沟槽中。
5.根据权利要求1所述的半导体结构，其中，所述RC缓冲器包括缓冲器沟槽，所述缓冲器沟槽比包括在所述功率晶体管中的所述栅极沟槽延伸得更深。
6.根据权利要求1所述的半导体结构，其中，所述多个缓冲器电极中的每个缓冲器电极被凹入在所述RC缓冲器相应的缓冲器沟槽中，
所述半导体结构还包括：
电介质罩，使每个缓冲器电极的一部分与所述源极内连线层绝缘。
7.根据权利要求1所述的半导体结构，其中，所述RC缓冲器包括缓冲器沟槽，所述缓冲器沟槽和包括在所述功率晶体管中的栅极沟槽延伸至相同的深度，所述RC缓冲器包括沿每个栅极沟槽底部延伸的电介质层，该电介质层比沿每个缓冲器沟槽底部延伸的电介质层厚。
8.根据权利要求1所述的半导体结构，其中，所述RC缓冲器包括缓冲器沟槽，并且所述功率晶体管包括栅极沟槽，所述缓冲器沟槽沿与所述栅极沟槽的行平行的行延伸，所述缓冲器沟槽的行散布在所述栅极沟槽的行之中。
9.根据权利要求1所述的半导体结构，其中，在所述芯管的有源区中形成所述功率晶体管，并且在电连接至所述栅电极的栅极衬垫下方延伸的区域中形成所述RC缓冲器。
10.根据权利要求1所述的半导体结构，其中，所述栅电极和所述缓冲器电极在所述硅区的顶部表面之上横向延伸并且与所述硅区的顶部表面绝缘。
11.根据权利要求1所述的半导体结构，其中，所述缓冲器电阻器具有在0.5到2.0欧姆的范围内的电阻。
12.根据权利要求1所述的半导体结构，其中，所述缓冲器电阻器具有与
Figure FSB00001043247600031
成比例的电阻值，其中C表示所述功率晶体管截止时的输出电容，且L包括其中容纳了半导体结构的封装的寄生电感。
13.根据权利要求1所述的半导体结构，其中，所述缓冲器电容器具有比所述功率晶体管截止时的输出电容更大的电容值。
14.一种半导体芯管，包括：
功率晶体管，包括沿行布置的栅电极、与漏区接触的漏极内连线、以及与源区接触的源极内连线，以及
RC缓冲器，与所述功率晶体管单片集成在一个半导体芯管中，所述RC缓冲器包括沿与所述栅电极的行平行的行布置的缓冲器电极，所述缓冲器电极通过缓冲器电介质与所述漏区绝缘，使得所述缓冲器电极和所述漏区形成具有预定电容值的缓冲器电容器，以及
至少两列接触点，与所述源极内连线和所述缓冲器电极彼此接触，从而形成具有预定电阻值的缓冲器电阻器，其中所述缓冲器电容器和所述缓冲器电阻器用来在所述功率晶体管切换状态时基本上使输出振铃衰减。
15.根据权利要求14所述的半导体芯管，其中，所述缓冲器电阻器具有在0.5到2.0欧姆的范围内的电阻。
16.根据权利要求14所述的半导体芯管，其中，所述缓冲器电阻器具有与成比例的电阻值，其中C表示所述功率晶体管截止时的输出电容，且L包括其中容纳了所述半导体芯管的封装的寄生电感。
17.根据权利要求14所述的半导体芯管，其中，所述缓冲器电容器具有比所述功率晶体管截止时的输出电容更大的电容值。
18.一种多芯片模块，包括：
高边开关，包括单片集成在第一芯管中的高边功率晶体管和高边RC缓冲器，所述高边功率晶体管包括高边漏极内连线、高边源极内连线、和高边栅极内连线，并且所述高边RC缓冲器包括在所述高边漏极内连线和所述高边源极内连线之间串联连接的高边缓冲器电容器和高边缓冲器电阻器，从而在所述高边开关变换状态时基本上使输出振铃衰减；以及
低边开关，包括单片集成在第二芯管中的低边功率晶体管和低边RC缓冲器，所述高边开关和所述低边开关串联连接，所述低边功率晶体管包括低边漏极内连线、低边源极内连线、和低边栅极内连线，并且所述低边RC缓冲器包括在所述低边漏极内连线和所述低边源极内连线之间串联连接的低边缓冲器电容器和低边缓冲器电阻器，从而在所述低边开关变换状态时基本上使输出振铃衰减。
19.根据权利要求18所述的多芯片模块，其中：
(a)所述高边功率晶体管还包括：
体区，在漏区中延伸，所述高边漏极内连线与所述漏区相接触；
栅电极，通过栅极电介质与所述体区绝缘，所述高边栅极内连线与所述栅电极相接触；
源区，在所述体区中延伸，所述源区和所述体区为相反的导电类型，所述高边源极内连线与所述源区相接触；以及
(b)所述高边RC缓冲器还包括：
缓冲器电极，通过缓冲器电介质与所述漏区绝缘，使得所述缓冲器电极和所述漏区形成所述高边缓冲器电容器，所述缓冲器电极以形成所述高边缓冲器电阻器的方式连接至所述高边源极内连线。
20.根据权利要求18所述的多芯片模块，其中：
(a)所述低边功率晶体管还包括：
体区，在漏区中延伸，所述低边漏极内连线与所述漏区相接触；
栅电极，通过栅极电介质与所述体区绝缘，所述低边栅极内连线与所述栅电极相接触；
源区，在所述体区中延伸，所述源区和所述体区为相反的导电类型，所述低边源极内连线与所述源区相接触；以及
(b)所述低边RC缓冲器还包括：
缓冲器电极，通过缓冲器电介质与所述漏区绝缘，使得所述缓冲器电极与所述漏区形成所述低边缓冲器电容器，所述缓冲器电极以形成所述低边缓冲器电阻器的方式连接至所述低边源极内连线。
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KR101619398B1 (ko) 2016-05-10
CN101630681A (zh) 2010-01-20
US8829624B2 (en) 2014-09-09
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US20100163950A1 (en) 2010-07-01

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