CN105097890A - 线型架构的功率半导体元件 - Google Patents
线型架构的功率半导体元件 Download PDFInfo
- Publication number
- CN105097890A CN105097890A CN201410396000.8A CN201410396000A CN105097890A CN 105097890 A CN105097890 A CN 105097890A CN 201410396000 A CN201410396000 A CN 201410396000A CN 105097890 A CN105097890 A CN 105097890A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- conductive structure
- power semiconductor
- line style
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 69
- 230000009471 action Effects 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000008520 organization Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract 1
- 230000012447 hatching Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thyristors (AREA)
Abstract
一种线型架构的功率半导体元件,其包括基材、多个线型功率半导体晶胞与保护环结构。此基材的一表面定义有一活动区域与一终端区域,终端区域位于活动区域的外侧。线型功率半导体晶胞排列于活动区域内。各个线型功率半导体晶胞分别包括一长条状闸极导电结构。保护环结构位于终端区域内,并且包括至少一环状导电结构。此环状导电结构环绕这些线型功率半导体晶胞。环状导电结构与长条状闸极导电结构位于同一个导电层,且至少一个长条状闸极导电结构与位于最内侧的环状导电结构相分离并通过一闸极金属垫电性连接至此位于最内侧的环状导电结构。
Description
技术领域
本发明有关于一种功率半导体元件,特别是关于一种线型架构的功率半导体元件。
背景技术
功率半导体元件具有低切换耗损与驱动电路简单的优势,搭配快速发展的半导体工艺技术,如今已成为电源控制的一个重要产品。功率半导体元件可依其通道(channel)位置的不同区分为沟槽式(trench)闸极与平面式闸极两种。沟槽式闸极功率半导体结构的通道是沿着垂直晶片表面的方向,而平面式闸极功率半导体结构的通道则是沿着晶片表面的方向。其次,功率半导体元件亦可依其晶胞设计方式的不同区分为方型(squaredcell)与线型(Stripedcell)两种。此二种晶胞设计各有其优缺点。一般而言,方型晶胞的设计可获得较低的导通电阻,线型晶胞则可提供较佳的米勒电容。
图1A为一典型功率半导体元件的外观示意图。如图1A所示,此功率半导体元件的上表面具有闸极金属垫G与源极金属垫S,此功率半导体元件的下表面另具有一汲极金属垫(图未示)。此功率半导体元件的上表面可区分为活动区域(activearea)A1与终端区域(terminationarea)A2。多个功率半导体单元(晶胞)位于此活动区域A1内。
图1B与图1C为此功率半导体元件的活动区域A1的示意图。图1B与图1C是以线型晶胞功率半导体元件为例,并省略位于最上方闸极金属垫G与源极金属垫S,以显示位于活动区域内的线型晶胞。如图1B所示,在活动区域A1内具有多个长条状闸极导电结构12,各个长条状闸极导电结构12对应至一个功率半导体晶胞。此功率半导体元件并具有环状导电结构22,其环绕活动区域A1。各个长条状闸极导电结构12的两端连接至环状导电结构22,以取得运作所需的闸极电位。图1C显示由图1A的导电结构(包括长条状闸极导电结构12与环状导电结构22)所定义出来的本体掺杂区14的分布状态。需说明的是,由于长条状闸极导电结构12的存在,活动区域A1内本体掺杂区会被切割成多个长条状本体掺杂区14,这些长条状本体掺杂区14的端部与邻近的掺杂区24间隔t1至t2不等的距离,因而导致在活动区域A1的周围产生不均匀的电场分布,使得功率半导体元件的效能变差。
图1D与图1E则是此功率半导体元件的终端区域A2的示意图。图中亦省略位于晶片最上方闸极金属垫G与源极金属垫S。如图1D与图1E所示,在功率半导体元件的终端区域A2内具有保护环结构,以提升功率半导体元件的崩溃电压。此保护环结构包括多晶硅终端图案。此多晶硅终端图案包括多晶硅闸极汇流排26与多个多晶硅环状结构22。这些多晶硅环状结构22由多晶硅闸极汇流排26的两侧向外延伸环绕活动区域A1。此多晶硅终端图案并在基材内定义出多个环状掺杂区24,依序环绕活动区域A1。需说明的是,由于多晶硅闸极汇流排26的存在,使得各个环状掺杂区在对应于多晶硅闸极汇流排26处会产生缺口,因而影响保护环结构对于电压的耐受能力,导致功率半导体元件所能承受的崩溃电压变小。
发明内容
有鉴于此,本发明提供一种线型架构的功率半导体元件,由此解决现有技术所述及的问题。
本发明的主要目的是提供一种线型架构的功率半导体元件,以解决传统线型架构的功率半导体元件的活动区域周围电场分布不均匀所造成的问题。
本发明的另一目的是提供一种线型架构的功率半导体元件,以解决传统功率半导体元件的终端区域内,因为多晶硅闸极汇流排的存在而导致环状掺杂区产生缺口,进而影响保护环结构的耐受电压的问题。
本发明提出一种线型架构的功率半导体元件。该功率半导体元件包括一基材、多个线型(striped)功率半导体晶胞与一保护环结构。该基材的一表面定义有一活动区域(activearea)与一终端区域(terminationarea),终端区域位于活动区域的外侧。线型功率半导体晶胞排列于活动区域内。各个线型功率半导体晶胞分别包括一长条状闸极导电结构。保护环结构位于终端区域内,并且包括至少一环状导电结构。此环状导电结构环绕这些线型功率半导体晶胞。至少一个长条状闸极导电结构与位于最内侧的环状导电结构相分离。
在本发明的一实施例中,环状导电结构与该些长条状闸极导电结构位于同一个导电层。
在本发明的一实施例中,各长条状闸极导电结构通过一闸极金属垫电性连接该终端区域的最内侧的环状导电结构。
在本发明的一实施例中,长条状闸极导电结构是一沟槽式闸极导电结构,长条状闸极导电结构是一平面式闸极导电结构。
在本发明的一实施例中,闸极金属垫是位于终端区域的一侧边且延伸覆盖长条状闸极导电结构的端部,并且,闸极金属垫的长边是垂直于长条状闸极导电结构的走向。
在本发明的一实施例中,闸极金属垫是由终端区域的一侧边的中央处向内延伸,并且,闸极金属垫的延伸方向是垂直于长条状闸极导电结构的走向。
在本发明的一实施例中,功率半导体元件包括二个闸极金属垫,对应该终端区域的相对两侧边。
在本发明的一实施例中,长条状闸极导电结构与环状导电结构上方覆盖有一层间介电层,层间介电层具有多个接触窗分别对应于长条状闸极导电结构与环状导电结构,闸极金属垫则是通过这些接触窗电性连接长条状闸极导电结构与环状导电结构。
在本发明的一实施例中,闸极金属垫位于多个环状导电结构的上方,此闸极金属垫是用以电性连接其中至少两个环状导电结构。
在本发明的一实施例中,各环状导电结构具有第一区段与第二区段,第二区段的宽度小于第一区段,形成于第一区段两侧的环状掺杂区互相分离,形成于第二区段两侧的环状掺杂区互相连结。而且,在本发明的一实施例中,各环状导电结构还包括第三区段,第三区段是位于第二区段的中央以电性连接至闸极金属垫,并且,第三区段的宽度大于第二区段。
关于本发明的优点与精神可以通过以下的发明详述与附图得到进一步的了解。
附图说明
图1A为一典型功率半导体元件的示意图。
图1B与图1C为图1A的功率半导体元件的活动区域A1的示意图。
图1D图与图1E为图1A的功率半导体元件的终端区域A2的示意图。
图2A至图2E显示本发明的功率半导体元件的第一实施例。
图3A为本发明功率半导体元件的第二实施例。
图3B为本发明功率半导体元件的第三实施例。
图4A至图4C为显示本发明功率半导体元件表面的闸极金属垫G与源极金属垫S的配置方式的三种不同实施例。
图5A至图5D显示本发明的功率半导体元件的第四实施例。
图6A至图6E显示本发明的功率半导体元件的第五实施例。
主要组件符号说明:
G:闸极金属垫
S:源极金属垫
A1:活动区域
A2:终端区域
12:长条状闸极导电结构
22:环状导电结构
14:本体掺杂区
20:基材
10:保护环结构
24:掺杂区
26:多晶硅闸极汇流排
22:多晶硅环状结构
112:长条状闸极导电结构
122:环状导电结构
114:本体掺杂区
124:掺杂区
130:层间介电层
132:接触窗
142:闸极金属垫
212:长条状闸极导电结构
222:环状导电结构
232:接触窗
242:闸极金属垫
312:长条状闸极导电结构
313:纵向连接结构
322:环状导电结构
332:接触窗
342:闸极金属垫
S1、S2:源极金属垫
G1、G2、G3:闸极金属垫
422:环状导电结构
424:掺杂区
442:闸极金属垫
432:接触窗
522:环状导电结构
524:掺杂区
522a:第二区段
524a:掺杂区
532:接触窗
542:闸极金属垫
522b:第三区段
具体实施方式
现在将详细参考本发明的示范性实施例,并在附图中说明所述示范性实施例的实例。另外,在附图与具体实施方式中所使用相同或类似标号的元件/构件是用来代表相同或类似部分。
在下述各实施例中,当元件被指为“连接”或“耦接”至另一元件时,其可为直接连接或耦接至另一元件,或可能存在介于其间的元件。术语“电路”可表示为至少一元件或多个元件,或者主动地且/或被动地而耦接在一起的元件以提供合适功能。术语“信号”可表示为至少一电流、电压、负载、温度、数据或其他信号。
图2A至图2E为本发明的功率半导体元件的第一实施例。此功率半导体元件采线型架构的配置方式。图2A显示此功率半导体元件表面的闸极金属垫G与源极金属垫S的配置,图2B为一俯视图显示功率半导体元件的活动区域A1内的线型晶胞结构,图2C与图2D是对应于图2B的C1至C2剖面线与C3至C4剖面线的剖面示意图,图2E为本实施例的功率半导体元件的活动区域A1内的本体掺杂区114的分布状态。
如图2A至图2E所示,此功率半导体元件包括基材20、多个线型(striped)功率半导体晶胞与保护环结构10。此基材20的表面定义有活动区域(activearea)A1与终端区域(terminationarea)A2。终端区域A2位于活动区域A1的外侧。线型功率半导体晶胞排列于活动区域A1内。这些线型功率半导体晶胞可以采用沟槽式闸极功率半导体结构,亦可采用平面式闸极功率半导体结构。
如图2B所示,各个线型功率半导体晶胞分别具有一长条状闸极导电结构112横向延伸于活动区域A1内。若是采用沟槽式闸极的设计,此长条状闸极导电结构112就会位于基材表面所形成的沟槽内;若是采用平面式闸极的设计,此长条状闸极导电结构112就会位于基材表面上方。保护环结构10位于终端区域A2内,并且包括至少一环状导电结构122(图中仅显示位于最内侧的环状导电结构122)。此环状导电结构122环绕位于活动区域A1内的线型功率半导体晶胞。
请参照图2C与图2D,环状导电结构122与长条状闸极导电结构112位于同一个导电层。换言之,此二个结构可利用同一道微影蚀刻工艺形成于基材上。而且,就一较佳实施例而言,此导电层可以是导电多晶硅层。
值得注意的是,如图2B所示,本实施例的各个长条状闸极导电结构112的两端是与保护环结构10中位于最内侧的环状导电结构122相分离。同时请参照图2E,通过此导电图案(包括长条状闸极导电结构112与环状导电结构122)所定义出来并形成于活动区域A1内的本体掺杂区114,是与位于终端区域A2内的掺杂区124间隔固定的距离t1,因而可避免在活动区域A1周围产生不均匀的电场分布。
其次,请同时参照图2B与图2D,本实施例的长条状闸极导电结构112虽然与环状导电结构122相分离,不过,覆盖于长条状闸极导电结构112与环状导电结构122上的层间介电层130内形成有多个接触窗132,对应于各个长条状闸极导电结构112与环状导电结构122。闸极金属垫142则是位于这些接触窗132的上方,电性连接各个长条状闸极导电结构112与终端区域A2最内侧的环状导电结构122。
相较于图1A的传统功率半导体元件,其闸极金属垫G局限于晶片一侧边的中央处,请参照图2A,本实施例的功率半导体元件的闸极金属垫G是位于终端区域A2的一侧边(即图中的左侧),并且延伸覆盖活动区域A1的边缘区域。进一步来说,此闸极金属垫G延伸覆盖长条状闸极导电结构112的端部,并且,此闸极金属垫G的长边方向垂直于长条状闸极导电结构112的走向。
图3A为本发明功率半导体元件的第二实施例。不同于图2A的实施例,闸极金属垫142位于活动区域A1的一侧边,本实施例的闸极金属垫242由终端区域A2的一侧边的中央处向内延伸。此闸极金属垫242位于多个长条状闸极导电结构212与环状导电结构222的上方,并通过接触窗232电性连接各个长条状闸极导电结构212与环状导电结构222。
图3B是本发明功率半导体元件的第三实施例。本实施例的相邻二个长条状闸极导电结构312是通过一纵向连接结构313相连,以构成一C型导电结构。本实施例的闸极金属垫342的配置位置大致相同于图2A的实施例,不过,此闸极金属垫342是通过接触窗332电性连接C型导电结构其中一个端部与环状导电结构322。因此,所需的接触窗的数量少于图2A的实施例。
图4A至图4C显示本发明功率半导体元件表面的闸极金属垫G与源极金属垫S的配置方式的不同实施例。在图4A中,闸极金属垫G是由晶片的一侧边的中央位置延伸至晶片的相对侧,二个源极金属垫S1与S2则是位于闸极金属垫的两侧。此闸极金属垫G可采用类似于图3A所示的方式与活动区域A1内的长条状闸极导电结构212电性连接。
图4B的功率半导体元件具有两个闸极金属垫G1与G2,此二个闸极金属垫G1、G2是对应于终端区域A2的相对两侧边。此二个闸极金属垫G1、G2可采用类似于图2A或图3B所示的方式与活动区域A1内的长条状闸极导电结构112、312电性连接。图4C的功率半导体元件使用三个闸极金属垫G1、G2与G3,此三个闸极金属垫G1、G2、G3分布于晶片的相对两侧边。如图中所示,闸极金属垫G1与G2位于同一侧,闸极金属垫G3则是位于相对侧。此三个闸极金属垫G1、G2、G3亦可采用类似于图2A或图3B所示的方式与活动区域A1内的长条状闸极导电结构112,312电性连接。
图5A至图5D显示本发明的功率半导体元件的第四实施例。其中,图5A为一俯视图显示功率半导体元件的终端区域A2内的多个环状导电结构422,图5B与图5C是对应于图5A的D1至D2剖面线与D3至D4剖面线的剖面示意图,图5D显示本实施例的功率半导体元件的终端区域A2内的掺杂区424的分布状态。
如图中所示,位于终端区域的保护环结构包括有多个环状导电结构422(图中是以五个为例),闸极金属垫442位于这些环状导电结构422的上方,并通过接触窗432电性连接环状导电结构422,使各个环状导电结构422具有相同的电位。就一较佳实施例而言,这些环状导电结构422可由导电多晶硅材料所构成,并且,可直接利用形成闸极多晶硅结构所需步骤形成于终端区域A2内。而且,本实施例的环状导电结构422位于基材表面,此等结构可搭配平面式闸极功率半导体结构的工艺。不过,本发明并不限于此。此环状导电结构422亦可形成于沟槽内,而能达到相类似的功效。
相较于图1C的保护环结构,由于多晶硅闸极汇流排26的存在,导致各个环状掺杂区在对应于多晶硅闸极汇流排26处会产生缺口,而影响保护环结构对于电压的耐受能力,如图5D所示,本实施例省略多晶硅闸极汇流排,改以位于上方的闸极金属垫442作为连接各个环状导电结构422所需的导电结构,因而可以形成完整的环状掺杂区424,以提升功率半导体元件所能承受的崩溃电压。
图6A至图6E显示本发明的功率半导体元件的第五实施例。其中,图6A为一俯视图显示功率半导体元件的终端区域A2内的多个环状导电结构522,图6B至图6D是对应于图6A的E1至E2剖面线、E3至E4剖面线与E5至E6剖面线的剖面示意图,图6E显示本实施例的功率半导体元件的终端区域A2内的掺杂区524的分布状态。
相较于本发明的第四实施例中,整个环状导电结构422具有相同的宽度,如图6A所示,本实施例的环状导电结构522具有一第一区段(即环状导电结构522的主要部分)与一第二区段522a(即对应于闸极金属垫542的部分),第二区段522a的宽度小于第一区段522。请同时参照图6B与图6D,其中,图6B是对应于第一区段522的剖面示意图,图6D则是对应于第二区段522a的剖面示意图,通过适当控制离子植入步骤的参数,可使第一区段522两侧的环状掺杂区524互相分离,同时使第二区段522a两侧的环状掺杂区524a互相连结以构成相邻环状掺杂区524a间的导电通道。
而且,如图6A所示,为了提供充分的空间设置接触窗532以电性连接至闸极金属垫542,此环状导电结构522更具有第三区段522b。此第三区段522b位于第二区段522a的中央处,并且,第三区段522b的宽度大于第二区段522a。请同时参照图6C,接触窗532设置于第三区段522b上方,闸极金属垫542则是通过此接触窗532电性连接至第三区段522b。
通过以上较佳具体实施例的详述,是希望能更加清楚描述本发明的特征与精神,而并非以上述所公开的较佳具体实施例来对本发明的范畴加以限制。相反地,其目的是希望能涵盖各种改变与具相等性的安排于本发明所欲申请的权利要求的范畴内。
Claims (11)
1.一种线型架构的功率半导体元件,其特征在于,包括:
一基材,具有一表面,其定义有一活动区域与一终端区域,上述终端区域位于上述活动区域的外侧;
多个线型功率半导体晶胞,位于上述活动区域内,各上述线型功率半导体晶胞包括一长条状闸极导电结构;以及
一保护环结构,包括至少一环状导电结构,位于上述终端区域内,且环绕该些线型功率半导体晶胞,
其中至少一上述长条状闸极导电结构与上述终端区域的最内侧的上述环状导电结构相分离。
2.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述环状导电结构与该些长条状闸极导电结构位于同一个导电层。
3.如权利要求1所述的线型架构的功率半导体元件,其特征在于,各上述长条状闸极导电结构通过一闸极金属垫电性连接上述终端区域的最内侧的上述环状导电结构。
4.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述环状导电结构是一环状多晶硅结构,上述长条状闸极导电结构是一长条状闸极多晶硅结构。
5.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述闸极金属垫位于上述终端区域的一侧边且延伸上述长条状闸极导电结构的一端部,并且,上述闸极金属垫的长边是垂直于上述长条状闸极导电结构的走向。
6.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述闸极金属垫由上述终端区域的一侧边的中央处延伸至上述活动区域内,并且,上述闸极金属垫的延伸方向是垂直于该些长条状闸极导电结构的走向。
7.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述功率半导体元件包括二个闸极金属垫,对应上述终端区域的相对两侧边。
8.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述长条状闸极导电结构与上述环状导电结构上方覆盖有一层间介电层,上述层间介电层具有多个接触窗分别对应上述长条状闸极导电结构与上述环状导电结构,上述闸极金属垫是通过该些接触窗电性连接上述长条状闸极导电结构与上述环状导电结构。
9.如权利要求1所述的线型架构的功率半导体元件,其特征在于,上述闸极金属垫位于该些环状导电结构的上方,以电性连接其中至少二个上述环状导电结构。
10.如权利要求9所述的线型架构的功率半导体元件,其特征在于,该些环状导电结构定义出多个环状掺杂区于上述终端区域内,各上述环状导电结构具有一第一区段与一第二区段,上述第二区段的宽度小于上述第一区段,形成于上述第一区段两侧的该些环状掺杂区互相分离,形成于上述第二区段两侧的该些环状掺杂区互相连结。
11.如权利要求10所述的线型架构的功率半导体元件,其特征在于,各上述环状导电结构还包括一第三区段,上述第三区段位于上述第二区段的中央处以电性连接上述闸极金属垫,并且,上述第三区段的宽度大于上述第二区段的宽度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103117623A TWI555208B (zh) | 2014-05-20 | 2014-05-20 | 線型架構之功率半導體元件 |
TW103117623 | 2014-05-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105097890A true CN105097890A (zh) | 2015-11-25 |
CN105097890B CN105097890B (zh) | 2018-04-17 |
Family
ID=54556643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410396000.8A Active CN105097890B (zh) | 2014-05-20 | 2014-08-13 | 线型架构的功率半导体元件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9583560B2 (zh) |
CN (1) | CN105097890B (zh) |
TW (1) | TWI555208B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11217541B2 (en) * | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040238884A1 (en) * | 2003-05-26 | 2004-12-02 | Masahiro Tanaka | Power semiconductor device |
CN101048874A (zh) * | 2004-10-29 | 2007-10-03 | 丰田自动车株式会社 | 绝缘栅极半导体器件及其生产方法 |
CN101180737A (zh) * | 2003-12-30 | 2008-05-14 | 飞兆半导体公司 | 功率半导体器件及制造方法 |
CN102891168A (zh) * | 2011-07-19 | 2013-01-23 | 万国半导体股份有限公司 | 用于高压端接的带场阈值mosfet的半导体器件 |
CN103035673A (zh) * | 2011-10-06 | 2013-04-10 | 飞兆半导体公司 | 用于功率半导体装置的边缘终端结构 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3851776B2 (ja) | 1999-01-11 | 2006-11-29 | フラウンホーファー−ゲゼルシャフト・ツール・フェルデルング・デル・アンゲヴァンテン・フォルシュング・アインゲトラーゲネル・フェライン | パワーmos素子及びmos素子の製造方法 |
US6893923B2 (en) * | 2001-03-21 | 2005-05-17 | International Rectifier Corporation | Reduced mask count process for manufacture of mosgated device |
EP1430537A1 (en) * | 2001-09-04 | 2004-06-23 | Koninklijke Philips Electronics N.V. | Method for producing a semiconductor device having an edge structure |
GB0122122D0 (en) * | 2001-09-13 | 2001-10-31 | Koninkl Philips Electronics Nv | Trench-gate semiconductor devices and their manufacture |
US7638841B2 (en) * | 2003-05-20 | 2009-12-29 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP4721653B2 (ja) | 2004-05-12 | 2011-07-13 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置 |
US7592650B2 (en) * | 2005-06-06 | 2009-09-22 | M-Mos Semiconductor Sdn. Bhd. | High density hybrid MOSFET device |
-
2014
- 2014-05-20 TW TW103117623A patent/TWI555208B/zh active
- 2014-08-13 CN CN201410396000.8A patent/CN105097890B/zh active Active
-
2015
- 2015-03-04 US US14/637,457 patent/US9583560B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040238884A1 (en) * | 2003-05-26 | 2004-12-02 | Masahiro Tanaka | Power semiconductor device |
CN101180737A (zh) * | 2003-12-30 | 2008-05-14 | 飞兆半导体公司 | 功率半导体器件及制造方法 |
CN101048874A (zh) * | 2004-10-29 | 2007-10-03 | 丰田自动车株式会社 | 绝缘栅极半导体器件及其生产方法 |
CN102891168A (zh) * | 2011-07-19 | 2013-01-23 | 万国半导体股份有限公司 | 用于高压端接的带场阈值mosfet的半导体器件 |
CN103035673A (zh) * | 2011-10-06 | 2013-04-10 | 飞兆半导体公司 | 用于功率半导体装置的边缘终端结构 |
Also Published As
Publication number | Publication date |
---|---|
CN105097890B (zh) | 2018-04-17 |
TW201545345A (zh) | 2015-12-01 |
US20150340433A1 (en) | 2015-11-26 |
US9583560B2 (en) | 2017-02-28 |
TWI555208B (zh) | 2016-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102479802B (zh) | 半导体组件 | |
CN101752375B (zh) | 一种具有改进型终端保护结构的沟槽型功率mos器件 | |
CN203910808U (zh) | 半导体器件 | |
CN101221960B (zh) | 像素结构 | |
CN101752417A (zh) | 横向扩散mos晶体管的版图设计的方法 | |
CN101950746B (zh) | 像素结构 | |
CN103354237B (zh) | 半导体器件 | |
CN105097890A (zh) | 线型架构的功率半导体元件 | |
CN102637738B (zh) | 高压多栅极元件及其制造方法 | |
CN102110691A (zh) | 一种功率场效应晶体管及其布图方法 | |
CN102339850A (zh) | 一种八边形网格状mosfet功率管版图结构 | |
CN103050442B (zh) | 具有抗静电放电能力的功率半导体器件及制造方法 | |
CN103066110A (zh) | 超级接面晶体管及其制作方法 | |
CN203134810U (zh) | 一种阵列基板及显示装置 | |
US9666598B2 (en) | Semiconductor device with an integrated heat sink array | |
CN101510559B (zh) | 功率金属氧化物半导体晶体管元件与布局 | |
US9508693B2 (en) | Semiconductor device with heat sinks | |
CN202996834U (zh) | 一种元胞结构 | |
CN202996835U (zh) | 具有抗静电放电能力的功率半导体器件 | |
CN110854115A (zh) | 一种基于FinFET工艺的标准单元衬底-耦合电容版图结构 | |
CN201608184U (zh) | 一种具有改进型终端保护结构的沟槽型功率mos器件 | |
US20130161752A1 (en) | Semiconductor device | |
CN102299179B (zh) | 横向扩散金属氧化物半导体组件 | |
CN102299153B (zh) | 具有低栅极输入电阻的功率半导体组件及其制作方法 | |
CN102623496B (zh) | 矩阵型mos场效应晶体管 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190814 Address after: Taiwan Hsinchu County China jhubei City, Taiwan 5 yuan a Street No. 9 Building 1 Patentee after: Upi Semiconductor Corp. Address before: 6, No. 5, Taiyuan street, No. 5, Taiyuan street, bamboo North City, county Patentee before: UBIQ Semiconductor Corp. |
|
TR01 | Transfer of patent right |