CN102891168A - 用于高压端接的带场阈值mosfet的半导体器件 - Google Patents

用于高压端接的带场阈值mosfet的半导体器件 Download PDF

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CN102891168A
CN102891168A CN2012102387541A CN201210238754A CN102891168A CN 102891168 A CN102891168 A CN 102891168A CN 2012102387541 A CN2012102387541 A CN 2012102387541A CN 201210238754 A CN201210238754 A CN 201210238754A CN 102891168 A CN102891168 A CN 102891168A
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CN102891168B (zh
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哈姆扎·依玛兹
马督儿·博德
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

一种设置在半导体衬底中的半导体功率器件，所述的半导体衬底含有一个形成在重掺杂层上的轻掺杂层，并且具有一个有源器件元区和一个边缘端接区。边缘端接区含有多个P-通道MOSFET。当外加电压等于或大于P-通道MOSFET晶体管的阈值电压Vt时，通过将栅极连接到漏极上，形成在边缘端接上的P-通道MOSFET晶体管可以顺序开启，从而优化了每个区域闭锁的电压。

Description

用于高压端接的带场阈值MOSFET的半导体器件
技术领域
本发明主要关于半导体功率器件。更确切的说，本发明是关于高压（HV）器件的新型、改良型边缘端接的结构和制备方法，以便减少终接区所占的面积，同时保持高击穿电压。
背景技术
由于浮动保护环（FGR）的间距以及金属层、钝化薄膜下方的电介质层中的电荷，和/或塑料成型复合物的电荷，致使端接区中传统的浮动保护环并不可靠，尤其是封装在塑料封装中的产品。其他的高压（400V以上）端接结构，例如结型端接延伸（JTE）、场保护环以及场板（FGR-FP），使FGR型高压（HV）端接的敏感度降至最低。
Hamza Yilmaz发明的《带有薄型结的高压闭锁结构的最优化及表面电荷灵敏度》发表在关于电子器件的IEEE会刊（1991年7月38卷3号1666-167页）上，提出了一种高压闭锁和端接结构，利用偏移（最优的）多场板和场-限制环（OFP-FLR）结构，并且优化了多区JFET（MZ-JTE）结构，在不增加钝化及工艺复杂性的同时，提高了击穿电压。在OFP-FLR结构中，每个场限制环都有一个场板，覆盖着位于硅衬底表面上的两个相邻的场限制环之间大部分的表面空间，两个场板之间有一个缝隙，多区JTE结构含有多个轻掺杂层，位于硅衬底的表面上，相互靠近，第一p-JTE位于p+电极附近。
Victor A.K. Temple发表在国际电子器件会议（1977年，423-426页）上的《结型端接外延（JTE），一项提高雪崩击穿电压并控制P-N结表面电场的新技术》，提出了一种制备结型端接位于的方法，利用植入提高击穿电压，而不是通过改造或刻蚀现有的半导体衬底。该方法的优势在于，快速、直观控制真实的掺杂电荷，精确度达到1%，并且增加了植入过程的灵活性，几乎可以在制备过程中的任何时刻进行。
美国专利6,011,298提出了一种用于提高击穿电压的带有掩埋场-成型区的高压端接结构。端接结构包括一个掩埋场-成型区，例如掩埋场-成型环，在器件区下方，分开一定的足够大距离，当器件区和衬底之间加载第一电压时，使耗尽区可以形成在掩埋场-成型区和器件区之间，并且当器件区和衬底之间加载的第二电压高于第一电压时，在器件区周围产生一个曲率半径较大的耗尽区。
美国专利4,158,206提出了一种半导体器件，包括半导体材料的本体，具有一个PN结端接在主表面上，掩埋场限制环形成在本体中，并且延伸到一部分PN结附近。掩埋场限制环降低了反向偏置的PN结的表面拦截处的电场强度，从而提高了感兴趣的PN结能承受的反向偏压，增大了半导体材料的击穿电压。
然而，传统的FGR-FP并没有使HV端接区的表面完全屏蔽来自于晶圆表面钝化薄膜和/或组装、封装材料（即成型混料和组装场所）的电荷。
因此，十分有必要提出一种通过多晶硅或金属栅极MOSFET结构，完全密封HV端接区表面的端接结构。
发明内容
因此，本发明的一个方面在于，提出了一种新型、改良的边缘端接结构，以降低在器件边缘处的阻挡结附近的电场拥挤效应，并且提供带有较小的表面电场的紧凑端接，紧凑端接对表面电荷较不敏感。它的实现，是通过在N区和两个P-型扩散区之间或两个浮动保护环（FGR）之间，形成多个P-通道MOSFET。在一个实施例中，在浮动保护环之间的区域上，设置一个覆盖着氧化层的多晶硅或金属层。该多晶硅或金属层作为P-通道MOSFET晶体管的平面栅极。在另一个实施例中，填充在沟槽中的栅极材料，作为P-通道MOSFET晶体管的沟槽栅极。将栅极连接到漏极电极后，P-通道MOSFET晶体管可以作为端接区中的一个通路，以串联的方式，在有源区和划线区（晶片边缘）之间。P-通道MOSFET的阈值电压将决定每个浮动保护环的电势能级。这种新型的HV端接结构可以用于基于平面和基于沟槽的HV器件。
阅读以下详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将显而易见。
附图说明
图1表示高压（HV）器件布局的俯视图；
图2表示依据本发明的第一实施例，图1所示的HV器件沿A-A线的剖面图；
图3表示本发明的图2所示的HV器件的一种可选结构的剖面图；
图4表示依据本发明的第二实施例，图1所示的HV器件沿A-A线的剖面图；
图5表示依据本发明的第三实施例，图1所示的HV器件沿A-A线的剖面图；
图6表示在HV器件端接区的硅表面上的电势分布图；
图7表示在HV器件端接区的硅表面上的电势分布的模拟图；
图8表示端接区的硅衬底中的电势线；
图9A-9B表示HV器件带场板和通道终止区的HV端接结构的剖面图。
具体实施方式
图1表示HV器件100的布局俯视图，HV器件100例如HV MOSFET或HV IGBT，含有一个有源区102和一个端接区104。高压（HV）器件100的有源区102含有多个平面栅极HV MOSFET/IGBT，或沟槽栅极HV MOSFET/IGBT 106。端接区104含有多个串联的P-通道MOSFET 108，称为场阈值MOSFET。场阈值MOSFET形成在端接区中，以承载很高的击穿电压。
图2表示依据本发明的第一实施例，图1所示类型的平面栅极HV器件200沿A-A线的剖面图。HV 器件200形成在半导体衬底上，半导体衬底包括位于重掺杂层105上方的轻掺杂N-型层205。对于HV MOSFET器件来说，重掺杂层105和轻掺杂层205的掺杂类型是一样的，对于HV IGBT器件来说，重掺杂层105和轻掺杂层205的掺杂类型是相反的。为了简便，本申请案中的说明仅用于表示HV MOSFET器件。HV器件200含有一个有源区201和一个端接区203。有源区201含有多个平面栅极N-通道垂直MOSFET 202，每个N-通道垂直MOSFET 202都含有一个n+源极204、一个形成在n+衬底105中的漏极以及一个平面栅极206。端接区203含有多个P-通道MOSFET 210，每个P-通道MOSFET 210都位于两个P-型扩散区之间，或两个浮动保护环（FGR）212之间。P-型浮动保护环的掺杂浓度高于轻掺杂的N-型层205。制备多个端接浮动保护环，使两个相邻的端接浮动保护环之间的间距为1至10微米，在半导体衬底中的深度为0.5至8微米。每个P-通道MOSFET 210含有一个导电层，例如掺杂的多晶硅或金属层214，氧化层215使导电层与半导体衬底绝缘，氧化层215设置在两个浮动保护环212之间的区域中，构成一个平面栅极横向MOSFET，在多晶硅或金属层214两边各有一个浮动保护环212，作为横向P-通道MOSFET的源极和漏极。该多晶硅或金属层214作为P-通道MOSFET 210的平面栅极。端接区203中的多晶硅或金属层214的两个栅极部分之间的浮动保护环212都作为P-通道MOSFET 210的漏极，以及其他P-通道MOSFET的源极。设置在栅极部分两个对边上的漏极和源极区，具有1e17cm-3至1e20cm-3的掺杂浓度。通过将P-通道MOSFET的栅极214连接到漏极212（P-通道MOSFET的漏极为电势较低的p-区），P-通道MOSFET晶体管210以串联的方式，作为端接区203中的电路。P-通道MOSFET的阈值电压将决定每个浮动保护环（FGR）的电势能级，并且可以利用表面植入（例如n-型植入）调节P-通道MOSFET的阈值电压，以改变顶部区域208的掺杂。制备有源晶体管的P本体区时可以同时制备浮动保护环212，两者的掺杂浓度也相同，端接区中的横向MOSFET的栅极214可以与有源晶体管平面栅极在同一制备过程中形成。以与有源区中的接触植入相同的方式，在浮动保护环212中制备很高掺杂的接触植入，以改善浮动保护环212的电接触。
图3表示图2所示的HV器件200的可选结构的剖面图。图3中的器件300除了端接区303中的P-通道MOSFET 211也含有n+虚拟源极区204之外，其他都与器件200类似，n+虚拟源极区204并没有在有源区301中的源极植入过程中，闭锁在端接区303中。P-通道MOSFET 211与图2所示的P-通道MOSFET 210的工作方式相同。此外，n+虚拟源极区204也配置平面栅极MOSFET像在端接区里那样作为N-通道垂直MOSFET，其中栅极短接至源极/本体区，以实现常闭。
本发明所述的新型HV端接结构，利用图2-3所示的场阈值MOSFET，也可以用于图4-5所示的沟槽栅极HV器件。
图4表示依据本发明的第二实施例，一种沟槽栅极高压（HV）器件400的剖面图。器件400的有源区401含有多个沟槽栅极垂直N-通道MOSFET 402，每个N-通道MOSFET 402都含有一个n+源极404、一个沟槽栅极406以及一个形成在n+衬底105中的漏极。与图2所示的器件200类似，器件400的端接区403含有多个P-通道平面栅极横向MOSFET 210，每个P-通道平面栅极横向MOSFET都位于两个P-型扩散区之间或两个浮动保护环212之间，其中栅极214连接到漏极212上。如上所述，P-通道MOSFET晶体管210以串联的方式，在有源区和划线区（晶片边缘）之间，作为一个电路。浮动保护环212可以与有源晶体管的P本体区同时形成，并且掺杂浓度相同。如图3所示，还可选择，端接区403可以含有多个P-通道MOSFET 211。
图5表示依据本发明的第三实施例，另一种沟槽栅极HV器件500的剖面图。在本实施例中，有源区501包括多个图4中所示类型的沟槽栅极垂直N-通道MOSFET 402。端接区503含有多个沟槽栅极P-通道横向MOSFET 504，每个P-通道横向MOSFET 504都含有与沟槽栅极MOSFET 402相同的结构，并且位于两个P-型扩散区或两个浮动保护环 512之间。形成多个端接沟槽，使两个相邻的端接沟槽之间的间距为0.5至5微米，在半导体衬底中的深度为0.5至8微米。每个P-通道MOSFET 504的栅极材料506都作为沟槽栅极，并且连接到漏极电极512上（沟槽MOSFET的漏极为带有较多负电势的p-区）。位于端接区503中的两个沟槽栅极506之间的每个浮动保护环 512都作为P-通道MOSFET 504的漏极，以及作为其他P-通道MOSFET的源极。如上所述，通过将栅极连接到漏极电极，P-通道MOSFET晶体管504以串联方式，作为一个电路。沟槽MOSFET的阈值电压，将确定每个浮动保护环（FGR）的电势能级，并且可以在外延生长区域508时，通过植入（例如n-型植入）或改变掺杂浓度，来调节沟槽MOSFET的阈值电压。图5所示的实施例表示阈值调节层508延伸到有源区501中。在另一个实施例中（图中没有表示出），可以仅通过在端接区中植入，而无需延伸到有源区501中，就能制备阈值调节层508。阈值调节层508的掺杂浓度高于外延层205。在一个实施例中，阈值调节层508的掺杂浓度高于有源区的P本体区。浮动保护环 512可以与有源晶体管的P本体区同时形成，并且掺杂浓度相同。与有源区中的接触植入方式相同，可以在浮动保护环 512中进行很高的掺杂接触植入，以便改善与浮动保护环 512的电接触。
为了将这些P-通道MOSFET都配置成场阈值MOSFET，而不是将栅极保留至浮动电压或者将栅极短接至源极，其中P-通道MOSFET为常闭；每个栅极都连接到它所对应的漏极上，从而使栅极和漏极处于相同的电势。当器件上加载阈值电压Vt时，即Vds=Vgs=Vt，其中Vds为漏源电压，Vgs为栅源电压，这些P-通道MOSFET全部开启。当功率器件上的电压升高时，这些P-通道MOSFET顺序开启，以承受器件上逐渐升高的电压。每个P-通道MOSFET或每个沟槽的电势都均匀升高到场阈值电压（例如50V）。因此，所需的P-通道MOSFET的数量，取决于设计的HV器件的击穿电压。一般来说，大约1至25个P-通道MOSFET形成在宽度为5微米至250微米的边缘端接区中。因此，带有这些多P-通道MOSFET的基于场阈值的端接，可以承受很高的击穿电压。图6表示硅衬底表面上的电势分布，其中多个P-通道MOSFET形成在端接区中。图7表示端接区的硅衬底表面上的电势分布模拟图。图8表示电势线在硅衬底上的分布图，从而降低电场拥挤，不需要很大的端接区，就能大幅提高击穿电压。
可以优化P-通道MOSFET的阈值电压的绝对值，凭借最适宜的HV端接区尺寸，获得很高的击穿电压。低Vt需要较多的P-通道MOSFET，因此端接区变得较大。与之相反，高Vt不会在端接区产生所需的击穿电压，器件的击穿电压将低于目标值。根据所需的高击穿电压的技术要求，P-通道MOSFET的Vt可以通过调整氧化物的厚度，或限定表面浓度的校正，从而提高N-型掺杂浓度，以便增大Vt，或者通过反向掺杂N-型区域的浓度来减小Vt。阈值电压Vt的范围为0.5至80V。
图9A-9B表示图2至5所示类型的HV端接结构与第一场板相结合的末端部分的剖面图，其中第一场板形成在最后一个P-型扩散区或最后一个浮动保护环附近，形成在通道终止区的场板，进一步拓展了边缘端接的高压闭锁性能。
如图9A-9B所示，第一场板904形成在最后一个P-型扩散区或最后一个浮动保护环212附近，如图3和5所示。第一场板904从最后一个浮动保护环212开始，向着划线920延伸。第一场板904通过金属910，电连接到最后一个浮动保护环212上。与半导体衬底的轻掺杂层导电类型相同的重掺杂通道终止区902，例如N+掺杂区902，形成在端接区边缘附近的半导体衬底的表面上，以便阻止半导体衬底表面处的电场。第二场板905也形成在通过终止区902附近，并且从通道终止区902开始，向着有源区延伸。第二场板905和通道终止区902通过金属912，互相电连接。通过场氧化层906，场板904和905相互电绝缘，并且通过含有硼酸的硅玻璃（BPSG）层908，相互隔离。场板904和905分散了端接区边缘处的电场，从而提高了击穿电压。
本发明所述的HV器件端接结构，也可以用于多种类型的高压器件，包括MOSFET、IGBT、JFET/SIT N-漂流二极管型器件。实施例仅用于解释说明N通道器件。通过转换掺杂极性的类型，也可以用于P通道器件。
尽管本发明已经详细说明了现有的较佳实施例，但应理解这些说明不应作为本发明的局限。本领域的技术人员阅读上述详细说明后，各种变化和修正无疑将显而易见。因此，应认为所附的权利要求书涵盖了本发明的真实意图和范围内的全部变化和修正。

Claims (33)

1.一种半导体功率器件，其设置在半导体衬底中，包括一个形成在重掺杂层上方的轻掺杂层，并且具有一个有源器件元区和一个边缘端接区，其特征在于，
所述的边缘端接区含有多个端接沟槽，形成在所述的轻掺杂层中，内衬电介质层，其中用导电材料填充；以及
多个串联的MOSFET晶体管，每个MOSFET晶体管都含有一个沟槽栅极区和设置在每个所述的端接沟槽的两个对边上的一个漏极区和一个源极区，每个所述的端接沟槽中所述的导电材料作为每个所述的MOSFET晶体管的沟槽栅极，其中每个沟槽栅极都电连接到所述的漏极区。
2.根据权利要求1所述的半导体功率器件，其特征在于，所述的多个MOSFET晶体管是由多个P-通道MOSFET晶体管构成的。
3.根据权利要求1所述的半导体功率器件，其特征在于，当所加的电压大于或等于所述的MOSFET晶体管的阈值电压时，多个MOSFET晶体管中的一个MOSFET晶体管开启，其中所述的阈值电压范围为0.5至80V。
4.根据权利要求1所述的半导体功率器件，其特征在于，所述的边缘端接的宽度范围为5微米至250微米，以便在所述的边缘端接中，形成1至25个端接沟槽。
5.根据权利要求1所述的半导体功率器件，其特征在于，所述的多个端接沟槽中，两个相邻的端接沟槽之间的间距为0.5至5微米。
6.根据权利要求1所述的半导体功率器件，其特征在于，所述的多个端接沟槽延伸到所述的半导体衬底中的深度为0.5至8微米。
7.根据权利要求1所述的半导体功率器件，其特征在于，设置在每个所述的端接沟槽的两个对边上的所述的漏极区和源极区，具有1e17cm-3至1e20cm-3的掺杂浓度。
8.根据权利要求1所述的半导体功率器件，其特征在于，通过限定沟槽电介质厚度的局部变化以及/或者限定半导体衬底所述的轻掺杂层的掺杂浓度的局部变化，调节每个MOSFET晶体管所述的阈值电压。
9.根据权利要求1所述的半导体功率器件，其特征在于，还包括：
一个第一场板，从最后一个浮动保护环的附近开始，向着划线延伸；
一个重掺杂的通道终止区；以及
一个第二场板，形成在所述的通道终止区附近，并且向着所述的有源器件元区延伸。
10.根据权利要求1所述的半导体功率器件，其特征在于，所述的重掺杂层的极性与轻掺杂层相反，构成一个IGBTs。
11.根据权利要求1所述的半导体功率器件，其特征在于，所述的重掺杂层的极性与轻掺杂层相同，构成MOSFETs。
12.一种半导体功率器件，其设置在半导体衬底中，含有形成在重掺杂层上方的轻掺杂层，并且具有一个有源器件元区和一个边缘端接区，其特征在于， 
所述的边缘端接区含有多个端接浮动保护环，形成在所述的轻掺杂层中，以及所述的半导体衬底的表面区域中，通过一个电介质层与所述的半导体衬底绝缘一个导电材料，电介质层设置在两个相邻的端接浮动保护环之间的区域上，所述的端接浮动保护环的导电类型与所述的半导体衬底的导电类型相反，掺杂浓度高于轻掺杂层；以及
多个串联的MOSFET晶体管包括一个平面栅极区、以及设置在两个浮动保护环之间的所述的平面栅极区的两个对边上的漏极区和源极区，所述的导电材料作为每个所述的MOSFET晶体管的所述的平面栅极，其中每个所述的平面栅极连接到所述的漏极区。
13.根据权利要求12所述的半导体功率器件，其特征在于，所述的多个MOSFET晶体管是由多个P-通道MOSFET晶体管构成的。
14.根据权利要求13所述的半导体功率器件，其特征在于，当所述的MOSFET晶体管加载阈值电压时，所述的多个MOSFET晶体管的其中一个开启，其中所述的阈值电压范围为0.5至80V。
15.根据权利要求12所述的半导体功率器件，其特征在于，通过限制表面电介质厚度的局部变化，以及/或者限制所述的半导体表面的表面掺杂浓度的局部变化，调节每个MOSFET晶体管的阈值电压。
16.根据权利要求13所述的半导体功率器件，其特征在于，两个相邻的端接浮动保护环之间的距离为1至10微米。
17.根据权利要求14所述的半导体功率器件，其特征在于，所述的多个端接浮动保护环，在所述的半导体衬底中的深度为0.5至8微米。
18.根据权利要求12所述的半导体功率器件，其特征在于，所述的漏极区和源极区的掺杂浓度为1e15cm-3至1e20cm-3。
19.根据权利要求10所述的半导体功率器件，其特征在于，还包括：
一个第一场板，从最后一个浮动保护环周围开始，向着划线延伸；
一个重掺杂的通道终止区，其导电类型与所述的轻掺杂层相同。
20.根据权利要求19所述的半导体功率器件，其特征在于，还包括：一个第二场板，形成在所述的通道终止区周围，向着所述的有源器件元区延伸。
21.根据权利要求12所述的半导体功率器件，其特征在于，所述的重掺杂层的极性与轻掺杂层相反，构成一个IGBTs。
22.根据权利要求12所述的半导体功率器件，其特征在于，所述的重掺杂层的极性与轻掺杂层相同，构成MOSFETs。
23.一种用于在半导体衬底上制备含有源区和端接区的半导体功率器件的方法，其特征在于，该方法包括：在有源区中制备多个垂直金属氧化物半导体场效应晶体管，在端接区中通过形成多个掺杂的浮动保护环，制备多个串联的横向MOSFET，每个浮动保护环都包围在掺杂的扩散区中，形成漏极区和源极区，设置在每个串联的横向MOSFET的栅极的对边上，以承受高击穿电压。
24.根据权利要求23所述的方法，其特征在于，所述的在有源区中制备多个垂直金属氧化物半导体场效应晶体管的步骤，包括在有源区中制备多个垂直平面MOSFET。
25.根据权利要求23所述的方法，其特征在于，所述的在有源区中制备多个垂直金属氧化物半导体场效应晶体管的步骤，包括在有源区中制备多个垂直沟槽MOSFET。
26.根据权利要求23所述的方法，其特征在于，所述的在端接区中制备多个串联的横向MOSFET的步骤，包括在端接区中，制成多个串联的横向P-通道MOSFET，将每个掺杂的掩埋浮动环制成P-型掺杂浮动保护环，并将每个横向P-通道MOSFET的栅极连接到作为所述的串联横向P-通道MOSFET的漏极区的P-掺杂浮动保护环的其中之一。
27.根据权利要求23所述的方法，其特征在于，所述的在端接区中制备多个串联的横向MOSFET的步骤，包括在端接区中，将多个串联的横向MOSFET制成端接区中串联的横向平面MOSFET。
28.根据权利要求23所述的方法，其特征在于，所述的在端接区中制备多个串联的横向MOSFETs的步骤，包括在端接区中，将多个串联的横向MOSFET制成端接区中串联的横向沟槽MOSFETs。
29.根据权利要求23所述的方法，其特征在于，所述的在端接区中制备多个串联的横向MOSFETs的步骤，包括在端接区中将多个串联的横向MOSFETs制成端接区中串联的横向P-通道平面MOSFETs，将每个掺杂的浮动环制成P-型掺杂浮动保护环，并将每个P-通道MOSFET的栅极制成平面栅极，将平面栅极连接到作为串联横向P-通道平面MOSFET的漏极区的P-掺杂浮动保护环的其中之一。
30.根据权利要求23所述的方法，其特征在于，在端接区中制备多个串联的横向MOSFETs的步骤，包括在端接区中将多个串联的横向MOSFETs制成在端接区中串联的横向P-通道沟槽MOSFETs，将每个掺杂的浮动环制成P-型掺杂浮动保护环，并将每个P-通道MOSFET的栅极制成沟槽栅极，以及将沟槽栅极连接到作为串联横向P-通道沟槽MOSFET的漏极区的P-掺杂浮动保护环的其中之一。
31.根据权利要求23所述的方法，其特征在于，还包含：制备含有第一导电板的第一场板，第一导电板在最外面的掺杂扩散区附近，并且将第一场板连接到被包围在最外面的掺杂扩散区中的掺杂浮动保护环上。
32.根据权利要求31所述的方法，其特征在于，制备含有第二导电板的第二场板，第二导电板在划线区周围的通道终止区中最外面的掺杂浮动保护环附近，并且将第一场板连接到最外面的掺杂浮动保护环上。
33.根据权利要求32所述的方法，其特征在于，在第一场板和第二场板之间，制备一个绝缘层，使第一场板与第二场板绝缘。
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