TWI538209B - 半導體功率元件及其製備方法 - Google Patents

半導體功率元件及其製備方法 Download PDF

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TWI538209B
TWI538209B TW101126114A TW101126114A TWI538209B TW I538209 B TWI538209 B TW I538209B TW 101126114 A TW101126114 A TW 101126114A TW 101126114 A TW101126114 A TW 101126114A TW I538209 B TWI538209 B TW I538209B
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power device
semiconductor power
effect transistors
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依瑪茲 哈姆札
博德 馬督兒
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萬國半導體股份有限公司
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

半導體功率元件及其製備方法
本發明是有關於一種半導體功率元件,特別是關於高壓(HV)元件的新型、改良型邊緣終止區的半導體功率元件結構和製備方法,以便減少終接區所占的面積,同時保持高擊穿電壓。
由於浮動保護環(FGR)的間距以及金屬層、鈍化薄膜下方的電介質層中的電荷,或塑膠成型複合物的電荷,致使終端區中傳統的浮動保護環並不可靠,尤其是封裝在塑膠封裝中的產品。其他的高壓(400V以上)端接結構,例如結型端接延伸(JTE)、場保護環以及電場板(FGR-FP),使FGR型高壓(HV)端接的敏感度降至最低。
Hamza Yilmaz發明的《帶有薄型結的高壓閉鎖結構的最佳化及表面電荷靈敏度》發表在關於電子元件的IEEE會刊(1991年7月38卷3號1666-167頁)上,提出了一種高壓閉鎖和端接結構,利用偏移(最佳的)多電場板和場-限制環(OFP-FLR)結構,並且優化了多區JFET(MZ-JTE)結構,在不增加鈍化及製程複雜性的同時,提高了擊穿電壓。在OFP-FLR結構中,每個場限制環都有一個電場板,覆蓋著位於矽基板表面上的兩個相鄰的場限制環之間大部分的表面空間,兩個電場板之間有一個縫隙,多區JTE結構含有多個輕摻雜層,位於矽基板 的表面上,相互靠近,第一p-JTE位於p+電極附近。
Victor A.K.Temple發表在國際電子元件會議(1977年,423-426頁)上的《結型端接外延(JTE),一項提高雪崩擊穿電壓並控制P-N結表面電場的新技術》,提出了一種製備結型端接位於的方法,利用植入提高擊穿電壓,而不是透過改造或刻蝕現有的半導體基板。該方法的優勢在於,快速、直觀控制真實的摻雜電荷,精確度達到1%,並且增加了植入過程的靈活性,幾乎可以在製備過程中的任何時刻進行。
美國專利6,011,298提出了一種用於提高擊穿電壓的帶有掩埋場-成型區的高壓端接結構。端接結構包括一個掩埋場-成型區,例如掩埋場-成型環,在元件區下方,分開一定的足夠大距離,當元件區和基板之間載入第一電壓時,使耗盡區可以形成在掩埋場-成型區和元件區之間,並且當元件區和基板之間載入的第二電壓高於第一電壓時,在元件區周圍產生一個曲率半徑較大的耗盡區。
美國專利4,158,206提出了一種半導體元件,包括半導體材料的本體,具有一個PN結端接在主表面上,掩埋場限制環形成在本體中,並且延伸到一部分PN結附近。掩埋場限制環降低了反向偏置的PN結的表面攔截處的電場強度,從而提高了感興趣的PN結能承受的反向偏壓,增大了半導體材料的擊穿電壓。
然而,傳統的FGR-FP並沒有使HV終端區的表面完全遮罩來自於晶圓表面鈍化薄膜或組裝、封裝材料(即成型混料和組裝場所)的電荷。
因此,十分有必要提出一種透過多晶矽或金屬閘極MOSFET結構,完全密封HV終端區表面的端接結構。
有鑑於上述習知技藝之問題,本發明之其中一目的就是在提供一種新型、改良的邊緣終止區結構,以降低在元件邊緣處的阻擋結附近的電場擁擠效應,並且提供帶有較小的表面電場的緊湊端接,緊湊端接對表面電荷較不敏感。它的實現,是透過在N區和兩個P-型擴散區之間或兩個浮動保護環(FGR)之間,形成多個P-通道MOSFET。在一個實施例中,在浮動保護環之間的區域上,設置一個覆蓋著氧化層的多晶矽或金屬層。多晶矽或金屬層作為P-通道MOSFET電晶體的平面閘極。在另一個實施例中,填充在溝槽中的閘極材料,作為P-通道MOSFET電晶體的溝槽閘極。將閘極連接到汲極電極後,P-通道MOSFET電晶體可以作為終端區中的一個通路,以串聯的方式,在有源區和劃線區(晶片邊緣)之間。P-通道MOSFET的門檻值電壓將決定每個浮動保護環的電勢能級。這種新型的HV端接結構可以用於基於平面和基於溝槽的HV元件。
閱讀以下詳細說明並參照附圖之後,本發明的這些和其他的特點和優勢,對於本發明技術領域中具有通常知識者而言,無疑將顯而易見。
100‧‧‧高壓(HV)元件
102、201、301、401、501‧‧‧有源區
104、203、303、403、503‧‧‧終端區
105‧‧‧重摻雜層
106‧‧‧溝槽閘極
108、210、211‧‧‧P-通道MOSFET
200‧‧‧平面閘極HV元件
202‧‧‧N-通道垂直MOSFET
204、404‧‧‧n+源極
205‧‧‧輕摻雜層
206‧‧‧平面閘極
208‧‧‧頂部區域
212、512‧‧‧浮動保護環
214‧‧‧多晶矽或金屬層
215‧‧‧氧化層
300‧‧‧元件
400‧‧‧溝槽閘極高壓(HV)元件
402‧‧‧垂直N-通道MOSFET
406、506‧‧‧溝槽閘極
500‧‧‧溝槽閘極HV元件
504‧‧‧P-通道橫向MOSFET
508‧‧‧外延生長區域
902‧‧‧通道終止區
904、905‧‧‧電場板
906‧‧‧場氧化層
908‧‧‧矽玻璃(BPSG)層
910、912‧‧‧金屬
A-A‧‧‧線
第1圖係為本發明之高壓(HV)元件佈局之俯視圖。
第2圖係為依據本發明之第一實施例,第1圖所示的HV元件沿線A-A之剖面圖。
第3圖係為本發明之第2圖所示之HV元件之一種可選結構之剖面圖。
第4圖係為依據本發明的第二實施例,第1圖所示的HV元件沿線A-A之剖面圖。
第5圖係為依據本發明的第三實施例,第1圖所示的HV元件沿線A-A之剖面圖。
第6圖係為在HV元件終端區的矽表面上之電勢分佈圖。
第7圖係為在HV元件終端區的矽表面上之電勢分佈之模擬圖。
第8圖係為終端區的矽基板中之電勢線之示意圖。
第9A圖及第9B圖係為HV元件帶電場板和通道終止區的HV端接結構之剖面圖。
以下將參照相關圖式,說明依本發明之半導體功率元件及其製備方法之實施例,為使便於理解,下述實施例中之相同元件係以相同之符號標示來說明。
請參閱第1圖,其表示高壓(HV)元件100之佈局俯視圖,高壓(HV)元件100例如高壓金氧半場效電晶體(HV MOSFET)或高壓絕緣閘雙極電晶體(HV IGBT),含有一個有源區102和一個終端區104。高壓(HV)元件100的有源區102含有多個平面閘極HV MOSFET/IGBT,或溝槽閘極HV MOSFET/IGBT 106。終端區104含有多個串聯的P-通道MOSFET 108,稱為場門檻值MOSFET。場門檻值MOSFET形成在終端區中,以承載很高的擊穿電壓。
請參閱第2圖,其表示依據本發明的第一實施例,第1圖所示類型的平面閘極HV元件200沿線A-A之剖面圖。平面閘極HV元件200形成在半導體基板上,半導體基板包括位於重摻雜層105上方的輕摻雜層205。對於HV MOSFET元件來說,重摻雜層105和輕摻雜層205的摻雜類型是一樣的,對於HV IGBT元件來說,重摻雜層105和輕摻雜層205的摻雜類型是相反的。為了簡便,本實施例中的說明僅用於表示HV MOSFET元件。平面閘極HV元件200含有一個有源區201和一個終端區203。有源區201含有多個平面閘極N-通道垂直MOSFET 202,每個N-通道垂直MOSFET 202都含有一個n+源極204、一個形成在重摻雜層105中的汲極以及一個平面閘極206。終端區203含有多個P-通道MOSFET 210,每個P-通道MOSFET 210都位於兩個P-型擴散區之間,或兩個浮動保護環(FGR)212之間。P-型浮動保護環的摻雜濃度高於輕摻雜的輕摻雜層205。製備多個端接浮動保護環,使兩個相鄰的端接浮動保護環之間的間距為1至10微米,在半導體基板中的深度為0.5至8微米。每個P-通道MOSFET 210含有一個導電層,例如摻雜的多晶矽或金屬層214,氧化層215使導電層與半導體基板絕緣,氧化層215設置在兩個浮動保護環212之間的區域中,構成一個平面閘極橫向MOSFET,在多晶矽或金屬層214兩邊各有一個浮動保護環212,作為橫向P-通道MOSFET的源極和汲極。該多晶矽或金屬層214作為P-通道MOSFET 210的平面閘極。終端區203中的多晶矽或金屬層214的兩個閘極部分之間的浮動保護環212都作為P-通道MOSFET 210的汲極,以及其他P-通道MOSFET的源極。設置在閘極部分兩個對邊上的汲極和源極區,具有1e17cm-3至1e20cm-3的摻雜濃度。透過將P-通道MOSFET的閘極214連接到汲極212(P-通道MOSFET的汲極為電勢較低的p-區),P-通道MOSFET 210以串聯的方式,作為終端區203 中的電路。P-通道MOSFET的門檻值電壓將決定每個浮動保護環(FGR)的電勢能級,並且可以利用表面植入(例如n-型植入)調節P-通道MOSFET的門檻值電壓,以改變頂部區域208的摻雜。製備有源電晶體的P本體區時可以同時製備浮動保護環212,兩者的摻雜濃度也相同,終端區中的橫向MOSFET的閘極214可以與有源電晶體平面閘極在同一製備過程中形成。以與有源區中的接觸植入相同的方式,在浮動保護環212中製備很高摻雜的接觸植入,以改善浮動保護環212的電接觸。
請參閱第3圖,其表示第2圖所示之平面閘極HV元件200的可選結構之剖面圖。第3圖中的元件300除了終端區303中的P-通道MOSFET 211也含有虛擬n+源極區204之外,其他都與平面閘極HV元件200類似,虛擬n+源極區204並沒有在有源區301中的源極植入過程中,閉鎖在終端區303中。P-通道MOSFET 211與第2圖所示的P-通道MOSFET 210的工作方式相同。此外,虛擬n+源極區204也配置平面閘極MOSFET像在終端區裏那樣作為N-通道垂直MOSFET,其中閘極短接至源極或本體區,以實現常閉。
本發明所述的新型HV端接結構,利用第2圖至第3圖所示的場門檻值MOSFET,也可以用於第4圖至第5圖所示的溝槽閘極HV元件。
請參閱第4圖,其表示依據本發明的第二實施例,一種溝槽閘極高壓(HV)元件400之剖面圖。溝槽閘極高壓(HV)元件400的有源區401含有多個溝槽閘極垂直N-通道MOSFET 402,每個N-通道MOSFET 402都含有一個n+源極404、一個溝槽閘極406以及一個形成在重摻雜層105中的汲極。與第2圖所示的平面閘極HV元件200類似,溝槽閘極高壓(HV)元件400的終端區403含有多個P-通道平 面閘極橫向MOSFET 210,每個P-通道平面閘極橫向MOSFET都位於兩個P-型擴散區之間或兩個浮動保護環212之間,其中閘極214連接到汲極212上。如上所述,P-通道MOSFET 210以串聯的方式,在有源區和劃線區(晶片邊緣)之間,作為一個電路。浮動保護環212可以與有源電晶體的P本體區同時形成,並且摻雜濃度相同。如第3圖所示,更可選擇,終端區403可以含有多個P-通道MOSFET 211。
請參閱第5圖,其表示依據本發明的第三實施例,另一種溝槽閘極HV元件500之剖面圖。在本實施例中,有源區501包括多個第4圖中所示類型的溝槽閘極垂直N-通道MOSFET 402。終端區503含有多個溝槽閘極P-通道橫向MOSFET 504,每個P-通道橫向MOSFET 504都含有與溝槽閘極垂直N-通道MOSFET 402相同的結構,並且位於兩個P-型擴散區或兩個浮動保護環512之間。形成多個端接溝槽,使兩個相鄰的端接溝槽之間的間距為0.5至5微米,在半導體基板中的深度為0.5至8微米。每個P-通道橫向MOSFET 504的閘極材料都作為溝槽閘極506,並且連接到汲極電極512上(溝槽MOSFET的汲極為帶有較多負電勢的p-區)。位於終端區503中的兩個溝槽閘極506之間的每個浮動保護環512都作為P-通道橫向MOSFET 504的汲極,以及作為其他P-通道MOSFET的源極。如上所述,透過將閘極連接到汲極電極,P-通道橫向MOSFET 504以串聯方式,作為一個電路。溝槽MOSFET的門檻值電壓,將確定每個浮動保護環(FGR)的電勢能級,並且可以在外延生長區域508時,透過植入(例如n-型植入)或改變摻雜濃度,來調節溝槽MOSFET的門檻值電壓。第5圖所示的實施例表示門檻值調節層508延伸到有源區501中。在另一個實施例中(圖中沒有表示出),可以僅透過在終端區中植入,而無需延伸到有源區501中,就能製備門檻值調節層508。門檻值調節層508的摻雜濃度高於外延層205。在一 個實施例中,門檻值調節層508的摻雜濃度高於有源區的P本體區。浮動保護環512可以與有源電晶體的P本體區同時形成,並且摻雜濃度相同。與有源區中的接觸植入方式相同,可以在浮動保護環512中進行很高的摻雜接觸植入,以便改善與浮動保護環512的電接觸。
為了將這些P-通道MOSFET都配置成場門檻值MOSFET,而不是將閘極保留至浮動電壓或者將閘極短接至源極,其中P-通道MOSFET為常閉;每個閘極都連接到它所對應的汲極上,從而使閘極和汲極處於相同的電勢。當元件上載入門檻值電壓Vt時,即Vds=Vgs=Vt,其中Vds為漏源電壓,Vgs為閘源電壓,這些P-通道MOSFET全部開啟。當功率元件上的電壓升高時,這些P-通道MOSFET順序開啟,以承受元件上逐漸升高的電壓。每個P-通道MOSFET或每個溝槽的電勢都均勻升高到場門檻值電壓(例如50V)。因此,所需的P-通道MOSFET的數量,取決於設計的HV元件的擊穿電壓。一般來說,大約1至25個P-通道MOSFET形成在寬度為5微米至250微米的邊緣終止區中。因此,帶有這些多P-通道MOSFET的基於場門檻值的端接,可以承受很高的擊穿電壓。第6圖表示矽基板表面上的電勢分佈,其中多個P-通道MOSFET形成在終端區中。第7圖表示終端區的矽基板表面上之電勢分佈模擬圖。第8圖表示電勢線在矽基板上之分佈圖,從而降低電場擁擠,不需要很大的終端區,就能大幅提高擊穿電壓。
可以優化P-通道MOSFET的門檻值電壓的絕對值,憑藉最適宜的HV終端區尺寸,獲得很高的擊穿電壓。低Vt需要較多的P-通道MOSFET,因此終端區變得較大。與之相反,高Vt不會在終端區產生所需的擊穿電壓,元件的擊穿電壓將低於目標值。根據所需的高擊穿電壓的技術要求,P-通道MOSFET的Vt可以透過調整氧化物的厚度,或限定表面濃度的校正,從而提高N-型摻雜濃度,以便增大Vt,或者透 過反向摻雜N-型區域的濃度來減小Vt。門檻值電壓Vt的範圍為0.5至80V。
請參閱第9A至9B圖,其分別表示第2圖至第5圖所示類型的HV端接結構與第一電場板相結合的末端部分之剖面圖,其中第一電場板形成在最後一個P-型擴散區或最後一個浮動保護環附近,形成在通道終止區的電場板,進一步拓展了邊緣終止區的高壓閉鎖性能。
如第9A至9B圖所示,第一電場板904形成在最後一個P-型擴散區或最後一個浮動保護環212附近,如第3圖和第5圖所示。第一電場板904從最後一個浮動保護環212開始,向著劃線920延伸。第一電場板904透過金屬910,電連接到最後一個浮動保護環212上。與半導體基板的輕摻雜層導電類型相同的重摻雜通道終止區902,例如N+摻雜區902,形成在終端區邊緣附近的半導體基板的表面上,以便阻止半導體基板表面處的電場。第二電場板905也形成在通道終止區902附近,並且從通道終止區902開始,向著有源區延伸。第二電場板905和通道終止區902通過金屬912,互相電連接。通過場氧化層906,電場板904和905相互電絕緣,並且通過含有硼酸的矽玻璃(BPSG)層908,相互隔離。電場板904和905分散了終端區邊緣處的電場,從而提高了擊穿電壓。
本發明所述的HV元件端接結構,也可以用於多種類型的高壓元件,包括MOSFET、IGBT、JFET/SIT N-漂流二極體型元件。實施例僅用於解釋說明N通道元件。透過轉換摻雜極性的類型,也可以用於P通道元件。
儘管本發明已經詳細說明了現有的較佳實施例,但應理解這些說明不應作為本發明的侷限。本發明所屬技術領域中具有通常知識 者閱讀上述詳細說明後,各種變化和修正無疑將顯而易見。因此,應認為所附的申請專利範圍涵蓋了本發明的真實意圖和範圍內的全部變化和修正。
100‧‧‧高壓(HV)元件
102‧‧‧有源區
104‧‧‧終端區
106‧‧‧溝槽閘極
108‧‧‧P-通道MOSFET

Claims (33)

  1. 一種半導體功率元件,其設置在一半導體基板中,該半導體功率元件包含一形成在一重摻雜層上方之輕摻雜層,並且具有一主動晶胞區和一邊緣終止區;其中,該邊緣終止區含有複數個端接溝槽,形成於該輕摻雜層中,一內襯電介質層,其中用一導電材料填充;以及複數個串聯的金氧半場效電晶體,各該金氧半場效電晶體係包含一溝槽閘極區及設置在各該端接溝槽的兩個對邊上的一汲極區和一源極區,各該端接溝槽中該導電材料作為各該金氧半場效電晶體之該溝槽閘極,其中各該溝槽閘極係電性連接至該汲極區,其中還在該輕摻雜層頂部形成摻雜濃度高於輕摻雜層的門檻值調節層,該門檻值調節層的摻雜濃度高於有源器件元區的本體區。
  2. 如申請專利範圍第1項所述之半導體功率元件,其中,該些金氧半場效電晶體係由複數個P-通道金氧半場效電晶體構成。
  3. 如申請專利範圍第1項所述之半導體功率元件,其中,當所加之電壓大於或等於該些金氧半場效電晶體之一門檻值電壓時,該些金氧半場效電晶體中之其中一該金氧半場效電晶體開啟,該門檻值電壓範圍為0.5伏特至80伏特。
  4. 如申請專利範圍第1項所述之半導體功率元件,其中該邊緣終止區之寬度範圍係為5微米至250微米,以在該邊緣終止區中,形成1至25個該些端接溝槽。
  5. 如申請專利範圍第1項所述之半導體功率元件,其中該些端接溝槽中,兩個相鄰之該端接溝槽之間的間距為0.5微米至5微米。
  6. 如申請專利範圍第1項所述之半導體功率元件,其中該些端接溝槽延伸到該半導體基板中的深度為0.5微米至8微米。
  7. 如申請專利範圍第1項所述之半導體功率元件,其中設置在各該端接溝槽的兩個對邊上的該汲極區和該源極區,係具有1e17cm-3至1e20cm-3的摻雜濃度。
  8. 如申請專利範圍第1項所述之半導體功率元件,其中藉由限定一溝槽電介質厚度的局部變化或者限定該半導體基板之該輕摻雜層的摻雜濃度的局部變化,以調節各該金氧半場效電晶體之該門檻值電壓。
  9. 如申請專利範圍第1項所述之半導體功率元件,其更包含:一第一電場板,從最後一浮動保護環的周圍開始,向著一劃線區延伸;一重摻雜的通道終止區;以及一第二電場板,形成在該通道終止區邊緣,並且向該主動晶胞區延伸。
  10. 如申請專利範圍第1項所述之半導體功率元件,其中該重摻雜層的極性與該輕摻雜層相反,以構成一絕緣閘極雙極性電晶體。
  11. 如申請專利範圍第1項所述之半導體功率元件,其中該重摻雜層的極性與該輕摻雜層相同,以構成各該金氧半場效 電晶體。
  12. 一種半導體功率元件,其設置在一半導體基板中,該半導體功率元件包含形成在一重摻雜層上方之一輕摻雜層,並且具有一主動晶胞區和一邊緣終止區;其中,該邊緣終止區含有複數個端接浮動保護環,形成在該輕摻雜層中,以及該半導體基板的表面區域中,藉由一電介質層與該半導體基板絕緣之一導電材料,該電介質層設置在兩個相鄰的各該端接浮動保護環之間的區域上,該些端接浮動保護環的導電類型與該半導體基板的導電類型相反,且其摻雜濃度高於該輕摻雜層;以及複數個串聯的金氧半場效電晶體,係包含一平面閘極區以及設置在兩個該端接浮動保護環之間的在該輕摻雜層頂部摻雜濃度高於輕摻雜層的門檻值調節層,該導電材料作為各該金氧半場效電晶體的該平面閘極,其中各該平面閘極區連接到形成該MOSFET汲極區的端接浮動保護環,並在該端接浮動保護環中形成高摻雜濃度的接觸植入,以改善浮動保護環與平面閘極的電連接。
  13. 如申請專利範圍第12項所述之半導體功率元件,其中該些金氧半場效電晶體是由複數個P-通道金氧半場效電晶體構成的。
  14. 如申請專利範圍第13項所述之半導體功率元件,其中當該些金氧半場效電晶體載入一門檻值電壓時,其中一該金氧半場效電晶體被開啟,該門檻值電壓範圍為0.5伏特至80伏特。
  15. 如申請專利範圍第12項所述之半導體功率元件,其中藉由限制表面電介質厚度的局部變化,或者限制該半導體基板表面的表面摻雜濃度的局部變化,以調節各該金氧半場效電晶體的該門檻值電壓。
  16. 如申請專利範圍第13項所述之半導體功率元件,其中兩個相鄰的該端接浮動保護環之間的距離為1微米至10微米。
  17. 如申請專利範圍第14項所述之半導體功率元件,其中該些端接浮動保護環,在該半導體基板中的深度為0.5微米至8微米。
  18. 如申請專利範圍第12項所述之半導體功率元件,其中該汲極區和該源極區的摻雜濃度為1e15cm-3至1e20cm-3
  19. 如申請專利範圍第12項所述之半導體功率元件,其中更包含:一第一電場板,從最後一端接浮動保護環周圍開始,向著一劃線區延伸;一重摻雜的通道終止區,其導電類型與該輕摻雜層相同。
  20. 如申請專利範圍第19項所述之半導體功率元件,其更包含一第二電場板,形成於該通道終止區周圍,且向該主動晶胞區延伸。
  21. 如申請專利範圍第12項所述之半導體功率元件,其中該重摻雜層的極性與該輕摻雜層相反,以構成一絕緣閘極雙極性電晶體。
  22. 如申請專利範圍第12項所述之半導體功率元件,其中該重摻雜層的極性與該輕摻雜層相同,以構成各該金氧半場效 電晶體。
  23. 一種用於在第一導電類型的半導體基板上製備含一有源區和一終端區之半導體功率元件之製備方法,其包含下列步驟:在該有源區中製備複數個垂直的功率元件;在該終端區中藉由形成複數個第二導電類型的摻雜浮動保護環,製備複數個串聯的橫向金氧半場效電晶體,各該摻雜的浮動保護環都包圍了第二導電類型的重摻雜的擴散區,形成串聯的橫向金氧半場效電晶體的汲極區或源極區,在該串聯的橫向金氧半場效電晶體中一汲極區和一源極區放置在兩個相鄰的設置在各該串聯的橫向金氧半場效電晶體的一閘極的對邊上的浮動保護環中,延伸在兩個相鄰的浮動保護環之間的該閘極置於半導體基板的頂面上,在該半導體基板的頂面並置於兩個相鄰的浮動保護環之間設置第一導電類型的摻雜的擴散區以調節串聯的橫向金氧半場效電晶體的門檻值;串聯的橫向金氧半場效電晶體的閘極連接到汲極,從而串聯的橫向金氧半場效電晶體不被打開並被用作為端接區的門檻值金氧半場效電晶體的鏈條。
  24. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其中在該有源區中製備該些垂直金屬氧化物半導體場效電晶體之步驟中,更包含下列步驟:在該有源區中製備複數個垂直平面金氧半場效電晶體。
  25. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其中在該有源區中製備該些垂直金屬氧化物半導體場 效電晶體之步驟中,更包含下列步驟:在該有源區中製備複數個垂直溝槽金氧半場效電晶體。
  26. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其中在該終端區中製備該些串聯的橫向金氧半場效電晶體之步驟中,更包含下列步驟:在該終端區中,製成複數個串聯的橫向P-通道金氧半場效電晶體,將各摻雜的掩埋浮動環製成P-型摻雜浮動保護環,並將各該橫向P-通道金氧半場效電晶體的閘極連接到作為該串聯的橫向P-通道金氧半場效電晶體的該汲極區的P-摻雜浮動保護環的其中之一。
  27. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其中在該終端區中製備該些串聯的橫向金氧半場效電晶體的步驟中,更包含下列步驟:在該終端區中,將該些串聯的橫向金氧半場效電晶體製成該終端區中串聯的該些橫向平面金氧半場效電晶體。
  28. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其中在該終端區中製備該些串聯的橫向金氧半場效電晶體之步驟中,更包含下列步驟:在該終端區中,將該些串聯的橫向金氧半場效電晶體製成該終端區中該些串聯的橫向溝槽金氧半場效電晶體。
  29. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其中在該終端區中製備該些串聯的橫向金氧半場效電晶體之步驟中,更包含下列步驟: 在該終端區中將該些串聯的橫向金氧半場效電晶體製成該終端區中串聯的該些橫向P-通道平面金氧半場效電晶體,將各摻雜的該浮動環製成P-型摻雜浮動保護環,並將各該P-通道金氧半場效電晶體的閘極製成一平面閘極,將該平面閘極連接到作為串聯橫向P-通道平面金氧半場效電晶體的該汲極區的P-摻雜浮動保護環的其中之一。
  30. 如申請專利範圍第23項所述之半導體功率元件的製備方法,其中在該終端區中製備該些串聯的橫向金氧半場效電晶體之步驟中,更包含下列步驟:在該終端區中將該些串聯的橫向金氧半場效電晶體製成在該終端區中串聯的橫向P-通道溝槽金氧半場效電晶體,將各摻雜的浮動環製成P-型摻雜浮動保護環,並將各P-通道金氧半場效電晶體的閘極製成一溝槽閘極,以及將該溝槽閘極連接到作為串聯橫向P-通道溝槽金氧半場效電晶體的該汲極區的P-摻雜浮動保護環的其中之一。
  31. 如申請專利範圍第23項所述之半導體功率元件之製備方法,其更包含下列步驟:製備含有一第一導電板之一第一電場板,該第一導電板在最外面的摻雜擴散區周圍,並且將該第一電場板連接到被包圍在最外面的摻雜擴散區中的摻雜的該浮動保護環上。
  32. 如申請專利範圍第31項所述之半導體功率元件之製備方法,其中製備含有一第二導電板的一第二電場板,該第二導電板在一劃線區周圍的該通道終止區中最外面的該摻雜 的浮動保護環周圍,並且將該第一電場板連接到最外面的該摻雜的浮動保護環上。
  33. 如申請專利範圍第32項所述之半導體功率元件之製備方法,其中在該第一電場板和該第二電場板之間,製備一絕緣層,使該第一電場板與該第二電場板絕緣。
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