CN105431946A - 具有平面状通道的垂直功率金氧半场效晶体管元胞 - Google Patents

具有平面状通道的垂直功率金氧半场效晶体管元胞 Download PDF

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CN105431946A
CN105431946A CN201480002340.6A CN201480002340A CN105431946A CN 105431946 A CN105431946 A CN 105431946A CN 201480002340 A CN201480002340 A CN 201480002340A CN 105431946 A CN105431946 A CN 105431946A
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layer
transistor
type
grid
conductivity
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CN105431946B (zh
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曾军
穆罕默德·恩·达维希
蒲奎
苏世宗
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Miracle Power Semiconductor Co ltd
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MaxPower Semiconductor Inc
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Abstract

本发明公开了一种具有平面状通道的垂直功率金氧半场效晶体管元胞，包括具有漏极电极的N+硅基板。低掺杂浓度N型漂移层长于该基板上。交替的N型纵列与P型纵列形成于该漂移层上并具有较高的掺杂浓度。然后具有高于该漂移区的掺杂浓度的N型层被形成且被蚀刻成具有侧壁。P井被形成于该N型层，并且N+源极区被形成于该P井中。栅极被形成于该P井的横向通道上，并且靠近该侧壁以作为一垂直场板。源极电极接触该P井与源极区。正栅极电压反型该横向通道并且沿着该侧壁来增加导电性。该源极与该漏极之间的电流横向地流动，然后透过多样的N层来垂直地流动。开启电阻被减少且该击穿电压被增加。

Description

具有平面状通道的垂直功率金氧半场效晶体管元胞
技术领域
本发明关于功率金氧半场效晶体管(metal-oxide-semiconductorfield-effecttransistor,金属氧化物半导体场效应晶体管，于下文中称作为MOSFET)，尤指具有平面状DMOS部与垂直导电部的垂直超级结MOSFET。
本申请案主张的优先权为在2014年2月4日由JunZeng等向美国智慧财产局所提出的申请案，其申请案号为61/935,707，在此并入其全部参考内容。
背景技术
垂直MOSFET作为高电压且高功率的晶体管是受欢迎的，由于能够提供厚的且低掺杂浓度的漂移层，以达到于该关闭状态中的高击穿电压。通常，该MOSFET包括高掺杂的N型基板、厚且低掺杂浓度的N型漂移层、靠合于该漂移层的P型主体层、于该主体层顶部的N型源极以及借由薄的栅极氧化物而自该主体区分开的栅极。其通常提供一垂直凹槽栅极。源极电极被形成于该顶面，并且漏极电极被形成于该底面。当该栅极对于该源极来说足够正时，该N型源极与该N型漂移层之间的P型主体的通道区，反型并创造在源极与漏极之间的垂直导电路径。
于该装置为关闭状态中，当该栅极与该源极为短路或为负时，于该源极与漏极之间的漂移层消耗及大的击穿电压(例如超过600伏特)能被持续。然而，由于厚的漂移层所需要的低掺杂，使得该开启电阻变差。增加该漂移层的掺杂会减少该开启电阻，但是会降低该击穿电压。
形成延伸至该基板的交替P型硅与N型硅的垂直纵列，以取代单一N型漂移层为现有技术，其中这些纵列中的电荷被平衡，且当该MOSFET被关闭时，于高电压的P型纵列与N型纵列完全地消耗。其被称为超级结(superjunction)。于此配置中，该N型纵列的掺杂浓度可高于现有N型漂移层的掺杂浓度。其结果，于相同的击穿电压下开启电阻能被减少。超级结MOSFET能借由多重磊晶生长与植入制程来被形成。形成延伸至该基板的厚且交替的P型纵列与N型纵列需要多次的循环，该循环为磊晶生长该纵列厚度的一部分，然后遮蔽并植入该P型掺杂与该N型掺杂，然后长出更多的纵列厚度并重复该遮蔽与植入制程。植入步骤的数量可能超过20次，取决于该厚度。在每一植入循环之间，由于高的制程温度，这些掺杂会产生不期望的横向扩散。其大幅地增加了胞数组中所需要的胞间距，使得该晶粒变更大。其结果，该MOSFET不理想地被形成，且制程非常耗时。
另外，超级结可借由P型延伸层再填充的N型硅中蚀刻深的凹槽来被形成。这些凹槽必须为深的，使得其为足够长的垂直漂移层，以于高击穿电压中作为一空乏区。形成深的凹槽耗时，因此成本昂贵。
这些功率MOSFET被形成具有大数量的相同的平行胞。这些装置之间的任何变化可能造成于该MOSFET上发生不均匀的电流与温度，会减少其效率与击穿电压。
功率MOSFET所需要的是，不具有上述现有技术的缺点与限制。
发明内容
于一实施例中，MOSFET被形成具有用于横向电流流动的平面状通道区，以及用于垂直电流流动的垂直导电路径。
于一实施例中，P井(主体区)被形成于N型层，其具有形成于该N型层的凹槽且该凹槽深于该P井，以产生该N型层的侧壁。该N型层相较于该MOSFET中的N型漂移层具有更高的掺杂。该MOSEFT包括借由导电材料(例如，掺杂的多晶硅)所形成的遮蔽垂直场板，该导电材料以介电材料(例如，氧化物)填充该凹槽并且自这些侧壁绝缘。P屏蔽层被形成于该凹槽的底部并且靠合于该侧壁的底部。该P屏蔽层亦靠合于P纵列的顶部。N纵列位于该通道区下方且横向地靠合于该P纵列。为了低的开启电阻，这些N纵列与P纵列为相对地高掺杂。该凹槽场板较深于该P井，以提供于该N-层中有效电场的减少。当该MOSFET关闭时，该场板与该P屏蔽有助于横向地消耗该N-层，为了低的开启电阻而允许该N-层为相对地高掺杂。该凹槽场板、该P屏蔽、该N型层、减少厚度的N型漂移层以及相对地高掺杂的N纵列与P纵列的综合效应，提供了增加的击穿电压、较低的开启电阻以及每一晶粒较低的成本。为了更快速的切换，该导电场板电极能够被连接至该栅极电极或是该源极电极，以提供较低的栅极-漏极电容。
每一单元区域的较低的开启电阻，允许于每一晶圆上形成更多的晶粒。
于一较佳实施例中的场板凹槽的深度，其为绝缘材料的厚度，该N型层的掺杂与厚度以及该P屏蔽的掺杂与深度被选择来使得该N层于该击穿电压处完全地被消耗。此外，该P纵列与该N纵列的掺杂、深度与宽度使得该P纵列与该N纵列于该击穿电压处完全地被消耗。
于一实施例中，功率MOSFET包括具有低掺杂浓度的第一N型层(该漂移层)的高掺杂的N型基板，大约30微米厚，并由该基板上磊晶生长。该第一N型层相较于现有漂移层更薄，由于其不需要在该关闭状态中维持整个源极-漏极电压。
该第一N型层被遮蔽并植入掺杂以形成大约4微米厚的交替的P型区与N型区，其被称为纵列。于该N型纵列中的N型掺杂浓度相较于该N型漂移层中的掺杂浓度更高。于一实施例中，对每一类型掺杂仅需要使用一次的植入来形成这些纵列，由于该纵列层相较于现有技术的纵列层更薄。因此，相较于现有技术，其具有更少的横向扩散使得这些纵列更为理想。
于该纵列层上方形成第二N型层(例如8微米厚)，其具有相较于该第一N型层的掺杂浓度更高的掺杂浓度。
其中该第二N型层被形成一P井，且该P井被形成于该表面的N型源极区。该源极区与该第二N型层的顶部之间的p井的顶面，形成沿着该装置的顶面的横向通道。
于这些胞的每一者中，凹槽被蚀刻于在这些P井之间的第二N型层中，并且该凹槽相较于这些P井更深。然后，薄的栅极介电质被形成于顶部的横向通道上方并沿着该凹槽的侧壁。然后，多晶硅栅极被形成于顶部的通道上方并沿着该凹槽的垂直侧壁，以使该多晶硅栅极的深度较深于该P井。自该通道与该侧壁分开栅极的介电层，可具有相同厚度或不同厚度而有不同的优点。该凹槽场板导致了较低的电场与较高的击穿电压，其允许该第二N型层的掺杂增加而使该开启电阻降低。
金属的源极电极接触该P井与这些源极区，并且金属的漏极电极接触该基板的底面。
于另一实施例中，借由单一或是多重高能量植入而形成P屏蔽的相同步骤期间，这些P纵列可被形成。
于一例子中，一负载被耦合于该源极电极与地之间，并且一正电压被施加于该漏极。当该栅极相对于该源极电极被足够地正偏压时，该源极区与该第二N型层之间的顶部的横向信道反型，并且电子沿着该第二N型层中的凹槽的垂直侧壁来累积。此电子的横向与垂直累积于该通道下方形成该源极与该N型纵列之间的低电阻路径。然后，该N型纵列与第一N型层完成了至该漏极电极的垂直导电路径。
由于该通道与该漏极电极之间没有厚的且低掺杂浓度的漂移区，每一单元区域的开启电阻(特别是开启电阻Ron*Area)相较于现有的垂直功率MOSFET的开启电阻会更低。该开启电阻较低的部分原因，是因为使用高掺杂浓度的N纵列与第二N型层(如同该第二N型层的较高的掺杂)，其中该第二N型层的较高掺杂借由该凹槽场板效应、该P屏蔽、及当该栅极被正偏压时沿着该第二N型层的垂直侧壁电子累积而被致能。于一实施例中特定的开启电阻达到4.5欧姆(Ohms)-mm2，其大约为现有功率MOSFET的一半。
由于每一单元区域中如此低的开启电压，该晶粒的尺寸相较于现有晶粒的尺寸可更小，以在每一晶粒具有相同开启电阻的情况下使每一晶圆的晶粒数量加倍。
在该MOSFET的关闭状态，且源极-漏极电压相较于该击穿电压稍微低时，该第一N型层、这些纵列与该第二N型层完全地消耗。该击穿电压可相同于具有相同厚度的现有的垂直MOSFET，但是该开启电阻较小。相反地，该击穿电压可借由形成较厚的层来被增加而高于现有技术的击穿电压，同时该开启电阻可与现有技术相同。此外，由于较薄的纵列层与较浅的凹槽，形成垂直MOSFET的制程复杂度低于现有技术的具有超级结的垂直MOSFET的制程复杂度。
该MOSFET中的PN二极管被偏压开启之后，该MOSFET结构亦可降低该回复时间。若该MOSFET以一交流电压来被使用，当该漏极较该源极更负时，该二极管将会导电。当该极性反转且该二极管被逆向偏压时，在该栅极被偏压至一开启状态之后，被储存的电荷必须在该MOSFET被完全地打开之前被移除。由于在该第二N型层与该N纵列中较高的掺杂程度，此被储存的电荷较快地被移除，以致能较快的切换时间。
于一较佳实施例中，P型屏蔽层被形成于该凹槽下方的P纵列的上方，以靠合该第二N型层的侧壁。此P型屏蔽层有助于横向地消耗该第二N型层以增加该击穿电压。
被说明的栅极配置亦有助于横向地消耗该第二N型层以增加该击穿电压。
使用顶部的横向通道、面向加强的垂直“通道”部分的垂直场板、以及超级结的上述胞的多种变化系被说明。用以形成该垂直MOSFET的创新技术亦被说明。
绝缘栅极双极性晶体管(insulatedgatebipolartransistor,IGBT)可借由使用一P型基板来取代被形成。
附图说明
图1为根据本发明一实施例的相同连续MOSFET胞的一大型数组中的单一垂直MOSFET胞的剖面图。
图2A至图2R为使用来制造图1的MOSFET的各种步骤。
图3为于一关闭状态中，该装置的基板顶面与一P井之间的空乏区的等位线，并示出击穿电压的虚拟最大化。
图4为具有较浅的纵列层或是较浅的凹槽的MOSFET，使得该P屏蔽不会接触底层的P纵列。
图5为具有N纵列薄于P纵列的MOSFET。
图6为该P井延伸至该凹槽侧壁的MOSFET。
图7A与图7B为不具有N纵列与P纵列的MOSFET。
图8A与图8B为具有多个纵列层的MOSFET。
图9为于该N-层的边缘上方具有较薄的氧化物的MOSFET，以减少氧化物击穿的可能性。
图10A为具有更均匀厚度的栅极多晶硅层的MOSFET。
图10B为具有分裂多晶硅层的MOSFET，其中该栅极重叠该N-层。
图10C为具有分裂多晶硅层的MOSFET，其中该栅极重叠该P屏蔽。
图10D为具有分裂多晶硅层的MOSFET，其未具有面向该N-层边缘的多晶硅。
图11A为一MOSFET，其中均匀薄的栅极氧化物重叠于该横向通道、该凹槽侧壁与该P屏蔽。
图11B与图11C为具有较薄的氧化物于该P屏蔽上方的MOSFET。
图11D为具有相邻该凹槽的可变厚度氧化物的MOSFET。
图12A与图12B为具有在该P井下方的P纵列的MOSFET。
图13A与图13B为具有分裂多晶硅层的MOSFET。
图14A至图14C为具有围绕该P纵列而共形的N层的MOSFET。
图15A至图15E为借由使用P+型基板以转换成IGBT的变化MOSFET实施例。
图16为使用所述的MOSFET胞或是IGBT胞中的任一者的胞数组的类型的俯视图，其中这些胞以带形来被配置。
图17为使用所述的MOSFET胞或是IGBT胞中的任一者的胞数组的另一类型的俯视图，其中这些胞以带形来被配置。
具体实施方式
图1为根据本发明一实施例的相同连续MOSFET胞的大型数组中的单一垂直MOSFET胞10的剖面图。所示的胞的宽度大约为8-11微米。该MOSFET胞10可具有超过600伏特的击穿电压，并且相同胞的数组中的胞10的数量决定该电流处理能力，例如20安培。该胞数组可为带形、四边形、六边形或是其他现有形状。
于正常操作期间，一正电压被施加至底部的漏极电极12与一负载，该负载连接于地与顶部的源极电极14之间。当一正电压被施加至该导电栅极16并大于该临界电压时，该P井18的顶面被反型，并且电子沿着该N-层20的垂直侧壁来累积。该栅极沿着该P井18下方的侧壁来延伸，并且创造一场板至该N-层20中较低的电场。该N++源极区22、该P井18与该N-层20顶面形成该MOSFET10的横向DMOS晶体管部。因此，在该开启状态中，透过该N++源极区22、该P井18的被反型的通道、该N-层20的侧壁、该通道下的N纵列24、该N--层26(该漂移层)与该N++基板28，在该源极电极14与该漏极电极12之间具有一导电N型通道。
该横向DMOS晶体管部的组合，该N-层20的较高的掺杂(允许以该凹槽场板效应与该垂直栅极部来沿着该N-层20的侧壁累积电子)、交替且高度地掺杂的N型纵列24与P型纵列30、以及该N--层26，与现有技术相较能减少该开启电阻，其将于下文中说明。若这些MOSET内部PN二极管变为正向偏压时，该结构相较于现有技术亦增加该击穿电压并加速该切换时间，其将于下文中说明。
于该剖面图中，该P井18的深度被夸大以方便说明，并且该多晶硅栅极16沿着该N-层20的侧壁延伸至该P井18下方。例如，沿着该N-层20的侧壁(以及沿着该侧壁的任一虚拟场板)的多晶硅栅极16可延伸于该P井18下方1-4微米。由于图3为模拟，故图3的栅极16的尺寸相对于该P井18会相对更为准确。
图2A至图2R为使用来制造图1的MOSFET10的各种步骤。
图2A示出，当生长期间被掺杂原位(in-situ)，该N--层26为磊晶生长于一N++硅基板28上，或是该N--层26被周期性地以大约1.5E12cm2的剂量植入N型掺杂。该基板28可具有大约5E19cm3的掺杂浓度。为使装置具有大约600V的击穿电压，该N--层26的最终掺杂密度大约为3.5E14cm3。该N--层26可为30微米厚。
图2B示出薄的热氧化物长于该N--层26上，接着覆盖式(blanket)的磷35植入并形成N纵列层36。该植入剂量可大约为1-2E12cm2。
图2C示出形成于该N纵列24的预定位置上方的被图案化的光阻剂层38。接着硼40以大约1E13cm2的计量来覆盖式植入以形成P纵列30。
于图2D中，该光阻剂与氧化物被分裂，并且一N-层20被磊晶生长以具有大约2.3E15cm3的掺杂密度，其高于该N--层26的掺杂密度。该N-层20大约为8微米厚。于另一实施例中，该N-层20的掺杂密度相同于该N--层26。
于图2E中，热氧化物层42被长于该N-层20上方。该N纵列24与该P纵列30的掺杂物被驱动并且散开，以形成大约4-5微米厚的纵列层，具有于该N纵列24的N型掺杂浓度约为2E15cm3，以及具有于该P纵列30的P型掺杂浓度约为1E16cm3。该N纵列24的掺杂密度可高于或是低于该N-层20的掺杂密度。
于图2F中，一多晶硅层被形成为大约1000埃厚，接着一氮化物层46大约2000埃厚，接着一氧化物层48大约10,000埃厚。
于图2G中，光阻剂50的一层被图案化，并且蚀刻掉这些层42,44,46的被暴露部分。
于图2H中，该光阻剂被剥离并且于该被暴露的硅上执行干性蚀刻，以于该N-层20中形成凹槽52。于该凹槽52下方，凹槽蚀刻留下大约3-4微米的N-层20。接着，硼54被植入大约4E12cm2的剂量至该凹槽52，以形成P屏蔽56。
于图2I中，厚的氧化物层借由干性蚀刻而被剥离，并且大约1000埃厚的一热牺牲氧化物层58被生长于该P屏蔽56上方与该N-层20的侧壁上方。
于图2J中，该热牺牲氧化物层被剥离，并且使用LOCOS制程以形成大约6000埃厚的一氧化物层60于该P屏蔽56上方与该N-层20的侧壁上方。
于图2K中，这些层42,44,46被剥离。
于图2L中，具有大约900埃的厚度的薄的栅极氧化物层，生长于该N-层20上方。然后，导电的多晶硅层64被沉积并图案化。
于图2M中，光阻剂层66被图案化并且暴露该多晶硅层64的中央部分，接着借由干性蚀刻以形成该栅极16。
于图2N中，该光阻剂层被剥离，并且硼68被植入至该N-层20，并且被嵌入以形成与该栅极16一起自我校准(self-aligned)的P井18，该P井18系具有大约2-3微米的深度。
于图2O中，砷或磷70被植入大约5E15cm2的剂量并且被嵌入以形成大约0.2-0.5微米深的N++源极区22，并与该栅极16一起自我校准。
于图2P中，该绝缘层72被沉积于一衬氧化物层所组成的栅极16上方与周围，其具有大约800埃的厚度，接着是BPSG层，其具有大约10000埃的厚度。然后，该绝缘层72的中央部以光阻剂来被遮蔽，并且被蚀刻以曝露该N++源极区22。然后，该光阻剂被剥离。
于图2Q中，透过该N++源极区22的被曝露部被蚀刻，以曝露该P井18。然后，硼74以大约2E15cm2的剂量被植入，并且被嵌入以于该P井18中形成P+接触区76。该P+接触区76的横向宽度大约1微米。若该P井18延伸至该晶粒的边缘，该P+接触区76仅需要被设置于该晶粒的边缘。
于图2R中，该结构被金属化(例如使用溅镀)，以形成顶部的源极电极14，与该P+接触区76及该N++源极区22的侧面相接触来与这些区一起电性地短路。该源极电极14可借由溅镀AlCu或是AlSiCu而被形成，并且可大约为4微米厚。底部的漏极电极12借由溅镀钛、镍与银的层来形成，其中该钛层约1000埃的厚度、该镍层约2000埃的厚度及该银层约10,000埃的厚度。然后，该结构以一保护层来被保护，并且该保护层被图案化/被蚀刻而暴露这些电极，用以与封装的引线相接触。例如，打线可接合该源极电极14至该封装的引线，并且该漏极电极12可直接地接合至该封装的散热片电极。
图3为于一关闭状态且电压略小于击穿电压中，该装置的基板28顶面与P井18之间空乏区的等位线，示出该电压基本上是均匀分布。此均匀的电压分布最大化该击穿电压。值得注意的是，于该关闭状态中的最大可允许电压，该P井18下方与该基板28上方的全部区域将被消耗。
该P屏蔽56增加该击穿电压，借由有效地增加该P纵列30的垂直尺寸而不必生长额外的磊晶层。当该栅极接地或是为负时，除了相邻该N-层20侧壁的栅极16的垂直场板之外的P屏蔽56，有助于横向地消耗该N-层20以达成图3中所示的电压的均匀分布。该横向消耗允许较高的N-层20的掺杂，用以减少开启电阻。
请再参照图1，该N--层26薄于现有的漂移层，由于其不需要整个延伸至该通道区。形成相邻P纵列30与N纵列24产生一超级结，其中这些纵列完全地消耗并且于该P区域及该N区域中的电荷平衡。于该开启状态(栅极正偏压)，该电流自该源极电极14流动，通过该源极区22，通过该横向通道，然后垂直地通过该N-层20(包括沿着电子聚集层的侧壁来通过)，然后垂直地通过底层的N纵列24、N--层26与基板28，以到达该漏极电极12。
由于该N纵列24具有相当高的掺杂浓度并高于该N--层26，其减少了开启电阻使导电性更优于该N--层26。此外，由于靠近被正偏压的栅极16，该N-层20被相当重的掺杂并且具有沿着其侧壁的增强的电子群，使得该横向通道与该N纵列24之间的垂直路径非常导电。特定的开启电阻(Ron*Area)是如此低，使该胞数组的所有开启电阻小于1Ohm。于一实施例中，特定的开启电阻达到4.5Ohms-mm2，其大约为现有功率MOSFET的一半。将产生较小的晶粒并且使每个晶圆的产量加倍。
由于是借由一凹槽栅极而非垂直通道，图1的该凹槽能够非常浅(例如4-10微米)，使其更容易被形成。由于不用形成深的凹槽所以该制程相当简单，因此图1的MOSFET10能使用标准制程设备来形成，并可降低每个晶圆的成本。
除了该MOSFET10具有被增加的击穿电压与较低的开启电阻之外，在该MOSFETPN二极管被偏压开启之后，该MOSFET10具有较快的回复时间。接着该源极/漏极电压反型后，在该PN二极管已被偏压开启之后于栅极控制切换中的延迟，由于当该二极管被逆向偏压时而被储存的电荷。被储存的电荷必须被移除，以使该二极管关闭并且该MOSFET开启。于该MOSFET10中的电荷的移除不但能借由非常高掺杂的N纵列24与N-层20来加速，该N-层20的侧壁上的正栅极效应亦能抽出(drawing)该侧壁的电子。
图1的基本的MOSFET10具有许多变化并保有较低的开启电阻与较高的击穿电压的优点。图4-15E示出一些变化态样。
图4为具有较浅的纵列层的MOSFET，因此该P屏蔽56不会与底层的P纵列30相接触。该P屏蔽56还具有该横向地消耗该N-层20的效应，使得该N-层20可相对地具有高掺杂以减少开启电阻。
图5为具有N纵列80深于P纵列82的MOSFET。由于该N纵列80相较于该N--层26具有更高的掺杂，因此可用于扩散电流以并免热点，更可减少开启电阻。
图6为该P井84延伸至该凹槽侧壁的MOSFET。当该栅极16被正偏压以开启该MOSFET时，重叠的栅极16与栅极16的侧壁部反型该P井84的顶面与侧面。由于薄的栅极氧化物仅重叠于该P井84，此结构减少了具有高漏极-栅极电压的顶部薄栅极氧化物击穿的可能性，并且该P井84处于该源极电压。
图7A与图7B为不具有N纵列与P纵列的MOSFET。于这些实施例中，图1的超级结的优点无法被使用，所以该N--层26较薄。因此，开启电阻无法像图1的MOSFET这么好。然而，与该N-层20相结合的栅极结构相较于现有技术依旧可减少开启电阻。
图8A与图8B为具有多个纵列层86及88的MOSFET。其允许使用较薄的纵列层以达到于这些纵列中更为均匀的掺杂浓度。具有一厚的纵列层，被植入的掺杂需要以更长的时间来被嵌入，横向地扩散这些掺杂亦相同。借由使用多个较薄的纵列层，减少所需的嵌入时间，使得这些掺杂不再需要这么长时间的横向地扩散。其允许较小的胞间距与较小的晶粒尺寸。假设足够高的源极-漏极电压，当该MOSFET关闭时这些纵列层消耗，并由于该超级结的消耗特性，使得该P纵列与该N纵列允许在这些纵列中的掺杂浓度相当高。
图9为于该N-层20的较上方边缘处具有较薄的凹槽氧化物90的MOSFET。由于其电场通常聚集于低半径角落处，较厚的氧化物有助于防止该N-层20与该栅极16之间的氧化层的击穿。不同的氧化物厚度借由遮蔽蚀刻所完成。
图10A为相较于图1的栅极多晶硅层，具有更均匀厚度的栅极多晶硅层92的MOSFET。由于较薄的多晶硅层，其可减少制程时间。
图10B为具有分裂的多晶硅层94与96的MOSFET，其中该间隙重叠该N-层20。该P井18上方的栅极部反型该通道。该多晶硅层96可被连接至该源极或是被浮空，以作为用以扩散该电场分布的场板，来达到更为均匀的电场剖面。当该MOSFET为开启时，该多晶硅层96本质上处于较低于该栅极的电压。这使得该多晶硅层96与该N-层20之间具有较小的电压差。由于该栅极部仅反型该通道，该N-层20中具有较小的导电性调整。该栅极至漏极电容(密勒电容)被显著的减少，减少了切换损耗。因此，与栅极电压相较，该MOSFET的导电性比图1的MOSFET更稍微的线性，开启电阻有稍微的增加，并且切换功率损耗被减少。
图10C为具有分裂的多晶硅层98与100的MOSFET，其中该间隙重叠于该P屏蔽56。于该P井18及该N-层20的侧壁上方的栅极反型该通道，并且沿着该N-层20的侧壁累积电子以用于较低的开启电阻。该多晶硅层100被连接至该源极或是被浮空。
图10D为具有分裂的多晶硅层102与104的MOSFET，其中未具有面向该N-层20的边缘的多晶硅。由于场聚集于该边缘，因此减少了该N-层20的边缘与该多晶硅之间的氧化物击穿的可能性。
图11A为一MOSFET，其中均匀薄的栅极氧化物106重叠该横向通道、该凹槽侧壁以及该P屏蔽56。因此，以减少开启电阻来说，本实施例的栅极16的效应最为明显；然而，栅极氧化物击穿的可能性增加。
图11B与图11C为具有较薄的氧化物108于该P屏蔽56上的MOSFET，以减少该P屏蔽56上的氧化物击穿的可能性。
图11D为相邻该凹槽的具有可变厚度的氧化物110的MOSFET，由于场聚集而减少氧化物击穿的可能性。
在上述的实施例中，宽的N纵列被垂直地设置于该P井18下方。图12A与图12B示出具有于该P井18下方的窄的P纵列112与相邻于中央的P纵列112的窄的N纵列114的MOSFET。当该MOSFET被关闭时，较窄的纵列改善了这些纵列的横向消耗，因此这些纵列能够为更高的掺杂以减少开启电阻。由于该电流路径主要是沿着该N-层20的边缘(且N纵列114于这些边缘下方)，该P井18中间下方的窄的P纵列112的位置不会对开启电阻有不好的影响。
图12B，中央的P纵列116延伸至该P井18。在该关闭状态时，其有助于横向地消耗该N-层20，允许该N-层20有更高的掺杂以改善开启电阻。
图13A与图13B示出相似于图10BMOSFET(具有分裂的多晶硅层)的MOSFET，但其中，中间的P纵列118延伸至该P井18与导电多晶硅部120，该导电多晶硅部120连接至该源极电极14，突出至该P纵列118并自该P纵列118绝缘。于该关闭状态，其有助于消耗该P纵列118。
图14A至图14C为具有围绕该P纵列118而共形的N层124的MOSFET，并且该P纵列118延伸至该P井18。该N层24具有一掺杂浓度大约等于该P纵列118的掺杂浓度。当该PN二极管被正向偏压时，该N层124减少载子注入至该P纵列118，以当该源极与漏极电压改变极性时致能更快的回复。在极性已被反转之后，其致能较快速的切换时间。该N层124亦减少电流扩散电阻为较低的开启电阻。
图14B与图14C加入了于该P井18周围的另一N-层126，其相较于该N-层20具有更高的掺杂以减少开启电阻。该N-层126有助于沿着该P井18的整个宽度来扩散电流，并且该N-层124沿着该N纵列24以垂直地传导该电流至该N--层26。
图15A至图15E示出借由P+型基板130来转换为IGBT的多种MOSFET的实施例。薄的N型缓冲层132被加入。该缓冲层132被用于控制自该P+基板130的电洞植入与该IGBT的击穿特性。此时该漏极电极为PNP晶体管的集极电极134，并且此时该源极电极为NPN晶体管的射极电极。因此，垂直的NPN晶体管与PNP晶体管被形成，并且当该栅极偏压为低时会阻止电流。当有足够地正栅极偏压时，初始电流在该源极与该漏极之间流动，其植入足够的电流以正向偏压该NPN与该PNP晶体管以创造该IGBT动作。这使得开启电阻相较于垂直MOSFET较低。然而，该最大切换频率被降低。IGBT的一般操作为现有技术。
图15B为具有不同掺杂的N型区136与138的N类型缓冲器。这些区136与138的掺杂浓度分别大约为1E17cm3与2E17cm3。较高的掺杂浓度减少自该集极至该射极的击穿电压，但是增加该装置关闭切换速度。此外，区136与138的不同掺杂程度可改善该击穿电压与该装置的正向电压之间的权衡。
图15C为该集极电极134，其直接地连接至该基板的P+区140与该基板的N+区142。当该集极电极134对于该源极(射极)电极来说足够负时，这些区142允许该IGBT为PN二极管。其集成了自由电力隔通二极管至IGBT中，在这些电压改变极性时，这对某些应用是有用的。
图15D加上了N缓冲器层144于该P+区140上方，以调整自该P+区140(集极)的电洞植入效率。
图15E组合许多前述特点至单一IGBT。
图16为使用于上述的MOSFET胞或是IGBT胞的任一者的胞数组的类型的俯视图，其中这些胞被配置为带形。在此仅示出该栅极16、源极区22与P+接触区76。该P+接触区76可仅在这些带形的每一者的一端。
图17为使用于上述的MOSFET胞或是IGBT胞的任一者的胞数组的另一类型的俯视图，其中这些胞被配置为四边形。在此仅示出该栅极16、源极区22与P+接触区76。六边形状或是其他形状亦可被使用。
上述的任一特点可被组合于MOSFET或是IGBT的任一组合中，以于一特定应用中达到特点中的特定优点。
虽然已示出与说明本发明的特定实施例，其使本领域技术人员可在不脱离本发明的广泛的范畴来改变与修改，因此对权利要求书的任何改变与修改，皆落入本发明真实的精神与范围中。

Claims (22)

1.一种具有平面状通道的垂直功率金氧半场效晶体管元胞，其特征在于，包括：
半导体基板，具有在其底面的第一电极；
第一层，为第一导电性类型且位于该基板上方，该第一层具有第一掺杂浓度；
第二层，为该第一导电性类型且位于该第一层上方，该第二层具有高于该第一掺杂浓度的第二掺杂浓度，该第二层具有一顶面；
凹槽，曝露该第二层的垂直侧壁；
井区，为第二导电性类型且位于该第二层的顶面，该井区具有一顶面；
第一区，为该第一导电性类型且位于该井区的顶面，其中该第一区与该井区的一边缘之间的区域包括用于借由一栅极来反型的通道；
导电栅极，重叠于该通道，当该栅极被偏压高于一临界电压时，该导电栅极于该第一区与该第二层之间创造一横向导电路径；
垂直场板，面向该第二层的垂直侧壁并且自该垂直侧壁绝缘，该垂直场板深于该井区；以及
第二电极，其电性地接触该井区与该第一区，其中当一电压被施加在该第一电极与该第二电极之间以及该栅极被偏压高于该临界电压时，一横向电流穿过该通道来流动，并且一实质垂直电流流动于该通道与该基板之间。
2.如权利要求1所述的晶体管元胞，其特征在于，还包括：
第三层，为该第一导电性类型且位于该第一层与该第二层之间，并设置于该通道下方；以及
第四层，为该第二导电性类型且于该第三层的相对侧来横向地靠合该第三层，该第三层与第四层中的掺杂浓度高于该第一掺杂浓度。
3.如权利要求2所述的晶体管元胞，其特征在于，还包括第五层，为第二导电性类型且位于该凹槽下方并横向地相邻于该第二层。
4.如权利要求3所述的晶体管元胞，其特征在于，该第五层靠合于该第四层。
5.如权利要求3所述的晶体管元胞，其特征在于，该第一层垂直地自该第四层分开。
6.如权利要求3所述的晶体管元胞，其特征在于，该栅极具有第一部分、第二部分与第三部分，该第一部分与该通道重叠，该第二部分面向该第二层的垂直侧壁以作为该垂直场板，该三部分与该第五层重叠，其中该栅极与该通道之间、与该垂直侧壁之间，以及与该第五层之间的介电层的厚度相等。
7.如权利要求3所述的晶体管元胞，其特征在于，该栅极具有第一部分、第二部分与第三部分，该第一部分与该通道重叠，该第二部分面向该第二层的垂直侧壁以作为该垂直场板，该三部分与该第五层重叠，其中该栅极与该通道之间的介电层的厚度小于该栅极与该第五层之间的介电层的厚度。
8.如权利要求3所述的晶体管元胞，其特征在于，该栅极具有第一部分、第二部分与第三部分，该第一部分与该通道重叠，该第二部分面向该第二层的垂直侧壁以作为该垂直场板，该三部分与该第五层重叠，其中该栅极与该垂直侧壁间之间具有介电层的多种厚度。
9.如权利要求1所述的晶体管元胞，其特征在于，该第四层包括于该井区下方的第一部分，该第一部分以该第三层来被靠合于相对横向侧。
10.如权利要求9所述的晶体管元胞，其特征在于，该第一部分延伸至该井区。
11.如权利要求10所述的晶体管元胞，其特征在于，第五层为该第一导电性类型，被形成以靠合该第四层的横向侧并且靠合该第四层的底面。
12.如权利要求2所述的晶体管元胞，其特征在于，还包括第五层，为该第一导电性类型且位于该井区与该第二层之间，该第五层具有高于该第二层的掺杂浓度的掺杂浓度。
13.如权利要求2所述的晶体管元胞，其特征在于，还包括：
第五层，为该第一导电性类型且位于该第三层下方；以及
第六层，为该第二导电性类型且于该第五层的相对侧来横向地靠合该第五层，该第六层位于该第四层下方，该第五层与该第六层的掺杂浓度高于该第一掺杂浓度。
14.如权利要求2所述的晶体管元胞，其特征在于，该基板为该第一导电性类型，并且该晶体管为金氧半场效晶体管。
15.如权利要求2所述的晶体管元胞，其特征在于，该基板为该第二导电性类型，并且该晶体管为绝缘栅极双极性晶体管。
16.如权利要求1所述的晶体管元胞，其特征在于，该栅极亦沿着该第二层的垂直侧壁设置以作为该垂直场板，以使当该栅极被偏压高于该临界电压时来调整该垂直侧壁的导电性。
17.如权利要求16所述的晶体管元胞，其特征在于，第一介电层设置于该栅极与该井区的顶面之间，其中第二介电层设置于该栅极与该侧壁之间，以及其中该第一介电层的厚度相同于该第二介电层的厚度。
18.如权利要求16所述的晶体管元胞，其特征在于，第一介电层设置于该栅极与该井区的顶面之间，其中第二介电层设置于该栅极与该侧壁之间，以及其中该第一介电层的厚度小于该第二介电层的厚度。
19.如权利要求1所述的晶体管元胞，其特征在于，该垂直场板为浮空。
20.如权利要求19所述的晶体管元胞，其特征在于，该垂直场板被连接至该第二电极。
21.如权利要求1所述的晶体管元胞，其特征在于，还包括第三层，为该第二导电性类型且位于该凹槽下方并横向地相邻于该第二层，其中该垂直场板与该第二层的第二掺杂浓度配置来增加该第二层的横向耗尽，使得该第二层于该晶体管的击穿电压完全地消耗。
22.如权利要求1所述的晶体管元胞，其特征在于，还包括：
第三层，为该第一导电性类型且位于该第一层与该第二层之间，并设置于该通道下方；以及
第四层，为该第二导电性类型且于该第三层的相对侧来横向地靠合该第三层，该第三层与第四层中的掺杂浓度高于该第一掺杂浓度，
其中该第三层与该第四层形成N型纵列与P型纵列，其中该N型纵列与该P型纵列于该晶体管的击穿电压完全地消耗。
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CN115207130A (zh) * 2022-09-09 2022-10-18 深圳芯能半导体技术有限公司 一种侧壁栅双沟槽碳化硅mosfet及其制备方法

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