US5314834A - Field effect transistor having a gate dielectric with variable thickness - Google Patents

Field effect transistor having a gate dielectric with variable thickness Download PDF

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US5314834A
US5314834A US07/750,155 US75015591A US5314834A US 5314834 A US5314834 A US 5314834A US 75015591 A US75015591 A US 75015591A US 5314834 A US5314834 A US 5314834A
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dielectric
forming
thickness
gate
control electrode
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Carlos A. Mazure
Marius K. Orlowski
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Motorola Solutions Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/981Utilizing varying dielectric thickness

Abstract

A field effect transistor, FET, (11) having a gate dielectric of varying thickness (14, 24) to improve device performance. The FET (11) is made on a substrate (10) and has a control electrode, or gate (16), and two current electrodes, or source and drain regions (28), which are separated by a channel region. The gate (16) is separated from the channel region by a gate dielectric. The gate dielectric has a centrally located first region that is of a first thickness (14) and a second region which is adjacent a perimeter of the first region that is of a second thickness (24). The second thickness (24) is made greater than the first thickness (14).

Description

FIELD OF THE INVENTION

The present invention relates generally to semiconductor transistors, and more particularly, to field effect transistors (FETs).

BACKGROUND OF THE INVENTION

When NMOS, PMOS and CMOS technologies were first put into production in the semiconductor industry most metal oxide semiconductor field effect transistors (MOSFETs) were fabricated with relatively thick gate oxides. For most applications gate oxides or gate dielectrics are used to isolate a conductive gate region from a substrate region which is usually called a channel. The thicker gate oxides gave the advantages of: (1) almost no leakage current resulting from valence band to conduction band transitions; (2) less MOSFET degradation with time, i.e. improved lifetime by reducing a well-known gate damaging hot electron injection phenomena; and (3) less Miller Capacitance, i.e. less gate-to-source and gate-to-drain capacitance which helps to improve on-to-off and off-to-on switching speed. However, the thicker gate oxides resulted in low gain or low current capability and short channel effects such as Drain Induced Barrier Lowering (DIBL) which adversely affect MOSFET turn on voltages or threshold voltages. DIBL is a phenomena that drastically reduces threshold voltages as the channel region length is reduced or, in other words, as the channel becomes a short channel.

To improve the performance and density of the MOSFET, the semiconductor industry began to shrink the geometry of this device not only in terms of surface area but also in terms of dielectric thickness which primarily involved the gate dielectric. As the gate dielectric was reduced in thickness, MOSFETs gained the advantage of higher source-to-drain currents which improved gain and resulted in a reduction of unwanted short channel behavior. The thinner gate dielectric also produced undesirable results, such as: (1) a higher gate current leakage from source-to-gate, from drain-to-gate and from channel-to-gate due to hot carrier effects; (2) valence band to conduction band current leakage in the source and drain; (3) strong degradation of the gate and therefore a shorter lifetime; and (4) larger Miller Capacitance which slowed the device. As the MOSFET size continued to shrink towards submicron sizes, it was realized that a new technology would have to be developed to keep current leakage and capacitance from becoming too extreme and performance limiting. This new technology had to be capable of further size reduction due to the fact that all the MOSFETs used up to this point in time were no longer electrically or mechanically capable of further reduction.

To correct some of the problems resulting from thin gate oxides and to allow further device size reduction in MOSFETs, Lightly Doped Drain (LDD) transistor structures were researched. LDD transistors helped reduce hot carrier effects and improve MOSFET lifetime as is taught in U.S. Pat. No. 4,951,100, issued Aug. 21, 1990, by Louis C. Parillo, entitled, "Hot Electron Collector for a LDD Transistor" and assigned to the assignee hereof. Although LDD transistor structures improved lifetime by reducing hot carrier effects, the structures, in general, did little to improve upon Miller Capacitance switching speed problems, short channel effects, and other typical thin dielectric MOSFET shortcomings. Not being able to shrink the presently existing LDD structures below critical dimensions of roughly 0.5 micron (μ) without introducing heavy current leakage and DIBL also hindered further progress.

A transistor structure referred to as an "Inverse T LDD" structure was also proposed. Although this transistor structure and other variations of this type of structure made some improvements over most thin gate MOSFET structures and LDD transistor structures, a noted disadvantage of Inverse T LDD MOSFETs is large pitch and therefore poor circuit density. In addition, the Inverse T LDD transistor structure still does not greatly improve upon valence band to conduction band transition leakage current or Miller Capacitance.

SUMMARY OF THE INVENTION

The previously mentioned needs are fulfilled and other advantages achieved with the present invention, in which a field effect transistor (FET) and method of formation is provided. The field effect transistor has a gate oxide of variable thickness. In one form, the FET has a substrate material of a first conductivity type. First and second current electrode regions of a second conductivity type are formed in the substrate material and separated by a channel region. A control electrode is formed overlying the channel region and between the first and second current electrode regions. A control electrode dielectric is formed overlying the channel region between the channel region and the control electrode. The control electrode dielectric has a first predetermined thickness in a first region which is centrally located beneath the control electrode and a second predetermined thickness in a second region which is adjacent a perimeter of the control electrode. The second predetermined thickness of the control electrode dielectric is made greater than the first predetermined thickness for: (1) minimizing hot carrier injection of the channel region and first and second current electrodes; (2) minimizing capacitance between the control electrode and the first and second current electrodes; and (3) reducing leakage current between the first and second current electrodes.

The present invention will be understood by one skilled in the art from the detailed description below in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1H illustrate, in cross-sectional form, a semiconductor device fabrication process for forming a FET in accordance with the present invention;

FIG. 2 illustrates, in cross-sectional form, an alternative FET structure subsequent to FIG. 1D in accordance with the present invention;

FIG. 3 illustrates, in cross-sectional form, an alternative FET structure subsequent to FIG. 1D in accordance with the present invention; and

FIG. 4 illustrates, in cross-sectional form, an alternative FET structure subsequent to FIG. 1D in accordance with the present invention.

DESCRIPTION OF A PREFERRED EMBODIMENT

As stated previously, the need exists for a device that can gain all the advantages of a thin dielectric gate MOSFET, such as large source-to-drain current for high gain and good short channel behavior, while still preserving the thick dielectric gate advantages, such as: (1) low current leakage both in terms of valence band to conduction band leakage current and hot carrier injection phenomena; (2) less gate degradation for improved lifetime; (3) improved short channel behavior; and (4) smaller capacitance for greater switching speeds. The device also needs to be capable of dimension shrinking into the submicron dimensions required for development of future technology.

Illustrated in FIGS. 1A-1H are cross-sectional diagrams which sequentially depict a process for forming an FET in accordance with the present invention. FIGS. 1A-1H illustrate the development of a device 11 having all the needs previously mentioned. Device 11 has a substrate 10 which can be silicon, either of P-type or N-type conductivity, or any other semiconducting starting material and a dielectric layer 12 usually referred to as a field oxide. The dielectric layer 12 is usually grown or deposited on the substrate 10 and removed in selected areas to form open areas or active areas where FETs can be placed. Device 11 also has a relatively thin dielectric layer in the active area which can in most cases be thermally grown or deposited and is usually referred to as a gate oxide or gate dielectric 14. A conductive layer, referred to as a gate 16, overlies the gate dielectric 14. The gate 16 is usually formed of either a material containing metal, a metal, polysilicon, or some other conducting material. Overlying the gate 16 is a dielectric layer 18 which is, in most cases, a deposited oxide. Overlying the dielectric layer 18 is another dielectric layer 20 which is usually a nonoxidizing dielectric substance such as nitride. The dielectric layers 18 and 20 are used to protect the gate 16 from impurities, mechanical and electrical damage, and other potential harm.

FIG. 1B depicts the formation of a dielectric cap 20' around all exposed faces of the gate by including dielectric layer 20. While the dielectric layers 18 and 20 are used for gate protection from damage and impurities, dielectric cap 20' is used to protect the gate not only vertically but laterally as well. The dielectric cap 20' completely encompasses the gate 16 and dielectric layer 18 and terminates on the gate dielectric 14.

FIG. 1C illustrates the next step in the process which is to form a thicker gate dielectric 24 overlying the gate dielectric 14. All surface areas of gate dielectric 14 that are not covered by the gate 16 or the dielectric cap 20' are covered by the gate dielectric 24 although the gate dielectric 24 could be further confined. The thicker gate dielectric 24 encroaches slightly under dielectric cap 20' forming a two-level stair stepping or sloping dielectric region formed by the gate dielectric 24 and gate dielectric 14. The dielectric cap 20' has now performed its function of protection and is etched off of the gate by using any of several etch techniques.

FIG. 1D shows a cross sectional diagram of a lateral gate extension step. The gate 16 is extended laterally by a gate extension 26. The gate extension 26 is generally made of either: (1) a metal containing substance; (2) a metal; (3) polysilicon; or (4) some other conducting material, and can be formed using one or many of several lateral layer forming techniques such as spacer technology, Chemical Vapor Deposition (CVD) steps, or growth techniques. The gate extension 26 will form over the thicker gate dielectric 24 to some predetermined amount.

FIG. 1E depicts one step in the formation of current electrodes otherwise known as a source and a drain. The source and drain electrodes of device 11 can be formed in many ways. One conventional way of forming source and drains, as depicted in FIG. 1E, is to ion implant impurities of the opposite conductivity type of substrate 10, either N-type or P-type, into the substrate 10. Ion implanting is a method of depositing impurities into a layer or substrate by accelerating the impurities in a direct path. The accelerated impurities form a thin current stream of high velocity impurities that deposit themselves into layers or a substrate by impact. An anneal phase, which usually involves heating the device, follows the implant and further forms the source and drain by repairing any damage that ion impacting may have caused and thermally spreading out the impurities. Another common method to form a source and a drain is to use diffusion technology. Diffusion technology is similar to implant technology but does not involve high velocity impact and is typically implemented at higher temperatures than implanting.

Once the impurities have been established in the substrate from the techniques discussed previously, FIG. 1F illustrates the location of the source and drain regions 28. The source and drain regions 28 extend vertically from the gate dielectric 24 into the substrate 10 by a controllable distance. Laterally, the source and drain regions 28 are confined to an area under the gate dielectric 24 and adjacent to the dielectric layer 12. The source and drain regions 28 are kept from forming near or under the gate dielectric 14. The region in substrate 10 between the source and drain regions 28 is known as the channel. This channel can also, at several points in the FIG. 1A-1H flow, be implanted or altered in many ways to improve the performance of the device.

FIG. 1G illustrates a second gate dielectric formation referred to as a dielectric layer 30. Dielectric layer 30 completely covers all faces of the exposed gate 16 and dielectric layer 18. The dielectric layer 30 comes in contact with the thick gate dielectric 24. Dielectric layer 30 is provided for electrical isolation and protection of gate 16. The addition of other dielectric layers, such as dielectric layer 30, may or may not add to the thickness of other layers across device 11, such as dielectric layer 12 and gate dielectric 24, depending upon the formation technique used.

After the dielectric layer 30 is formed over the gate 16, another oxide is formed over dielectric layer 30 using one or more of several techniques such as CVD, spacer technology or growth technology. A new dielectric extension region 32 is illustrated in FIG. 1H and adds thickness to the dielectric layer 30 in a uniform or non-uniform manner depending on the application. For most applications the dielectric will cover all of dielectric layer 30 and will be more slender at the top of the gate 16 while being formed wider closer to the gate dielectric 24 or closer to the bottom of the gate 16.

While the present invention has been depicted and described with reference to a specific embodiment, further modifications and improvements will occur to those skilled in the art. For example, FIG. 2 illustrates an alternative structure that can result from a process similar to the process discussed in FIGS. 1A-1H. FIG. 2 illustrates a device 13 which is device 11 fabricated slightly different to illustrate how lightly doped drain (LDD) technology could be added in accordance with the present invention. The conductive gate extension 26 illustrated in FIG. 1D could either be fabricated as spacers or used as spacers for the LDD formation of the LDD current electrodes 29. The regions occupied by the LDD current electrodes 29 are usually referred to as the LDD source and drain regions and are formed using the same principles discussed for FIG. 1E. The formation of the dielectric extension region 32, which was depicted in FIG. 1H, can either be fabricated as or used as spacers for the source and drain formation of the source and drain regions 28. The source and drain regions 28 are usually referred to as the highly doped drain (HDD) regions.

FIG. 3 depicts another alternative structure resulting from the process flow followed for device 11 in FIGS. 1A-1H. FIG. 3 illustrates a device 15 which has an added selective source and drain extension step that would occur after the process steps in FIG. 1H. Source and drain extensions 34 are elevated source and drain regions which are, in most cases, formed by selective silicon epitaxy where the substrate 10 is silicon. Source and drain extensions 34 are additional substrate material that is formed to provide a larger surface area connection to the source and drain regions 28. The formation of the elevated source and drain extensions 34 is confined to a region defined by the dielectric layer 12, the lateral dielectric extension region 32, and the source and drain regions 28. It should be noted that some of the source and drain regions 28 could be consumed by the formation of the elevated source and drain extensions 34.

FIG. 4 illustrates another alternative structure resulting from the process flow followed for device 11 in FIGS. 1A-1H. FIG. 4 illustrates a device 17 which has an added salicide formation step that occurs after the process steps illustrated in FIG. 1H. Salicide formations 36 are formed overlying a large portion of gate 16 and overlying the source and drain regions 28 that are exposed between the thick gate dielectric 24 and the dielectric layer 30. The salicide formations 36 may consume some of the underlying material depending on the composition of the underlying material and the formation technique. Salicide regions are useful for making lower resistive electrical connections to current electrode regions such as the source and drain regions 28 and/or the control region, gate 16.

It is to be understood that this invention is not limited to the particular forms shown and that it is intended in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention. For example, use of the invention is not limited to the use of salicide for the source, drain and gate overlying formation as illustrated in FIG. 4.

In summary, device 11 of FIG. 1H provides the advantages of a thin gate dielectric FET and the advantages of a thick gate dielectric FET while at the same time avoiding the disadvantages of both thin and thick gate dielectric FETs.

Firstly, due to the fact that the thin gate dielectric 14 is centrally located to overlie most of the channel region between the source and drain regions 28, the channel region will be capable of carrying larger currents as would a thin gate dielectric FET. The ability of a FET to carry larger currents results in larger gain which is beneficial.

Secondly, the thin gate dielectric 14 which covers most of the channel region results in improved short channel behavior. In other words, the channel region holds a more stable potential as the distance between the source and drain or the channel length is reduced, i.e., as the device is shrunk in size to the submicron range and beyond. This stable channel potential reduces the previously mentioned drain induced barrier lowering (DIBL) which adversely effects turn on or threshold voltages.

Thirdly, the thicker gate dielectric 24, which is shown in FIG. 1H, is placed strategically between the areas where the source 28 and the gate 16, and the drain 28 and the gate 16 are in the closest proximity to one another. It is these two regions that have a high potential for current leakage. Current leakage and gate dielectric damage resulting in degraded lifetime caused by hot carrier injection is reduced by the thicker gate dielectric 24. In addition, the thicker gate dielectric 24 reduces valence band to conduction band current leakage because the thicker oxide reduces the normally excessive electric fields that bend both of the bands to a higher rate of current leakage.

Fourthly, the thicker gate dielectric 24 reduces Miller Capacitance between the source 28 and the gate 16, and the drain 28 and the gate 16 primarily because Miller capacitance is proportional to the inverse of the dielectric gate 24 thickness. The reduction in capacitance allows the device to operate at faster switching frequencies and allows the device to gain all the other benefits resulting from quicker operation as well.

Finally, because device 11 resembles a nonoverlap FET configuration, the device can be sized much smaller than current conventional devices. It is also important to reiterate that device 11 can be used with existing technology such as threshold implants, LDD technology, selective silicon epitaxy, salicide growth, and other techniques to further improve performance for certain applications.

While the present invention has been illustrated and described with reference to specific embodiments, further modifications and improvements will occur to those skilled in the art. By now it should be apparent that there has been provided a process for making a FET having a gate dielectric with at least two different thicknesses that result in several stated advantages. It is to be understood, therefore, that this invention is not limited to the particular forms shown and that it is intended in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention.

Claims (5)

We claim:
1. A process for forming a field effect transistor having a gate dielectric with variable thickness, comprising the steps of:
providing a semiconductor substrate;
forming a dielectric overlying the substrate and having a first thickness;
forming a control electrode on the dielectric with a first predetermined width;
forming a non-oxidizing film of material around the control electrode;
increasing the first thickness of the dielectric to a second thickness adjacent a perimeter of the control electrode;
removing the non-oxidizing film of material from the control electrode after the second thickness of the dielectric has been formed;
extending the first predetermined width of the control electrode by laterally enlarging the control electrode to a second predetermined width after the second thickness of the dielectric is formed so that the dielectric which is below the control electrode has a thickness in a central portion beneath the control electrode which is less than an outer perimeter portion beneath the control electrode; and
forming first and second current electrodes in the semiconductor substrate to form a channel region underlying the control electrode.
2. The process for forming the field effect transistor of claim 1 further comprising the step of:
forming third and fourth current electrode regions underlying a portion of the second predetermined thickness of the gate dielectric, the third current electrode region being adjacent to the first current electrode region and having the second conductivity type but being electrically doped lighter than the first current electrode region, the fourth current electrode region being adjacent to the second current electrode region and having the second conductivity type but being electrically doped lighter than the second current electrode region.
3. The process for forming the field effect transistor of claim 1 further comprising the step of:
forming first and second current electrode extensions respectively overlying a portion of said first and second current electrode regions, for respectively making electrical contact to the first and second current electrode regions.
4. The process for forming the field effect transistor of claim 1 further comprising the step of:
forming a layer of conductive material overlying a portion of each of said first and second current electrode regions and at least a portion of said control electrode, the conductive material making electrical contact to the first and second current electrode regions and the control electrode.
5. The process of claim 4 wherein the step of forming a layer of conductive material further comprises using salicide as the conductive material.
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Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5486484A (en) * 1993-02-22 1996-01-23 Texas Instruments Incorporated Lateral power MOSFET structure using silicon carbide
US5501995A (en) * 1993-12-17 1996-03-26 Samsung Electronics Co., Ltd. Method for manufacturing a gate electrode of a MOS transistor
US5595922A (en) * 1994-10-28 1997-01-21 Texas Instruments Process for thickening selective gate oxide regions
US5940692A (en) * 1995-10-18 1999-08-17 Micron Technology, Inc. Method of forming a field effect transistor
US5945698A (en) * 1995-08-09 1999-08-31 Micron Technology, Inc. Field effect transistor assemblies and transistor gate block stacks
US6013929A (en) * 1997-07-08 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, having a nitride film on the gate insulation layer and an organic resin interlayer film on the transistor
US6078086A (en) * 1996-10-25 2000-06-20 Lg Semicon Co., Ltd. Metal oxide semiconductor field effect transistor and method of manufacturing the same
US6097070A (en) * 1999-02-16 2000-08-01 International Business Machines Corporation MOSFET structure and process for low gate induced drain leakage (GILD)
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
US6160277A (en) * 1996-10-28 2000-12-12 Micron Technology, Inc. Field effect transistor assemblies and transistor gate block stacks
US6165918A (en) * 1999-05-06 2000-12-26 Integrated Device Technology, Inc. Method for forming gate oxides of different thicknesses
US6177343B1 (en) 1995-09-14 2001-01-23 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6200843B1 (en) 1998-09-24 2001-03-13 International Business Machines Corporation High-voltage, high performance FETs
US6214749B1 (en) 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US6225669B1 (en) * 1998-09-30 2001-05-01 Advanced Micro Devices, Inc. Non-uniform gate/dielectric field effect transistor
US6235648B1 (en) * 1997-09-26 2001-05-22 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6255175B1 (en) * 2000-01-07 2001-07-03 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with minimized parasitic Miller capacitance
US6271572B1 (en) 1997-02-12 2001-08-07 Yamaha Corporation Multi-voltage level semiconductor device and its manufacture
US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6326318B1 (en) 1995-09-14 2001-12-04 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US20030092106A1 (en) * 1998-08-19 2003-05-15 Genentech, Inc. Secreted and transmembrane polypeptides and nucleic acids encoding the same
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US20040113214A1 (en) * 2002-09-20 2004-06-17 Seiko Epson Corporation Semiconductor device, electro-optical device, electronic apparatus, and method for manufacturing semiconductor device
US20040137689A1 (en) * 2003-01-15 2004-07-15 International Business Machines Corporation Low-GIDL MOSFET structure and method for fabrication
US20040152275A1 (en) * 2000-01-17 2004-08-05 Masahiro Yoshida Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
US6831015B1 (en) 1996-08-30 2004-12-14 Sanyo Electric Co., Ltd. Fabrication method of semiconductor device and abrasive liquid used therein
US6844252B2 (en) 1996-09-17 2005-01-18 Micron Technology, Inc. Semiconductor processing methods of forming a conductive gate and line
US6933554B1 (en) * 2000-07-11 2005-08-23 Advanced Micro Devices, Inc. Recessed tunnel oxide profile for improved reliability in NAND devices
US20060199371A1 (en) * 1995-09-14 2006-09-07 Sanyo Electric Co., Ltd. Semiconductor devices passivation film
US20060202259A1 (en) * 2005-03-09 2006-09-14 Yoshio Ozawa Semiconductor device and method of fabricating the same
US20080157199A1 (en) * 2006-12-27 2008-07-03 Spansion Llc Dielectric extension to mitigate short channel effects
US20100025770A1 (en) * 2008-07-31 2010-02-04 Martin Trentzsch Gate dielectrics of different thickness in pmos and nmos transistors
US20110104861A1 (en) * 2004-07-15 2011-05-05 Jun Cai Integrated complementary low voltage rf-ldmos
EP2568516A1 (en) * 2011-09-12 2013-03-13 Sony Corporation Thin-film transistor and electronic unit
US20140252495A1 (en) * 1996-04-08 2014-09-11 Renesas Electronics Corporation Method of forming a cmos structure having gate insulation films of different thicknesses
US20150001637A1 (en) * 2013-06-27 2015-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric and method of making the same
US9093522B1 (en) 2014-02-04 2015-07-28 Maxpower Semiconductor, Inc. Vertical power MOSFET with planar channel and vertical field plate
US20150231548A1 (en) * 2014-02-19 2015-08-20 Chen-Hsin Lin Air cleaning device
US9184248B2 (en) 2014-02-04 2015-11-10 Maxpower Semiconductor Inc. Vertical power MOSFET having planar channel and its method of fabrication
US9761702B2 (en) 2014-02-04 2017-09-12 MaxPower Semiconductor Power MOSFET having planar channel, vertical current path, and top drain electrode
US10256319B2 (en) 2015-02-19 2019-04-09 International Business Machines Corporation Non-uniform gate dielectric for U-shape MOSFET
US10276679B2 (en) * 2017-05-30 2019-04-30 Vanguard International Semiconductor Corporation Semiconductor device and method for manufacturing the same
US10361296B2 (en) 2017-06-29 2019-07-23 Monolith Semiconductor Inc. Metal oxide semiconductor (MOS) controlled devices and methods of making the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051794A (en) * 1988-07-05 1991-09-24 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method for manufacturing the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051794A (en) * 1988-07-05 1991-09-24 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method for manufacturing the same

Cited By (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5486484A (en) * 1993-02-22 1996-01-23 Texas Instruments Incorporated Lateral power MOSFET structure using silicon carbide
US5501995A (en) * 1993-12-17 1996-03-26 Samsung Electronics Co., Ltd. Method for manufacturing a gate electrode of a MOS transistor
US6214749B1 (en) 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US5595922A (en) * 1994-10-28 1997-01-21 Texas Instruments Process for thickening selective gate oxide regions
US5945698A (en) * 1995-08-09 1999-08-31 Micron Technology, Inc. Field effect transistor assemblies and transistor gate block stacks
US20060199371A1 (en) * 1995-09-14 2006-09-07 Sanyo Electric Co., Ltd. Semiconductor devices passivation film
US6177343B1 (en) 1995-09-14 2001-01-23 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6326318B1 (en) 1995-09-14 2001-12-04 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6268657B1 (en) 1995-09-14 2001-07-31 Sanyo Electric Co., Ltd. Semiconductor devices and an insulating layer with an impurity
US5940692A (en) * 1995-10-18 1999-08-17 Micron Technology, Inc. Method of forming a field effect transistor
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
US20140252495A1 (en) * 1996-04-08 2014-09-11 Renesas Electronics Corporation Method of forming a cmos structure having gate insulation films of different thicknesses
US9111909B2 (en) * 1996-04-08 2015-08-18 Tessera Advanced Technologies, Inc. Method of forming a CMOS structure having gate insulation films of different thicknesses
US6831015B1 (en) 1996-08-30 2004-12-14 Sanyo Electric Co., Ltd. Fabrication method of semiconductor device and abrasive liquid used therein
US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US7170139B2 (en) 1996-09-17 2007-01-30 Micron Technology, Inc. Semiconductor constructions
US6844252B2 (en) 1996-09-17 2005-01-18 Micron Technology, Inc. Semiconductor processing methods of forming a conductive gate and line
US6078086A (en) * 1996-10-25 2000-06-20 Lg Semicon Co., Ltd. Metal oxide semiconductor field effect transistor and method of manufacturing the same
US6160277A (en) * 1996-10-28 2000-12-12 Micron Technology, Inc. Field effect transistor assemblies and transistor gate block stacks
US7022574B2 (en) 1997-02-12 2006-04-04 Yamaha Corporation Multi-voltage level semiconductor device and its manufacture
US20010026983A1 (en) * 1997-02-12 2001-10-04 Yamaha Corporation Multi-voltage level semiconductor device and its manufacture
US6271572B1 (en) 1997-02-12 2001-08-07 Yamaha Corporation Multi-voltage level semiconductor device and its manufacture
US6013929A (en) * 1997-07-08 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, having a nitride film on the gate insulation layer and an organic resin interlayer film on the transistor
US6501132B1 (en) 1997-07-08 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Transistor with variable channel width
US6235648B1 (en) * 1997-09-26 2001-05-22 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US20030203610A1 (en) * 1998-07-30 2003-10-30 Terry Gilton Semiconductor processing method
US6713355B2 (en) 1998-07-30 2004-03-30 Micron Technology, Inc. Semiconductor processing method
US6838365B2 (en) 1998-07-30 2005-01-04 Micron Technology, Inc. Methods of forming electronic components, and a conductive line
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
US20040126937A1 (en) * 1998-07-30 2004-07-01 Terry Gilton Methods of forming electronic components, and a conductive line
US6576939B1 (en) 1998-07-30 2003-06-10 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
US20030092106A1 (en) * 1998-08-19 2003-05-15 Genentech, Inc. Secreted and transmembrane polypeptides and nucleic acids encoding the same
US6200843B1 (en) 1998-09-24 2001-03-13 International Business Machines Corporation High-voltage, high performance FETs
US6744101B2 (en) * 1998-09-30 2004-06-01 Advanced Micro Devices, Inc. Non-uniform gate/dielectric field effect transistor
US6225669B1 (en) * 1998-09-30 2001-05-01 Advanced Micro Devices, Inc. Non-uniform gate/dielectric field effect transistor
US6097070A (en) * 1999-02-16 2000-08-01 International Business Machines Corporation MOSFET structure and process for low gate induced drain leakage (GILD)
US6165918A (en) * 1999-05-06 2000-12-26 Integrated Device Technology, Inc. Method for forming gate oxides of different thicknesses
US6255175B1 (en) * 2000-01-07 2001-07-03 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with minimized parasitic Miller capacitance
US6448613B1 (en) * 2000-01-07 2002-09-10 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with minimized parasitic Miller capacitance
US7309899B2 (en) 2000-01-17 2007-12-18 Oki Electric Industry Co., Ltd. Semiconductor device including a MOSFET with nitride side wall
US7078303B2 (en) 2000-01-17 2006-07-18 Oki Electric Industry Co., Ltd. Method for manufacturing semiconductor device having thick insulating layer under gate side walls
US20050087799A1 (en) * 2000-01-17 2005-04-28 Masahiro Yoshida A semiconductor device including a mosfet with nitride side wall
US6953732B2 (en) * 2000-01-17 2005-10-11 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls
US20050221562A1 (en) * 2000-01-17 2005-10-06 Masahiro Yoshida Method for manufacturing semiconductor device having thick insulating layer under gate side walls
US20040152275A1 (en) * 2000-01-17 2004-08-05 Masahiro Yoshida Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls
US6933554B1 (en) * 2000-07-11 2005-08-23 Advanced Micro Devices, Inc. Recessed tunnel oxide profile for improved reliability in NAND devices
US6882016B2 (en) * 2002-09-20 2005-04-19 Seiko Epson Corporation Semiconductor device, electro-optical device, electronic apparatus, and method for manufacturing semiconductor device
US20040113214A1 (en) * 2002-09-20 2004-06-17 Seiko Epson Corporation Semiconductor device, electro-optical device, electronic apparatus, and method for manufacturing semiconductor device
CN101410951B (en) 2003-01-15 2010-05-05 国际商业机器公司 Low-GIDL MOSFET structure and method for fabrication
US6841826B2 (en) * 2003-01-15 2005-01-11 International Business Machines Corporation Low-GIDL MOSFET structure and method for fabrication
US6878582B2 (en) 2003-01-15 2005-04-12 International Business Machines Corporation Low-GIDL MOSFET structure and method for fabrication
US20040248356A1 (en) * 2003-01-15 2004-12-09 International Business Machines Corporation Low-GIDL MOSFET structure and method for fabrication
WO2004066367A3 (en) * 2003-01-15 2009-05-28 Ibm Low-gidl mosfet structure and method for fabrication
US20040137689A1 (en) * 2003-01-15 2004-07-15 International Business Machines Corporation Low-GIDL MOSFET structure and method for fabrication
US8324042B2 (en) 2004-07-15 2012-12-04 Fairchild Semiconductor Corporation Integrated complementary low voltage RF-LDMOS
US20110104861A1 (en) * 2004-07-15 2011-05-05 Jun Cai Integrated complementary low voltage rf-ldmos
US20060202259A1 (en) * 2005-03-09 2006-09-14 Yoshio Ozawa Semiconductor device and method of fabricating the same
US8026133B2 (en) 2005-03-09 2011-09-27 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device with a non-uniform gate insulating film
US20090269894A1 (en) * 2005-03-09 2009-10-29 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same cross-reference to related applications
US9318333B2 (en) 2006-12-27 2016-04-19 Cypress Semiconductor Corporation Dielectric extension to mitigate short channel effects
US20080157199A1 (en) * 2006-12-27 2008-07-03 Spansion Llc Dielectric extension to mitigate short channel effects
US20100025770A1 (en) * 2008-07-31 2010-02-04 Martin Trentzsch Gate dielectrics of different thickness in pmos and nmos transistors
US7994037B2 (en) * 2008-07-31 2011-08-09 Advanced Micro Devices, Inc. Gate dielectrics of different thickness in PMOS and NMOS transistors
EP2568516A1 (en) * 2011-09-12 2013-03-13 Sony Corporation Thin-film transistor and electronic unit
US9917168B2 (en) * 2013-06-27 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric
US20150001637A1 (en) * 2013-06-27 2015-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric and method of making the same
WO2015119709A1 (en) * 2014-02-04 2015-08-13 Maxpower Semiconductor, Inc. Vertical power mosfet including planar channel
US9093522B1 (en) 2014-02-04 2015-07-28 Maxpower Semiconductor, Inc. Vertical power MOSFET with planar channel and vertical field plate
TWI550851B (en) * 2014-02-04 2016-09-21 Maxpower Semiconductor Inc Vertical power metal oxide semiconductor field effect transistor having a flat channel
US9461127B2 (en) 2014-02-04 2016-10-04 Maxpower Semiconductor, Inc. Vertical power MOSFET having planar channel and its method of fabrication
US9761702B2 (en) 2014-02-04 2017-09-12 MaxPower Semiconductor Power MOSFET having planar channel, vertical current path, and top drain electrode
US9947779B2 (en) 2014-02-04 2018-04-17 Maxpower Semiconductor Inc. Power MOSFET having lateral channel, vertical current path, and P-region under gate for increasing breakdown voltage
US9184248B2 (en) 2014-02-04 2015-11-10 Maxpower Semiconductor Inc. Vertical power MOSFET having planar channel and its method of fabrication
US20150231548A1 (en) * 2014-02-19 2015-08-20 Chen-Hsin Lin Air cleaning device
US10256319B2 (en) 2015-02-19 2019-04-09 International Business Machines Corporation Non-uniform gate dielectric for U-shape MOSFET
US10276679B2 (en) * 2017-05-30 2019-04-30 Vanguard International Semiconductor Corporation Semiconductor device and method for manufacturing the same
US10361296B2 (en) 2017-06-29 2019-07-23 Monolith Semiconductor Inc. Metal oxide semiconductor (MOS) controlled devices and methods of making the same

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