CN113990931B - 击穿电压温度系数可调的Trench MOSFET器件及制备方法 - Google Patents
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- 230000015556 catabolic process Effects 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000008859 change Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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Abstract
本发明提供一种击穿电压温度系数可调的Trench MOSFET器件及制备方法，包括P+衬底、金属化漏极、P‑漂移区、氧化层、金属化源极、栅电极、N‑掺杂区、P+重掺杂区、N+重掺杂区；本发明有效解决了Trench MOSFET穿通击穿电压随温度升高而增大所带来的可靠性问题。显然，本发明中所有的N型区和P型区可完全对换，对换后形成导电类型相反的器件。
Description
技术领域
本发明属于本发明涉及场效应晶体管器件结构，属于功率半导体技术领域。
背景技术
随着电力控制能力的提高，交通、医疗、消费类电子、电力传输等领域都得到了巨大的发展，人们对电子产品的依赖飞速提高。功率MOSFET在电力技术中扮演着极其重要的作用，科学技术能发展如此迅速得益于功率MOSFET器件的发展。传统的双扩散MOSFET采用双扩散技术形成体区，因此元胞宽度大，同时由于其内部JFET区的存在，使得其导通电阻较大。而Trench MOSFET的栅极沟槽处于体区，并深入漂移区，导电沟道为纵向沟道，因此可以提高元胞密度和消除JFET区电阻，使导通电阻更接近于理想值，该结构的优化也将功率MOSFET的工作频率提高到1MHZ的范围,使其广泛应用于低压高频产品领域。
击穿电压的温度系数是MOSFET器件较为重要的运行参数之一。器件的穿通击穿电压随温度增大而逐渐增大，导致器件存在着由温度变化所带来的不稳定性问题，这将会严重影响到MOSFET器件的可靠性。本发明提出的结构可以在Trench MOSFET结构的基础上改善温度变化带来的不稳定性问题，增强MOSFET器件在应用中的可靠性。
发明内容
本发明的目的是提供一种击穿电压温度系数可调的Trench MOSFET器件。以P沟道Trench MOSFET为例，引入P+重掺杂区7、N+重掺杂区8PN结，利用PN结耗尽区宽度随着温度升高而变小，导致P+重掺杂区7的电阻减小，其压降减小，以补偿Trench MOSFET穿通击穿电压随温度升高而增大的特性。
为实现上述发明目的，本发明技术方案如下：
一种击穿电压温度系数可调的Trench MOSFET器件，包括P+衬底2、位于P+衬底背面的金属化漏极1、位于P+衬底上面的P-漂移区3、位于P-漂移区3上方的氧化层5、位于氧化层5顶部的金属化源极9、被氧化层5包裹的栅电极4；氧化层5的两侧均有一个N-掺杂区6和P+重掺杂区7，P+重掺杂区7位于N-掺杂区6的上侧；在垂直深度上栅电极4的底部低于N-掺杂区6的底部，栅电极4的顶部高于N-掺杂区6的顶部；P+重掺杂区7的内部上方且远离氧化层5的一侧是N+重掺杂区8，且N+重掺杂区8的顶部与P+重掺杂区7的顶部平齐；金属化源极9覆盖氧化层5的上表面且与部分P+重掺杂区7接触，金属化源极9和栅电极4相隔离，金属化电极10位于N+重掺杂区8的顶部；
当器件正向导通时，栅电极4接负电位，金属化漏极1接负电位，金属化源极9和金属化电极10接零电位；当器件反向阻断时，栅电极4和金属化源极9短接，且接零电位，金属化漏极1接负电位，金属化电极10接正电位。
作为优选方式，氧化层5为二氧化硅，或者二氧化硅和氮化硅的复合材料。
作为优选方式，栅电极4材料为多晶硅。
作为优选方式，整个器件的材料是体硅、或碳化硅、或砷化镓或锗硅。
作为优选方式，所有的N型区和所有的P型区完全对换，对换后形成导电类型相反的器件。
作为优选方式，P+重掺杂区7的掺杂浓度大于1e17/cm3，N+重掺杂区8的掺杂浓度大于1e19/cm3。
本发明还提供一种击穿电压温度系数可调的Trench MOSFET的器件的制备方法，包括如下步骤：
(1)单晶硅准备及外延生长；采用重掺杂单晶硅P+衬底2，晶向为<100>；采用气相外延VPE方法生长P-漂移区3；
(2)刻槽；淀积硬掩膜作为后续挖槽的阻挡层，利用光刻板进行沟槽刻蚀，刻蚀出槽栅区，刻蚀工艺使用反应离子刻蚀或等离子刻蚀；
(3)在沟槽内热生长氧化层；去掉硬掩膜，在槽内生长二氧化硅层，形成氧化层5；
(4)多晶硅的淀积与刻蚀；淀积多晶硅，形成栅电极4；利用光刻板刻掉多余的多晶硅和二氧化硅；
(5)淀积氧化层；对槽栅区淀积氧化层，形成多晶硅顶部的氧化层，并刻蚀掉沟槽顶部以外左右两个区域的氧化层；其中，刻蚀后的氧化层高于硅表面；
(6)离子注入；磷注入，形成N-掺杂区6，其中N-掺杂区6的底部的垂直深度不低于栅电极4底部的垂直深度；
(7)离子注入；硼注入，形成P+重掺杂区7，然后进行砷注入，形成N+重掺杂区8；
(8)金属化；正面金属化，金属刻蚀，背面金属化，钝化；
下面从两个方面说明本发明的工作原理：
(1)器件的正向导通
本发明所提供的一种击穿电压温度系数可调的Trench MOSFET器件，其正向导通时的电极连接方式为：栅电极4接负电位，金属化漏极1接负电位，金属化源极9和金属化电极10短接，接零电位。当栅电极4施加的负偏压达到阈值电压时，在N-掺杂区6中靠近氧化层5的一侧形成反型层沟道，在金属化漏极1的反向偏压下，空穴作为载流子从P+重掺杂区7经过N-掺杂区6中的反型层沟道，注入P-漂移区3，并到达金属化漏极1形成正向电流，器件导通。
(2)器件的反向阻断
本发明所提供的一种击穿电压温度系数可调的Trench MOSFET器件，其反向阻断时的电极连接方式为：栅电极4与金属化源极9短接，并接零电位，金属化漏极1接负电位，金属化电极10接正电位。由于栅电极4零偏压时，N-掺杂区6中没有反型层沟道，多子空穴的导电通路被夹断。增大反向电压时，N-掺杂区6完全耗尽，即穿通。由于N+重掺杂区8和P+重掺杂区7的引入，N+重掺杂区8与沟槽之间形成了一个JFET区，随着温度的升高，N+重掺杂区8与P+重掺杂区7之间的PN结耗尽区宽度减小，JFET区电阻减小，其压降减小。较传统TrenchMOSFET器件，相当于在其一侧串联了负温度系数的温变电阻，即上述的JFET区电阻，这可补偿击穿电压的正温度系数。其中，器件在反向阻断时，金属化电极10上施加的正压值，可改变P+重掺杂区7、N+重掺杂区8之间的PN结耗尽区的宽度，以实现对温变电阻阻值的调节，进而实现器件击穿电压温度系数的可调性。
本发明的有益效果为：本发明所提供的一种击穿电压温度系数可调的TrenchMOSFET器件，有效解决了Trench MOSFET穿通击穿电压随温度升高而增大所带来的可靠性问题。显然，本发明中所有的N型区和P型区可完全对换，对换后形成导电类型相反的器件。
附图说明
图1是本发明提供的一种击穿电压温度系数可调的Trench MOSFET器件剖面结构示意图。
图2-1至图2-8是本发明提供的一种击穿电压温度系数可调的Trench MOSFET器件的一种制造工艺流程的示意图。
图3-1是传统的Trench MOSFET器件在300K、350K、400K的温度下的穿通击穿电压随温度变化的曲线。
图3-2是本发明的器件在300K、350K、400K的温度下的击穿电压随温度变化的曲线图。
1为金属化漏极，2为P+衬底，3为P-漂移区，4为栅电极，5为氧化层，6为N-掺杂区，7为P+重掺杂区，8为N+重掺杂区，9为金属化源极，10为金属化电极。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
一种击穿电压温度系数可调的Trench MOSFET器件，包括P+衬底2、位于P+衬底背面的金属化漏极1、位于P+衬底上面的P-漂移区3、位于P-漂移区3上方的氧化层5、位于氧化层5顶部的金属化源极9、被氧化层5包裹的栅电极4；氧化层5的两侧均有一个N-掺杂区6和P+重掺杂区7，P+重掺杂区7位于N-掺杂区6的上侧；在垂直深度上栅电极4的底部低于N-掺杂区6的底部，栅电极4的顶部高于N-掺杂区6的顶部；P+重掺杂区7的内部上方且远离氧化层5的一侧是N+重掺杂区8，且N+重掺杂区8的顶部与P+重掺杂区7的顶部平齐；金属化源极9覆盖氧化层5的上表面且与部分P+重掺杂区7接触，金属化源极9和栅电极4相隔离，金属化电极10位于N+重掺杂区8的顶部；
当器件正向导通时，栅电极4接负电位，金属化漏极1接负电位，金属化源极9和金属化电极10接零电位；当器件反向阻断时，栅电极4和金属化源极9短接，且接零电位，金属化漏极1接负电位，金属化电极10接正电位。
氧化层5为二氧化硅，或者二氧化硅和氮化硅的复合材料。
栅电极4材料为多晶硅。
整个器件的材料是体硅、或碳化硅、或砷化镓或锗硅。
所有的N型区和所有的P型区完全对换，对换后形成导电类型相反的器件。
P+重掺杂区7的掺杂浓度大于1e17/cm3，N+重掺杂区8的掺杂浓度大于1e19/cm3。本实施例还提供一种击穿电压温度系数可调的Trench MOSFET的器件的制备方法，包括如下步骤：
(1)单晶硅准备及外延生长；如图2-1，采用重掺杂单晶硅P+衬底2，晶向为<100>；采用气相外延VPE方法生长P-漂移区3；
(2)刻槽；如图2-2，淀积硬掩膜(如氮化硅)作为后续挖槽的阻挡层，利用光刻板进行沟槽刻蚀，刻蚀出槽栅区，刻蚀工艺使用反应离子刻蚀或等离子刻蚀；
(3)在沟槽内热生长氧化层；如图2-3，去掉硬掩膜，在槽内生长二氧化硅层，形成氧化层5；
(4)多晶硅的淀积与刻蚀；如图2-4，淀积多晶硅，形成栅电极4；利用光刻板刻掉多余的多晶硅和二氧化硅；
(5)淀积氧化层；如图2-5，对槽栅区淀积氧化层，形成多晶硅顶部的氧化层，并刻蚀掉沟槽顶部以外左右两个区域的氧化层；其中，刻蚀后的氧化层高于硅表面；
(6)离子注入；如图2-6，磷注入，形成N-掺杂区6，其中N-掺杂区6的底部的垂直深度不低于栅电极4底部的垂直深度；
(7)离子注入；如图2-7，硼注入，形成P+重掺杂区7，然后进行砷注入，形成N+重掺杂区8；
(8)金属化；如图2-8，正面金属化，金属刻蚀，背面金属化，钝化。
制作器件时，还可用碳化硅、砷化镓或锗硅等半导体材料替代体硅。
在40V左右的耐压下，传统器件的雪崩击穿的温度系数大概是40mV/K，穿通击穿的温度系数在20mV/K左右，分别选取300K、350K、400K的温度，穿通结构击穿电压随温度变化的曲线如图3-1所示。本设计基于Trench MOSFET器件优化，以2.8μm的元胞宽度、8μm的漂移区厚度、1.6μm的沟槽深度、0.67μm的沟槽宽度、0.05μm栅氧厚度，通过参数拉偏，最终确定以下参数以满足本发明要求：P-漂移区3的电阻率为2，N-掺杂区6掺杂剂量、注入能量、推结时间为4.4e12/cm2和150Kev、60分钟，P+重掺杂区7的掺杂剂量、注入能量、推结时间为3e13/cm2和60Kev、20分钟，N+重掺杂区8的两次掺杂剂量、注入能量分别为5e14/cm2和25Kev，5e13/cm2和20Kev。在金属化电极10接6V正压情况下，本发明的击穿电压随温度变化的曲线如图3-2所示，其温度系数为2.9mV/K，可见本发明能够有效降低击穿电压的温度系数。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。
Claims (6)
1.一种击穿电压温度系数可调的Trench MOSFET器件，其特征在于：包括P+衬底（2）、位于P+衬底背面的金属化漏极（1）、位于P+衬底上面的P-漂移区（3）、位于P-漂移区（3）上方的氧化层（5）、位于氧化层（5）顶部的金属化源极（9）、被氧化层（5）包裹的栅电极（4）；氧化层（5）的两侧均有一个N-掺杂区（6）和P+重掺杂区（7），P+重掺杂区（7）位于N-掺杂区（6）的上侧；在垂直深度上栅电极（4）的底部低于N-掺杂区（6）的底部，栅电极（4）的顶部高于N-掺杂区（6）的顶部；P+重掺杂区（7）的内部上方且远离氧化层（5）的一侧是N+重掺杂区（8），且N+重掺杂区（8）的顶部与P+重掺杂区（7）的顶部平齐；金属化源极（9）覆盖氧化层（5）的上表面且与部分P+重掺杂区（7）接触，金属化源极（9）和栅电极（4）相隔离，金属化电极（10）位于N+重掺杂区（8）的顶部；
当器件正向导通时，栅电极（4）接负电位，金属化漏极（1）接负电位，金属化源极（9）和金属化电极（10）接零电位；当器件反向阻断时，栅电极（4）和金属化源极（9）短接，且接零电位，金属化漏极（1）接负电位，金属化电极（10）接正电位。
2.根据权利要求1所述的一种击穿电压温度系数可调的Trench MOSFET器件，其特征在于：氧化层（5）为二氧化硅，或者二氧化硅和氮化硅的复合材料。
3.根据权利要求1所述的一种击穿电压温度系数可调的Trench MOSFET器件，其特征在于：栅电极（4）材料为多晶硅。
4.根据权利要求1所述的一种击穿电压温度系数可调的Trench MOSFET器件，其特征在于：所有的N型区和所有的P型区完全对换，对换后形成导电类型相反的器件。
5.根据权利要求1所述的一种击穿电压温度系数可调的Trench MOSFET器件，其特征在于：P+重掺杂区（7）的掺杂浓度大于1e17/cm3，N+重掺杂区（8）的掺杂浓度大于1e19/cm3。
6.一种根据权利要求1所述的击穿电压温度系数可调的Trench MOSFET器件的制备方法，其特征在于包括如下步骤：
（1）单晶硅准备及外延生长：采用重掺杂单晶硅P+衬底（2），晶向为<100>；采用气相外延VPE方法生长P-漂移区（3）；
（2）刻槽：淀积硬掩膜作为后续挖槽的阻挡层，利用光刻板进行沟槽刻蚀，刻蚀出槽栅区，刻蚀工艺使用反应离子刻蚀或等离子刻蚀；
（3）在沟槽内热生长氧化层：去掉硬掩膜，在槽内生长二氧化硅层，形成氧化层（5）；
（4）多晶硅的淀积与刻蚀：淀积多晶硅，形成栅电极（4）；利用光刻板刻掉多余的多晶硅和二氧化硅；
（5）淀积氧化层：对槽栅区淀积氧化层，形成多晶硅顶部的氧化层，并刻蚀掉沟槽顶部以外左右两个区域的氧化层；其中，刻蚀后的氧化层高于硅表面；
（6）离子注入：磷注入，形成N-掺杂区（6），其中N-掺杂区（6）的底部的垂直深度不低于栅电极（4）底部的垂直深度；
（7）离子注入：硼注入，形成P+重掺杂区（7），然后进行砷注入，形成N+重掺杂区（8）；
（8）金属化：正面金属化形成金属化源极（9），金属刻蚀，背面金属化形成金属化漏极（1），钝化。
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