WO2021169381A1 - 一种优化电特性的dmos - Google Patents

一种优化电特性的dmos Download PDF

Info

Publication number
WO2021169381A1
WO2021169381A1 PCT/CN2020/126044 CN2020126044W WO2021169381A1 WO 2021169381 A1 WO2021169381 A1 WO 2021169381A1 CN 2020126044 W CN2020126044 W CN 2020126044W WO 2021169381 A1 WO2021169381 A1 WO 2021169381A1
Authority
WO
WIPO (PCT)
Prior art keywords
lto
layer
dmos
trench
upper side
Prior art date
Application number
PCT/CN2020/126044
Other languages
English (en)
French (fr)
Inventor
李加洋
胡兴正
薛璐
刘海波
Original Assignee
南京华瑞微集成电路有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京华瑞微集成电路有限公司 filed Critical 南京华瑞微集成电路有限公司
Publication of WO2021169381A1 publication Critical patent/WO2021169381A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the utility model belongs to the technical field of semiconductors, and specifically relates to a DMOS with optimized electrical characteristics.
  • DMOS is a commonly used power device. It has a similar structure to CMOS devices. It also has active, drain, and gate electrodes, but the drain terminal has a high breakdown voltage.
  • the DMOS of the existing structure will reduce the capacitance parameters (such as input capacitance Ciss, output capacitance Coss and Miller capacitance Crss) while losing part of Rsp (resistance per unit area), so that when optimizing the switching loss, the conduction loss increases. Therefore, further optimization of DMOS products is restricted.
  • the technical problem solved by the utility model is to provide a DMOS with optimized electrical characteristics.
  • the utility model provides a DMOS with optimized electrical characteristics, which includes a substrate of a first conductivity type and an epitaxial layer arranged on the upper side of the substrate.
  • the epitaxial layer is provided with a second conductivity type withstand voltage ring area
  • the LTO trench is provided with silicon dioxide
  • a JEFT area is formed on the upper side of the epitaxial layer around the LTO trench
  • a gate oxide layer is grown on the upper side of the JEFT area around the LTO trench.
  • the silicon oxide and the surrounding gate oxide layer are provided with a polycrystalline gate in the middle of the upper side, and the second conductivity type body region is formed in the JEFT area not covered by the gate oxide layer.
  • the first conductivity type active region and the second conductivity type active region are sequentially arranged from the inside to the outside, and a SIN dielectric layer is deposited on the upper side of the poly gate, the gate oxide layer and the first conductivity type active region.
  • the LTO dielectric layer is deposited on the upper side of the SIN dielectric layer and the epitaxial layer, the LTO dielectric layer is etched with connection holes, the upper side of the LTO dielectric layer and the connection holes are sputtered to form a metal layer, and the metal layer is etched Etching forms the gate and source regions of the DMOS.
  • the silicon dioxide is LTO formed and/or used for filling through a furnace tube wet method to grow an oxide layer.
  • the width of the LTO trench is 0.5 ⁇ m to 2 ⁇ m, and the depth thereof is 0.5 ⁇ m to 6 ⁇ m.
  • the width of the LTO trench is 2 ⁇ m, and its depth is 4 ⁇ m.
  • a passivation layer is deposited on the upper side of the metal layer, and the upper side of the passivation layer is etched to form the gate opening area and the source opening area.
  • a back gold layer is provided on the lower side of the substrate.
  • the thickness of the gate oxide layer is 700-1200 angstroms.
  • the thickness of the SIN dielectric layer is 1000 angstroms.
  • the thickness of the LTO dielectric layer is 11,000 angstroms.
  • the thickness of the passivation layer is 7000 angstroms to 12000 angstroms.
  • the DMOS of the present invention greatly increases BVDSS and reduces capacitance parameters, optimizes its output characteristics, and reduces operating losses.
  • Figure 1 is a schematic diagram of a partial structure after LTO trenches are fabricated on the epitaxial layer
  • FIG. 2 is a schematic diagram of a partial structure after filling with silicon dioxide and forming a JEFT area
  • FIG. 3 is a schematic diagram of a partial structure after forming a polycrystalline gate
  • Figure 4 is a schematic diagram of a partial structure after the body area is made in the JEFT area
  • FIG. 5 is a schematic diagram of a partial structure after fabricating the first conductivity type active region in the body region
  • Figure 6 is a schematic diagram of a partial structure after depositing a SIN dielectric layer
  • FIG. 7 is a schematic diagram of a partial structure after fabricating a second conductivity type active region, depositing an LTO dielectric layer, and etching to form a connection hole;
  • FIG. 8 is a schematic diagram of a partial structure of a metal layer formed by sputtering
  • FIG. 9 is a schematic diagram of a partial structure after deposition to form a passivation layer and evaporation to form a back gold layer;
  • FIG. 10 is a simulation diagram of the electric field distribution near the LTO trench of the DMOS with optimized electrical characteristics as the depth of the LTO trench changes;
  • FIG. 11 is a simulation experiment diagram of the drain-source breakdown voltage of the DMOS with optimized electrical characteristics as a function of the depth and width of the LTO trench;
  • Figure 12 is a simulation experiment diagram of the DMOS unit area resistance varying with the depth and width of the LTO trench for optimized electrical characteristics
  • FIG. 13 is a simulation experiment diagram of the DMOS threshold value varying with the depth and width of the LTO trench for optimizing electrical characteristics
  • FIG. 14 is a simulation experiment diagram of the input capacitance of DMOS with optimized electrical characteristics as a function of the depth and width of the LTO trench;
  • FIG. 15 is a simulation experiment diagram of the output capacitance of DMOS with optimized electrical characteristics as a function of the depth and width of the LTO trench;
  • FIG. 16 is a simulation experiment diagram of the Miller capacitance of the DMOS with optimized electrical characteristics as a function of the depth and width of the LTO trench.
  • the embodiments of the present invention provide a method for manufacturing a DMOS with optimized electrical characteristics, including:
  • a substrate 1 of the first conductivity type is provided, an epitaxial layer 2 is fabricated on the substrate 1, and a pressure ring region of the second conductivity type is fabricated on the epitaxial layer 2.
  • the substrate 1 is heavily doped, and the epitaxial layer 2 is lightly doped of the first conductivity type.
  • the first conductivity type is N-type and the second conductivity type is P-type as an example to illustrate this embodiment.
  • the substrate 1 generally adopts an N-type (100) crystal orientation, doped with arsenic or antimony, and its resistivity is usually less than 0.1 ⁇ cm.
  • the specific manufacturing process of the pressure ring zone is as follows: pre-grow a 800-1000 angstrom oxide layer 15 on the epitaxial layer 2 as a barrier layer for Ring ring injection, and pass Ring photolithography, injection and furnace tube annealing processes to form a high voltage terminal structure. Ion implantation energy: 100-140KeV, implantation dose: 3E13-8E13, implantation element: boron (B), annealing conditions: 1180°C/300-500min. Since the pressure ring area and the subsequent process and structure of the area are the same as the prior art, this part is not shown in the figure in this embodiment.
  • An LTO trench 3 is formed by etching on the upper side of the epitaxial layer 2, and the LTO trench 3 is filled with silicon dioxide 4. Specifically, the LTO trench 3 is formed on the upper side of the oxide layer 15 through glue coating, photolithography and dry etching processes.
  • JEFT implantation and JEFT well push operations are performed on the upper side of the epitaxial layer 2 outside the LTO trench 3 to form a JEFT region 5.
  • a certain concentration of phosphorus can be implanted on the surface of the epitaxial layer 2, and the JFET region 5 can be formed in the 3-6um area near the surface of the epitaxial layer 2 through a high-temperature well push process, which is effective without affecting the withstand voltage of the bottom epitaxial layer.
  • the oxide layer 15 needs to be etched away, and then the long gate oxide layer 6 on the upper side of the epitaxial layer 2 around the LTO trench 3, and the silicon dioxide 4 and Polycrystalline is deposited on the upper and middle part of the gate oxide layer 6 around it, and the polycrystalline is etched to form a polycrystalline gate 7.
  • the thickness of the gate oxide layer 6 is generally 700-1200 angstroms
  • the growth temperature is generally 900-1000° C.
  • the deposited polycrystalline thickness is 6000-8000 angstroms
  • the polycrystalline silicon is heavily doped polysilicon.
  • the polycrystalline gate 7 is formed by polycrystalline glue coating, photolithography and dry etching processes, and a polycrystalline field plate structure is formed in the terminal area of the device, which effectively improves the withstand voltage effect.
  • the second conductivity type body region is formed in the JEFT region far away from the LTO trench.
  • the specific process is as follows: implant B element, implant energy 60KeV ⁇ 120KeV, and adjust the implant dose according to the requirements of VTH parameters , Usually around 1E13-8E13, body region push trap temperature: 1150°C, time: 100-200 minutes.
  • a first conductivity type active region 9 is formed in the body region 8 on the lower side of the periphery of the gate oxide layer 6.
  • the specific process is as follows: firstly apply glue and photolithography on the body region 8 to form an NSD implantation area, forming an NSD implantation dose: 5E15-1E16, implantation energy: 120KeV-160KeV, and implantation element: phosphorus.
  • a SIN dielectric layer 10 is deposited on the upper side of the poly gate 7, the gate oxide layer 6 and the first conductive type active region 9.
  • the thickness of the SIN dielectric layer 10 is about 1000 angstroms, which can effectively improve the reliability of the device.
  • a second conductivity type active region 11 is formed in the surrounding body region 8 of the first conductivity type active region 9.
  • the specific process is as follows: first, the implantation area of the PSD is formed by applying glue and photolithography to form the PSD implantation dose: 5E15 ⁇ 1E16, implantation energy: 120KeV-160KeV, implantation element: B. Need to use RTA (rapid annealing 950 °C, 30s) process to activate the implanted atoms.
  • RTA rapid annealing 950 °C, 30s
  • the LTO dielectric layer 12 is deposited on the upper side of the SIN dielectric layer 10.
  • the LTO dielectric layer 12 adopts the deposition medium BPSG (borophosphosilicate glass), and the thickness is preferably 11000 angstroms.
  • the connecting hole 13 is formed by etching on the LTO dielectric layer 12.
  • a metal layer 14 is formed by sputtering on the upper side of the LTO dielectric layer 12 and in the connection hole 13, and is etched to form the gate region and source region of the DMOS.
  • the sputtered metal is preferably aluminum, and the thickness of sputtered aluminum is preferably 4 ⁇ m.
  • the silicon dioxide 4 of the embodiment of the present invention can be formed by wet-growing an oxide layer through a furnace tube.
  • the thickness of the grown oxide layer is 20,000 angstroms under the general process, which does not require a field oxygen structure or the width of the LTO trench 3 is relatively large.
  • LTO Low Thermal Oxide
  • Figure 10 shows the electric field distribution diagrams with or without LTO trench 3 and different trench depths, along the center of the LTO trench 3 perpendicular to the X axis
  • the surface electric field intensity of DMOS decreases, which can effectively increase BVDSS, but as the groove depth increases, the influence on the potential line in the DMOS body increases, and the curvature radius of the potential line at the bottom of the LTO trench 3 decreases.
  • BVDSS decreased.
  • Figures 11 to 13 are the corresponding relationship diagrams of the depth (unit: micron) and width (1 ⁇ m, 2 ⁇ m, 3 ⁇ m) of the LTO trench 3 and BVDSS (drain-source breakdown voltage), Rsp (resistance per unit area) and Vth (threshold) .
  • the electrical parameters are simulation results under different process conditions. From the results, when the width of the LTO trench 3 is 1um, the BVDSS, Rsp and Vth are less affected by the increase in the depth of the LTO trench 3, and as the depth of the LTO trench 3 increases, the BVDSS first has a parabolic rise stage. Then it drops rapidly, Rsp rises slowly, and Vth fluctuates cyclically.
  • Figures 14 to 16 show the corresponding relationship between the depth and width of the LTO trench 3 and Ciss (input capacitance), Coss (output capacitance) and Crss (Miller capacitance), where the electrical parameters are the simulation results under different process conditions .
  • Ciss and Vth behave the same, both exhibit periodic fluctuations.
  • Both Coss and Crss decrease rapidly as the depth of the LTO trench 3 increases, and at the same depth, the greater the width of the LTO trench 3, the smaller the capacitance value. Therefore, the width of the LTO trench 3 in the embodiment of the present invention is 0.5 ⁇ m to 2 ⁇ m, preferably 2 ⁇ m.
  • the depth of the LTO trench 3 is 0.5 ⁇ m to 6 ⁇ m, preferably 4 ⁇ m.
  • a passivation layer 16 can also be provided on the upper side of the metal layer 14.
  • the passivation layer 16 is preferably formed by silicon nitride deposition.
  • the thickness of the passivation layer 16 is 7000 angstroms to 12000 angstroms.
  • the gate opening area and the source opening area are etched on the layer 16.
  • the original thickness of the generally used substrate 1 is preferably 625-675 ⁇ m. After the production is completed, the substrate 1 needs to be reduced from the lower side to the remaining thickness of the device to be 200 ⁇ m-300 ⁇ m to facilitate packaging.
  • a back gold layer 17 may also be provided on the lower side of the substrate 1.
  • the back gold layer 17 is preferably formed by sequentially evaporating Ti-Ni-Ag (titanium-nickel-silver).
  • the embodiments of the present invention also provide a DMOS with optimized electrical characteristics.
  • the DMOS includes a substrate 1 of the first conductivity type and 1.
  • the first conductivity type is N-type
  • the second conductivity type is P-type as an example to illustrate this embodiment.
  • the substrate 1 generally adopts an N-type (100) crystal orientation, doped with arsenic or antimony, and its resistivity is usually less than 0.1 ⁇ cm.
  • different device withstand voltages can be obtained, usually epitaxial thickness: 40-80um, epitaxial resistivity: 9-24 ⁇ .cm, device withstand voltage can reach 500V-900V.
  • the epitaxial layer 2 is provided with a second conductivity type withstand voltage ring area and an LTO trench 3.
  • the specific manufacturing process of the pressure ring region is as follows: pre-grow an 800-1000 angstrom oxide layer on the epitaxial layer 2 as a barrier layer for Ring ring injection, and pass the Ring photolithography, injection and furnace tube annealing processes to form High-voltage terminal structure. Ion implantation energy: 100-140KeV, implantation dose: 3E13-8E13, implantation element: boron (B), annealing conditions: 1180°C/300-500min. Since the pressure ring area and the subsequent process and structure of the area are the same as the prior art, this part is not shown in the figure in this embodiment.
  • the LTO trench 3 is formed on the upper side of the oxide layer 15 through glue coating, photolithography and dry etching processes. Silicon dioxide 4 is provided in the LTO trench 3, and a JEFT region 5 is formed on the upper side of the epitaxial layer 2 around the LTO trench 3. Specifically, the JEFT region 5 is formed by JEFT implantation and JEFT well push operation. Specifically, a certain concentration of phosphorus can be implanted on the surface of the epitaxial layer 2, and the JFET region 5 can be formed in the 3-6um area near the surface of the epitaxial layer 2 through a high-temperature well push process, which is effective without affecting the withstand voltage of the bottom epitaxial layer. Reduce surface channel resistance. Injection dose: 2E12-5E12, injection energy: 100KeV-150KeV, trapping conditions: 1150°C/120min-190min.
  • the oxide layer 15 needs to be etched away first, and then a gate oxide layer 6 grows on the upper side of the epitaxial layer 2 around the LTO trench 3, and the gate oxide layer on the silicon dioxide 4 and its surroundings Polycrystalline is deposited in the middle of the upper side of 6 and the polycrystalline is etched to form a polycrystalline gate 7.
  • the thickness of the gate oxide layer 6 is generally 700-1200 angstroms
  • the growth temperature is generally 900-1000° C.
  • the deposited polycrystalline thickness is 6000-8000 angstroms
  • the polycrystalline silicon is undoped polysilicon.
  • the polycrystalline gate 7 is formed by polycrystalline glue coating, photolithography and dry etching processes, and a polycrystalline field plate structure is formed in the terminal area of the device, which effectively improves the withstand voltage effect.
  • a body region of the second conductivity type is formed in the JEFT area far away from the LTO trench. Specifically, the B element is injected, the energy is 60KeV ⁇ 120KeV, and the dose is adjusted according to the requirements of VTH parameters, usually around 1E13-8E13, and the body region is pushed Trap temperature: 1150°C, time: 100-200 minutes.
  • a first conductive type active region (NSD) 9 and a second conductive type active region (PSD) 11 are sequentially arranged from the inside to the outside in the body region 8 on the lower side around the gate oxide layer 6. Specifically, coating and photolithography are first performed on the body region 8 to form an NSD implantation region, which constitutes the NSD implantation dose: 5E15 to 1E16, the implantation energy: 120KeV-160KeV, and the implantation element: phosphorus. NSD trap temperature: 950°C, time: 25 minutes.
  • the specific process of the PSD is as follows: first, the injection area of the PSD is formed by applying glue and photolithography to form the PSD injection dose: 5E15 to 1E16, the injection energy: 120KeV-160KeV, and the injection element: B. Need to use RTA (rapid annealing 950 °C, 30s) process to activate the implanted atoms.
  • RTA rapid annealing 950 °C, 30s
  • the SIN dielectric layer 10 is deposited on the upper side of the poly gate 7, the gate oxide layer 6 and the first conductivity type active region 9 first.
  • the thickness of the SIN dielectric layer 10 is about 1000 angstroms, which can effectively improve the reliability of the device.
  • An LTO dielectric layer 12 is deposited on the upper side of the SIN dielectric layer 10, and the LTO dielectric layer 12 uses a deposition dielectric BPSG (borophosphosilicate glass), preferably with a thickness of 11000 angstroms.
  • a connecting hole 13 is etched on the LTO dielectric layer 12, a metal layer 14 is formed by sputtering on the upper side of the LTO dielectric layer 12 and in the connecting hole 13, and the metal layer 14 is etched to form the gate region and source region of the DMOS.
  • the sputtered metal is preferably aluminum, and the thickness of sputtered aluminum is preferably 4 ⁇ m.
  • the silicon dioxide 4 of the embodiment of the present invention can be formed by wet-growing an oxide layer in a furnace tube.
  • the thickness of the oxide layer grown in a general process is 20,000 angstroms, which results in the absence of a field oxygen structure or the large width of the LTO trench 3
  • LTO Low Thermal Oxide
  • Figure 10 shows the electric field distribution diagrams with or without LTO trench 3 and different trench depths, along the center of the LTO trench 3 perpendicular to the X axis
  • the surface electric field intensity of DMOS decreases, which can effectively increase BVDSS, but as the groove depth increases, the influence on the potential line in the DMOS body increases, and the curvature radius of the potential line at the bottom of the LTO trench 3 decreases.
  • BVDSS decreased.
  • 11 to 13 are diagrams showing the corresponding relationship between the depth (unit: micrometer) and width (1 ⁇ m, 2 ⁇ m, 3 ⁇ m) of the LTO trench 3 and BVDSS (drain-source breakdown voltage), Rsp (resistance per unit area), and Vth (threshold value).
  • the electrical parameters are simulation results under different process conditions. From the results, when the width of LTO trench 3 is 1um, the influence of BVDSS, Rsp and Vth as the depth of LTO trench 3 increases is smaller, and as the depth of LTO trench 3 increases, BVDSS first has a parabolic rise stage , Then rapidly decline, Rsp rises slowly, and Vth fluctuates cyclically.
  • the width of the LTO trench 3 in the embodiment of the present invention is 0.5 ⁇ m to 2 ⁇ m, preferably 2 ⁇ m.
  • the depth of the LTO trench 3 is 0.5 ⁇ m to 6 ⁇ m, preferably 4 ⁇ m.
  • a passivation layer 16 can also be provided on the upper side of the metal layer 14.
  • the passivation layer 16 is preferably formed by silicon nitride deposition, and the thickness of the passivation layer 16 is 7000 angstroms to 12000 angstroms, and then the gate is etched on the passivation layer Pole opening area and source opening area.
  • the original thickness of the substrate 1 used is preferably 625-675 ⁇ m.
  • the substrate 1 needs to be reduced from the lower side to the remaining thickness of the device to be 200 ⁇ m-300 ⁇ m to facilitate packaging.
  • a back gold layer 17 may also be provided on the lower side of the substrate 1.
  • the back gold layer 17 is preferably formed by sequentially evaporating Ti-Ni-Ag (titanium-nickel-silver).

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种优化电特性的DMOS。包括衬底和外延层，外延层上设耐压环区及LTO沟槽，沟槽内设二氧化硅，沟槽四周的外延层上侧形成JFET区域，沟槽四周的JFET区域上设栅氧化层，二氧化硅及栅氧化层上侧中部设多晶栅，远离沟槽的JFET区域内设第二导电类型的体区，栅氧化层四周下侧的体区由内向外依次设第一和第二导电类型有源区，多晶栅、栅氧化层和第一导电类型有源区上侧淀积SiN介质层，SiN介质层上侧淀积LTO介质层，LTO介质层上设连接孔，LTO介质层上侧及连接孔内溅射成金属层，金属层经刻蚀形成DMOS的栅区和源区。改变沟槽深度和宽度，可改变沟槽周围的电场分布和电学参数，在Rsp增加较小的前提下，增加BVDSS、降低电容参数，优化输出特性，降低工作损耗。

Description

一种优化电特性的DMOS 技术领域
本实用新型属于半导体技术领域，具体涉及一种优化电特性的DMOS。
背景技术
DMOS是常用的功率器件，它与CMOS器件结构类似，也有源、漏、栅等电极，但是漏端击穿电压高。现有结构的DMOS在降低电容参数(如输入电容Ciss、输出电容Coss和米勒电容Crss)的同时将损失部分Rsp(单位面积电阻)，从而在优化开关损耗时，导通损耗有所增加，因此，限制了DMOS产品进一步优化。
实用新型内容
本实用新型解决的技术问题：提供一种优化电特性的DMOS。
技术方案：为了解决上述技术问题，本实用新型采用的技术方案如下：
本实用新型提供了一种优化电特性的DMOS，包括第一导电类型的衬底和设置在所述衬底上侧的外延层，所述外延层上设有第二导电类型的耐压环区和LTO沟槽，所述LTO沟槽内设有二氧化硅，且其四周的外延层上侧形成有JEFT区域，所述LTO沟槽四周的JEFT区域上侧长有栅氧化层，所述二氧化硅及其四周的栅氧化层上侧中部设有多晶栅，未被栅氧化层覆盖的JEFT区域内形成有第二导电类型的体区，所述栅氧化层四周下侧的体区由内向外依次设有第一导电类型有源区和第二导电类型有源区，所述多晶栅、栅氧化层和第一导电类型有源区的上侧淀积有SIN介质层，所述SIN介质层和外延层上侧沉淀有LTO介质层，所述LTO介质层上刻蚀有连接孔，所述LTO介质层上侧及连接孔内溅射形成有金属层，所述金属层经刻蚀形成DMOS的栅区和源区。
进一步的，二氧化硅为经过炉管湿法生长氧化层的方式形成和/或用于填充的LTO。
进一步的，LTO沟槽的宽度为0.5μm至2μm，且其深度为0.5μm至6μm。
进一步的，LTO沟槽的宽度为2μm，且其深度为4μm。
进一步的，金属层上侧沉积有钝化层，所述钝化层上侧刻蚀形成有栅极开口区和源极的开口区。
进一步的，衬底下侧设有背金层。
进一步的，栅氧化层的厚度为700-1200埃。
进一步的，SIN介质层的厚度为1000埃。
进一步的，LTO介质层的厚度为11000埃。
进一步的，钝化层的厚度为7000埃至12000埃。
有益效果：与现有技术相比，本实用新型具有以下优点：
1、本实用新型的DMOS在Rsp增加较小的前提下，大幅增加BVDSS和降低电容参数，优化其输出特性，降低工作损耗。
2、与现有工艺平台兼容，工艺实现简单且工艺窗口足够。
附图说明
图1是在外延层上制作LTO沟槽后的局部结构示意图；
图2是填充二氧化硅并形成JEFT区域后的局部结构示意图；
图3是形成多晶栅后的局部结构示意图；
图4是在JEFT区域内制作体区后的局部结构示意图；
图5是在体区内制作第一导电类型有源区后的局部结构示意图；
图6是淀积SIN介质层后的局部结构示意图；
图7是制作第二导电类型有源区、淀积LTO介质层并刻蚀形成连接孔后的局部结构示意图；
图8是溅射形成金属层后的局部结构示意图；
图9是沉积形成钝化层和蒸发形成背金层后的局部结构示意图；
图10是优化电特性的DMOS在LTO沟槽附近的电场分布随LTO沟槽的深度变化的仿真图；
图11是优化电特性的DMOS的漏源击穿电压随LTO沟槽的深度和宽度变化的仿真实验图；
图12是优化电特性的DMOS的单位面积电阻随LTO沟槽的深度和宽度变化的仿真实验图；
图13是优化电特性的DMOS的阈值随LTO沟槽的深度和宽度变化的仿真实验图；
图14是优化电特性的DMOS的输入电容随LTO沟槽的深度和宽度变化的仿真实验图；
图15是优化电特性的DMOS的输出电容随LTO沟槽的深度和宽度变化的仿真实验图；
图16是优化电特性的DMOS的米勒电容随LTO沟槽的深度和宽度变化的仿真实验图。
具体实施方式
下面结合具体实施例，进一步阐明本实用新型，实施例在以本实用新型技术方案为前提下进行实施，应理解这些实施例仅用于说明本实用新型而不用于限制本实用新型的范围。
如图1至9所示，本实用新型实施例提供一种优化电特性的DMOS的制造方法，包括：
如图1所示，提供第一导电类型的衬底1，并在衬底1上制作外延层2，在外延层2上制作第二导电类型的耐压环区。其中，衬底1为重掺杂，外延层2为第一导电类型轻掺杂。以下第一导电类型为N型，第二导电类型为P型为例进行阐述本实施例。衬底1一般采用N型(100)晶向，砷元素或锑元素掺杂，电阻率通常小于0.1Ω.cm。选择不同的外延电阻率和厚度，可得到不同的器件耐压，通常外延厚度：40-80um，外延电阻率：9-24Ω.cm，器件耐压可以达到500V-900V。耐压环区的具体制作工艺为：在外延层2上预生长一层800-1000埃的氧化层15作为Ring环注入的阻挡层，经过Ring光刻、注入和炉管退火工艺，形成高压终端结构。离子注入能量：100-140KeV，注入剂量：3E13-8E13，注入元素：硼(B)，退火条件：1180℃/300-500min。由于耐压环区及该区域的后续工艺和结构与现有技术相同，所以本实施例中未对该部分进行图示。
在外延层2上侧刻蚀形成LTO沟槽3，向LTO沟槽3内填满二氧化硅4。具体的，LTO沟槽3在氧化层15上侧经涂胶、光刻和干法刻蚀工艺形成。
如图2所示，对LTO沟槽3以外的外延层2上侧执行JEFT注入和JEFT推阱操作，以形成JEFT区域5。具体的，可在外延层2的表面注入一定浓度的磷元素，经过高温推阱工艺，在近外延层2表面3-6um区域形成JFET区域5，在不影响底部外延层耐压的同时，有效降低表面沟道电阻。注入剂量：2E12-5E12，注入能量：100KeV-150KeV，推阱条件：1150℃/120min-190min。
如图3所示，在制作好JEFT区域5后，需要先将氧化层15刻蚀掉，然后 在LTO沟槽3四周的外延层2上侧长栅氧化层6，并在二氧化硅4及其四周的栅氧化层6上侧中部沉积多晶，并将多晶刻蚀形成多晶栅7。具体而言，栅氧化层6厚度一般为700-1200埃，生长温度一般为900-1000℃，沉积多晶厚度为6000-8000埃，且多晶为重掺杂的多晶硅。多晶栅7由多晶经涂胶、光刻和干法刻蚀工艺形成，并在器件的终端区形成多晶场版结构，有效提高耐压效果。
如图4所示，远离所述LTO沟槽的所述JEFT区域内形成第二导电类型的体区，具体的工艺如下：注入B元素，注入能量60KeV～120KeV，注入剂量根据VTH参数的需求调整，通常1E13-8E13左右，体区推阱温度：1150℃，时间：100-200分钟。
如图5所示，在栅氧化层6四周下侧的体区8内制作第一导电类型有源区9(NSD)。具体的工艺如下：先在体区8上进行涂胶和光刻形成NSD的注入区，构成NSD注入剂量：5E15～1E16,注入能量：120KeV-160KeV，注入元素：磷。NSD推阱温度：950℃，时间：25分钟。
如图6所示，在多晶栅7、栅氧化层6和第一导电类型有源区9的上侧淀积SIN介质层10。SIN介质层10的厚度为1000埃左右即可，可有效改善器件可靠性。
如图7所示，在位于第一导电类型有源区9的四周体区8内制作第二导电类型有源区11(PSD)。具体工艺如下：先经涂胶和光刻形成PSD的注入区，构成PSD注入剂量：5E15～1E16,注入能量：120KeV-160KeV，注入元素：B。需要用RTA(快速退火950℃、30s)工艺激活注入原子。
在SIN介质层10的上侧淀积LTO介质层12。LTO介质层12采用沉积介质BPSG(硼磷硅玻璃)，优选厚度为11000埃。在LTO介质层12上刻蚀形成连接孔13。
如图8所示，在LTO介质层12上侧及连接孔13内溅射形成金属层14，并刻蚀形成DMOS的栅区和源区。溅射的金属优选采用铝，溅射铝的厚度优选4μm。
本实用新型实施例的二氧化硅4可以通经过炉管湿法生长氧化层的方式形成，一般工艺下生长氧化层的厚度为20000埃，在不需要场氧结构或者LTO沟槽3宽度较大导致氧化层不足以将LTO沟槽3填充满时，可使用LTO(Low Thermal Oxide-低温二氧化硅)进行填充。
结合图10至16，对于常用的单位元胞的尺寸为15μm的DMOS来说，图10是有无LTO沟槽3及不同槽深的电场分布图，沿LTO沟槽3中心位置垂直于X轴做剖面，增加LTO沟槽3后，DMOS的表面电场强度降低，可有效提高BVDSS，但随着槽深度增加，对DMOS体内电势线的影响增加，LTO沟槽3底部电势线曲率半径减小，BVDSS降低。图11至13为LTO沟槽3的深度(单位：微米)和宽度(1μm、2μm、3μm)与BVDSS(漏源击穿电压)、Rsp(单位面积电阻)和Vth(阈值)的对应关系图。其中，各电学参数均为不同工艺条件下的仿真结果。从结果来看，LTO沟槽3宽度在1um时，BVDSS、Rsp和Vth受LTO沟槽3深度增加的影响更小，且随着LTO沟槽3深度的增加，BVDSS先有一个抛物线上升阶段，再迅速下降，Rsp呈缓慢上升，Vth呈周期性波动。图14至16为LTO沟槽3深度和宽度与Ciss(输入电容)、Coss(输出电容)和Crss(米勒电容)的对应关系图，其中，各电学参数均为不同工艺条件下的仿真结果。Ciss与Vth表现相同，都呈现周期性波动，Coss和Crss都随着LTO沟槽3深度的增加而迅速降低，且相同的深度下，LTO沟槽3宽度越大电容值越小。因此，本实用新型实施例的LTO沟槽3的宽度为0.5μm至2μm，优选为2μm。LTO沟槽3的深度为0.5μm至6μm，优选为4μm。
如图9所示，还可以在金属层14的上侧设置钝化层16，钝化层16优选采用氮化硅沉积形成，钝化层16的厚度为7000埃至12000埃，然后在钝化层16上刻蚀出栅极开口区和源极开口区。
一般所采用的衬底1的原始厚度优选为625-675μm，当制作完毕后，需要将衬底1从下侧减小至器件所剩余厚度为200μm-300μm，以便于封装。还可在衬底1的下侧设有背金层17，背金层17优选依次蒸发Ti-Ni-Ag(钛-镍-银)形成。
基于以上实施例，本领域技术人员可以理解，本实用新型实施例还提供了一种优化电特性的DMOS，如图9所示，该DMOS包括第一导电类型的衬底1和设置在衬底1上侧的外延层2，其中，衬底1为重掺杂，外延层2为第一导电类型轻掺杂。以下第一导电类型为N型，第二导电类型为P型为例进行阐述本实施例。衬底1一般采用N型(100)晶向，砷元素或锑元素掺杂，电阻率通常小于0.1Ω.cm。选择不同的外延电阻率和厚度，可得到不同的器件耐压，通常外延厚度：40-80um，外延电阻率：9-24Ω.cm，器件耐压可以达到500V-900V。
外延层2上设有第二导电类型的耐压环区和LTO沟槽3。具体的，耐压环区的具体制作工艺为：在外延层2上预生长一层800-1000埃的氧化层作为Ring环注入的阻挡层，经过Ring光刻、注入和炉管退火工艺，形成高压终端结构。离子注入能量：100-140KeV，注入剂量：3E13-8E13，注入元素：硼(B)，退火条件：1180℃/300-500min。由于耐压环区及该区域的后续工艺和结构与现有技术相同，所以本实施例中未对该部分进行图示。LTO沟槽3在氧化层15上侧经涂胶、光刻和干法刻蚀工艺形成。LTO沟槽3内设有二氧化硅4，在LTO沟槽3四周的外延层2上侧形成有JEFT区域5。具体的，JEFT区域5经过JEFT注入和JEFT推阱操作形成。具体的，可在外延层2的表面注入一定浓度的磷元素，经过高温推阱工艺，在近外延层2表面3-6um区域形成JFET区域5，在不影响底部外延层耐压的同时，有效降低表面沟道电阻。注入剂量：2E12-5E12，注入能量：100KeV-150KeV，推阱条件：1150℃/120min-190min。
在制作好JEFT区域5后，需要先将氧化层15刻蚀掉，然后在LTO沟槽3四周的外延层2上侧长有栅氧化层6，在二氧化硅4及其四周的栅氧化层6的上侧中部沉积多晶，并将多晶刻蚀形成多晶栅7。具体而言，栅氧化层6厚度一般为700-1200埃，生长温度一般为900-1000℃，沉积多晶厚度为6000-8000埃，且多晶为未掺杂的多晶硅。多晶栅7由多晶经涂胶、光刻和干法刻蚀工艺形成，并在器件的终端区形成多晶场版结构，有效提高耐压效果。
远离所述LTO沟槽的所述JEFT区域内形成第二导电类型的体区，具体的，注入B元素，能量60KeV～120KeV，剂量根据VTH参数的需求调整，通常1E13-8E13左右，体区推阱温度：1150℃，时间：100-200分钟。
在栅氧化层6四周下侧的体区8由内向外依次设有第一导电类型有源区(NSD)9和第二导电类型有源区(PSD)11。具体的，先在体区8上进行涂胶和光刻形成NSD的注入区，构成NSD注入剂量：5E15～1E16,注入能量：120KeV-160KeV，注入元素：磷。NSD推阱温度：950℃，时间：25分钟。PSD的具体工艺如下：先经涂胶和光刻形成PSD的注入区，构成PSD注入剂量：5E15～1E16,注入能量：120KeV-160KeV，注入元素：B。需要用RTA(快速退火950℃、30s)工艺激活注入原子。在PSD制作之前，先在多晶栅7、栅氧化层6和第一导电类型有源区9的上侧淀积SIN介质层10。SIN介质层10的厚度 为1000埃左右即可，可有效改善器件可靠性。
在SIN介质层10上侧沉淀有LTO介质层12，LTO介质层12采用沉积介质BPSG(硼磷硅玻璃)，优选厚度为11000埃。LTO介质层12上刻蚀有连接孔13，LTO介质层12上侧及连接孔13内溅射形成金属层14，金属层14经刻蚀形成DMOS的栅区和源区。溅射的金属优选采用铝，溅射铝的厚度优选4μm。
本实用新型实施例的二氧化硅4可以通过炉管湿法生长氧化层的方式形成，一般工艺下生长氧化层的厚度为20000埃，在不需要场氧结构或者LTO沟槽3宽度较大导致氧化层不足以将LTO沟槽3填充满时，可使用LTO(Low Thermal Oxide-低温二氧化硅)进行填充。
结合图10至16，对于常用的单位元胞的尺寸为15μm的DMOS来说，图10是有无LTO沟槽3及不同槽深的电场分布图，沿LTO沟槽3中心位置垂直于X轴做剖面，增加LTO沟槽3后，DMOS的表面电场强度降低，可有效提高BVDSS，但随着槽深度增加，对DMOS体内电势线的影响增加，LTO沟槽3底部电势线曲率半径减小，BVDSS降低。图11至13为LTO沟槽3的深度(单位：微米)和宽度(1μm、2μm、3μm)与BVDSS(漏源击穿电压)、Rsp(单位面积电阻)和Vth(阈值)对应关系图。其中，各电学参数均为不同工艺条件下的仿真结果。从结果来看，LTO沟槽3宽度在1um时，BVDSS、Rsp和Vth随LTO沟槽3深度的增加的影响更小，且随着LTO沟槽3深度的增加，BVDSS先有一个抛物线上升阶段，再迅速下降，Rsp呈缓慢上升，Vth呈周期性波动。图14至16为LTO沟槽3深度和宽度与Ciss(输入电容)、Coss(输出电容)和Crss(米勒电容)对应关系图，其中，各电学参数均为不同工艺条件下的仿真结果。Ciss与Vth表现相同，都呈现周期性波动，Coss和Crss都随着LTO沟槽3深度的增加而迅速降低，且相同的深度下，LTO沟槽3宽度越大电容值越小。因此，本实用新型实施例的LTO沟槽3的宽度为0.5μm至2μm，优选为2μm。LTO沟槽3的深度为0.5μm至6μm，优选为4μm。
还可以在金属层14的上侧设置钝化层16，钝化层16优选采用氮化硅沉积形成，钝化层16的厚度为7000埃至12000埃，然后在钝化层上刻蚀出栅极开口区和源极开口区。
一般所采用的衬底1的原始厚度优选为625-675μm，当制作完毕后，需要将 衬底1从下侧减小至器件所剩余厚度为200μm-300μm，以便于封装。还可在衬底1的下侧设有背金层17，背金层17优选依次蒸发Ti-Ni-Ag(钛-镍-银)形成。
以上所述仅是本实用新型的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本实用新型原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本实用新型的保护范围。

Claims (10)

  1. 一种优化电特性的DMOS，包括第一导电类型的衬底和设置在所述衬底上侧的外延层，其特征在于，所述外延层上设有第二导电类型的耐压环区和LTO沟槽，所述LTO沟槽内设有二氧化硅，且其四周的外延层上侧形成有JEFT区域，所述LTO沟槽四周的JEFT区域上侧长有栅氧化层，所述二氧化硅及其四周的栅氧化层上侧中部设有多晶栅，远离所述LTO沟槽的所述JEFT区域内形成第二导电类型的体区，所述栅氧化层四周下侧的体区由内向外依次设有第一导电类型有源区和第二导电类型有源区，所述多晶栅、栅氧化层和第一导电类型有源区的上侧淀积有SIN介质层，所述SIN介质层上侧沉淀有LTO介质层，所述LTO介质层上刻蚀有连接孔，所述LTO介质层上侧及连接孔内溅射形成有金属层，所述金属层经刻蚀形成DMOS的栅区和源区。
  2. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述二氧化硅为经过炉管湿法生长氧化层的方式形成和/或用于填充的LTO。
  3. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述LTO沟槽的宽度为0.5μm至2μm，且其深度为0.5μm至6μm。
  4. 根据权利要求3所述的优化电特性的DMOS，其特征在于，所述LTO沟槽的宽度为2μm，且其深度为4μm。
  5. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述金属层上侧沉积有钝化层，所述钝化层上侧刻蚀形成有栅极开口区和源极开口区。
  6. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述衬底下侧设有背金层。
  7. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述栅氧化层的厚度为700-1200埃。
  8. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述SIN介质层的厚度为1000埃。
  9. 根据权利要求1所述的优化电特性的DMOS，其特征在于，所述LTO介质层的厚度为11000埃。
  10. 根据权利要求5所述的优化电特性的DMOS，其特征在于，所述钝化层的厚度为7000埃至12000埃。
PCT/CN2020/126044 2020-02-25 2020-11-03 一种优化电特性的dmos WO2021169381A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202020206878.1U CN211295110U (zh) 2020-02-25 2020-02-25 一种优化电特性的dmos
CN202020206878.1 2020-02-25

Publications (1)

Publication Number Publication Date
WO2021169381A1 true WO2021169381A1 (zh) 2021-09-02

Family

ID=72021422

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/126044 WO2021169381A1 (zh) 2020-02-25 2020-11-03 一种优化电特性的dmos

Country Status (2)

Country Link
CN (1) CN211295110U (zh)
WO (1) WO2021169381A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497604A (zh) * 2023-12-29 2024-02-02 深圳天狼芯半导体有限公司 一种改进型平面栅mosfet及制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN211295110U (zh) * 2020-02-25 2020-08-18 南京华瑞微集成电路有限公司 一种优化电特性的dmos

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140367771A1 (en) * 2013-06-18 2014-12-18 Monolith Semiconductor, Inc. High voltage semiconductor devices and methods of making the devices
CN104392932A (zh) * 2014-12-10 2015-03-04 中国电子科技集团公司第四十七研究所 一种vdmos器件及其制造方法
CN104952929A (zh) * 2015-07-02 2015-09-30 电子科技大学 一种碳化硅vdmos器件及其制作方法
CN110047930A (zh) * 2019-04-02 2019-07-23 芯兴(北京)半导体科技有限公司 Vdmos器件
CN211295110U (zh) * 2020-02-25 2020-08-18 南京华瑞微集成电路有限公司 一种优化电特性的dmos

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140367771A1 (en) * 2013-06-18 2014-12-18 Monolith Semiconductor, Inc. High voltage semiconductor devices and methods of making the devices
CN104392932A (zh) * 2014-12-10 2015-03-04 中国电子科技集团公司第四十七研究所 一种vdmos器件及其制造方法
CN104952929A (zh) * 2015-07-02 2015-09-30 电子科技大学 一种碳化硅vdmos器件及其制作方法
CN110047930A (zh) * 2019-04-02 2019-07-23 芯兴(北京)半导体科技有限公司 Vdmos器件
CN211295110U (zh) * 2020-02-25 2020-08-18 南京华瑞微集成电路有限公司 一种优化电特性的dmos

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497604A (zh) * 2023-12-29 2024-02-02 深圳天狼芯半导体有限公司 一种改进型平面栅mosfet及制备方法

Also Published As

Publication number Publication date
CN211295110U (zh) 2020-08-18

Similar Documents

Publication Publication Date Title
CN107275407B (zh) 一种碳化硅vdmos器件及其制作方法
TWI441336B (zh) 帶有減小的擊穿電壓的金屬氧化物半導體場效應管裝置
CN107248533B (zh) 一种碳化硅vdmos器件及其制作方法
US10680067B2 (en) Silicon carbide MOSFET device and method for manufacturing the same
KR20040033313A (ko) 셀 트렌치 게이트 전계 효과 트렌지스터 및 그 제조 방법
CN114122123B (zh) 集成高速续流二极管的碳化硅分离栅mosfet及制备方法
CN107464837B (zh) 一种超结功率器件
WO2021169381A1 (zh) 一种优化电特性的dmos
CN113571584A (zh) 一种SiC MOSFET器件及其制备方法
JP4990458B2 (ja) 自己整合されたシリコンカーバイトｌｍｏｓｆｅｔ
WO2021232806A1 (zh) 沟槽栅金属氧化物半导体场效应管及其制备方法
CN115799339A (zh) 一种屏蔽栅沟槽mosfet结构及其制造方法
CN115714141A (zh) JFET注入型N沟道SiC MOSFET器件及其制备方法
CN113851523A (zh) 一种屏蔽栅mosfet及制作方法
US20210134989A1 (en) Semiconductor device and method of manufacturing thereof
CN110676305A (zh) 具有低栅电荷特性的垂直沟道器件及制造方法
WO2023093132A1 (zh) Iegt结构及其制作方法
CN115810546A (zh) 一种具有高k介质的屏蔽栅沟槽MOSFET的制造方法
CN206697480U (zh) 一种p型多晶硅沟槽结构的肖特基二极管
CN113314592B (zh) 一种集成sbr的低损耗高压超结器件及其制备方法
US11444167B2 (en) Method of manufacturing trench type semiconductor device
CN110223959B (zh) 深浅沟槽的金属氧化物半导体场效应晶体管及其制备方法
CN111463282A (zh) 集成启动管和采样管的低压超结dmos结构及制备方法
CN110729196A (zh) 一种降低沟槽型金属氧化物半导体导通电阻的方法
CN113990928B (zh) 低击穿电压温度系数的Trench MOSFET器件及制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20921483

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20921483

Country of ref document: EP

Kind code of ref document: A1