CN110223959B - 深浅沟槽的金属氧化物半导体场效应晶体管及其制备方法 - Google Patents
深浅沟槽的金属氧化物半导体场效应晶体管及其制备方法 Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000005669 field effect Effects 0.000 title claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 9
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 20
- 230000000873 masking effect Effects 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000005360 phosphosilicate glass Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 2
- 238000001465 metallisation Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000007747 plating Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910017750 AgSn Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/8232—Field-effect technology
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- H01L27/0883—Combination of depletion and enhancement field effect transistors
Abstract
本发明公开深浅沟槽的金属氧化物半导体场效应晶体管及其制备方法,深浅沟槽的金属氧化物半导体场效应晶体管包括垂直相交的深沟槽和浅沟槽,深沟槽和浅沟槽侧壁和底部均生长有一层氧化层,内部填充有多晶硅。本发明提出了一种立体的三维结构来实现高击穿电压,低开启电压的特性。包括垂直相交的深浅沟槽,整个沟槽制备过程无需增加光刻板以及多次淀积、刻蚀去实现沟槽内部复杂的构造,制备流程更简洁,工艺更易控制。
Description
技术领域
本发明涉及半导体领域,更确切地说是深浅沟槽的金属氧化物半导体场效应晶体管的制备方法。
背景技术
现有技术为了达到低的开启电压,高的击穿电压的结构,通常分为两种结构。一种是底部厚栅氧上半部分薄栅氧的沟槽结构,另一种是分栅结构。这两种结构的沟槽内部形貌都相对比较复杂,制备工艺较为繁琐,不易控制,降低了器件制备效率。
发明内容
本发明的目的是提供深浅沟槽的金属氧化物半导体场效应晶体管的制备方法,其可以解决现有技术中的上述缺点。
本发明采用以下技术方案:
深浅沟槽的金属氧化物半导体场效应晶体管的制备方法,包括以下步骤:
外延圆片由低电阻率的基片和外延层组成;
在外延层上生长一层掩蔽层;
进行沟槽光刻,并对掩蔽层进行刻蚀,刻蚀出沟槽刻蚀窗口;
去除光刻胶,进行深沟槽刻蚀,在掩蔽层的掩蔽作用下形成较深的沟槽,此深沟槽深度需远深于沟道区深度;
去除掩蔽层,进行牺牲氧化,并去掉氧化层;生长较厚的氧化层,淀积绝缘介质层,将沟槽以及硅表面填充满;
淀积一层光刻胶,并在与深沟槽垂直的方向刻蚀出浅沟槽刻蚀窗口;
去除光刻胶,进行浅沟槽刻蚀;
在浅沟槽底部以及侧壁生长出一层较薄的氧化层;
去除介质层,将淀积在表面以及深沟槽内部的介质层刻蚀掉;
淀积重掺杂多晶硅,填充满深浅沟槽内部;
刻蚀掉多余的多晶硅,使多晶硅表面与源区表面相平,即源区表面的多晶硅被刻蚀掉,但沟槽内的多晶硅保留,形成MOSFET的栅极。
还包括以下步骤:
在表面淀积一层氧化层,并刻蚀,氧化层表面预留厚度在100~300A;
进行沟道注入区光刻、注入,去除光刻胶,通过离子注入方式注入P型杂质离子,加热退火形成到期望的沟道区杂质分布;
进行源区光刻、注入,去除光刻胶。通过离子注入的方式注入高浓度N型杂质离子,并进行退火,激活杂质,形成源极。
还包括以下步骤:
淀积介质层,通常材料为磷硅玻璃;
淀积光刻胶,进行接触孔光刻;
去除光刻胶,进行接触孔刻蚀并注入,再进行退火;
淀积金属,并刻蚀表面多余金属。
还包括以下步骤:
减薄芯片背面,通过化学镀层的方式镀上金属层,形成器件漏极。
还包括以下步骤:金属层为TiNiAg或AgSn或Au中的任意一种。
掩蔽层材料的成分可以为氧化硅、氮化硅或者两者结合。
介质层通常为SiN。
深浅沟槽的金属氧化物半导体场效应晶体管,其通过上述方法制备得到。
包括垂直相交的深沟槽和浅沟槽,深沟槽和浅沟槽侧壁和底部均生长有一层栅氧化层,内部填充有多晶硅,且深沟槽内部的第一栅氧化层的厚度厚于浅沟槽内部的第二栅氧化层的厚度。
深沟槽和浅沟槽均设于外延圆片内部,且外延圆片由低电阻率的基片和外延层组成,外延层的电阻率根据实际需要进行选择。
深沟槽内部的栅氧化层的厚度厚于浅沟槽内部栅氧化物层的厚度。
深沟槽和浅沟槽之间的外延层上淀设有氧化物层,且外延层内部设有沟道区注入层和源区注入层。
氧化物层上还淀设有一介质层。
所述深沟槽和浅沟槽之间还设有接触孔,接触孔的底部设有接触孔注入层,且接触孔注入层设于沟道区注入层内部。
介质层的外侧及接触孔内部淀设金属层。
基片的背面设有金属镀层,形成漏极。
本发明的优点是:本发明提出了一种立体的三维结构来实现高击穿电压,低开启电压的特性;包括垂直相交的深浅沟槽,整个沟槽制备过程无需增加光刻板以及多次淀积、刻蚀去实现沟槽内部复杂的构造,制备流程更简洁,工艺更易控制。
附图说明
下面结合实施例和附图对本发明进行详细说明,其中:
图1至图34是本发明的制备方法的流程示意图。
图35是本发明的结构示意图。
图36是本发明的单个元胞俯视图。
图37是本发明的施加反向电压时X方向耗尽层分布示意图。
具体实施方式
下面进一步阐述本发明的具体实施方式:
如图1至图34所示,本发明公开了本发明通过两次沟槽刻蚀,在整个圆片上形成横纵相交的深沟槽和浅沟槽,沟槽内分别生长厚栅氧和薄栅氧,薄栅氧的浅沟槽保证了较低的开启电压,厚栅氧的深沟槽提供了较高的击穿电压。
本发明中的浅沟槽深度通常为0.5~2um,深沟槽厚度通常为2~10um,根据实际产品参数决定。
深沟槽与浅沟槽除了刻蚀深度以及栅氧化层厚度不同外,沟槽刻蚀宽度、间距均保持相同。
将深沟槽刻蚀方向定义为x方向,浅沟槽方向定义为y方向,x方向与y方向互相垂直。
本发明整个元胞的具体制备工艺步骤如下:(x方向/y方向表示该截面图的方向):
根据MOSFET的特性需求选择合适的外延圆片,该圆片由低电阻率的基片1和外延层2组成,如图1所示;
在外延层2上生长一层掩蔽层3,该掩蔽层3的作用是为后面的沟槽刻蚀提供掩蔽,掩蔽层材料的成分可以为氧化硅、氮化硅或者两者结合,在掩蔽层的外侧淀积光刻胶4,如图2~3所示,为x方向);
进行沟槽光刻,并对掩蔽层进行刻蚀,刻蚀出沟槽刻蚀窗口5,如图4所示,x方向;
去除光刻胶,进行深沟槽6刻蚀,在掩蔽层的掩蔽作用下形成较深的沟槽,此深沟槽深度需远深于沟道区深度,如图5所示,x方向;
去除掩蔽层,进行牺牲氧化,并去掉氧化层。牺牲氧化层一般生长为500A左右,主要作用是为了去除表面的杂质,如图6所示,x方向;
生长较厚的氧化层7,通常为干法生长,在沟槽侧壁、底部以及圆片表生长出一层第一栅氧化层,如图7所示,x方向,第一栅氧化层的厚度为通常为1000A~6000A,具体厚度根据实际产品参数决定;
淀积绝缘介质层8,将沟槽以及硅表面填充满,该介质层通常可用SiN,如图8所示,x方向;
淀积一层光刻胶9,并在与深沟槽垂直的方向刻蚀出浅沟槽刻蚀窗口。如图9所示,x方向,如图10所示,y方向,图9为深沟槽结构截面图,图10为与深沟槽垂直方向的浅沟槽方向的结构截面图。
去除光刻胶,进行浅沟槽10刻蚀,如图11所示,y方向;
在浅沟槽底部以及侧壁生长出一层较薄的第二栅氧化层11,如图12所示,y方向,第二栅氧化层厚度为200A~400A,具体厚度根据实际产品参数决定;
去除介质层,将淀积在表面以及深沟槽内部的介质层刻蚀掉,如图13所示,y方向,图14 x方向;
淀积重掺杂多晶硅12,填充满深浅沟槽内部,如图15所示,y方向,图16所示,x方向;
刻蚀掉多余的多晶硅,使多晶硅表面与源区表面相平,即源区表面的多晶硅被刻蚀掉,但沟槽内的多晶硅保留,形成MOSFET的栅极,如图17所示,y方向,如图18所示x方向;
在表面淀积一层氧化层13,并刻蚀,氧化层表面预留厚度在100~300A左右,如图19所示y方向,如图20所示x方向);
进行沟道注入区14光刻、注入,去除光刻胶。通过离子注入方式注入P型杂质离子,加热退火形成到期望的沟道区杂质分布,如图21所示y方向,如图22所示x方向;
进行源区光刻、注入,去除光刻胶,形成源区注入层15。通过离子注入的方式注入高浓度N型杂质离子,并进行退火,激活杂质,形成源极,如图23所示y方向,如图24所示x方向。
淀积介质层16,通常材料为磷硅玻璃,如图25所示y方向,如图26所示x方向;
淀积光刻胶,进行接触孔18光刻,如图27所示y方向,如图28所示x方向,
去除光刻胶,进行接触孔刻蚀并注入形成接触孔注入层19,再进行退火,如图29所示y方向,如图30所示x方向。
淀积金属20,并刻蚀表面多余金属,通常金属材料为钨,如图31所示y方向,如图32所示x方向;
背面金属镀层21,根据实际需求减薄芯片背面,通过化学镀层的方式镀上金属层,此金属层一般为TiNiAg或AgSn或Au,厚度一般为几个微米,形成器件漏极,如图33所示y方向,如图34所示x方向。
整个元胞区的制备流程如上述所述,该流程不涉及终端区的制备,但可与常规MOS终端制备流程兼容。其中相关的淀积,注入,刻蚀、退火参数均为常规工艺流程,根据实际具体参数需求可进行调整。
如图35、36所示,深浅沟槽的金属氧化物半导体场效应晶体管,通过上述方法制备得到,包括垂直相交的深沟槽6和浅沟槽10,深沟槽6和浅沟槽10侧壁和底部均生长有一层栅氧化层,内部填充有多晶硅12,且深沟槽内部的第一栅氧化层7的厚度厚于浅沟槽内部的第二栅氧化层11的厚度。深沟槽6和浅沟槽10均设于外延圆片内部,且外延圆片由低电阻率的基片1和外延层2组成,深沟槽和浅沟槽设于外延层内部。
深沟槽和浅沟槽之间的外延层上淀设有氧化层13,且外延层内部设有沟道区注入层14和源区注入层15。氧化层13上还淀设有一介质层16。所述深沟槽和浅沟槽之间还设有接触孔18,接触孔18的底部设有接触孔注入层19,且接触孔注入层19设于沟道区注入层内部。介质层16的外侧及接触孔18内部淀设金属层。基片的背面设有金属镀层21,形成漏极。
本发明的深浅沟槽的金属氧化物半导体场效应晶体管通过深沟槽和浅沟槽垂直相交,浅沟槽底部和侧壁生长有相对较薄的栅氧化层,深沟槽底部和侧壁生长相对较厚的栅氧化层。当时施加正向电压时,浅沟槽更薄的栅氧使器件更易开启,提供了更低的开启电压;当施加反向电压时,相邻深沟槽和较厚的栅氧使载流子在浅沟槽下部区域耗尽并保证了更高的击穿电压。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.深浅沟槽的金属氧化物半导体场效应晶体管的制备方法,其特征在于,包括以下步骤:外延圆片由低电阻率的基片和外延层组成;
在外延层上生长一层掩蔽层;
进行沟槽光刻,并对掩蔽层进行刻蚀,刻蚀出沟槽刻蚀窗口;
去除光刻胶,进行深沟槽刻蚀,在掩蔽层的掩蔽作用下形成较深的沟槽,此深沟槽深度需远深于沟道区深度;
去除掩蔽层,进行牺牲氧化,并去掉氧化层;生长第一栅氧化层,淀积绝缘介质层,将沟槽以及硅表面填充满;
淀积一层光刻胶,并在与深沟槽垂直的方向刻蚀出浅沟槽刻蚀窗口;
去除光刻胶,进行浅沟槽刻蚀;
在浅沟槽底部以及侧壁生长出一层第二栅氧化层;
去除介质层,将淀积在表面以及深沟槽内部的介质层刻蚀掉;
淀积重掺杂多晶硅,填充满深浅沟槽内部;
刻蚀掉多余的多晶硅,使多晶硅表面与源区表面相平,即源区表面的多晶硅被刻蚀掉,但沟槽内的多晶硅保留,形成MOSFET的栅极。
2.根据权利要求1所述的深浅沟槽的金属氧化物半导体场效应晶体管的制备方法,其特征在于,还包括以下步骤:
在表面淀积一层氧化层,并刻蚀,氧化层表面预留厚度在100~300A;
进行沟道注入区光刻、注入,去除光刻胶,通过离子注入方式注入P型杂质离子,加热退火形成到期望的沟道区杂质分布;
进行源区光刻、注入,去除光刻胶;通过离子注入的方式注入高浓度N型杂质离子,并进行退火,激活杂质,形成源极。
3.根据权利要求2所述的深浅沟槽的金属氧化物半导体场效应晶体管的制备方法,其特征在于,还包括以下步骤:
淀积介质层,材料为磷硅玻璃;
淀积光刻胶,进行接触孔光刻;
去除光刻胶,进行接触孔刻蚀并注入,再进行退火;
淀积金属,并刻蚀表面多余金属。
4.深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,通过如权利要求1至3中任意一项的方法制备得到,包括垂直相交的深沟槽和浅沟槽,深沟槽和浅沟槽侧壁和底部均生长有一层栅氧化层,内部填充有多晶硅,且深沟槽内部的第一栅氧化层的厚度厚于浅沟槽内部的第二栅氧化层的厚度。
5.根据权利要求4所述的深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,深沟槽和浅沟槽均设于外延圆片内部,且外延圆片由低电阻率的基片和外延层组成。
6.根据权利要求5所述的深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,深沟槽和浅沟槽之间的外延层上淀设有氧化物层,且外延层内部设有沟道区注入层和源区注入层。
7.根据权利要求6所述的深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,氧化物层上还淀设有一介质层。
8.根据权利要求7所述的深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,所述深沟槽和浅沟槽之间还设有接触孔,接触孔的底部设有接触孔注入层,且接触孔注入层设于沟道区注入层内部。
9.根据权利要求8所述的深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,介质层的外侧及接触孔内部淀设金属层。
10.根据权利要求9所述的深浅沟槽的金属氧化物半导体场效应晶体管,其特征在于,基片的背面设有金属镀层,形成漏极。
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