JP5500898B2 - トレンチゲート電極を有する金属−絶縁体−半導体デバイスの製造方法 - Google Patents
トレンチゲート電極を有する金属−絶縁体−半導体デバイスの製造方法 Download PDFInfo
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- JP5500898B2 JP5500898B2 JP2009175470A JP2009175470A JP5500898B2 JP 5500898 B2 JP5500898 B2 JP 5500898B2 JP 2009175470 A JP2009175470 A JP 2009175470A JP 2009175470 A JP2009175470 A JP 2009175470A JP 5500898 B2 JP5500898 B2 JP 5500898B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 16
- 210000000746 body region Anatomy 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 3
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000012212 insulator Substances 0.000 description 16
- 239000004020 conductor Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/0873—Drain regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
絶縁層416は、一般にドライエッチングを用いてエッチングされ、これにより、図4Kに示されるように、p型本体領域412およびN+ソース領域411の一部が露出する。
一般に堆積された(例えば、物理気相成長法、メッキ、スパッタリング、または、蒸発によって)金属または金属合金である導体417を用いて、本体領域412およびソース領域411への電気接点が形成される。ゲート414への電気接点は、図4Kの面の外側に3次元的に形成される。ドレイン(図示せず)への電気接点は、N+基板(図示せず)のN−エピタキシャル層413が成長した面とは反対側の面に形成される。
MOSFET50は、多くの点で図3のMOSFET30と類似している。特に、トレンチ19の側壁だけに沿って薄いゲート絶縁体15が延び、一方、厚い絶縁層31がトレンチ19の底部に沿って延在している。図3のMOSFET30においては、トレンチ19の底部で積層中に広がる抵抗が増大することに起因して、厚い絶縁層31がMOSFET30のオン抵抗(Ron)を大きくする可能性がある。しかし、図5のMOSFET50は、電流がより効果的に拡散することを助ける高ドーピング領域53をトレンチ19の底部に有している。高ドーピング領域53は、N+基板55上にあるN−エピタキシャル層13中に形成されている。高ドーピング領域53は、図4Aに示されるようにトレンチがエッチングされた後、マスク450が除去される前に、ヒ素またはリン等のn型ドーパントを注入することにより形成されても良い。このように、厚い絶縁層31がゲート−ドレイン間キャパシタンスCgdを最小限に抑えるとともに、高ドーピング領域53がオン抵抗(Ron)を最小にすることで、高周波の用途に十分適したトレンチMOSFET50が形成される。
Claims (11)
- a)半導体基板を準備する工程、
b)側壁と底部とを有するトレンチを前記基板中に形成する工程、
c)少なくとも前記トレンチの前記底部に隣接して前記基板中に高度にドープされた領域を形成する工程、
d)前記トレンチの前記側壁上及び前記底部上に厚い絶縁層を堆積させる工程、
e)窒化ケイ素のバリア層を堆積させて前記トレンチを溢れさせる工程、
f)前記バリア層に対する高い選択性と前記厚い絶縁層に対する低い選択性を有する第1のエッチング剤を用いて、前記バリア層をエッチングすることにより、前記トレンチの前記底部に前記バリア層の一部を残す工程、
g)前記厚い絶縁層に対する高い選択性と前記バリア層に対する低い選択性を有する第2のエッチング剤を用いて、前記厚い絶縁層をエッチングすることにより、前記側壁の露出部を形成する工程、
h)前記トレンチの前記底部の前記厚い絶縁層の一部は残して、前記工程f)でトレンチの底部に残されたバリア層を除去する工程、
i)前記側壁の前記露出部上に、前記トレンチの前記底部の前記厚い絶縁層の一部に接続した薄い絶縁層を形成する工程、
j)前記厚い絶縁層の上側に、前記トレンチ内の前記薄い絶縁層に隣接して、ゲートを形成する工程、
k)前記基板中に前記側壁に隣接して本体領域を形成し、前記基板中に該本体領域の下にドレイン領域を形成する工程、及び、
l)前記本体領域中に前記側壁と前記基板の上面とに隣接してソース領域を形成する工程、
を有する金属−絶縁体−半導体デバイスの製造方法。 - 前記薄い絶縁層を形成する工程i)は、前記側壁を熱酸化する工程を含むことを特徴とする請求項1に記載の方法。
- 前記薄い絶縁層を形成する工程i)の直前に、前記側壁上に薄い犠牲酸化膜を成長させる工程と、前記犠牲酸化膜を除去する工程を更に含むことを特徴とする請求項2に記載の方法。
- 前記ゲートを形成する工程j)は、ドープしたポリシリコンを前記トレンチ内に堆積させる工程と、前記ドープしたポリシリコンを前記基板の表面とほぼ等しい高さまでエッチングする工程とを含むことを特徴とする請求項1に記載の方法。
- 前記窒化ケイ素バリア層が、化学気相成長法によって堆積させられ、且つ、2〜4μmの厚さを有することを特徴とする請求項1に記載の方法。
- 前記バリア層のエッチング工程f)が、ドライエッチングの後にウェットエッチングを行う工程を含むことを特徴とする請求項1に記載の方法。
- 前記工程f)におけるバリア層のエッチング完了時において、前記トレンチの底部に、0.1〜0.2μmの前記バリア層が残っていることを特徴とする請求項1に記載の方法。
- 前記厚い絶縁層が、0.1〜0.3μmの範囲の厚さを有することを特徴とする請求項1に記載の方法。
- 前記薄い絶縁層が、100〜1000Åの範囲の厚さを有することを特徴とする請求項1に記載の方法。
- 前記トレンチが、0.5〜1.2μmの範囲の幅及び1〜2μmの範囲の深さを有することを特徴とする請求項1に記載の方法。
- 前記バリア層がフォトレジストでないことを特徴とする請求項1に記載の方法。
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US09/927,320 | 2001-08-10 | ||
US09/927,320 US6882000B2 (en) | 2001-08-10 | 2001-08-10 | Trench MIS device with reduced gate-to-drain capacitance |
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JP2009175470A Expired - Lifetime JP5500898B2 (ja) | 2001-08-10 | 2009-07-28 | トレンチゲート電極を有する金属−絶縁体−半導体デバイスの製造方法 |
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JP (2) | JP2004538648A (ja) |
KR (1) | KR100624683B1 (ja) |
TW (1) | TW552680B (ja) |
WO (1) | WO2003015179A2 (ja) |
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US6882000B2 (en) * | 2001-08-10 | 2005-04-19 | Siliconix Incorporated | Trench MIS device with reduced gate-to-drain capacitance |
AU2002355547A1 (en) * | 2001-08-10 | 2003-02-24 | Siliconix Incorporated | Mis device having a trench gate electrode and method of making the same |
US6781196B2 (en) * | 2002-03-11 | 2004-08-24 | General Semiconductor, Inc. | Trench DMOS transistor having improved trench structure |
US6838722B2 (en) * | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US8080459B2 (en) * | 2002-09-24 | 2011-12-20 | Vishay-Siliconix | Self aligned contact in a semiconductor device and method of fabricating the same |
US8629019B2 (en) * | 2002-09-24 | 2014-01-14 | Vishay-Siliconix | Method of forming self aligned contacts for a power MOSFET |
US7279743B2 (en) * | 2003-12-02 | 2007-10-09 | Vishay-Siliconix | Closed cell trench metal-oxide-semiconductor field effect transistor |
US8183629B2 (en) * | 2004-05-13 | 2012-05-22 | Vishay-Siliconix | Stacked trench metal-oxide-semiconductor field effect transistor device |
JP2006030318A (ja) * | 2004-07-12 | 2006-02-02 | Sanyo Electric Co Ltd | 表示装置 |
US7494876B1 (en) | 2005-04-21 | 2009-02-24 | Vishay Siliconix | Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same |
EP1742257B1 (en) * | 2005-07-08 | 2012-09-05 | STMicroelectronics Srl | Method of manufacturing a semiconductor power device |
US9111754B2 (en) * | 2005-07-26 | 2015-08-18 | Vishay-Siliconix | Floating gate structure with high electrostatic discharge performance |
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-
2001
- 2001-08-10 US US09/927,320 patent/US6882000B2/en not_active Expired - Lifetime
-
2002
- 2002-07-19 WO PCT/US2002/022937 patent/WO2003015179A2/en not_active Application Discontinuation
- 2002-07-19 EP EP02750165A patent/EP1417717A2/en not_active Ceased
- 2002-07-19 JP JP2003520004A patent/JP2004538648A/ja active Pending
- 2002-07-19 KR KR1020047002073A patent/KR100624683B1/ko active IP Right Grant
- 2002-07-26 TW TW091116779A patent/TW552680B/zh not_active IP Right Cessation
- 2002-10-03 US US10/264,816 patent/US6921697B2/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
---|---|
US6882000B2 (en) | 2005-04-19 |
TW552680B (en) | 2003-09-11 |
JP2009283969A (ja) | 2009-12-03 |
WO2003015179A2 (en) | 2003-02-20 |
US20030030092A1 (en) | 2003-02-13 |
JP2004538648A (ja) | 2004-12-24 |
US20030062570A1 (en) | 2003-04-03 |
WO2003015179A3 (en) | 2003-12-04 |
KR100624683B1 (ko) | 2006-09-19 |
US6921697B2 (en) | 2005-07-26 |
EP1417717A2 (en) | 2004-05-12 |
KR20040051584A (ko) | 2004-06-18 |
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