TWI550851B - 具有平面狀通道的垂直功率金氧半場效電晶體 - Google Patents

具有平面狀通道的垂直功率金氧半場效電晶體 Download PDF

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TWI550851B
TWI550851B TW104103811A TW104103811A TWI550851B TW I550851 B TWI550851 B TW I550851B TW 104103811 A TW104103811 A TW 104103811A TW 104103811 A TW104103811 A TW 104103811A TW I550851 B TWI550851 B TW I550851B
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layer
transistor
gate
portion
conductivity type
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TW104103811A
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TW201535712A (zh
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軍 曾
恩達維希 穆罕默德
蒲奎
蘇世宗
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馬克斯半導體股份有限公司
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions

Description

具有平面狀通道的垂直功率金氧半場效電晶體

本發明關於功率金氧半場效電晶體(於下文中稱作為MOSFET),尤指具有一平面狀DMOS部與一垂直導電部的一垂直超級接面MOSFET。

本申請案主張的優先權為在2014年2月4日由Jun Zeng等向美國智慧財產局所提出的申請案,其申請案號為61/935,707,在此併入其全部參考內容。

垂直MOSFET作為高電壓且高功率之電晶體係受歡迎的,係由於能夠提供一厚的且低摻雜濃度的漂移層,以達到於該關閉狀態中之一高崩潰電壓。通常,該MOSFET包括高摻雜之一N型基板、厚且低摻雜濃度之一N型漂移層、靠合於該漂移層的一P型主體層、於該主體層頂部的一N型源極以及藉由薄的一閘極氧化物而自該主體區分開的一閘極。其通常提供一垂直凹槽閘極。一源極電極被形成於該頂面,並且一汲極電極被形成於該底面。當該閘極對於該源極來說係足夠正時,該N型源極與該N型漂移層之間的P型主體之通道區,係反向並創造在源極與汲極之間的一垂直導電路徑。

於該裝置係為關閉狀態中,當該閘極係與該源極為短路或為負時,於該源極與汲極之間的漂移層消耗及大的崩潰電壓(例如超過600伏特)能被持續。然而,由於厚的漂移層所需要之低摻雜,係使得該開啟電阻變差。增加 該漂移層之摻雜會減少該開啟電阻,但是會降低該崩潰電壓。

形成延伸至該基板的交替P型矽與N型矽之垂直縱列,以取代單一N型漂移層係為習知技術,其中該等縱列中之電荷被平衡,且當該MOSFET被關閉時,於一高電壓之P型縱列與N型縱列完全地消耗。其被稱為一超級接面(super junction)。於此配置中,該N型縱列的摻雜濃度可高於習知N型漂移層的摻雜濃度。其結果,於相同的崩潰電壓下開啟電阻能被減少。一超級接面MOSFET能藉由一多重磊晶生長與植入製程來被形成。形成延伸至該基板之厚且交替的P型縱列與N型縱列係需要多次的循環,該循環係為磊晶生長該縱列厚度的一部分,然後遮蔽並植入該P型摻雜與該N型摻雜,然後長出更多之縱列厚度並重複該遮蔽與植入製程。植入步驟的數量可能超過20次,係取決於該厚度。在每一植入循環之間,由於高的製程溫度,該等摻雜會產生不期望的橫向擴散。其大幅地增加了胞陣列中所需要的胞間距,使得該晶粒變更大。其結果,該MOSFET係不理想地被形成,且製程非常耗時。

另外,一超級接面可藉由一P型延伸層再填充之N型矽中蝕刻深的凹槽來被形成。該等凹槽必須為深的,係使得其為足夠長的一垂直漂移層,以於一高崩潰電壓中作為一空乏區。形成深的凹槽係耗時,因此成本昂貴。

該等功率MOSFET被形成具有大數量之相同的平行胞。該等裝置之間的任何變化可能造成於該MOSFET上發生不均勻的電流與溫度,會減少其效率與崩潰電壓。

一功率MOSFET所需要的是,不具有上述習知技術的缺點與限制。

於一實施例中,一MOSFET被形成具有用於一橫向電流流動的一平面狀通道區,以及用於一垂直電流流動的一垂直導電路徑。

於一實施例中,一P井(一主體區)被形成於一N型層,其具有形成於該N型層的一凹槽且該凹槽係深於該P井,以產生該N型層的側壁。該N型層相較於該MOSFET中的N型漂移層具有更高的摻雜。該MOSEFT包括藉由一導電材料(例如,摻雜的多晶矽)所形成的一遮蔽垂直場平面,該導電材料以一介電材料(例如,氧化物)填充該凹槽並且自該等側壁絕緣。一P遮罩層被形成於該凹槽的底部並且靠合於該側壁的底部。該P遮罩層亦靠合於一P縱列的頂部。一N縱列係位於該通道區下方且橫向地靠合於該P縱列。為了低的開啟電阻,該等N縱列與P縱列係為相對地高摻雜。該凹槽場平面係較深於該P井,以提供於該N-層中一有效電場之減少。當該MOSFET係關閉時,該場平面與該P遮罩有助於橫向地消耗該N-層,為了低的開啟電阻而允許該N-層係為相對地高摻雜。該凹槽場平面、該P遮罩、該N型層、減少厚度的一N型漂移層以及相對地高摻雜的N縱列與P縱列的綜合效應,係提供了增加的一崩潰電壓、較低的開啟電阻以及每一晶粒較低的成本。為了更快速的切換,該導電場平面電極能夠被連接至該閘極電極或是該源極電極,以提供較低的閘極-汲極電容。

每一單元區域之較低的開啟電阻,允許於每一晶圓上形成更多的晶粒。

於一較佳實施例中之場平面凹槽的深度,其為絕緣材料的厚度,該N型層的摻雜與厚度以及該P遮罩的摻雜與深度係被選擇來使得該N層於該崩潰電壓處完全地被消耗。此外,該P縱列與該N縱列的摻雜、深度與寬度係 使得該P縱列與該N縱列於該崩潰電壓處完全地被消耗。

於一實施例中,一功率MOSFET包括具有低摻雜濃度之第一N型層(該漂移層)的一高摻雜之N型基板,係大約30微米厚,並由該基板上磊晶生長。該第一N型層相較於習知漂移層更薄,係由於其不需要在該關閉狀態中維持整個源極-汲極電壓。

該第一N型層被遮蔽並植入摻雜以形成大約4微米厚之交替的P型區與N型區,其被稱為縱列。於該N型縱列中的N型摻雜濃度相較於該N型漂移層中的摻雜濃度更高。於一實施例中,對每一類型摻雜僅需要使用一次的植入來形成該等縱列,係由於該縱列層相較於習知技術的縱列層更薄。因此,相較於習知技術,其具有更少的橫向擴散使得該等縱列更為理想。

於該縱列層上方形成一第二N型層(例如8微米厚),其具有相較於該第一N型層之摻雜濃度更高的一摻雜濃度。

其中該第二N型層被形成一P井,且該P井被形成於該表面的一N型源極區。該源極區與該第二N型層的頂部之間的p井的頂面,係形成沿著該裝置之頂面的一橫向通道。

於該等胞的每一者中,一凹槽被蝕刻於在該等P井之間的第二N型層中,並且該凹槽相較於該等P井更深。然後,薄的一閘極介電質被形成於頂部的橫向通道上方並沿著該凹槽的側壁。然後,一多晶矽閘極被形成於頂部的通道上方並沿著該凹槽的垂直側壁,以使該多晶矽閘極的深度較深於該P井。自該通道與該側壁分開閘極的介電層,係可具有相同厚度或不同厚度而有不同的優點。該凹槽場平面導致了較低的一電場與較高的一崩潰電壓,其允許該第二N型層之摻雜增加而使該開啟電阻降低。

金屬的一源極電極接觸該P井與該等源極區,並且金屬的一汲極電極接觸該基板的底面。

於一另一實施例中,藉由單一或是多重高能量植入而形成P遮罩的相同步驟期間,該等P縱列可被形成。

於一例子中,一負載被耦合於該源極電極與地之間,並且一正電壓被施加於該汲極。當該閘極相對於該源極電極被足夠地正偏壓時,該源極區與該第二N型層之間的頂部之橫向通道反向,並且電子沿著該第二N型層中之凹槽的垂直側壁來累積。此電子的橫向與垂直累積係於該通道下方形成該源極與該N型縱列之間的一低電阻路徑。然後,該N型縱列與第一N型層完成了至該汲極電極的垂直導電路徑。

由於該通道與該汲極電極之間沒有厚的且低摻雜濃度的漂移區,每一單元區域之開啟電阻(特別是開啟電阻Ron*Area)相較於習知的垂直功率MOSFET之開啟電阻會更低。該開啟電阻較低的部份原因,是因為使用高摻雜濃度之N縱列與第二N型層(係如同該第二N型層之較高的摻雜),其中該第二N型層之較高摻雜係藉由該凹槽場平面效應、該P遮罩、及當該閘極被正偏壓時沿著該第二N型層之垂直側壁電子累積而被致能。於一實施例中特定之開啟電阻達到4.5Ohms-mm2,其大約為習知功率MOSFET的一半。

由於每一單元區域中如此低的開啟電壓,該晶粒的尺寸相較於習知晶粒的尺寸可更小,以在每一晶粒具有相同開啟電阻的情況下使每一晶圓之晶粒數量加倍。

在該MOSFET的關閉狀態,且一源極-汲極電壓相較於該崩潰電壓稍微低時,該第一N型層、該等縱列與該第二N型層完全地消耗。該崩潰電 壓可相同於具有相同厚度之習知的垂直MOSFET,但是該開啟電阻較小。相反地,該崩潰電壓可藉由形成較厚的層來被增加而高於習知技術的崩潰電壓,同時該開啟電阻可與習知技術相同。此外,由於較薄的縱列層與較淺的凹槽,形成垂直MOSFET的製程複雜度係低於習知技術之具有超級接面的垂直MOSFET之製程複雜度。

該MOSFET中之PN二極體被偏壓開啟之後,該MOSFET結構亦可降低該回復時間。若該MOSFET以一交流電壓來被使用,當該汲極較該源極更負時,該二極體將會導電。當該極性反轉且該二極體被逆向偏壓時,在該閘極被偏壓至一開啟狀態之後,被儲存之電荷必須在該MOSFET被完全地打開之前被移除。由於在該第二N型層與該N縱列中較高的摻雜程度,此被儲存之電荷較快地被移除,以致能較快的切換時間。

於較佳的一實施例中,一P型遮罩層被形成於該凹槽下方之P縱列的上方,以靠合該第二N型層的側壁。此P型遮罩層有助於橫向地消耗該第二N型層以增加該崩潰電壓。

被說明之閘極配置亦有助於橫向地消耗該第二N型層以增加該崩潰電壓。

使用頂部的一橫向通道、面向加強的一垂直「通道」部份的一垂直場平面、以及一超級接面的上述胞之多種變化係被說明。用以形成該垂直MOSFET之創新技術亦被說明。

一絕緣閘極雙極性電晶體(insulated gate bipolar transistor,IGBT)可藉由使用一P型基板來取代被形成。

10‧‧‧胞

12‧‧‧汲極電極

14‧‧‧源極電極

16‧‧‧閘極

18‧‧‧P井

20‧‧‧N-層

22‧‧‧N++源極區

24‧‧‧N型縱列

26‧‧‧N--層

28‧‧‧N++矽基板

30‧‧‧P型縱列

35‧‧‧磷

36‧‧‧N縱列層

38‧‧‧光阻劑層

40‧‧‧硼

42,44,46‧‧‧層

48‧‧‧氧化物層

50‧‧‧光阻劑

52‧‧‧凹槽

54‧‧‧硼

56‧‧‧P遮罩

58‧‧‧熱犧牲氧化物層

60‧‧‧氧化物層

64‧‧‧多晶矽層

66‧‧‧光阻劑層

68‧‧‧硼

70‧‧‧磷

72‧‧‧絕緣層

74‧‧‧硼

76‧‧‧P+接觸區

80‧‧‧N縱列

82‧‧‧P縱列

84‧‧‧P井

86,88‧‧‧縱列層

90‧‧‧凹槽氧化物

92‧‧‧閘極多晶矽層

94,96,98,100,102,104‧‧‧多晶矽層

106‧‧‧閘極氧化物

108,110‧‧‧氧化物

112‧‧‧P縱列

114‧‧‧N縱列

116,118‧‧‧P縱列

120‧‧‧導電多晶矽部

124‧‧‧N層

126‧‧‧N-層

130‧‧‧P+基板

132‧‧‧緩衝層

134‧‧‧集極電極

136,138‧‧‧N型區

140‧‧‧P+區

142‧‧‧N+區

144‧‧‧N緩衝器層

第1圖係為根據本發明一實施例之相同連續MOSFET胞的一大型陣列中之單一垂直MOSFET胞的一剖面圖。

第2A圖至第2R圖係為使用來製造第1圖之MOSFET的各種步驟。

第3圖係為於一關閉狀態中,該裝置的基板頂面與一P井之間的空乏區之等位線,並示出崩潰電壓的一虛擬最大化。

第4圖係為具有較淺之一縱列層或是較淺之一凹槽的一MOSFET,使得該P遮罩不會接觸底層的P縱列。

第5圖係為具有N縱列薄於P縱列的一MOSFET。

第6圖係為該P井延伸至該凹槽側壁的一MOSFET。

第7A圖與第7B圖係為不具有N縱列與P縱列的MOSFET。

第8A圖與第8B圖係為具有多個縱列層的MOSFET。

第9圖係為於該N-層的邊緣上方具有較薄的一氧化物的一MOSFET,以減少氧化物崩潰的可能性。

第10A圖係為具有更均勻厚度的閘極多晶矽層的一MOSFET。

第10B圖係為具有一分裂多晶矽層的一MOSFET,其中該閘極重疊該N-層。

第10C圖係為具有一分裂多晶矽層的一MOSFET,其中該閘極重疊該P遮罩。

第10D圖係為具有一分裂多晶矽層的一MOSFET,其未具有面向該N-層邊緣之多晶矽。

第11A圖係為一MOSFET,其中一均勻薄的閘極氧化物重疊於該橫向通道、該凹槽側壁與該P遮罩。

第11B圖與第11C圖係為具有較薄的一氧化物於該P遮罩上方的MOSFET。

第11D圖係為具有相鄰該凹槽之一可變厚度氧化物的MOSFET。

第12A圖與第12B圖係為具有在該P井下方之一P縱列的MOSFET。

第13A圖與第13B圖係為具有一分裂多晶矽層的MOSFET。

第14A圖至第14C圖係為具有圍繞該P縱列而共形之一N層的MOSFET。

第15A圖至第15E圖係為藉由使用一P+型基板以轉換成IGBT的變化MOSFET實施例。

第16圖係為使用所述之MOSFET胞或是IGBT胞中之任一者的胞陣列的一類型的一俯視圖,其中該等胞係以帶形來被配置。

第17圖係為使用所述之MOSFET胞或是IGBT胞中之任一者的胞陣列的另一類型的一俯視圖,其中該等胞係以帶形來被配置。

第1圖係為根據本發明一實施例之相同連續MOSFET胞的大型陣列中之單一垂直MOSFET胞10的剖面圖。所示之胞的寬度大約為8-11微米。該MOSFET胞10可具有超過600伏特的一崩潰電壓,並且相同胞之一陣列中的胞10之數量決定該電流處理能力,例如20安培。該胞陣列可為帶形、四邊形、六邊形或是其他習知形狀。

於正常操作期間,一正電壓被施加至底部的汲極電極12與一負載,該負載係連接於地與頂部的源極電極14之間。當一正電壓被施加至該導電 閘極16並大於該臨界電壓時,該P井18的頂面被反向,並且電子沿著該N-層20的垂直側壁來累積。該閘極沿著該P井18下方的側壁來延伸,並且創造一場平面至該N-層20中較低的一電場。該N++源極區22、該P井18與該N-層20頂面形成該MOSFET胞10的一橫向DMOS電晶體部。因此,在該開啟狀態中,透過該N++源極區22、該P井18之被反向的通道、該N-層20之側壁、該通道下之N型縱列24、該N--層26(該漂移層)與該N++矽基板28,在該源極電極14與該汲極電極12之間具有一導電N型通道。

該橫向DMOS電晶體部的組合,該N-層20之較高的摻雜(允許以該凹槽場平面效應與該垂直閘極部來沿著該N-層20之側壁累積電子)、交替且高度地摻雜的N型縱列24與P型縱列30、以及該N--層26,與習知技術相較能減少該開啟電阻,其將於下文中說明。若該等MOSET內部PN二極體變為正向偏壓時,該結構相較於習知技術亦增加該崩潰電壓並加速該切換時間,其將於下文中說明。

於該剖面圖中,該P井18的深度被誇大以方便說明,並且該多晶矽閘極16沿著該N-層20之側壁延伸至該P井18下方。例如,沿著該N-層20之側壁(以及沿著該側壁的任一虛擬場平面)的多晶矽閘極16可延伸於該P井18下方1-4微米。由於第3圖係為一模擬,故第3圖之閘極16的尺寸相對於該P井18會相對更為準確。

第2A圖至第2R圖係為使用來製造第1圖之MOSFET胞10的各種步驟。

第2A圖示出,當生長期間被摻雜原位(in-situ),該N--層26係磊晶生長於一N++矽基板28上,或是該N--層26被週期性地以大約1.5E12cm2 的劑量植入N型摻雜。該N++矽基板28可具有大約5E19cm3的摻雜濃度。為使一裝置具有大約600V的一崩潰電壓,該N--層26的最終摻雜密度大約為3.5E14cm3。該N--層26可為30微米厚。

第2B圖示出薄的一熱氧化物長於該N--層26上,接著一覆蓋式(blanket)的磷35植入並形成一N縱列層36。該植入劑量可大約為1-2E12cm2

第2C圖示出形成於該N型縱列24的預定位置上方的被圖案化之一光阻劑層38。接著硼40以大約1E13cm2的計量來覆蓋式植入以形成P型縱列30。

於第2D圖中,該光阻劑與氧化物被分裂,並且一N-層20被磊晶生長以具有大約2.3E15cm3的一摻雜密度,其高於該N--層26的摻雜密度。該N-層20大約為8微米厚。於另一實施例中,該N-層20的摻雜密度相同於該N--層26。

於第2E圖中,一熱氧化物層42被長於該N-層20上方。該N型縱列24與該P型縱列30的摻雜物被驅動並且散開,以形成大約4-5微米厚的一縱列層,具有於該N型縱列24之一N型摻雜濃度約為2E15cm3,以及具有於該P型縱列30之一P型摻雜濃度約為1E16cm3。該N型縱列24之摻雜密度可高於或是低於該N-層20之摻雜密度。

於第2F圖中,一多晶矽層被形成為大約1000埃厚,接著一氮化物層46大約2000埃厚,接著一氧化物層48大約10,000埃厚。

於第2G圖中,光阻劑50之一層被圖案化,並且蝕刻掉該等層42,44,46的被暴露部份。

於第2H圖中,該光阻劑被剝離並且於該被暴露之矽上執行一乾 性蝕刻,以於該N-層20中形成凹槽52。於該凹槽52下方,凹槽蝕刻留下大約3-4微米的N-層20。接著,硼54被植入大約4E12cm2的劑量至該凹槽52,以形成P遮罩56。

於第2I圖中,厚的氧化物層藉由乾性蝕刻而被剝離,並且大約1000埃厚的一熱犧牲氧化物層58被生長於該P遮罩56上方與該N-層20之側壁上方。

於第2J圖中,該熱犧牲氧化物層被剝離,並且使用一LOCOS製程以形成大約6000埃厚的一氧化物層60於該P遮罩56上方與該N-層20之側壁上方。

於第2K圖中,該等層42,44,46被剝離。

於第2L圖中,具有大約900埃之厚度之薄的一閘極氧化物層,係生長於該N-層20上方。然後,導電的一多晶矽層64被沉積並圖案化。

於第2M圖中,一光阻劑層66被圖案化並且暴露該多晶矽層64的中央部份,接著藉由一乾性蝕刻以形成該閘極16。

於第2N圖中,該光阻劑層被剝離,並且硼68被植入至該N-層20,並且被嵌入以形成與該閘極16一起自我校準(self-aligned)的P井18,該P井18係具有大約2-3微米的一深度。

於第2O圖中,砷或磷70被植入大約5E15cm2的劑量並且被嵌入以形成大約0.2-0.5微米深的一N++源極區22,並與該閘極16一起自我校準。

於第2P圖中,該絕緣層72被沉積於一襯氧化物層所組成的閘極16上方與週圍,其具有大約800埃之厚度,接著是一硼磷矽玻璃(boro-phospho-silicate-glass,BPSG)層,其具有大約10000埃之厚度。然後,該絕 緣層72的中央部係以光阻劑來被遮蔽,並且被蝕刻以曝露該N++源極區22。然後,該光阻劑被剝離。

於第2Q圖中,透過該N++源極區22之被曝露部被蝕刻,以曝露該P井18。然後,硼74以大約2E15cm2的劑量被植入,並且被嵌入以於該P井18中形成一P+接觸區76。該P+接觸區76的橫向寬度大約1微米。若該P井18延伸至該晶粒的邊緣,該P+接觸區76僅需要被設置於該晶粒的邊緣。

於第2R圖中,該結構被金屬化(例如使用濺鍍),以形成頂部的一源極電極14,係與該P+接觸區76及該N++源極區22之側面相接觸來與該等區一起電性地短路。該源極電極14可藉由濺鍍AlCu或是AlSiCu而被形成,並且可大約為4微米厚。底部的一汲極電極12藉由濺鍍鈦、鎳與銀之層來形成,其中該鈦層約1000埃之厚度、該鎳層約2000埃之厚度及該銀層約10,000埃之厚度。然後,該結構係以一保護層來被保護,並且該保護層被圖案化/被蝕刻而暴露該等電極,用以與封裝的引線相接觸。例如,一打線可接合該源極電極14至該封裝的一引線,並且該汲極電極12可直接地接合至該封裝的一散熱片電極。

第3圖係為於一關閉狀態且電壓略小於崩潰電壓中,該裝置的N++矽基板28頂面與P井18之間空乏區的等位線,示出該電壓基本上是均勻分布。此均勻的電壓分佈最大化該崩潰電壓。值得注意的是,於該關閉狀態中的一最大可允許電壓,該P井18下方與該N++矽基板28上方的全部區域將被消耗。

該P遮罩56增加該崩潰電壓,係藉由有效地增加該P型縱列30的垂直尺寸而不必生長額外的一磊晶層。當該閘極係為接地或是負時,除了相 鄰該N-層20側壁的閘極16之垂直場平面之外的P遮罩56,有助於橫向地消耗該N-層20以達成第3圖中所示之電壓的均勻分布。該橫向消耗允許較高的N-層20之一摻雜,用以減少開啟電阻。

請再參考第1圖,該N--層26係薄於習知的漂移層,由於其不需要整個延伸至該通道區。形成相鄰P型縱列30與N型縱列24產生一超級接面,其中該等縱列完全地消耗並且於該P區域及該N區域中的電荷平衡。於該開啟狀態(閘極正偏壓),該電流自該源極電極14流動,通過該源極區22,通過該橫向通道,然後垂直地通過該N-層20(包括沿著一電子聚集層的側壁來通過),然後垂直地通過底層的N型縱列24、N--層26與N++矽基板28,以到達該汲極電極12。

由於該N型縱列24具有相當高的一摻雜濃度並高於該N--層26,其減少了開啟電阻使導電性更優於該N--層26。此外,由於靠近被正偏壓之閘極16,該N-層20被相當重的摻雜並且具有沿著其側壁的增強之一電子群,使得該橫向通道與該N型縱列24之間的垂直路徑係非常導電。特定的開啟電阻(Ron*Area)是如此低,使該胞陣列的所有開啟電阻係小於1Ohm。於一實施例中,特定的開啟電阻達到4.5Ohms-mm2,其係大約為習知功率MOSFET的一半。將產生較小的晶粒並且使每個晶圓的產量加倍。

由於是藉由一凹槽閘極而非垂直通道,第1圖之該凹槽能夠非常淺(例如4-10微米),使其更容易被形成。由於不用形成深的凹槽所以該製程係相當簡單,因此第1圖之MOSFET胞10能使用標準製程設備來形成,並可降低每個晶圓的成本。

除了該MOSFET胞10具有被增加的一崩潰電壓與較低的開啟 電阻之外,在該MOSFET PN二極體被偏壓開啟之後,該MOSFET胞10具有較快的回復時間。接著該源極/汲極電壓反向後,在該PN二極體已被偏壓開啟之後於閘極控制切換中的延遲,係由於當該二集體被逆向偏壓時而被儲存的電荷。被儲存之電荷必須被移除,以使該二極體關閉並且該MOSFET開啟。於該MOSFET胞10中的電荷之移除係不但能藉由非常高摻雜的N型縱列24與N-層20來加速,該N-層20的側壁上的正閘極效應亦能抽出(drawing)該側壁之電子。

第1圖之基本的MOSFET胞10具有許多變化並保有較低的開啟電阻與較高的崩潰電壓之優點。第4-15E圖示出一些該等變化態樣。

第4圖係為具有較淺之一縱列層的一MOSFET,因此該P遮罩56不會與底層之P型縱列30相接觸。該P遮罩56還具有該橫向地消耗該N-層20之效應,使得該N-層20可相對地具有高摻雜以減少開啟電阻。

第5圖係為具有N縱列80深於P縱列82的一MOSFET。由於該N縱列80相較於該N--層26具有更高的摻雜,因此可用於擴散電流以並免熱點,更可減少開啟電阻。

第6圖係為該P井84延伸至該凹槽側壁的一MOSFET。當該閘極16被正偏壓以開啟該MOSFET時,重疊的閘極16與閘極16的側壁部反向該P井84的頂面與側面。由於薄的閘極氧化物僅重疊於該P井84,此結構減少了具有高汲極-閘極電壓之頂部薄閘極氧化物崩潰的可能性,並且該P井84係處於該源極電壓。

第7A圖與第7B圖係為不具有N縱列與P縱列的MOSFET。於該等實施例中,第1圖之超級接面的優點無法被使用,所以該N--層26較薄。因此,開啟電阻無法像第1圖之MOSFET這麼好。然而,與該N-層20相結合 的閘極結構相較於習知技術依舊可減少開啟電阻。

第8A圖與第8B圖係為具有多個縱列層86及88的MOSFET。其允許使用較薄的縱列層以達到於該等縱列中更為均勻的摻雜濃度。具有一厚的縱列層,被植入之摻雜需要以更長的時間來被嵌入,橫向地擴散該等摻雜亦相同。藉由使用多個較薄的縱列層,減少所需的嵌入時間,使得該等摻雜不再需要這麼長時間的橫向地擴散。其允許較小的胞間距與較小的晶粒尺寸。假設足夠高的一源極-汲極電壓,當該MOSFET係關閉時該等縱列層消耗,並由於該超級接面的消耗特性,使得該P縱列與該N縱列允許在該等縱列中的摻雜濃度係相當高。

第9圖係為於該N-層20的較上方邊緣處具有較薄的一凹槽氧化物90的一MOSFET。由於其之電場通常聚集於低半徑角落處,較厚的氧化物有助於防止該N-層20與該閘極16之間的氧化層之崩潰。不同的氧化物厚度係藉由一遮蔽蝕刻所完成。

第10A圖係為相較於第1圖之閘極多晶矽層,具有更均勻厚度的閘極多晶矽層92的一MOSFET。由於較薄的多晶矽層,其可減少製程時間。

第10B圖係為具有分裂之多晶矽層94與96的一MOSFET,其中該間隙重疊該N-層20。該P井18上方的閘極部反向該通道。該多晶矽層96可被連接至該源極或是被浮動,以作為用以擴散該電場分布的一場平面,來達到更為均勻的一電場剖面。當該MOSFET係為開啟時,該多晶矽層96本質上處於較低於該閘極的一電壓。這使得該多晶矽層96與該N-層20之間具有較小的電壓差。由於該閘極部僅反向該通道,該N-層20中具有較小的一導電性調整。該閘極至汲極電容(密勒電容)被顯著的減少,減少了切換損耗。因此,與閘極電 壓相較,該MOSFET之導電性比第1圖之MOSFET更稍微的線性,開啟電阻有稍微的增加,並且切換功率損耗被減少。

第10C圖係為具有分裂的多晶矽層98與100的一MOSFET,其中該間隙重疊於該P遮罩56。於該P井18及該N-層20之側壁上方的閘極反向該通道,並且沿著該N-層20之側壁累積電子以用於較低的一開啟電阻。該多晶矽層100係被連接至該源極或是被浮動。

第10D圖係為具有分裂的多晶矽層102與104的一MOSFET,其中未具有面向該N-層20之邊緣的多晶矽。由於場聚集於該邊緣,因此減少了該N-層20之邊緣與該多晶矽之間的氧化物崩潰的可能性。

第11A圖係為一MOSFET,其中均勻薄的一閘極氧化物106重疊該橫向通道、該凹槽側壁以及該P遮罩56。因此,以減少開啟電阻來說,本實施例之閘極16的效應最為明顯;然而,閘極氧化物崩潰的可能性係增加。

第11B圖與第11C圖係為具有較薄的一氧化物108於該P遮罩56上的MOSFET,以減少該P遮罩56上之氧化物崩潰的可能性。

第11D圖係為相鄰該凹槽之具有可變厚度的一氧化物110的一MOSFET,係由於場聚集而減少氧化物崩潰的可能性。

在上述的實施例中,寬的一N縱列被垂直地設置於該P井18下方。第12A圖與第12B圖示出具有於該P井18下方之窄的一P縱列112與相鄰於中央之P縱列112之窄的N縱列114的MOSFET。當該MOSFET被關閉時,較窄的縱列改善了該等縱列的橫向消耗,因此該等縱列能夠為更高的摻雜以減少開啟電阻。由於該電流路徑主要是沿著該N-層20之邊緣(且N縱列114係於該等邊緣下方),該P井18中間下方之窄的P縱列112的位置不會對開啟電阻有 不好的影響。

第12B圖,中央的P縱列116延伸至該P井18。在該關閉狀態時,其有助於橫向地消耗該N-層20,允許該N-層20有更高的摻雜以改善開啟電阻。

第13A圖與該13B圖示出相似於第10B圖MOSFET(具有分裂之多晶矽層)之MOSFET,但其中,中間之P縱列118延伸至該P井18與一導電多晶矽部120,該導電多晶矽部120係連接至該源極電極14,突出至該P縱列118並自該P縱列118絕緣。於該關閉狀態,其有助於消耗該P縱列118。

第14A圖至第14C圖係為具有圍繞該P縱列118而共形之一N層124的MOSFET,並且該P縱列118延伸至該P井18。該N層124具有一摻雜濃度大約等於該P縱列118的摻雜濃度。當該PN二極體被正向偏壓時,該N層124減少載子注入至該P縱列118,以當該源極與汲極電壓改變極性時致能更快的回復。在極性已被反轉之後,其致能較快速的切換時間。該N層124亦減少電流擴散電阻為較低的開啟電阻。

第14B圖與第14C圖加入了於該P井18週圍的另一N-層126,其相較於該N-層20具有更高的摻雜以減少開啟電阻。該N-層126有助於沿著該P井18的整個寬度來擴散電流,並且該N-層124沿著該N型縱列24以垂直地傳導該電流至該N--層26。

第15A圖至第15E圖示出藉由一P+型基板130來轉換為IGBT的多種MOSFET的實施例。薄的一N型緩衝層132被加入。該緩衝層132被用於控制自該P+基板130的電洞植入與該IGBT的崩潰特性。此時該汲極電極係為一PNP電晶體的集極電極134,並且此時該源極電極係為一NPN電晶體的一 射極電極。因此,垂直的一NPN電晶體與一PNP電晶體被形成,並且當該閘極偏壓為低時會阻止電流。當有足夠地一正閘極偏壓時,一初始電流在該源極與該汲極之間流動,其植入足夠的電流以正向偏壓該NPN與該PNP電晶體以創造該IGBT動作。這使得開啟電阻相較於一垂直MOSFET較低。然而,該最大切換頻率被降低。IGBT的一般操作係為習知技術。

第15B圖係為具有不同摻雜的N型區136與138之一N類型緩衝器。該等N型區136與138的摻雜濃度分別大約為1E17cm3與2E17cm3。較高的一摻雜濃度減少自該集極至該射極的崩潰電壓,但是增加該裝置關閉切換速度。此外,該等N型區136與138的一不同摻雜程度可改善該崩潰電壓與該裝置的正向電壓之間的權衡。

第15C圖係為該集極電極134,其係直接地連接至該基板的P+區140與該基板的N+區142。當該集極電極134對於該源極(射極)電極來說係足夠負時,該等N+區142允許該IGBT為一PN二極體。其集成了自由電力隔通二極體至一IGBT中,在該等電壓改變極性時,這對某些應用是有用的。

第15D圖加上了一N緩衝器層144於該P+區140上方,以調整自該P+區140(集極)的電洞植入效率。

第15E圖組合許多前述特點至單一IGBT。

第16圖係為使用於上述之MOSFET胞或是IGBT胞之任一者的胞陣列之一類型的一俯視圖,其中該等胞被配置為帶形。在此僅示出該閘極16、源極區22與P+接觸區76。該P+接觸區76係可僅在該等帶形之每一者的一端。

第17圖係為使用於上述之MOSFET胞或是IGBT胞之任一者的胞陣列之另一類型的一俯視圖,其中該等胞被配置為四邊形。在此僅示出該閘 極16、源極區22與P+接觸區76。六邊形狀或是其他形狀亦可被使用。

上述之任一特點可被組合於一MOSFET或是IGBT的任一組合中,以於一特定應用中達到特點中之特定優點。

雖然已示出與說明本發明之特定實施例,其使本發明所屬技術領域中具有通常知識者可在不脫離本發明之廣泛的範疇來改變與修改,因此下述之申請專利範圍之任何改變與修改,皆落入本發明真實的精神與範圍中。

10‧‧‧胞

12‧‧‧汲極電極

14‧‧‧源極電極

16‧‧‧閘極

18‧‧‧P井

20‧‧‧N-層

22‧‧‧N++源極區

24‧‧‧N型縱列

26‧‧‧N--層

28‧‧‧N++矽基板

30‧‧‧P型縱列

56‧‧‧P遮罩

76‧‧‧P+接觸區

Claims (24)

  1. 一種垂直式電晶體,包括:一半導體基板,係具有在其底面的一第一電極;一第一層,係為一第一導電性類型且位於該基板上方,該第一層具有一第一摻雜濃度;一第二層,係為該第一導電性類型且位於該第一層上方,該第二層具有高於該第一摻雜濃度的一第二摻雜濃度,該第二層具有一頂面;一凹槽,係曝露該第二層的一垂直側壁;一井區,係為一第二導電性類型且位於該第二層的頂面,該井區具有一頂面;一第一區,係為該第一導電性類型且位於該井區的頂面,其中該第一區與該井區的一邊緣之間的一區域包括用於藉由一閘極來反向的一通道;一導電閘極,係重疊於該通道,當該閘極被偏壓高於一臨界電壓時,該導電閘極於該第一區與該第二層之間創造一橫向導電路徑;一垂直場平面,係面向該第二層之垂直側壁並且自該垂直側壁絕緣,該垂直場平面係為該閘極的延伸,該垂直場平面係圍繞該第二層;以及一第二電極,其係電性地接觸該井區與該第一區,其中當一電壓被施加在該第一電極與該第二電極之間以及該閘極被偏壓 高於該臨界電壓時,一橫向電流穿過該通道來流動,並且一實質垂直電流流動於該通道與該基板之間。
  2. 如請求項1所述之電晶體,更包括:一第三層,係為該第一導電性類型且位於該第一層與該第二層之間,並設置該通道下方;以及一第四層,係為該第二導電性類型且於該第三層的相對側來橫向地靠合該第三層,該第三層與第四層中的一摻雜濃度係高於該第一摻雜濃度。
  3. 如請求項2所述之電晶體,更包括一第五層,係為第二導電性類型且位於該凹槽下方並橫向地相鄰於該第二層。
  4. 如請求項3所述之電晶體,其中該第五層係靠合於該第四層。
  5. 如請求項3所述之電晶體,其中該第一層係垂直地自該第四層分開。
  6. 如請求項3所述之電晶體,其中該閘極具有一第一部份、一第二部份與一第三部份,該第一部份係與該通道重疊,該第二部份係面向該第二層的垂直側壁以作為該垂直場平面,該第三部份係與該第五層重疊,其中該閘極與該通道之間的一介電層的厚度、該垂直側壁與該第五層係相等。
  7. 如請求項3所述之電晶體,其中該閘極具有一第一部份、一第二部份與一第三部份,該第一部份係與該通道重疊,該第二部份係面向該第二層的垂直側壁以作為該垂直場平面,該第三部份係與該 第五層重疊,其中該閘極與該通道之間的一介電層的一厚度係小於該閘極與該第五層之間的一介電層的一厚度。
  8. 如請求項3所述之電晶體,其中該閘極具有一第一部份、一第二部份與一第三部份,該第一部份係與該通道重疊,該第二部份係面向該第二層的垂直側壁以作為該垂直場平面,該第三部份係與該第五層重疊,其中該閘極與該垂直側壁間之間具有一介電層的多種厚度。
  9. 如請求項2所述之電晶體,其中該第四層包括於該井區下方的一第一部份,該第一部份以該第三層來被靠合於相對橫向側。
  10. 如請求項9所述之電晶體,其中該第一部份係延伸至該井區。
  11. 如請求項10所述之電晶體,更包括一第五層,係為該第一導電性類型,係被形成以靠合該第四層的橫向側並且靠合該第四層的一底面。
  12. 如請求項2所述之電晶體,更包括一第五層,係為該第一導電性類型且位於該井區與該第二層之間,該第五層係具有高於該第二層之摻雜濃度的一摻雜濃度。
  13. 如請求項2所述之電晶體,更包括:一第五層,係為該第一導電性類型且位於該第三層下方;以及一第六層,係為該第二導電性類型且於該第五層的相對側來橫向地靠合該第五層,該第六層係位於該第四層下方,該第五層與該第六層的一摻雜濃度係高於該第一摻雜濃度。
  14. 如請求項2所述之電晶體,其中該基板係為該第一導電性類型,並且該電晶體係為一金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor,MOSFET)。
  15. 如請求項2所述之電晶體,其中該基板係為該第二導電性類型,並且該電晶體係為一絕緣閘極雙極性電晶體(insulated gate bipolar transistor,IGBT)。
  16. 如請求項1所述之電晶體,其中該閘極亦沿著該第二層之垂直側壁設置以作為該垂直場平面,以使當該閘極被偏壓高於該臨界電壓時來調整該垂直側壁的導電性。
  17. 如請求項16所述之電晶體,更包括一第一介電層,係設置於該閘極與該井區的頂面之間,其中一第二介電層設置於該閘極與該側壁之間,以及其中該第一介電層的厚度係相同於該第二介電層的厚度。
  18. 如請求項16所述之電晶體,更包括一第一介電層,係設置於該閘極與該井區的頂面之間,其中一第二介電層設置於該閘極與該側壁之間,以及其中該第一介電層的厚度係小於該第二介電層的厚度。
  19. 如請求項1所述之電晶體,更包括一第三層,係為該第二導電性類型且位於該凹槽下方並橫向地相鄰於該第二層,其中該垂直場平面與該第二層的第二摻雜濃度係配置來增加該第二層的橫向消耗,使得該第二層於該電晶體的一崩潰電壓係完全地消耗。
  20. 如請求項1所述之電晶體,更包括: 一第三層,係為該第一導電性類型且位於該第一層與該第二層之間,並設置該通道下方;以及一第四層,係為該第二導電性類型且於該第三層的相對側來橫向地靠合該第三層,該第三層與第四層中的摻雜濃度係高於該第一摻雜濃度,其中該第三層與該第四層係形成N型縱列與P型縱列,其中該N型縱列與該P型縱列於該電晶體的一崩潰電壓係完全地消耗。
  21. 如請求項2所述之電晶體,其中該第三層之摻雜濃度係高於該第一層與該第二層。
  22. 如請求項1所述之電晶體,更包括一第三層,係具有該第二導電性類型且位於該井區下方並橫向地相鄰於該第二層。
  23. 如請求項22所述之電晶體,更包括於該凹槽與該第三層上的一導電材料,該導電材料係被電性地連接至該第二電極。
  24. 如請求項1所述之電晶體,其中該垂直場平面係深於該井區。
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