CN107785367A - 集成有耗尽型结型场效应晶体管的器件及其制造方法 - Google Patents

集成有耗尽型结型场效应晶体管的器件及其制造方法 Download PDF

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Publication number
CN107785367A
CN107785367A CN201610793855.3A CN201610793855A CN107785367A CN 107785367 A CN107785367 A CN 107785367A CN 201610793855 A CN201610793855 A CN 201610793855A CN 107785367 A CN107785367 A CN 107785367A
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jfet
trap
type
conduction type
source electrodes
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CN201610793855.3A
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CN107785367B (zh
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顾炎
程诗康
张森
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CSMC Technologies Corp
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CSMC Technologies Corp
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Priority to CN201610793855.3A priority Critical patent/CN107785367B/zh
Priority to PCT/CN2017/098314 priority patent/WO2018040973A1/zh
Priority to EP17845275.1A priority patent/EP3509102A4/en
Priority to JP2019511877A priority patent/JP6770177B2/ja
Priority to US16/329,348 priority patent/US10867995B2/en
Publication of CN107785367A publication Critical patent/CN107785367A/zh
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及一种集成有耗尽型结型场效应晶体管的功率器件及其制造方法，所述器件包括：阱区，为第二导电类型且形成于第一导电类型区内；JFET源极，为第一导电类型且形成于阱区内；JFET源极的金属电极，形成于JFET源极上且与JFET源极接触；横向沟道区，为第一导电类型，形成于两相邻JFET源极之间且两端与两相邻JFET源极接触；JFET金属栅极，形成于阱区上。本发明可以通过调节横向沟道区的注入剂量和能量，得到不同档位的夹断电压，因而与传统的纵向沟道形成的JFET相比，其夹断电压调控更加方便。同时由于横向沟道浓度更加均匀，其夹断电压也会更加稳定。

Description

集成有耗尽型结型场效应晶体管的器件及其制造方法
技术领域
本发明涉及半导体制造技术，特别是涉及一种集成有耗尽型结型场效应晶体管的器件，还涉及一种集成有耗尽型结型场效应晶体管的器件的制造方法。
背景技术
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-EffectTransistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。
传统结构的高压集成JFET有较简单的工艺可以实现，但其夹断电压的不稳定和调控性较差等特性限制了其在智能功率集成领域的大规模应用。
发明内容
基于此，有必要针对传统的JFET夹断电压不稳定和调控性较差的问题，提供一种集成有耗尽型结型场效应晶体管的器件。
一种集成有耗尽型结型场效应晶体管的功率器件，包括设于所述器件背面的第一导电类型的漏极，和设于所述漏极朝向所述器件正面的一面的第一导电类型区，所述器件包括JFET区和功率器件区，所述JFET区包括：阱区，为第二导电类型且形成于所述第一导电类型区内；所述第一导电类型和第二导电类型为相反的导电类型；JFET源极，为第一导电类型且形成于所述阱区内；JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；横向沟道区，为第一导电类型，形成于两相邻JFET源极之间且两端与所述两相邻JFET源极接触；JFET金属栅极，形成于所述阱区上。
在其中一个实施例中，所述阱区为复合阱区结构，包括第一阱和位于所述第一阱内的第二阱，所述第二阱的离子浓度大于所述第一阱。
在其中一个实施例中，所述JFET区还包括JFET栅极欧姆接触，所述JFET栅极欧姆接触在所述两相邻JFET源极所在的阱区内各形成有一个，且设于JFET源极远离所述横向沟道区的一侧，为第二导电类型；所述JFET金属栅极形成于所述JFET栅极欧姆接触上且与所述JFET栅极欧姆接触相接触。
在其中一个实施例中，所述JFET区和功率器件区交界处形成有所述第一阱，作为JFET区和功率器件区的隔离。
在其中一个实施例中，所述功率器件是垂直双扩散金属氧化物半导体场效应晶体管。
在其中一个实施例中，所述功率器件区包括栅极，第二阱，设于所述第二阱内的第一导电类型的VDMOS源极，以及设于所述第二阱内、所述VDMOS源极下方的非钳位感性开关区；所述非钳位感性开关区为第二导电类型且离子浓度大于所述第二阱的离子浓度。
在其中一个实施例中，所述栅极的下方两侧各有一个第二阱，所述VDMOS源极形成于这两个第二阱内，且所述VDMOS源极在这两个第二阱的每一个内都分为两块，所述器件还包括形成于两块VDMOS源极之间的第二导电类型的欧姆接触区。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
本发明还提供一种集成有耗尽型结型场效应晶体管的器件的制造方法。
一种集成有耗尽型结型场效应晶体管的功率器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；注入第一导电类型的离子，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极；光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质形成沟道注入窗口，并向所述沟道注入窗口内注入第一导电类型的离子，形成横向沟道区；光刻并刻蚀接触孔，淀积金属层填入所述接触孔内分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
在其中一个实施例中，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱作为JFET区和功率器件区的隔离。
在其中一个实施例中，所述在所述第一导电类型区表面形成多晶硅层的步骤之后，还包括步骤：向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱，位于所述JFET区的每一第二阱各形成于一第一阱内；所述在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤，是通过向所述第二阱注入第一导电类型的离子，分别在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极。
在其中一个实施例中，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质形成沟道注入窗口的步骤之前，还包括形成注入阻挡层的步骤，以及向所述功率器件区的所述第二阱中注入第二导电类型的离子，以在所述第二阱内所述功率器件源极的下方和JFET源极的下方形成非钳位感性开关区的步骤，且注入能量大于所述注入第一导电类型的离子的步骤的注入能量。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层，所述功率器件是垂直双扩散金属氧化物半导体场效应晶体管。
上述集成有耗尽型结型场效应晶体管的器件及其制造方法，可以通过调节横向沟道区的注入剂量和能量，得到不同档位的夹断电压，因而与传统的纵向沟道形成的JFET相比，其夹断电压调控更加方便。同时由于横向沟道浓度更加均匀，其夹断电压也会更加稳定。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一种传统的高压集成JFET的剖面结构示意图；
图2是一实施例中集成有耗尽型结型场效应晶体管的器件的剖面结构示意图；
图3是一实施例中集成有耗尽型结型场效应晶体管的器件的制造方法的流程图；
图4a～4d是图3所述的制造方法在制造过程中的器件剖面结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
一种传统的集成高压耗尽型结型场效应晶体管(Junction Field-EffectTransistor，JFET)的垂直双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffused MOSFET，VDMOS)的结构如图1所示。包括栅极101、源极102、高压P阱103、体接触104、N型外延层105以及N+接触106。
当VDMOS处于开启阶段时，电流从底部漏端流过JFET，从source2流出。当source2上加逐渐变大的电压Vg2，同时栅gate上也加同样的电压Vg1，当Vg2>夹断电压Voff时，JFET的耗尽层阻断了电流，即发生了夹断。此时Vg1>Vth，VDMOS开启，完成了一个开启过程。JFET在此吸收了DMOS在米勒平台时的突变电流，让启动更为平缓，电流可以成近似线性变换，所以JFET在启动过程中对器件稳定性提升有着很显著作用。功率器件在其工艺平台上集成寄生JFET则更具有优势。
集成寄生JFET，其最主要特性是整体击穿电压的稳定性和夹断电压的稳定性，最为理想的是，集成后器件的击穿电压保持不变，击穿点最好保持在功率VDMOS的击穿点。传统的集成结构VDMOS与JFET交接处仅用了衬底进行隔离，仅可以拉长衬底外延的横向距离来保证耗尽时的余量，这样会增加整个管芯的面积。同时，由于外延层规范有所偏差，工艺上略有变动就会出现击穿点转移，击穿点会从体内的cell区转移至JFET区或是交接处，大大降低了击穿的稳定性，还会发生击穿电压蠕变的现象。传统结构一般用自对准P型注入的衬底作为P型夹断衬底，由于VDMOS的元胞(cell)的P型衬底其纵向结深很浅，一般只有3～5微米，因此JFET的纵向沟道很短，人为无法去调整纵向沟道长度，所以夹断电压很不稳定。通过仿真可得知当漏端电压从50V到100V变化时，夹断电压Voff会从11V变大至20V，而在实际应用中需要Voff稳定，因此此传统结构难以满足实际需求。
图2是一实施例中集成有耗尽型结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，功率器件为VDMOS。如图2中所示，将器件按结构分为JFET区和VDMOS区，JFET区和VDMOS区共享设于器件背面(即图2中朝下的面)的N型的漏极201，和设于漏极201正面(即图2中朝上的面)的N型区214。在本实施例中，漏极201为N+漏极，N型区214为N-外延层(在其他实施例中也可以直接使用N型衬底)。
在本实施例中，JFET区包括横向沟道区208、JFET源极210、JFET源极的金属电极212、JFET金属栅极213、以及阱区。
其中N+的JFET源极210形成于阱区内，横向沟道区208为N-沟道，形成于两相邻JFET源极210之间且两端与这两个JFET源极210接触。JFET源极的金属电极212形成于JFET源极210上，作为JFET源极210的源极接触。JFET金属栅极213形成于阱区上。
上述集成有耗尽型结型场效应晶体管的器件，可以通过调节横向沟道区的注入剂量和能量，得到不同档位的夹断电压，因而与传统的纵向沟道形成的JFET相比，其夹断电压调控更加方便。同时由于横向沟道浓度更加均匀，其夹断电压也会更加稳定。
在图2所示实施例中，阱区为由第一阱202和第二阱205组成的复合阱区结构。复合阱区结构形成于N-外延层内，其中第一阱202为P-阱，第二阱205为位于第一阱202内的高压P阱。第二阱205的离子浓度大于第一阱202的离子浓度。在一个元胞内，横向沟道区208的两侧各形成有一个复合阱区结构，第二阱205作为器件的N型接触，形成导电沟道。
复合阱区结构与单一的P-阱相比，其浓度更大，可以防止漏端加高压导致PN结的耗尽穿通。可以理解的，在其他实施例中，阱区也可以采用单一的P阱或P-阱结构。
在图2所示实施例中，横向沟道区208延伸至第二阱205内，JFET源极210形成于第二阱205内。可以理解的，在其他实施例中横向沟道区208的两端也可以距第二阱205一段距离，JFET源极210可以位于第二阱205外、第一阱205内。
在图2所示实施例中，JFET区和VDMOS区交界处形成有一个第一阱202，作为JFET区和VDMOS区的隔离。利用P-的第一阱202辅助耗尽隔离，通过较深的P-阱隔离，可以完全阻断电流的流通路径，防止JFET和VDMOS间的漏电，且在器件反偏耐压时可以辅助下方的N-外延层(即N型区214)参与耗尽，提升局部区域的击穿电压来固化击穿点作用。同时，该第一阱202作为结终端扩展技术中终端的耗尽结构，能够有效缩短高压VDMOS的芯片面积。另外由于该结终端扩展的结工艺存在，P-阱结深大大超过了传统技术中VDMOS的P型衬底的结深，从而有了较长的纵向电流沟道。相较于传统结构，器件的夹断电压稳定性会提高较多，同时夹断电压也会显著降低。
在图2所示实施例中，JFET区还包括P型的JFET栅极欧姆接触211。JFET栅极欧姆接触211在横向沟道区208两侧的两个第二阱205内各形成有一个，且设于JFET源极210远离横向沟道区208的一侧。JFET金属栅极213形成于JFET栅极欧姆接触211上且与JFET栅极欧姆接触211相接触。在本实施例中，JFET栅极欧姆接触211的离子浓度大于第二阱205的离子浓度。
在图2所示实施例中，VDMOS区包括栅极(栅极包括栅氧层203和多晶硅栅204)、第二阱205、设于第二阱205内的N+的VDMOS源极206、以及设于VDMOS源极206下方的P型的非钳位感性开关(Unclamped Inductive Switching,UIS)区207。非钳位感性开关区207的离子浓度大于第二阱205的离子浓度。在图2所示实施例中，JFET区也形成有非钳位感性开关区207，具体是设于JFET源极210下方，且在本实施例中为第二阱205内，在其他实施例中也可以是第二阱205外、第一阱202内。
在图2所示实施例中，栅极的下方两侧各有一个第二阱205，VDMOS源极206形成于这两个第二阱205内，且VDMOS源极206在这两个第二阱205的每一个内都分为两块。器件还包括形成于两块VDMOS源极206之间的P型的欧姆接触区209。
图3是一实施例中集成有耗尽型结型场效应晶体管的器件的制造方法的流程图，以下以器件是VDMOS，第一导电类型是N型，第二导电类型是P型为例，介绍集成有耗尽型结型场效应晶体管的器件的制造方法：
S510，提供第一导电类型的衬底，衬底上形成有第一导电类型区。
在本实施例中，是在N+衬底上外延形成N型区214，衬底后续将会作为器件的漏极201。
S520，注入第二导电类型的离子并推阱，在第一导电类型区内形成第一阱。
在本实施例中，是向N型区214中注入P型离子并推阱，在N型区214内形成第一阱202。图4a是步骤S520完成后器件的剖面结构示意图。
S530，生长场氧层和栅氧层，并形成多晶硅层。
生长厚的场氧层然后生长栅氧层，并在N型区214表面形成多晶硅层604。在本实施例中，阱区为由第一阱202和第二阱205组成的复合阱区结构。故以场氧层和多晶硅层604为掩膜向N型区214注入P型离子，推阱形成多个第二阱205。其中JFET区的每一第二阱205各形成于一第一阱202内。第二阱205的离子浓度大于第一阱202的离子浓度。图4b是步骤S530完成后器件的剖面结构示意图。
S540，注入第一导电类型的离子，在JFET区形成JFET源极、在功率器件区形成功率器件源极。
在本实施例中，是用光刻工艺以光刻胶为掩膜注入N型离子，在JFET区的第二阱205内形成JFET源极，在功率器件区的第二阱205内形成VDMOS源极206。其中VDMOS源极206形成于栅极两侧的各一个第二阱205内，且在每个第二阱205内都分成两块，中间留出给后续步骤形成的欧姆接触区209的位置。
参见图4c，在本实施例中，在执行步骤S550之前，还包括向第二阱205中注入P型离子的步骤，以在第二阱205内的VDMOS源极206的下方形成非钳位感性开关区207。为了防止向第二阱205中注入的P型离子对沟道区造成不利影响，本实施例中在注入P型离子形成非钳位感性开关区207的步骤之前，还包括形成注入阻挡层的步骤。在本实施例中形成注入阻挡层是通过再形成一层氧化层，由于注入P型离子形成非钳位感性开关区207的注入窗口处的氧化层较薄，因此高能注入的P型离子可以穿过氧化层形成非钳位感性开关区207。而其他位置处的氧化层形成于场氧层、多晶硅层604等结构上，因此整个注入阻挡层的厚度较厚，P型离子难以穿过注入阻挡层进入N型区214内。
S550，光刻并刻蚀去除多晶硅及其它表面介质，注入第一导电类型的离子，形成横向沟道区。
在本实施例中，是通过光刻和刻蚀去除两相邻JFET源极210之间的位置上方的介质(例如场氧层、注入阻挡层)和多晶硅层604，然后注入N型杂质，在N型区214的表面、两相邻JFET源极210之间形成横向沟道区208。多余的多晶硅层604被去除后形成图2所示的多晶硅栅204。图4d是步骤S550完成后器件的剖面结构示意图。
S560，光刻并刻蚀接触孔，淀积金属层，填入接触孔内，形成JFET源极的金属电极和JFET金属栅极。
在本实施例中，刻蚀出接触孔后还包括向接触孔内注入P型离子，分别在JFET区的第二阱205内形成JFET栅极欧姆接触211，在功率器件区的第二阱205内形成欧姆接触区209的步骤。填入接触孔的金属与JFET栅极欧姆接触211相接触形成JFET金属栅极213，与JFET源极210相接触形成JFET源极的金属电极212。淀积金属层后在器件表面形成钝化层，完成后器件的剖面如图2所示。
综合上述优势，上述集成有耗尽型结型场效应晶体管的器件在传统技术的基础上提升了夹断电压的稳定性，固化了击穿点，加强了UIS能力，工艺上完全匹配，并且实现了夹断电压大小的可调性。
在其中一个实施例中，步骤S520包括在JFET区和功率器件区交界处形成一个第一阱202作为JFET区和功率器件区的隔离。
在其中一个实施例中，步骤S520的第一阱202的注入浓度为1.5E13cm-2～2.2E13cm-2，第一阱202的阱深为8.5微米～13.5微米。
在其中一个实施例中，对于夹断电压在5V～15V范围内的器件，步骤S550注入的N型离子采用As(砷)或P(磷)，对于砷离子，注入能量为100kev～180keV,注入剂量为2e12cm-2～7e12cm-2；对于磷离子，注入能量为60kev～120kev，注入剂量为2e12cm-2～7e12cm-2。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

1.一种集成有耗尽型结型场效应晶体管的器件，所述器件包括JFET区、功率器件区、设于所述器件背面的第一导电类型的漏极，和设于所述漏极朝向所述器件正面的面上的第一导电类型区，所述JFET区和功率器件区共享所述漏极和第一导电类型区；其特征在于，所述JFET区还包括：
阱区，为第二导电类型且形成于所述第一导电类型区内；
JFET源极，为第一导电类型且形成于所述阱区内；
JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；
横向沟道区，为第一导电类型，形成于两相邻JFET源极之间，且两端与所述两相邻JFET源极接触；
JFET金属栅极，形成于所述阱区上；
所述第一导电类型和第二导电类型为相反的导电类型。
2.根据权利要求1所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述阱区为复合阱区结构，包括第一阱和位于所述第一阱内的第二阱，所述第二阱的离子浓度大于所述第一阱的离子浓度。
3.根据权利要求1所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述JFET区还包括JFET栅极欧姆接触，所述JFET栅极欧姆接触在所述两相邻JFET源极所在的阱区内各形成有一个，且设于JFET源极远离所述横向沟道区的一侧，为第二导电类型；所述JFET金属栅极形成于所述JFET栅极欧姆接触上且与所述JFET栅极欧姆接触相接触。
4.根据权利要求2所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述JFET区和功率器件区交界处形成有一所述第一阱，作为JFET区和功率器件区的隔离。
5.根据权利要求2所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
6.根据权利要求5所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述功率器件区包括栅极，第二阱，设于所述第二阱内的第一导电类型的VDMOS源极，以及设于所述第二阱内、所述VDMOS源极下方的非钳位感性开关区；所述非钳位感性开关区为第二导电类型且离子浓度大于所述第二阱的离子浓度。
7.根据权利要求6所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述栅极的下方两侧各有一个第二阱，所述VDMOS源极形成于两个所述第二阱内，且所述VDMOS源极在两个所述第二阱的每一个内都分为两块，所述器件还包括形成于两块VDMOS源极之间的第二导电类型的欧姆接触区。
8.根据权利要求1-7中任意一项所述的集成有耗尽型结型场效应晶体管的器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
9.一种集成有耗尽型结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，其特征在于，所述方法包括：
提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；
向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；
先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；
注入第一导电类型的离子，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极；
光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质，形成沟道注入窗口，并向所述沟道注入窗口内注入第一导电类型的离子，形成横向沟道区；
光刻并刻蚀接触孔，淀积金属层，填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
10.根据权利要求9所述的方法，其特征在于，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱，作为JFET区和功率器件区的隔离。
11.根据权利要求9所述的方法，其特征在于，所述在所述第一导电类型区表面形成多晶硅层的步骤之后，还包括步骤：向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱，位于所述JFET区的所述第二阱分别形成于不同的所述第一阱内；
所述在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤，是通过向所述第二阱注入第一导电类型的离子，分别在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极。
12.根据权利要求11所述的方法，其特征在于，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质形成沟道注入窗口的步骤之前，还包括形成注入阻挡层的步骤，以及向所述功率器件区的所述第二阱中注入第二导电类型的离子，以在所述第二阱内所述功率器件源极的下方和JFET源极的下方形成非钳位感性开关区的步骤，且注入能量大于所述注入第一导电类型的离子的步骤的注入能量。
13.根据权利要求9-12中任一项所述的方法，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
14.根据权利要求13所述的方法，其特征在于，所述向所述沟道注入窗口内注入第一导电类型的离子的步骤中，注入的离子为砷离子，注入能量为100kev～180kev，注入剂量为2e12cm-2～7e12cm-2；或者注入的离子为磷离子，注入能量为60kev～120kev，注入剂量为2e12cm-2～7e12cm-2。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111415869A (zh) * 2019-01-04 2020-07-14 立锜科技股份有限公司 结型场效应晶体管制造方法
CN113937167A (zh) * 2021-10-20 2022-01-14 杭州芯迈半导体技术有限公司 Vdmos器件及其制造方法
CN116314338A (zh) * 2023-05-18 2023-06-23 深圳平创半导体有限公司 一种半导体结构及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112820778A (zh) * 2021-03-29 2021-05-18 厦门芯一代集成电路有限公司 一种新型的高压vdmos器件及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1190265A (zh) * 1997-01-27 1998-08-12 夏普公司 分路光电二极管
JP2000252475A (ja) * 1999-03-03 2000-09-14 Kansai Electric Power Co Inc:The 電圧制御型半導体装置とその製法及びそれを用いた電力変換装置
US6262459B1 (en) * 2000-01-18 2001-07-17 United Microelectronics Corp. High-voltage device and method for manufacturing high-voltage device
US6391723B1 (en) * 1999-05-31 2002-05-21 Stmicroelectronics S.R.L. Fabrication of VDMOS structure with reduced parasitic effects
US7211845B1 (en) * 2004-04-19 2007-05-01 Qspeed Semiconductor, Inc. Multiple doped channel in a multiple doped gate junction field effect transistor
CN102034820A (zh) * 2010-01-28 2011-04-27 崇贸科技股份有限公司 半导体装置
CN103035725A (zh) * 2011-09-30 2013-04-10 马克西姆综合产品公司 双栅极捆扎的vdmos器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923065A (en) 1996-06-12 1999-07-13 Megamos Corporation Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings
US6841812B2 (en) 2001-11-09 2005-01-11 United Silicon Carbide, Inc. Double-gated vertical junction field effect power transistor
TWI256536B (en) * 2004-06-25 2006-06-11 Richtek Techohnology Corp Single-chip co-drain junction FET device, step-down converter, step-up converter, inversed converter, switching device, and DC-to-DC converter applying the same
DE102006045312B3 (de) * 2006-09-26 2008-05-21 Siced Electronics Development Gmbh & Co. Kg Halbleiteranordnung mit gekoppelten Sperrschicht-Feldeffekttransistoren
US8674439B2 (en) * 2010-08-02 2014-03-18 Microsemi Corporation Low loss SiC MOSFET
CN102386185A (zh) * 2010-08-30 2012-03-21 苏州博创集成电路设计有限公司 一种高低压集成的工艺器件及其制备方法
US8841718B2 (en) * 2012-01-16 2014-09-23 Microsemi Corporation Pseudo self aligned radhard MOSFET and process of manufacture
CN103872137B (zh) * 2014-04-04 2017-01-25 厦门元顺微电子技术有限公司 增强型、耗尽型和电流感应集成vdmos功率器件
CN103928464B (zh) * 2014-04-18 2015-08-12 杭州士兰微电子股份有限公司 复合器件及开关电源
CN105679820B (zh) * 2016-03-16 2018-08-21 上海华虹宏力半导体制造有限公司 Jfet及其制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1190265A (zh) * 1997-01-27 1998-08-12 夏普公司 分路光电二极管
JP2000252475A (ja) * 1999-03-03 2000-09-14 Kansai Electric Power Co Inc:The 電圧制御型半導体装置とその製法及びそれを用いた電力変換装置
US6391723B1 (en) * 1999-05-31 2002-05-21 Stmicroelectronics S.R.L. Fabrication of VDMOS structure with reduced parasitic effects
US6262459B1 (en) * 2000-01-18 2001-07-17 United Microelectronics Corp. High-voltage device and method for manufacturing high-voltage device
US7211845B1 (en) * 2004-04-19 2007-05-01 Qspeed Semiconductor, Inc. Multiple doped channel in a multiple doped gate junction field effect transistor
CN102034820A (zh) * 2010-01-28 2011-04-27 崇贸科技股份有限公司 半导体装置
CN103035725A (zh) * 2011-09-30 2013-04-10 马克西姆综合产品公司 双栅极捆扎的vdmos器件

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111415869A (zh) * 2019-01-04 2020-07-14 立锜科技股份有限公司 结型场效应晶体管制造方法
CN113937167A (zh) * 2021-10-20 2022-01-14 杭州芯迈半导体技术有限公司 Vdmos器件及其制造方法
CN113937167B (zh) * 2021-10-20 2023-06-23 杭州芯迈半导体技术有限公司 Vdmos器件及其制造方法
CN116314338A (zh) * 2023-05-18 2023-06-23 深圳平创半导体有限公司 一种半导体结构及其制备方法
CN116314338B (zh) * 2023-05-18 2023-08-01 深圳平创半导体有限公司 一种半导体结构及其制备方法

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