WO2018040973A1 - 集成有耗尽型结型场效应晶体管的器件及其制造方法 - Google Patents

集成有耗尽型结型场效应晶体管的器件及其制造方法 Download PDF

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WO2018040973A1
WO2018040973A1 PCT/CN2017/098314 CN2017098314W WO2018040973A1 WO 2018040973 A1 WO2018040973 A1 WO 2018040973A1 CN 2017098314 W CN2017098314 W CN 2017098314W WO 2018040973 A1 WO2018040973 A1 WO 2018040973A1
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region
jfet
conductivity type
well
source
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PCT/CN2017/098314
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English (en)
French (fr)
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顾炎
程诗康
张森
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无锡华润上华科技有限公司
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Priority to JP2019511877A priority Critical patent/JP6770177B2/ja
Priority to EP17845275.1A priority patent/EP3509102A4/en
Priority to US16/329,348 priority patent/US10867995B2/en
Publication of WO2018040973A1 publication Critical patent/WO2018040973A1/zh

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Definitions

  • the present invention relates to semiconductor manufacturing technology, and more particularly to a device integrated with a depletion junction field effect transistor, and a method of fabricating a device integrated with a depletion junction field effect transistor.
  • JFET junction-effect transistor
  • the traditional high-voltage integrated JFET has a simpler process, but its pinch-off voltage instability and poor regulation limit its large-scale application in the field of intelligent power integration.
  • a device integrated with a depletion junction field effect transistor and a method of fabricating the same are provided.
  • a device integrated with a depletion junction field effect transistor the device being divided into a JFET region and a power device region, the device comprising: a first conductivity type drain, the drain portion for forming the a JFET region, a portion for forming the power device region; and a first conductivity type region disposed on a surface of the first conductivity type drain facing the front surface of the device, the first conductivity type region portion being used for forming
  • the JFET region is partially used to form the power device region;
  • the JFET region includes: a second conductivity type well region formed in the first conductivity type region, the first conductivity type and the second conductivity type Conversely; at least two JFET sources having a first conductivity type and formed on the second conductivity a type well region; a metal electrode of the JFET source is formed on the JFET source and in contact with the JFET source; and a lateral channel region is a first conductivity type formed between two adjacent JFET sources And the two ends of the lateral channel region
  • a method of fabricating a power device integrated with a depletion junction field effect transistor, the device comprising a JFET region and a power device region comprising: providing a substrate of a first conductivity type, the substrate being formed Having a first conductivity type region; the first conductivity type and the second conductivity type being opposite conductivity types; implanting a second conductivity type of ions into the first conductivity type region and pushing a well, in the first conductivity type region Forming a first well therein; growing a field oxide layer and a gate oxide layer on the surface of the device, and forming a polysilicon layer on the surface of the first conductive type region; implanting ions of the first conductivity type to form at least the JFET region a second JFET source, forming a power device source in the power device region; photolithography and etching to remove polysilicon and other surface dielectrics above the position between the two adjacent JFET sources to form a channel implantation window, and to Injecting ions of a first conductor.
  • the above device integrated with a depletion junction field effect transistor and a manufacturing method thereof can obtain a pinch-off voltage of different gear positions by adjusting an implantation dose and energy of a lateral channel region, and thus a JFET formed with a conventional longitudinal channel Compared to its pinch-off voltage regulation is more convenient. At the same time, since the lateral channel concentration is more uniform, the pinch-off voltage is also more stable.
  • FIG. 1 is a cross-sectional structural view of a device in which a depletion junction field effect transistor is integrated in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating a device in which a depletion junction field effect transistor is integrated in an embodiment
  • 3a-3d are schematic cross-sectional views of the device in the manufacturing process of the manufacturing method of Fig. 2.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • FIG. 1 is a schematic cross-sectional view of a device in which a depletion-type junction field effect transistor is integrated in an embodiment.
  • an N type is defined as a first conductivity type
  • a P type is a second conductivity type
  • a power device is VDMOS.
  • the device is divided into JFET regions and VDMOS by structure. Area.
  • the portion of the drain 201 of the N+ type disposed on the back side of the device i.e., the face facing downward in FIG. 1 is used to form a JFET region and a portion for forming a VDMOS region.
  • the N-type region 214 portion disposed on the front side of the drain 201 i.e., the upward facing surface in FIG.
  • the drain 201 is an N+ drain and the N-type region 214 is an N- epitaxial layer.
  • an N-type substrate can also be used directly as the N-type region 214.
  • the JFET region includes a lateral channel region 208, a JFET source 210, a JFET source metal electrode 212, a JFET metal gate 213, and a well region.
  • the N+ JFET source 210 is formed in the well region, and the lateral channel region 208 is an N-channel formed between the two adjacent JFET sources 210 and both ends are in contact with the two JFET sources 210.
  • a metal electrode 212 of the JFET source is formed on the JFET source 210 as a source contact of the JFET source 210.
  • a JFET metal gate 213 is formed over the well region.
  • the device integrated with the depletion junction field effect transistor can obtain the pinch-off voltage of different gear positions by adjusting the implantation dose and energy of the lateral channel region, and thus compared with the JFET formed by the conventional vertical channel.
  • the pinch-off voltage regulation is more convenient.
  • the pinch-off voltage is also more stable.
  • the well region is a composite well region structure composed of a first well 202 and a second well 205.
  • the composite well region structure is formed in the N- epitaxial layer, wherein the first well 202 is a P-well and the second well 205 is a high voltage P well located within the first well 202.
  • the ion concentration of the second well 205 is greater than the ion concentration of the first well 202.
  • a composite well region structure is formed on each side of the lateral channel region 208, and the second well 205 acts as an N-type contact of the device to form a conductive channel.
  • the composite well region Compared with a single P-well, the composite well region has a larger ion concentration, which prevents the drain terminal from being subjected to high voltage and causes the PN junction to be depleted. It will be appreciated that in other embodiments, the well region may also employ a single P-well or P-well structure.
  • lateral channel region 208 extends into second well 205 of the composite well region structure, and JFET source 210 is formed within second well 205 of the composite well region structure. It can be understood that in other embodiments, the two ends of the lateral channel region 208 may also be away from the second well 205 of the composite well region structure, and the JFET source 210 may be located outside the second well 205 of the composite well region structure, compounded.
  • a first well 202 is formed at the junction of the JFET region and the VDMOS region as isolation between the JFET region and the VDMOS region.
  • the first well 202 of P- is used to assist depletion and form isolation, and the deep P-well isolation can completely block the current flow path, prevent leakage between the JFET and the VDMOS, and can be used when the device is reverse biased.
  • the N-epitaxial layer (i.e., N-type region 214) under the auxiliary is involved in depletion, and the breakdown voltage of the local region is raised to cure the breakdown point.
  • the first well 202 serves as a depletion structure of the terminal in the junction terminal extension technology, and can effectively shorten the chip area of the high voltage VDMOS.
  • the junction depth of the P-well greatly exceeds the junction depth of the P-type substrate of the VDMOS in the conventional art, thereby having a long longitudinal current channel.
  • the pinch-off voltage stability of the device is increased more, and the pinch-off voltage is also significantly reduced.
  • the JFET region also includes a P-type JFET gate ohmic contact 211.
  • JFET gate ohmic contact 211 is formed in each of two second wells 205 on either side of lateral channel region 208 and is disposed on a side of JFET source 210 remote from lateral channel region 208.
  • JFET metal gate 213 is formed on JFET gate ohmic contact 211 and is in contact with JFET gate ohmic contact 211.
  • the ion concentration of the JFET gate ohmic contact 211 is greater than the ion concentration of the second well 205.
  • the VDMOS region includes a gate (the gate includes a gate oxide layer 203 and a polysilicon gate 204), a second well 205, an N+ VDMOS source 206 disposed in the second well 205, and A P-type Unclamped Inductive Switching (UIS) region 207 below the VDMOS source 206.
  • the ion concentration of the non-clamped inductive switch region 207 is greater than the ion concentration of the second well 205.
  • the JFET region is also formed with a non-clamped inductive switching region 207, specifically under the JFET source 210, and in the second well 205 of the JFET region in this embodiment, in other In the embodiment, it may also be outside the second well 205 of the JFET region and in the first well 202.
  • a second well 205 is formed on each of the lower sides of the gate, a VDMOS source 206 is formed in the two second wells 205, and the VDMOS source 206 is in the two second wells.
  • Each of the 205 is divided into two pieces.
  • the device also includes a P-type ohmic contact region 209 formed between the two VDMOS source 206.
  • FIG. 2 is a flow chart showing a method of fabricating a device in which a depletion junction field effect transistor is integrated in an embodiment.
  • the following device is a VDMOS, the first conductivity type is an N type, and the second conductivity type is a P type.
  • a method of manufacturing a device integrated with a depletion junction field effect transistor is described:
  • an N-type region 214 is epitaxially formed on the N+ substrate, and the substrate will subsequently serve as the drain 201 of the device.
  • FIG. 3a is a schematic cross-sectional view of the device after the step S520 is completed.
  • a thick field oxide layer 302 is grown on the surface of the device and then a gate oxide layer 304 is grown, and a polysilicon layer 604 is formed on the surface of the N-type region 214.
  • the well region of the JFET region is a composite well region structure composed of the first well 202 and the second well 205. Therefore, P-type ions are implanted into the N-type region 214 using the field oxide layer and the polysilicon layer 604 as a mask, and the wells are formed to form a plurality of second wells 205. Each of the second wells 205 of the JFET region is formed in a first well 202. The ion concentration of the second well 205 is greater than the ion concentration of the first well 202.
  • FIG. 3b is a schematic cross-sectional view of the device after the step S530 is completed.
  • a photolithography process is used to implant N-type ions with a photoresist as a mask, a JFET source is formed in a second well 205 of the JFET region, and a VDMOS source is formed in the second well 205 of the power device region.
  • Polar 206 The VDMOS source 206 is formed in each of the second wells 205 on both sides of the gate, and is divided into two in each of the second wells 205, leaving a position for the ohmic contact region 209 formed in the subsequent step.
  • a step of implanting P-type ions into the second well 205 is further included to form a non-clamping inductive property under the VDMOS source 206 in the second well 205.
  • Switch area 207 In order to prevent the P-type ion pair channel region implanted into the second well 205
  • the step of forming the implant barrier layer is further included before the step of implanting the P-type ions to form the unclamped inductive switch region 207.
  • the step of forming the implant barrier layer is further included before the step of implanting the P-type ions to form the unclamped inductive switch region 207.
  • the step of forming the implant barrier layer is further included before the step of implanting the P-type ions to form the unclamped inductive switch region 207.
  • the formation of the implantation barrier layer is performed by re-forming an oxide layer.
  • the oxide layer at the implantation window where the P-type ions are formed to form the unclamped inductive switch region 207 is thin, the high-energy implanted P-type ions can be worn.
  • the peroxide layer forms a non-clamped inductive switch region 207.
  • the oxide layer at other locations is formed on the structure of the field oxide layer, the polysilicon layer 604, etc., so that the thickness of the entire implant barrier layer is thick, and it is difficult for the P-type ions to pass through the implant barrier layer into the N-type region 214.
  • the medium for example, the field oxide layer, the implantation barrier layer
  • the polysilicon layer 604 above the position between the two adjacent JFET source 210 are removed by photolithography and etching, and then the N-type impurity is implanted.
  • a lateral channel region 208 is formed between the surface of the N-type region 214 and between two adjacent JFET source 210.
  • the excess polysilicon layer 604 is removed to form the polysilicon gate 204 shown in FIG. Figure 3d is a schematic cross-sectional view of the device after completion of step S550.
  • the method further comprises: implanting P-type ions into the contact hole, forming a JFET gate ohmic contact 211 in the second well 205 of the JFET region, respectively, and a second well 205 in the power device region.
  • the metal filled in the contact hole is in contact with the JFET gate ohmic contact 211 to form a JFET metal gate 213 which is in contact with the JFET source 210 to form a JFET source metal electrode 212.
  • a passivation layer is formed on the surface of the device, and the cross section of the device is completed as shown in FIG.
  • the above-mentioned device integrated with depletion-type junction field effect transistor improves the stability of the pinch-off voltage on the basis of the conventional technology, solidifies the breakdown point, strengthens the UIS capability, perfectly matches the process, and realizes The adjustable size of the pinch-off voltage.
  • step S520 includes forming a first well 202 at the junction of the JFET region and the power device region as isolation of the JFET region and the power device region.
  • the first well 202 of step S520 has an implantation concentration of 1.5E13 cm -2 to 2.2 E13 cm -2 , and the first well 202 has a well depth of 8.5 ⁇ m to 13.5 ⁇ m.
  • the N-type ions implanted in step S550 are made of As (arsenic) or P (phosphorus), and for the arsenic ions, the injected energy is 100 keV to 180 keV.
  • the dose is 2e12cm -2 to 7e12cm -2 ; for phosphorus ions, the implantation energy is 60kev ⁇ 120kev, and the implantation dose is 2e12cm -2 ⁇ 7e12cm -2 .

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Abstract

一种集成有耗尽型结型场效应晶体管的功率器件及其制造方法，该器件包括：阱区，为第二导电类型且形成于第一导电类型区(214)内；JFET源极(210)，为第一导电类型且形成于阱区内；JFET源极的金属电极(212)，形成于JFET源极(210)上且与JFET源极(210)接触；横向沟道区(208)，为第一导电类型，形成于两相邻JFET源极(210)之间且两端与两相邻JFET源极(210)接触；JFET金属栅极(213)，形成于阱区上。

Description

集成有耗尽型结型场效应晶体管的器件及其制造方法 技术领域
本发明涉及半导体制造技术，特别是涉及一种集成有耗尽型结型场效应晶体管的器件，还涉及一种集成有耗尽型结型场效应晶体管的器件的制造方法。
背景技术
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。
传统结构的高压集成JFET有较简单的工艺可以实现，但其夹断电压的不稳定和调控性较差等特性限制了其在智能功率集成领域的大规模应用。
发明内容
根据本申请的各种实施例，提供一种集成有耗尽型结型场效应晶体管的器件及其制造方法。
一种集成有耗尽型结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：第一导电类型漏极，所述漏极部分用于形成所述JFET区、部分用于形成所述功率器件区；及第一导电类型区，设于所述第一导电类型漏极朝向所述器件正面的面上，所述第一导电类型区部分用于形成所述JFET区、部分用于形成所述功率器件区；所述JFET区包括：第二导电类型阱区，形成于所述第一导电类型区内，所述第一导电类型和第二导电类型相反；至少二JFET源极，具有第一导电类型且形成于所述第二导电 类型阱区内；JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；横向沟道区，为第一导电类型，形成于两相邻JFET源极之间，且所述横向沟道区两端与所述两相邻JFET源极接触；及JFET金属栅极，形成于所述第二导电类型阱区上。
一种集成有耗尽型结型场效应晶体管的功率器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；在所述器件表面先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；注入第一导电类型的离子，在所述JFET区形成至少二JFET源极、在所述功率器件区形成功率器件源极；光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质形成沟道注入窗口，并向所述沟道注入窗口内注入第一导电类型的离子，形成横向沟道区；光刻并刻蚀接触孔，淀积金属层填入所述接触孔内分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
上述集成有耗尽型结型场效应晶体管的器件及其制造方法，可以通过调节横向沟道区的注入剂量和能量，得到不同档位的夹断电压，因而与传统的纵向沟道形成的JFET相比，其夹断电压调控更加方便。同时由于横向沟道浓度更加均匀，其夹断电压也会更加稳定。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中集成有耗尽型结型场效应晶体管的器件的剖面结构示意图；
图2是一实施例中集成有耗尽型结型场效应晶体管的器件的制造方法的流程图；
图3a～3d是图2所述的制造方法在制造过程中的器件剖面结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中集成有耗尽型结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，功率器件为VDMOS。如图1中所示，将器件按结构分为JFET区和VDMOS 区。设于器件背面(即图1中朝下的面)的N+型的漏极201部分用于形成JFET区、部分用于形成VDMOS区。同样的，设于漏极201正面(即图1中朝上的面)的N-型区214部分用于形成JFET区、部分用于形成VDMOS区。在本实施例中，漏极201为N+漏极，N型区214为N-外延层。在其他实施例中，也可以直接使用N型衬底作为N型区214。
在本实施例中，JFET区包括横向沟道区208、JFET源极210、JFET源极的金属电极212、JFET金属栅极213以及阱区。
其中N+的JFET源极210形成于阱区内，横向沟道区208为N-沟道，形成于两相邻JFET源极210之间且两端与这两个JFET源极210接触。JFET源极的金属电极212形成于JFET源极210上，作为JFET源极210的源极接触。JFET金属栅极213形成于阱区上。
上述集成有耗尽型结型场效应晶体管的器件，可以通过调节横向沟道区的注入剂量和能量，得到不同档位的夹断电压，因而与传统的纵向沟道形成的JFET相比，其夹断电压调控更加方便。同时由于横向沟道浓度更加均匀，其夹断电压也会更加稳定。
在图1所示实施例中，阱区为由第一阱202和第二阱205组成的复合阱区结构。复合阱区结构形成于N-外延层内，其中第一阱202为P-阱，第二阱205为位于第一阱202内的高压P阱。第二阱205的离子浓度大于第一阱202的离子浓度。在一个元胞内，横向沟道区208的两侧各形成有一个复合阱区结构，第二阱205作为器件的N型接触，形成导电沟道。
复合阱区结构与单一的P-阱相比，其离子浓度更大，可以防止漏端加高压导致PN结的耗尽穿通。可以理解的，在其他实施例中，阱区也可以采用单一的P阱或P-阱结构。
在图1所示实施例中，横向沟道区208延伸至复合阱区结构的第二阱205内，JFET源极210形成于复合阱区结构的第二阱205内。可以理解的，在其他实施例中横向沟道区208的两端也可以距复合阱区结构的第二阱205一段距离，JFET源极210可以位于复合阱区结构的第二阱205外、复合阱区结构 的第一阱202内。
在图1所示实施例中，JFET区和VDMOS区交界处形成有一个第一阱202，作为JFET区和VDMOS区的隔离。利用P-的第一阱202辅助耗尽、形成隔离，通过较深的P-阱隔离，可以完全阻断电流的流通路径，防止JFET和VDMOS间的漏电，且在器件反偏耐压时可以辅助下方的N-外延层(即N型区214)参与耗尽，提升局部区域的击穿电压来固化击穿点作用。同时，该第一阱202作为结终端扩展技术中终端的耗尽结构，能够有效缩短高压VDMOS的芯片面积。另外由于该结终端扩展的结工艺存在，P-阱结深大大超过了传统技术中VDMOS的P型衬底的结深，从而有了较长的纵向电流沟道。相较于传统结构，器件的夹断电压稳定性会提高较多，同时夹断电压也会显著降低。
在图1所示实施例中，JFET区还包括P型的JFET栅极欧姆接触211。JFET栅极欧姆接触211在横向沟道区208两侧的两个第二阱205内各形成有一个，且设于JFET源极210远离横向沟道区208的一侧。JFET金属栅极213形成于JFET栅极欧姆接触211上且与JFET栅极欧姆接触211相接触。在本实施例中，JFET栅极欧姆接触211的离子浓度大于第二阱205的离子浓度。
在图1所示实施例中，VDMOS区包括栅极(栅极包括栅氧层203和多晶硅栅204)、第二阱205、设于第二阱205内的N+的VDMOS源极206、以及设于VDMOS源极206下方的P型的非钳位感性开关(Unclamped Inductive Switching，UIS)区207。非钳位感性开关区207的离子浓度大于第二阱205的离子浓度。在图1所示实施例中，JFET区也形成有非钳位感性开关区207，具体是设于JFET源极210下方，且在本实施例中为JFET区的第二阱205内，在其他实施例中也可以是JFET区的第二阱205外、第一阱202内。
在图1所示实施例中，栅极的下方两侧各有一个第二阱205，VDMOS源极206形成于这两个第二阱205内，且VDMOS源极206在这两个第二阱205的每一个内都分为两块。器件还包括形成于两块VDMOS源极206之间的P型的欧姆接触区209。
图2是一实施例中集成有耗尽型结型场效应晶体管的器件的制造方法的流程图，以下一器件是VDMOS，第一导电类型是N型，第二导电类型是P型为例，介绍集成有耗尽型结型场效应晶体管的器件的制造方法：
S510，提供第一导电类型的衬底，衬底上形成有第一导电类型区。
在本实施例中，是在N+衬底上外延形成N型区214，衬底后续将会作为器件的漏极201。
S520，注入第二导电类型的离子并推阱，在第一导电类型区内形成第一阱。
在本实施例中，是向N型区214中注入P型离子并推阱，在N型区214内形成第一阱202。图3a是步骤S520完成后器件的剖面结构示意图。
S530，生长场氧层和栅氧层，并形成多晶硅层。
在器件表面生长厚的场氧层302然后生长栅氧层304，并在N型区214表面形成多晶硅层604。在本实施例中，JFET区的阱区为由第一阱202和第二阱205组成的复合阱区结构。故以场氧层和多晶硅层604为掩膜向N型区214注入P型离子，推阱形成多个第二阱205。其中JFET区的每一第二阱205各形成于一第一阱202内。第二阱205的离子浓度大于第一阱202的离子浓度。图3b是步骤S530完成后器件的剖面结构示意图。
S540，注入第一导电类型的离子，在JFET区形成JFET源极、在功率器件区形成功率器件源极。
在本实施例中，是用光刻工艺以光刻胶为掩膜注入N型离子，在JFET区的第二阱205内形成JFET源极，在功率器件区的第二阱205内形成VDMOS源极206。其中VDMOS源极206形成于栅极两侧的各一个第二阱205内，且在每个第二阱205内都分成两块，中间留出给后续步骤形成的欧姆接触区209的位置。
参见图3c，在本实施例中，在执行步骤S550之前，还包括向第二阱205中注入P型离子的步骤，以在第二阱205内的VDMOS源极206的下方形成非钳位感性开关区207。为了防止向第二阱205中注入的P型离子对沟道区 造成不利影响，本实施例中在注入P型离子形成非钳位感性开关区207的步骤之前，还包括形成注入阻挡层的步骤。在本实施例中形成注入阻挡层是通过再形成一层氧化层，由于注入P型离子形成非钳位感性开关区207的注入窗口处的氧化层较薄，因此高能注入的P型离子可以穿过氧化层形成非钳位感性开关区207。而其他位置处的氧化层形成于场氧层、多晶硅层604等结构上，因此整个注入阻挡层的厚度较厚，P型离子难以穿过注入阻挡层进入N型区214内。
S550，光刻并刻蚀去除多晶硅及其它表面介质，注入第一导电类型的离子，形成横向沟道区。
在本实施例中，是通过光刻和刻蚀去除两相邻JFET源极210之间的位置上方的介质(例如场氧层、注入阻挡层)和多晶硅层604，然后注入N型杂质，在N型区214的表面、两相邻JFET源极210之间形成横向沟道区208。多余的多晶硅层604被去除后形成图1所示的多晶硅栅204。图3d是步骤S550完成后器件的剖面结构示意图。
S560，光刻并刻蚀接触孔，淀积金属层，填入接触孔内，形成JFET源极的金属电极和JFET金属栅极。
在本实施例中，刻蚀出接触孔后还包括向接触孔内注入P型离子，分别在JFET区的第二阱205内形成JFET栅极欧姆接触211，在功率器件区的第二阱205内形成欧姆接触区209的步骤。填入接触孔的金属与JFET栅极欧姆接触211相接触形成JFET金属栅极213，与JFET源极210相接触形成JFET源极的金属电极212。淀积金属层后在器件表面形成钝化层，完成后器件的剖面如图1所示。
综合上述优势，上述集成有耗尽型结型场效应晶体管的器件在传统技术的基础上提升了夹断电压的稳定性，固化了击穿点，加强了UIS能力，工艺上完全匹配，并且实现了夹断电压大小的可调性。
在其中一个实施例中，步骤S520包括在JFET区和功率器件区交界处形成一个第一阱202作为JFET区和功率器件区的隔离。
在其中一个实施例中，步骤S520的第一阱202的注入浓度为1.5E13cm-2～2.2E13cm-2，第一阱202的阱深为8.5微米～13.5微米。
在其中一个实施例中，对于夹断电压在5V～15V范围内的器件，步骤S550注入的N型离子采用As(砷)或P(磷)，对于砷离子，注入能量为100kev～180keV，注入剂量为2e12cm-2～7e12cm-2；对于磷离子，注入能量为60kev～120kev，注入剂量为2e12cm-2～7e12cm-2。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种集成有耗尽型结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：
    第一导电类型漏极，所述漏极部分用于形成所述JFET区、部分用于形成所述功率器件区；及
    第一导电类型区，设于所述第一导电类型漏极朝向所述器件正面的面上，所述第一导电类型区部分用于形成所述JFET区、部分用于形成所述功率器件区；所述JFET区包括：
    第二导电类型阱区，形成于所述第一导电类型区内，所述第一导电类型和第二导电类型相反；
    至少二JFET源极，具有第一导电类型且形成于所述第二导电类型阱区内；
    JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；
    横向沟道区，为第一导电类型，形成于两相邻JFET源极之间，且所述横向沟道区两端与所述两相邻JFET源极接触；及
    JFET金属栅极，形成于所述第二导电类型阱区上。
  2. 根据权利要求1所述的器件，其特征在于，所述第二导电类型阱区包括第一阱和位于所述第一阱内的第二阱，所述第二阱的离子浓度大于所述第一阱的离子浓度。
  3. 根据权利要求1所述的器件，其特征在于，所述JFET区还包括至少两个JFET栅极欧姆接触，所述JFET栅极欧姆接触在所述两相邻JFET源极所在的第二导电类型阱区内各形成有一个，且设于JFET源极远离所述横向沟道区的一侧，具有第二导电类型；所述JFET金属栅极形成于所述JFET栅极欧姆接触上且与所述JFET栅极欧姆接触相接触。
  4. 根据权利要求2所述的器件，其特征在于，所述第一阱设于所述JFET 区和功率器件区的交界处，用于将所述JFET区和功率器件区隔离。
  5. 根据权利要求1所述的器件，其特征在于，所述功率器件是VDMOS。
  6. 根据权利要求5所述的，其特征在于，所述功率器件区包括：
    栅极；
    第二阱；
    VDMOS第一导电类型源极，设于所述第二阱内；以及
    第一非钳位感性开关区，设于所述第二阱内、所述VDMOS第一导电类型源极下方，具有第二导电类型且离子浓度大于所述第二阱的离子浓度。
  7. 根据权利要求6所述的器件，其特征在于，还包括第二非钳位感性开关区，设于所述JFET源极下方、所述第二阱内，具有第二导电类型且离子浓度大于所述第二阱的离子浓度。
  8. 根据权利要求6所述的器件，其特征在于，所述栅极的下方两侧各有一个第二阱，所述VDMOS第一导电类型源极形成于这两个第二阱内，且所述VDMOS第一导电类型源极在这两个第二阱的每一个内都分为两块。
  9. 根据权利要求8所述的器件，其特征在于，还包括形成于两块VDMOS第一导电类型源极之间的第二导电类型欧姆接触区。
  10. 根据权利要求1所述的器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
  11. 一种集成有耗尽型结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：
    提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型相反；
    向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；
    在所述第一导电类型区表面先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；
    注入第一导电类型的离子，在所述JFET区形成至少二JFET源极、在所 述功率器件区形成功率器件源极；
    光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质，形成沟道注入窗口，并向所述沟道注入窗口内注入第一导电类型的离子，形成横向沟道区；及
    光刻并刻蚀接触孔，淀积金属层，填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
  12. 根据权利要求11所述的方法，其特征在于，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱，作为JFET区和功率器件区的隔离。
  13. 根据权利要求11所述的方法，其特征在于，所述在所述第一导电类型区表面形成多晶硅层的步骤之后，还包括步骤：向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱，位于所述JFET区的所述第二阱分别形成于不同的所述第一阱内。
  14. 根据权利要求11所述的方法，其特征在于，所述在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤，是通过向所述第二阱注入第一导电类型的离子，分别在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极。
  15. 根据权利要求13所述的方法，其特征在于，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述光刻并刻蚀去除两相邻JFET源极之间的位置上方的多晶硅及其它表面介质形成沟道注入窗口的步骤之前，还包括向所述功率器件区的所述第二阱中注入第二导电类型的离子，以在所述第二阱内所述功率器件源极的下方和JFET源极的下方形成非钳位感性开关区的步骤，且注入能量大于所述注入第一导电类型的离子的步骤的注入能量。
  16. 根据权利要求15所述的方法，其特征在于，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述向所述功率器件区的所述第二阱中注入第二导电类型的离子的步骤之前，还包括形成注入 阻挡层的步骤。
  17. 根据权利要求11所述的方法，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层，所述功率器件是VDMOS。
  18. 根据权利要求11所述的方法，其特征在于，所述向所述沟道注入窗口内注入第一导电类型的离子的步骤中，注入的离子为砷离子，注入能量为100kev～180kev，注入剂量为2e12cm-2～7e12cm-2；或者注入的离子为磷离子，注入能量为60kev～120kev，注入剂量为2e12cm-2～7e12cm-2。
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