WO2018041192A1 - 集成有结型场效应晶体管的器件及其制造方法 - Google Patents

集成有结型场效应晶体管的器件及其制造方法 Download PDF

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WO2018041192A1
WO2018041192A1 PCT/CN2017/099841 CN2017099841W WO2018041192A1 WO 2018041192 A1 WO2018041192 A1 WO 2018041192A1 CN 2017099841 W CN2017099841 W CN 2017099841W WO 2018041192 A1 WO2018041192 A1 WO 2018041192A1
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region
jfet
conductivity type
well
type
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PCT/CN2017/099841
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English (en)
French (fr)
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顾炎
程诗康
张森
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无锡华润上华科技有限公司
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Priority to US16/329,550 priority Critical patent/US10872823B2/en
Priority to JP2019511843A priority patent/JP6986553B2/ja
Priority to EP17845494.8A priority patent/EP3509110A4/en
Publication of WO2018041192A1 publication Critical patent/WO2018041192A1/zh

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    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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Definitions

  • the present invention relates to semiconductor manufacturing technology, and more particularly to a device integrated with a junction field effect transistor, and to a method of fabricating a device incorporating a junction field effect transistor.
  • JFET junction-effect transistor
  • the traditional high-voltage integrated JFET has a simpler process, but its unstable pinch-off voltage limits its large-scale application in the field of intelligent power integration.
  • VDMOS vertical double-diffused metal-oxide-semiconductor field-effect transistor
  • the JFET absorbs the abrupt current of the VDMOS on the Miller platform, which makes the start-up more gradual, and the current can be approximately linearly transformed. Therefore, the JFET has a significant effect on the stability of the device during the startup process. Power devices have the advantage of integrating parasitic JFETs on their process platforms.
  • the most important characteristic of the integrated parasitic JFET is the stability of the overall breakdown voltage and the stability of the pinch-off voltage.
  • the breakdown voltage of the integrated device remains unchanged, and the breakdown point is preferably kept at The breakdown point of the power VDMOS.
  • the traditional integrated structure VDMOS and JFET interface is only isolated by the substrate, and can only lengthen the lateral distance of the substrate extension to ensure the margin when depleted, which will increase the area of the entire die.
  • the breakdown point will be transferred from the cell (cell) region of the body to the JFET region or the junction, greatly reducing the breakdown.
  • the stability of the breakdown voltage also occurs.
  • Conventional structures generally use a self-aligned P-type implanted substrate as a P-type pinch-off substrate. Since the P-type substrate of the cell region of the VDMOS has a shallow longitudinal depth, generally only 3 to 5 ⁇ m, the longitudinal trench of the JFET The track is very short, and it is impossible to adjust the longitudinal channel length, so the pinch-off voltage is very unstable. It can be seen from the simulation that when the drain voltage changes from 50V to 100V, the pinch-off voltage Voff will increase from 11V to 20V, and Voff is required to be stable in practical applications, so the conventional structure is difficult to meet the actual demand.
  • a device integrated with a junction field effect transistor the device being divided into a JFET region and a power device region, the device comprising: a drain having a first conductivity type, a portion of the drain being located in the JFET region Another portion is located in the power device region; and a first conductivity type region is disposed on a front surface of the drain, a portion of the first conductivity type region is located in the JFET region, and another portion is located in the power device region;
  • the JFET region includes: a first well having a second conductivity type and formed in the first conductivity type region; and a second well having a second conductivity type and formed in the first conductivity type region, ion concentration An ion concentration greater than the first well; the first conductivity type and the second conductivity type being opposite; a JFET source having a first conductivity type; a metal electrode formed on the JFET source and the JFET source a pole contact; and a second conductivity type buried layer formed under the JFET source and the
  • a method of fabricating a device incorporating a junction field effect transistor, the device comprising a JFET region and a power device region comprising: providing a substrate of a first conductivity type, the substrate being formed with a first conductivity a type of region; the first conductivity type and the second conductivity type are opposite conductivity types; forming a second conductivity type buried in the first conductivity type region of the JFET region a layer; implanting ions of a second conductivity type into the first conductivity type region and pushing a well, forming a first well in the first conductivity type region; sequentially growing a field oxide layer and a gate oxide layer, and at the first Forming a polysilicon layer on the surface of the conductive type region; implanting ions of the second conductivity type into the first conductivity type region and pushing the well to form a plurality of second wells; implanting ions of the first conductivity type, forming a JFET source in the JFET region Forming a power device source in the power device region
  • FIG. 1 is a cross-sectional structural view of a device in which a junction field effect transistor is integrated in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating a device in which a junction field effect transistor is integrated in an embodiment
  • FIG. 3a-3d are schematic cross-sectional views of the manufacturing method of Fig. 2 in the process of fabricating a device.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • FIG. 1 is a schematic cross-sectional view of a device in which a junction field effect transistor is integrated in an embodiment.
  • an N type is defined as a first conductivity type
  • a P type is a second conductivity type
  • the device is a VDMOS.
  • the device is divided into a JFET region and a VDMOS region by structure, and an N-type drain 201 portion provided on the back surface of the device (ie, the face facing downward in FIG. 1) is used to form a JFET region, and a portion is used for Form a VDMOS area.
  • the N-type regions (including the first N-type region 202 and the second N-type region 204) disposed on the front side of the drain 201 (ie, the upward facing surface in FIG. 1) are used to form a JFET region and a portion for forming. VDMOS area.
  • the drain 201 is an N+ drain and the N-type region is an N- epitaxial layer.
  • the N-type is divided into two epitaxes to form the first N-type region 202 and the second N-type region 204, respectively. It will be understood that in other embodiments, the desired P-type buried layer is formed.
  • the N-type region can also be a single-layer structure.
  • the variation of the thickness and concentration of the epitaxial layer changes the pinch-off voltage.
  • the thickness is generally greater than 4 microns, typically 4 microns to 7 microns, and the pinch-off effect is better.
  • the JFET region includes:
  • the first well 205 is a P-well and is formed in the N-type region.
  • the second well 207 is a high voltage P well and is formed in the N-type region, and the ion concentration is greater than the ion concentration of the first well 205.
  • a conductive channel is formed as an N-type contact of the device.
  • JFET source 212 N+ JFET source 212 is the source contact of the JFET.
  • a metal electrode of the JFET source is formed on JFET source 212 and in contact with JFET source 212.
  • a P-type buried layer 203 is formed under the JFET source 212 and the second well 207.
  • the device integrated with the junction field effect transistor utilizes a lateral channel formed by the P-type buried layer 203 and the second well 207 to make the channel concentration more uniform, and a longer lateral channel is designed by the layout, and the pinch-off is performed.
  • the voltage will be more stable.
  • a first well 205 is also formed at the junction of the JFET region and the VDMOS region as an isolation well for isolating the JFET region from the VDMOS region.
  • the first well 205 of P- is used to assist the depletion isolation. Through the deep P-well isolation, the current flow path can be completely blocked, the leakage between the JFET and the VDMOS can be prevented, and the device can be assisted under the reverse bias voltage.
  • the N- epitaxial layer ie, the first N-type region 202 participates in depletion, boosting the breakdown voltage of the local region to cure the breakdown point effect.
  • the first well 205 functions as a depletion structure of the terminal in the junction terminal extension technology, and can effectively shorten the chip area of the high voltage VDMOS.
  • the junction depth of the first well 205 greatly exceeds the junction depth of the P-type substrate of the VDMOS in the conventional art, thereby having a long longitudinal current channel.
  • the pinch-off voltage stability of the device is increased more, and the pinch-off voltage is also significantly reduced.
  • the JFET region also includes a JFET metal gate 213 and a JFET gate ohmic contact 214.
  • JFET metal gate 213 is formed on JFET gate ohmic contact 214 and is in contact with JFET gate ohmic contact 214.
  • Each JFET gate ohmic contact 214 is formed in a first well 205 and a second well 207 of the JFET region, respectively, and each JFET gate ohmic contact 214 is equipotically coupled together by a JFET metal gate 213.
  • the P-type buried layer 203 is in contact with at least a first well 205.
  • a P-type buried layer 203 is formed on each of the lower sides of the second well 207.
  • P-type buried Layer 203 is in contact with a first well 205, respectively.
  • the first well 205 formed by the deep well diffusion is connected to the P-type buried layer 203, and the potential of the P-type buried layer 203 can be extracted, thereby avoiding the floating of the P-type buried layer 203, so that the pinch-off voltage is in accordance with the drain voltage. Change is more stable.
  • JFET source 212 is formed between second well 207 and first well 205 (one first well 205 adjacent second well 207).
  • the VDMOS region includes a gate 206, a second well 207, an N+ VDMOS source 209 disposed in the second well 207, and a P++ type non-clamp disposed under the VDMOS source 209.
  • the ion concentration of the non-clamped inductive switch region 208 is greater than the ion concentration of the second well 207.
  • the JFET region is also formed with a non-clamped inductive switching region 208, specifically below the JFET gate ohmic contact 214 disposed in the second well 207, and in this embodiment is a second In the well 207, in other embodiments, the second well 207 may be outside the first well 205.
  • the unclamped inductive switching region 208 can reduce the base resistance of the parasitic NPN transistor and increase the avalanche tolerance of the device.
  • the VDMOS source 209 is formed in the two second wells 207, and the VDMOS source 209 is in the two second Each of the wells 207 is divided into two.
  • the device also includes a P+ type ohmic contact region 210 formed between two VDMOS source electrodes 209.
  • FIG. 2 is a flow chart of a method for fabricating a device in which a junction field effect transistor is integrated in an embodiment.
  • the device is VDMOS, the first conductivity type is N type, and the second conductivity type is P type.
  • Method of manufacturing a device for a junction field effect transistor :
  • Step S510 providing a substrate of a first conductivity type on which a first conductivity type region is formed.
  • an N-type region is epitaxially formed on the N+ substrate, and the substrate will subsequently serve as the drain 201 of the device.
  • Step S520 forming a second conductivity type buried layer in the first conductivity type region of the JFET region.
  • the first conductivity type region includes a first epitaxial layer (ie, a first N-type layer 202) and a second epitaxial layer (ie, a second N-type layer 204).
  • Step S520 is to perform photolithography, P-type ion implantation and push-pull formation of the P-type buried layer 203 on the first epitaxial layer
  • FIG. 3a is a cross-section of the device after the P-type buried layer 203 is formed. Schematic diagram of the surface structure. After the P-type buried layer 203 is formed, a second epitaxial layer is formed on the surface of the first epitaxial layer. The P-type buried layer 203 is in contact with at least a first well 205.
  • Step S530 injecting ions of the second conductivity type and pushing the well to form a first well in the first conductivity type region.
  • a P-type ion is implanted into the N-type region and the well is pushed, and a first well 205 is formed in the N-type region.
  • Step S540 growing a field oxide layer and a gate oxide layer, and forming a polysilicon layer.
  • a thick field oxide layer is grown on the surface of the N-type region and then a gate oxide layer is grown, and a polysilicon layer 604 is formed on the surface of the N-type region.
  • Step S550 injecting ions of the second conductivity type into the first conductivity type region and pushing the well to form a plurality of second wells.
  • FIG. 3b is a schematic cross-sectional view of the device after the step S550 is completed.
  • the method before performing step S560, the method further includes the step of implanting P-type ions into the second well 207 to form an unclamped inductive switch region in the JFET region and the second well 207 of the power device region. 208.
  • the step of forming the implant barrier layer is further included in the present embodiment before the step of implanting the P-type ions to form the unclamped inductive switch region 208.
  • the formation of the implantation barrier layer is performed by re-forming an oxide layer.
  • the oxide layer at the implantation window where the P-type ions are formed to form the unclamped inductive switching region 208 is thin, the high-energy implanted P-type ions can be worn.
  • the peroxide layer forms a non-clamped inductive switching region 208.
  • the oxide layer at other positions is formed on the structure of the field oxide layer, the polysilicon layer 604, etc., so that the thickness of the entire implant barrier layer is thick, and it is difficult for the P-type ions to pass through the injection barrier layer into the N-type region.
  • Step S560 implanting ions of the first conductivity type, forming a JFET source in the JFET region, and forming a power device source in the power device region.
  • a N-type ion is implanted by using a photoresist as a mask by a photolithography process.
  • a JFET source is formed in the second well 207 of the JFET region, and a VDMOS source 209 is formed in the second well 207 of the power device region.
  • the VDMOS source 209 is formed in each of the second wells 207 on both sides of the gate, and is divided into two in each of the second wells 207, leaving a position for the ohmic contact region 210 formed in the subsequent step.
  • the step of forming the gate ohmic contact 214 and the ohmic contact region 210 in the first well 205 and the second well 207 is further included. Specifically, a JFET gate ohmic contact 214 is formed in the first well 205 and the second well 207 of the JFET region, and an ohmic contact region 210 is formed in the second well 207 of the power device region.
  • Step S570 photolithography and etching the contact holes, depositing a metal layer, filling the contact holes to form a metal contact of the JFET source metal electrode, the JFET metal gate, and the power device source.
  • the metal filled in the contact hole contacts the JFET gate ohmic contact 214 to form a JFET metal gate 213 that contacts the JFET source 212 to form a JFET source metal electrode.
  • a passivation layer is formed on the surface of the device, and the cross section of the device is completed as shown in FIG.
  • the above-mentioned device integrated with a junction field effect transistor improves the stability of the pinch-off voltage on the basis of the conventional technology, solidifies the breakdown point, strengthens the UIS capability, perfectly matches the process, and realizes pinch-off. Adjustable voltage size.
  • step S520 includes forming a first well 205 as an isolation well at the junction of the JFET region and the power device region for isolating the JFET region from the power device region.
  • the first well 205 of step S530 has an implant concentration of 1.5E13 cm -2 to 2.2 E13 cm -2 , and the well depth of the first well 205 is 8.5 ⁇ m to 13.5 ⁇ m.

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Abstract

一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：漏极（201），具有第一导电类型，所述漏极（201）的一部分位于所述JFET区、另一部分位于所述功率器件区；及第一导电类型区，设于所述漏极（201）的正面，所述第一导电类型区的一部分位于所述JFET区、另一部分位于所述功率器件区；所述JFET区包括：第一阱（205），具有第二导电类型且形成于所述第一导电类型区内；第二阱（207），具有第二导电类型且形成于所述第一导电类型区内，离子浓度大于所述第一阱（205）的离子浓度；所述第一导电类型和第二导电类型相反；JFET源极（212），具有第一导电类型；金属电极，形成于所述JFET源极（212）上且与所述JFET源极（212）接触；及第二导电类型埋层（203），形成于所述JFET源极（212）和第二阱（207）下方。

Description

集成有结型场效应晶体管的器件及其制造方法 技术领域
本发明涉及半导体制造技术，特别是涉及一种集成有结型场效应晶体管的器件，还涉及一种集成有结型场效应晶体管的器件的制造方法。
背景技术
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。
传统结构的高压集成JFET有较简单的工艺可以实现，但其夹断电压的不稳定的特性限制了其在智能功率集成领域的大规模应用。
对于一种传统的集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)的垂直双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffused MOSFET，VDMOS)，当VDMOS处于开启阶段时，电流从底部漏端流过JFET，从source2流出。当source2上加逐渐变大的电压Vg2，同时栅gate上也加同样的电压Vg1，当Vg2＞夹断电压Voff时，JFET的耗尽层阻断了电流，即发生了夹断。此时Vg1＞Vth，Vth为VDMOS的阈值电压，VDMOS开启，完成了一个开启过程。JFET在此吸收了VDMOS在米勒平台时的突变电流，让启动更为平缓，电流可以成近似线性变换，所以JFET在启动过程中对器件稳定性提升有着很显著作用。功率器件在其工艺平台上集成寄生JFET则更具有优势。
集成寄生JFET，其最主要特性是整体击穿电压的稳定性和夹断电压的稳定性，最为理想的是，集成后器件的击穿电压保持不变，击穿点最好保持在 功率VDMOS的击穿点。传统的集成结构VDMOS与JFET交接处仅用了衬底进行隔离，仅可以拉长衬底外延的横向距离来保证耗尽时的余量，这样会增加整个管芯的面积。同时，由于外延层规范有所偏差，工艺上略有变动就会出现击穿点转移，击穿点会从体内的cell(元胞)区转移至JFET区或是交接处，大大降低了击穿的稳定性，还会发生击穿电压蠕变的现象。传统结构一般用自对准P型注入的衬底作为P型夹断衬底，由于VDMOS的cell区的P型衬底其纵向结深很浅，一般只有3～5微米，因此JFET的纵向沟道很短，人为无法去调整纵向沟道长度，所以夹断电压很不稳定。通过仿真可得知当漏端电压从50V到100V变化时，夹断电压Voff会从11V变大至20V，而在实际应用中需要Voff稳定，因此该传统结构难以满足实际需求。
发明内容
根据本申请的各实施例，有必要针对传统的JFET夹断电压不稳定的问题，提供一种集成有结型场效应晶体管的器件及其制造方法。
一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：漏极，具有第一导电类型，所述漏极的一部分位于所述JFET区、另一部分位于所述功率器件区；及第一导电类型区，设于所述漏极的正面，所述第一导电类型区的一部分位于所述JFET区、另一部分位于所述功率器件区；所述JFET区包括：第一阱，具有第二导电类型且形成于所述第一导电类型区内；第二阱，具有第二导电类型且形成于所述第一导电类型区内，离子浓度大于所述第一阱的离子浓度；所述第一导电类型和第二导电类型相反；JFET源极，具有第一导电类型；金属电极，形成于所述JFET源极上且与所述JFET源极接触；及第二导电类型埋层，形成于所述JFET源极和第二阱下方。一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；在所述JFET区的所述第一导电类型区内形成第二导电类型埋 层；向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱；注入第一导电类型的离子，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极；光刻并刻蚀接触孔，淀积金属层，填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图；
图2是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图；
图3a～3d是图2所述的制造方法在制造器件的过程中的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用 的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，器件为VDMOS。如图1中所示，将器件按结构分为JFET区和VDMOS区，设于器件背面(即图1中朝下的面)的N型的漏极201部分用于形成JFET区、部分用于形成VDMOS区。同样的，设于漏极201正面(即图1中朝上的面)的N型区(包括第一N型区202和第二N型区204)部分用于形成JFET区、部分用于形成VDMOS区。在本实施例中，漏极201为N+漏极，N型区为N-外延层。为便于形成P型埋层203，N型区分两次外延分别形成第一N型区202和第二N型区204，可以理解的，在其他实施例中在确保形成所需的P型埋层203的前提下，N型区也可以为单层结构。外延层厚度和浓度的变化会改变夹断电压大小，浓度越小，外延厚度越薄(考虑到反扩和P阱的结深，第一N型区202和第二N型区204总的外延厚度一般要大于4微米，典型的厚度为4微米～7微米)，夹断效果越好。
在本实施例中，JFET区包括：
第一阱205，为P-阱且形成于N型区内。
第二阱207，为高压P阱且形成于N型区内，离子浓度大于第一阱205的离子浓度。作为器件的N型接触，形成导电沟道。
JFET源极212，N+的JFET源极212作为JFET的源极接触。
JFET源极的金属电极，形成于JFET源极212上且与JFET源极212接触。
P型埋层203，形成于JFET源极212和第二阱207下方。
上述集成有结型场效应晶体管的器件，利用了P型埋层203与第二阱207形成的横向沟道，使沟道浓度更加均匀，通过版图设计出较长的横向沟道，其夹断电压也会更加稳定。
在图1所示实施例中，JFET区和VDMOS区交界处也形成有一个第一阱205，作为隔离阱，用于将JFET区和VDMOS区隔离。利用P-的第一阱205辅助耗尽隔离，通过较深的P-阱隔离，可以完全阻断电流的流通路径，防止JFET和VDMOS间的漏电，且在器件反偏耐压时可以辅助下方的N-外延层(即第一N型区202)参与耗尽，提升局部区域的击穿电压来固化击穿点作用。同时，该第一阱205作为结终端扩展技术中终端的耗尽结构，能够有效缩短高压VDMOS的芯片面积。另外，由于该结终端扩展的结工艺存在，第一阱205结深大大超过了传统技术中VDMOS的P型衬底的结深，从而有了较长的纵向电流沟道。相较于传统结构，器件的夹断电压稳定性会提高较多，同时夹断电压也会显著降低。
在图1所示的实施例中，JFET区还包括JFET金属栅极213和JFET栅极欧姆接触214。JFET金属栅极213形成于JFET栅极欧姆接触214上且与JFET栅极欧姆接触214相接触。各JFET栅极欧姆接触214分别形成于JFET区的第一阱205和第二阱207内，各JFET栅极欧姆接触214通过JFET金属栅极213等电位地连接在一起。
在其中一个实施例中，P型埋层203至少与一第一阱205相接触，在图1所示实施例中第二阱207的下方两侧各有一个P型埋层203，这两个P型埋 层203分别与一个第一阱205相接触。通过深阱扩散形成的第一阱205与P型埋层203相连，可以将P型埋层203的电位引出，避免了P型埋层203的浮空，使其夹断电压在随漏极电压变化时更加稳定。
在图1所示的实施例中，JFET源极212形成于第二阱207和第一阱205(与第二阱207相邻的一个第一阱205)之间。
在图1所示实施例中，VDMOS区包括栅极206、第二阱207、设于第二阱207内的N+的VDMOS源极209、以及设于VDMOS源极209下方的P++型的非钳位感性开关(Unclamped Inductive Switching，UIS)区208。非钳位感性开关区208的离子浓度大于第二阱207的离子浓度。在图1所示实施例中，JFET区也形成有非钳位感性开关区208，具体是设于第二阱207内的JFET栅极欧姆接触214的下方，且在本实施例中为第二阱207内，在其他实施例中也可以是第二阱207外、第一阱205内。非钳位感性开关区208可以减小寄生NPN三极管的基极电阻，增大器件的雪崩耐量。
在图1所示实施例中，栅极206的下方两侧各有一个第二阱207，VDMOS源极209形成于这两个第二阱207内，且VDMOS源极209在这两个第二阱207的每一个内都分为两块。器件还包括形成于两块VDMOS源极209之间的P+型的欧姆接触区210。
图2是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图，以下以器件是VDMOS，第一导电类型是N型，第二导电类型是P型为例，介绍集成有结型场效应晶体管的器件的制造方法：
步骤S510，提供第一导电类型的衬底，衬底上形成有第一导电类型区。
在本实施例中，是在N+衬底上外延形成N型区，衬底后续将会作为器件的漏极201。
步骤S520，在JFET区的第一导电类型区内形成第二导电类型埋层。
在本实施例中，第一导电类型区包括第一外延层(即第一N型层202)和第二外延层(即第二N型层204)。步骤S520是对第一外延层进行光刻、P型离子注入和推阱形成P型埋层203，图3a是P型埋层203形成后器件的剖 面结构示意图。P型埋层203形成后在第一外延层表面形成第二外延层。P型埋层203至少与一第一阱205相接触。
步骤S530，注入第二导电类型的离子并推阱，在第一导电类型区内形成第一阱。
在本实施例中，是向N型区中注入P型离子并推阱，在N型区内形成第一阱205。
步骤S540，生长场氧层和栅氧层，并形成多晶硅层。
在N型区的表面生长厚的场氧层然后生长栅氧层，并在N型区表面形成多晶硅层604。
步骤S550，向第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱。
在本实施例中，是以场氧层和多晶硅层604为掩膜向N型区注入P型离子，推阱形成多个第二阱207。图3b是步骤S550完成后器件的剖面结构示意图。
参见图3c，在本实施例中，执行步骤S560之前还包括向第二阱207中注入P型离子的步骤，以在JFET区和功率器件区的第二阱207内形成非钳位感性开关区208。为了防止向第二阱207中注入的P型离子对沟道区造成不利影响，本实施例中在注入P型离子形成非钳位感性开关区208的步骤之前，还包括形成注入阻挡层的步骤。在本实施例中形成注入阻挡层是通过再形成一层氧化层，由于注入P型离子形成非钳位感性开关区208的注入窗口处的氧化层较薄，因此高能注入的P型离子可以穿过氧化层形成非钳位感性开关区208。而其他位置处的氧化层形成于场氧层、多晶硅层604等结构上，因此整个注入阻挡层的厚度较厚，P型离子难以穿过注入阻挡层进入N型区内。
步骤S560，注入第一导电类型的离子，在JFET区形成JFET源极、在功率器件区形成功率器件源极。
参见图3d，在本实施例中，是用光刻工艺以光刻胶为掩膜注入N型离子， 在JFET区的第二阱207内形成JFET源极，在功率器件区的第二阱207内形成VDMOS源极209。其中VDMOS源极209形成于栅极两侧的各一个第二阱207内，且在每个第二阱207内都分成两块，中间留出给后续步骤形成的欧姆接触区210的位置。
在本实施例中，步骤S560完成后，还包括在第一阱205、第二阱207中形成栅极欧姆接触214和欧姆接触区210的步骤。具体是在JFET区的第一阱205和第二阱207中形成JFET栅极欧姆接触214，在功率器件区的第二阱207中形成欧姆接触区210。
步骤S570，光刻并刻蚀接触孔，淀积金属层，填入接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
填入接触孔的金属与JFET栅极欧姆接触214相接触形成JFET金属栅极213，与JFET源极212相接触形成JFET源极的金属电极。淀积金属层后在器件表面形成钝化层，完成后器件的剖面如图1所示。
综合上述优势，上述集成有结型场效应晶体管的器件在传统技术的基础上提升了夹断电压的稳定性，固化了击穿点，加强了UIS能力，工艺上完全匹配，并且实现了夹断电压大小的可调性。
在其中一个实施例中，步骤S520包括在JFET区和功率器件区交界处形成一个第一阱205作为隔离阱，用于将JFET区和功率器件区隔离。
在其中一个实施例中，步骤S530的第一阱205的注入浓度为1.5E13cm-2～2.2E13cm-2，第一阱205的阱深为8.5微米～13.5微米。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：
    漏极，具有第一导电类型，所述漏极的一部分位于所述JFET区、另一部分位于所述功率器件区；及
    第一导电类型区，设于所述漏极的正面，所述第一导电类型区的一部分位于所述JFET区、另一部分位于所述功率器件区；
    所述JFET区包括：
    第一阱，具有第二导电类型且形成于所述第一导电类型区内；
    第二阱，具有第二导电类型且形成于所述第一导电类型区内，离子浓度大于所述第一阱的离子浓度；所述第一导电类型和第二导电类型相反；
    JFET源极，具有第一导电类型；
    金属电极，形成于所述JFET源极上且与所述JFET源极接触；及
    第二导电类型埋层，形成于所述JFET源极和第二阱下方。
  2. 根据权利要求1所述的器件，其中，还包括隔离阱，位于所述JFET区和功率器件区交界处，用于将所述JFET区和功率器件区隔离。
  3. 根据权利要求2所述的器件，其中，所述JFET区还包括JFET金属栅极和JFET栅极欧姆接触，所述JFET金属栅极形成于所述JFET栅极欧姆接触上且与所述JFET栅极欧姆接触相接触，所述JFET栅极欧姆接触形成于所述JFET区的第一阱、第二阱和所述隔离阱内，各所述JFET栅极欧姆接触通过所述JFET金属栅极等电位地连接在一起。
  4. 根据权利要求3所述的器件，其中，所述第二导电类型埋层至少与一所述JFET区的第一阱相接触。
  5. 根据权利要求1所述的器件，其中，所述JFET源极形成于所述JFET区的第二阱和与所述JFET区的第二阱相邻的JFET区的第一阱之间。
  6. 根据权利要求1所述的器件，其中，所述器件是VDMOS。
  7. 根据权利要求6所述的器件，其中，所述功率器件区包括：
    栅极；
    第二阱；
    VDMOS源极，设于所述功率器件区的第二阱内具有第一导电类型；及
    非钳位感性开关区，设于所述功率器件区的第二阱内、所述VDMOS源极下方的，所述非钳位感性开关区具有第二导电类型，且非钳位感性开关区的离子浓度大于所述功率器件区的第二阱的离子浓度。
  8. 根据权利要求7所述的集成有结型场效应晶体管的器件，其中，所述栅极的下方两侧各有一个功率器件区的第二阱，所述VDMOS源极形成于两个所述功率器件区的第二阱内，且所述VDMOS源极在两个所述功率器件区的第二阱的每一个内都分为两块，所述器件还包括形成于两块VDMOS源极之间的第二导电类型的欧姆接触区。
  9. 根据权利要求1所述的器件，其中，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
  10. 根据权利要求9所述的器件，其中，所述N型外延层包括第一N型区和第一N型区上的第二N型区。
  11. 根据权利要求10所述的器件，其中，所述N型外延层的厚度为4微米～7微米。
  12. 一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：
    提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；
    在所述JFET区的所述第一导电类型区内形成第二导电类型埋层；
    所述第一导电类型和第二导电类型相反；
    向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成JFET区的第一阱；
    在所述第一导电类型区的表面先后生长场氧层和栅氧层，并在所述第一 导电类型区表面形成多晶硅层；
    向所述第一导电类型区注入第二导电类型的离子并推阱形成多个JFET区的第二阱；
    注入第一导电类型的离子，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极；及
    光刻并刻蚀接触孔，淀积金属层，填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
  13. 根据权利要求12所述的方法，其中，所述在所述第一导电类型区内形成隔离阱的步骤，包括在所述JFET区和功率器件区交界处形成隔离阱，作为JFET区和功率器件区的隔离。
  14. 根据权利要求12所述的方法，其中，所述第一导电类型区包括第一外延层和第二外延层；所述在所述JFET区的第一导电类型区内形成第二导电类型埋层的步骤，是对第一外延层进行光刻、第二导电类型离子注入和推阱形成第二导电类型埋层；所述向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱的步骤之前，还包括在所述第一外延层表面形成第二外延层的步骤；所述第二导电类型埋层至少与一所述JFET区的第一阱相接触。
  15. 根据权利要求12所述的方法，其中，所述向所述第一导电类型区注入第二导电类型的离子并推阱形成多个JFET区的第二阱的步骤之后、所述注入第一导电类型的离子的步骤之前，还包括形成注入阻挡层的步骤，以及向所述JFET区的第二阱中注入第二导电类型的离子以形成非钳位感性开关区的步骤，且非钳位感性开关区的注入能量大于所述注入第一导电类型的离子的步骤的注入能量。
  16. 根据权利要求12所述的方法，其中，所述在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述光刻并刻蚀接触孔的步骤之前，还包括注入第二导电类型的离子，在所述JFET区的第一阱和第二阱中形成JFET栅极欧姆接触、及在所述功率器件区的第二阱中形成欧 姆接触区的步骤。
  17. 根据权利要求12所述的方法，其中，所述第一导电类型为N型，所述第二导电类型为P型，所述器件VDMOS。
  18. 根据权利要求12所述的方法，其中，所述向第一导电类型区中注入第二导电类型的离子并推阱的步骤，注入浓度为1.5E13cm-2～2.2E13cm-2；
    所述在所述第一导电类型区内形成第一阱的步骤，形成的所述第一阱的阱深为8.5微米～13.5微米。
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JP2020161711A (ja) * 2019-03-27 2020-10-01 ローム株式会社 半導体装置
JP7329348B2 (ja) 2019-03-27 2023-08-18 ローム株式会社 半導体装置

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