WO2018041208A1 - 集成有结型场效应晶体管的器件及其制造方法 - Google Patents

集成有结型场效应晶体管的器件及其制造方法 Download PDF

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WO2018041208A1
WO2018041208A1 PCT/CN2017/099860 CN2017099860W WO2018041208A1 WO 2018041208 A1 WO2018041208 A1 WO 2018041208A1 CN 2017099860 W CN2017099860 W CN 2017099860W WO 2018041208 A1 WO2018041208 A1 WO 2018041208A1
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region
conductivity type
well
jfet
source
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PCT/CN2017/099860
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English (en)
French (fr)
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顾炎
程诗康
张森
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无锡华润上华科技有限公司
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Priority to EP17845510.1A priority Critical patent/EP3509101B1/en
Priority to US16/329,413 priority patent/US10879385B2/en
Priority to JP2019511876A priority patent/JP6861274B2/ja
Publication of WO2018041208A1 publication Critical patent/WO2018041208A1/zh

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Definitions

  • the present invention relates to semiconductor manufacturing technology, and more particularly to a device integrated with a junction field effect transistor, and to a method of fabricating a device incorporating a junction field effect transistor.
  • JFET junction-effect transistor
  • VDMOS vertical double-diffused metal-oxide-semiconductor field-effect transistor
  • the JFET absorbs the abrupt current of the VDMOS on the Miller platform, which makes the start-up more gradual, and the current can be approximately linearly transformed. Therefore, the JFET has a significant effect on the stability of the device during the startup process. Power devices have the advantage of integrating parasitic JFETs on their process platforms.
  • the most important characteristic of the integrated parasitic JFET is the stability of the overall breakdown voltage and the stability of the pinch-off voltage.
  • the breakdown voltage of the integrated device remains unchanged, and the breakdown point is preferably kept at The breakdown point of the VDMOS power device.
  • the traditional integrated structure VDMOS and JFET interface is only isolated by the substrate, and can only lengthen the lateral distance of the substrate extension to ensure the margin when depleted, which will increase the area of the entire die.
  • the breakdown point will be transferred from the cell (cell) region of the body to the JFET region or the junction, greatly reducing the breakdown.
  • the stability of the breakdown voltage also occurs.
  • Conventional structures generally use a self-aligned P-type implanted substrate as a P-type pinch-off substrate. Since the P-type substrate of the cell region of the VDMOS has a shallow longitudinal depth, generally only 3 to 5 ⁇ m, the longitudinal trench of the JFET The track is very short, and it is impossible to adjust the longitudinal channel length, so the pinch-off voltage is very unstable. It can be seen from the simulation that when the drain voltage changes from 50V to 100V, the pinch-off voltage Voff will increase from 11V to 20V, and Voff is required to be stable in practical applications, so the conventional structure is difficult to meet the actual demand.
  • a device integrated with a junction field effect transistor and a method of fabricating the same are provided.
  • a device integrated with a junction field effect transistor the device being divided into a JFET region and a power device region, the device comprising: a drain having a first conductivity type, a portion of the drain being located in the JFET region Another portion is located in the power device region; and a first conductivity type region is disposed on a front surface of the drain, a portion of the first conductivity type region is located in the JFET region, and another portion is located in the power device region;
  • the JFET region further includes: a JFET source having a first conductivity type; a first well having a second conductivity type disposed in the first conductivity type region and formed on both sides of the JFET source; a first conductivity type and a second conductivity type opposite; a metal electrode formed on the JFET source and in contact with the JFET source; a JFET metal gate, the first one disposed on both sides of the JFET source And a first clamping region located below the JFET metal gate, in the first well, being
  • a method of fabricating a device incorporating a junction field effect transistor, the device comprising a JFET region and a power device region comprising: providing a substrate of a first conductivity type, the substrate being shaped Forming a first conductivity type region; the first conductivity type and the second conductivity type being opposite conductivity types; implanting a second conductivity type of ions into the first conductivity type region and pushing a well, wherein the first conductivity type Forming a first well in the region; growing a field oxide layer and a gate oxide layer, forming a polysilicon layer on the surface of the first conductivity type region, and injecting a second conductivity type into the first conductivity type region of the power device region Ioning and sinking a well to form a plurality of second wells; implanting ions of a first conductivity type into a second well of the power device region to form a power device source; and between two adjacent second wells of the JFET region Injecting ions of a first conductivity type to form a
  • FIG. 1 is a cross-sectional structural view of a device in which a junction field effect transistor is integrated in an embodiment
  • FIG. 2 is a comparison curve of the pinch-off voltage of the device shown in FIG. 1 at different drain voltages Vd;
  • FIG. 3 is a flow chart showing a method of fabricating a device in which a junction field effect transistor is integrated in an embodiment
  • FIG. 4a-4e are schematic cross-sectional views of the manufacturing method of Fig. 2 in the process of fabricating a device.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • FIG. 1 is a schematic cross-sectional view of a device in which a junction field effect transistor is integrated in an embodiment.
  • an N type is defined as a first conductivity type
  • a P type is a second conductivity type
  • a power device is a VDMOS.
  • the device is divided into a JFET region and a VDMOS region by structure, and an N-type drain 201 portion provided on the back surface of the device (ie, the face facing downward in FIG. 1) is used to form a JFET region and a portion for Form a VDMOS area.
  • the N-type region 214 portion disposed on the front side of the drain 201 i.e., the upward facing surface in FIG.
  • the drain 201 is an N+ drain
  • the N-type region 214 is an N- epitaxial layer as a drift region of the VDMOS (in other embodiments, an N-type substrate can also be used directly).
  • the JFET region includes a JFET source 208, a JFET source metal electrode 212, a JFET metal gate 213, a first well 202, and a clamping region 210.
  • the first well 202 of P- is disposed in the N-type region 214 and is formed on both sides of the N+ JFET source 208.
  • the JFET source 208 extends into the JFET source 208 on both sides.
  • a metal electrode 212 of the JFET source is formed on JFET source 208 in contact with JFET source 208.
  • JFET metal gate 213 is disposed on first well 202 on both sides of JFET source 208.
  • the P-type clamping region 210 is located below the JFET metal gate 213, within the first well 202, and has an ion concentration greater than the ion concentration of the first well 202.
  • the device integrated with the junction field effect transistor improves the ion concentration of the first well 202 through the clamping region 210, enhances the depletion ability of the channel region, and the JFET pinch-off voltage stability is improved to some extent.
  • the presence of the clamping region 210 enhances the electric field strength at that location, changes the path of the avalanche current, and improves the stability of the device.
  • Clamp region 210 employs high energy P-type ion implantation to achieve sufficient implant depth.
  • the implantation energy is about 480 keV.
  • Clamping zone 210 is capable of curing the breakdown point.
  • a first well 202 is formed at the junction of the JFET region and the VDMOS region as an isolation well for isolating the JFET region from the VDMOS region.
  • the first well 202 of P- is used to assist the depletion isolation, and the isolation of the deeper first well 202 can completely block the current flow path, prevent leakage between the JFET and the VDMOS, and can assist in the reverse bias voltage of the device.
  • the lower N- epitaxial layer ie, N-type region 214) participates in depletion, boosting the breakdown voltage of the local region to cure the breakdown point effect.
  • the first well 202 serves as a depletion structure of the terminal in the junction terminal extension technology, and can effectively shorten the chip area of the high voltage VDMOS.
  • the junction depth of the P-well greatly exceeds the junction depth of the P-type substrate of the VDMOS in the conventional art, thereby having a long longitudinal current channel.
  • the pinch-off voltage stability of the device is increased more, and the pinch-off voltage is also significantly reduced.
  • the well depth of the first well 202 is between 8.5 microns and 13.5 microns.
  • the VDMOS region includes a gate (the gate includes a gate oxide layer 203 and a polysilicon gate 204), a second well 205, and an N+ VDMOS source 206 disposed in the second well 205, and
  • the VDMOS region also includes a P-type clamping region 210 disposed at the bottom of the second well 205.
  • a trench is formed in the second well 205 of the VDMOS region and the first well 202 of the JFET region, the VDMOS region is provided with a metal contact 211 of the VDMOS source, and each of the second wells 205 is trenched.
  • a P-type ohmic contact region 209 is formed at the bottom contact of the trench and in the first well 202 in contact with the bottom of the trench.
  • the metal contact 211 of the VDMOS source is filled in the trench of the VDMOS region and penetrates the VDMOS source downward.
  • the pole 206 extends to the ohmic contact region 209.
  • the JFET metal gate 213 is filled in the trench of the JFET region and extends down to the ohmic contact region 209.
  • the ion concentration of the ohmic contact region 209 is greater than the ion concentration of the second well 205.
  • a P-type Unclamped Inductive Switching (UIS) region is formed between the VDMOS source 206 and the ohmic contact region 209 in the second well 205 of the VDMOS region. 207.
  • the ion concentration of the non-clamped inductive switch region 207 is greater than the ion concentration of the second well 205.
  • FIG. 2 is a simulated comparison of pinch-off voltages of the device of FIG. 1 at different drain voltages Vd, wherein the abscissa is the source voltage and the ordinate is the drain current.
  • Simulation of different drain voltages Vd by SILVACO software shows the pinch-off voltage variation when the drain voltage Vd is 50V, 100V, 200V, and 600V, respectively.
  • the pinch-off voltage change in the interval from 50V to 200V is maintained at a linear change of about 0.5V.
  • the pinch-off voltage is increased by 5V. This is due to the addition of the thermal model.
  • the carrier At high voltages, the carrier has higher temperature, increased momentum, and faster motion rate per unit time.
  • the simulation in Figure 4 is for a device with a breakdown voltage of 650V.
  • the junction field effect transistor described above basically achieves controllable pinch-off voltage within the normal range of use.
  • the junction field effect transistor described above is also applicable to ultrahigh voltage devices after epitaxial layer thickening, as well as low voltage trench gate devices.
  • the main advantage of the above-described devices incorporating junction field effect transistors is to improve the stability of the original integrated JFET channel pinch-off.
  • the first well 202 simultaneously serves as a junction termination extension ring of the VDMOS.
  • the deepest depth is limited by its terminal technology, but at this point it has greatly exceeded the depth required for the P-well of the depletion JFET, so the two are compatible.
  • FIG. 3 is a flow chart of a method for fabricating a device in which a junction field effect transistor is integrated in an embodiment.
  • the power device is VDMOS
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • Step S510 providing a substrate of a first conductivity type on which a first conductivity type region is formed.
  • an N-type region 214 is epitaxially formed on the N+ substrate, and the substrate will subsequently serve as the drain 201 of the device.
  • Step S520 implanting ions of the second conductivity type and pushing the well to form a first well in the first conductivity type region.
  • P-type ions are implanted into the N-type region 214 and the well is pushed, and the first well 202 is formed in the N-type region 214.
  • 4a is a schematic cross-sectional view of the device after the step S520 is completed.
  • Step S530 growing a field oxide layer and a gate oxide layer, forming a polysilicon layer, implanting ions of the second conductivity type and pushing the well to form a plurality of second wells.
  • a thick field oxide layer is grown on the surface of the N-type region 214, then a gate oxide layer is grown, and a polysilicon layer 604 is formed on the surface of the N-type region 214, and the N-type region 214 is implanted with the field oxide layer and the polysilicon layer 604 as a mask.
  • the type ions, the push wells form a plurality of second wells 205.
  • the ion concentration of the second well 205 is greater than the ion concentration of the first well 202.
  • 4b is a schematic cross-sectional view of the device after the step S530 is completed.
  • Step S540 injecting ions of the first conductivity type into the second well of the power device region to form a source of the power device.
  • N-type ions are implanted into the second well 205 of the VDMOS region to form a VDMOS source 206.
  • the method further includes the step of implanting P-type ions into the second well 205 of the power device region to be in the second well 205.
  • An unclamped inductive switch region 207 is formed below the VDMOS source 206.
  • the step of forming the implant barrier layer is further included in the present embodiment before the step of implanting the P-type ions to form the unclamped inductive switch region 207. .
  • the formation of the implantation barrier layer is formed by re-forming an oxide layer due to implantation of P.
  • the oxide layer at the implantation window where the type ions form the unclamped inductive switching region 207 is relatively thin, so that the high energy implanted P-type ions can pass through the oxide layer to form the unclamped inductive switching region 207.
  • the oxide layer at other locations is formed on the structure of the field oxide layer, the polysilicon layer 604, etc., so that the thickness of the entire implant barrier layer is thick, and it is difficult for the P-type ions to pass through the implant barrier layer into the N-type region 214.
  • the dielectric and polysilicon layer 604 over the JFET source 208 is removed by photolithography and etching, and then N-type impurities are implanted to form a JFET source 208 on the surface of the N-type region 214.
  • the excess polysilicon layer 604 is removed to form the polysilicon gate 204 shown in Figure 4d.
  • Figure 4d is a schematic cross-sectional view of the device after completion of step S550.
  • the step S560 further includes the step of etching the trench 602 in each of the second wells 205 and the first wells 202.
  • This step requires injecting P-type ions into the second well 205 in two steps, wherein the first implantation is in contact with the bottom of the trench 602 in the second well 205 on both sides of the gate, and on both sides of the source 208.
  • a P-type ohmic contact region 209 is formed in a well 202 in contact with the bottom of the trench 602, and is implanted a second time in the bottom of the second well 205 on both sides of the gate, and in the first well 202 on both sides of the source 208.
  • a P-type clamping region 210 is formed.
  • the deposited metal layer fills the trench 602 in the second well 205 of the JFET region to form a JFET metal gate 213 that fills the trench 602 in the second well 205 of the power device region to form a metal contact of the VDMOS source. 211.
  • a passivation layer is formed on the surface of the device, and the cross section of the device is completed as shown in FIG.
  • the implanted P-type clamping region 210 is a high-energy P-type implant with an implantation energy of about 480 keV.
  • the structure of the region 207) is intended to enhance the UIS characteristics of the VDMOS device.
  • the UIS capability of the device is enhanced by UIS injection, but limited by the depth of implantation and concentration dispersion, the effect is not satisfactory.
  • the deep trench etches the cell region of the VDMOS, removes excess N-type impurities, and injects P-type ions intensively, increasing the electron bleed path during the UIS process, greatly enhancing the UIS capability of the device.
  • the second well 205 in the device may be a P-type substrate of a cell region in the VDMOS, but the concentration of the P-type substrate is limited by the cell design parameter in the VDMOS, and thus In the case where precise adjustment is required, lithography that specifically adjusts the second well 205 is also required. This lithography is compatible with the DMOS process, so the total number of lithography layers in the entire process is constant.
  • the above-mentioned device integrated with a junction field effect transistor improves the stability of the pinch-off voltage on the basis of the conventional technology, solidifies the breakdown point, strengthens the UIS capability, perfectly matches the process, and realizes pinch-off. Adjustable voltage size.
  • step S520 includes forming a first well 202 as an isolation well at the junction of the JFET region and the power device region for isolating the JFET region from the power device region.
  • the first well 202 of step S520 has an implantation concentration of 1.5E13 cm -2 to 2.2 E13 cm -2 , and the first well 202 is formed to have a well depth of 8.5 ⁇ m to 13.5 ⁇ m.

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Abstract

一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：漏极（201），具有第一导电类型，所述漏极（201）的一部分位于所述JFET区、另一部分位于所述功率器件区；及第一导电类型区（214），设于所述漏极的正面，所述第一导电类型区（214）的一部分位于所述JFET区、另一部分位于所述功率器件区；所述JFET区还包括：JFET源极（208），具有第一导电类型；第一阱（202），具有第二导电类型，设于所述第一导电类型区（214）内且形成于所述JFET源极（208）两侧；金属电极（212），形成于所述JFET源极（208）上并与所述JFET源极（208）接触；JFET金属栅极（213），设于所述JFET源极（208）两侧的所述第一阱（202）上；及第一钳位区（210），位于所述JFET金属栅极（213）的下方、所述第一阱（202）内，为第二导电类型且其离子浓度大于所述第一阱的离子浓度。

Description

集成有结型场效应晶体管的器件及其制造方法 技术领域
本发明涉及半导体制造技术，特别是涉及一种集成有结型场效应晶体管的器件，还涉及一种集成有结型场效应晶体管的器件的制造方法。
背景技术
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。
传统结构的高压集成JFET有较简单的工艺可以实现，但其夹断电压的不稳定限制了其在智能功率集成领域的大规模应用。
对于一种传统的集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)的垂直双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffused MOSFET，VDMOS)，当VDMOS处于开启阶段时，电流从底部漏端流过JFET，从source2流出。当source2上加逐渐变大的电压Vg2，同时栅gate上也加同样的电压Vg1，当Vg2＞夹断电压Voff时，JFET的耗尽层阻断了电流，即发生了夹断。此时Vg1＞Vth，Vth为VDMOS的阈值电压，VDMOS开启，完成了一个开启过程。JFET在此吸收了VDMOS在米勒平台时的突变电流，让启动更为平缓，电流可以成近似线性变换，所以JFET在启动过程中对器件稳定性提升有着很显著作用。功率器件在其工艺平台上集成寄生JFET则更具有优势。
集成寄生JFET，其最主要特性是整体击穿电压的稳定性和夹断电压的稳定性，最为理想的是，集成后器件的击穿电压保持不变，击穿点最好保持在 VDMOS功率器件的击穿点。传统的集成结构VDMOS与JFET交接处仅用了衬底进行隔离，仅可以拉长衬底外延的横向距离来保证耗尽时的余量，这样会增加整个管芯的面积。同时，由于外延层规范有所偏差，工艺上略有变动就会出现击穿点转移，击穿点会从体内的cell(元胞)区转移至JFET区或是交接处，大大降低了击穿的稳定性，还会发生击穿电压蠕变的现象。传统结构一般用自对准P型注入的衬底作为P型夹断衬底，由于VDMOS的cell区的P型衬底其纵向结深很浅，一般只有3～5微米，因此JFET的纵向沟道很短，人为无法去调整纵向沟道长度，所以夹断电压很不稳定。通过仿真可得知当漏端电压从50V到100V变化时，夹断电压Voff会从11V变大至20V，而在实际应用中需要Voff稳定，因此该传统结构难以满足实际需求。
发明内容
根据本申请的各实施例，提供一种集成有结型场效应晶体管的器件及其制造方法。
一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：漏极，具有第一导电类型，所述漏极的一部分位于所述JFET区、另一部分位于所述功率器件区；及第一导电类型区，设于所述漏极的正面，所述第一导电类型区的一部分位于所述JFET区、另一部分位于所述功率器件区；所述JFET区还包括：JFET源极，具有第一导电类型；第一阱，具有第二导电类型，设于所述第一导电类型区内且形成于所述JFET源极两侧；所述第一导电类型和第二导电类型相反；金属电极，形成于所述JFET源极上并与所述JFET源极接触；JFET金属栅极，设于所述JFET源极两侧的所述第一阱上；及第一钳位区，位于所述JFET金属栅极的下方、所述第一阱内，为第二导电类型且其离子浓度大于所述第一阱的离子浓度。
一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：提供第一导电类型的衬底，所述衬底上形 成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；先后生长场氧层和栅氧层，在所述第一导电类型区表面形成多晶硅层，向所述功率器件区的所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱；向所述功率器件区的第二阱中注入第一导电类型的离子，形成功率器件源极；向所述JFET区的两相邻第二阱之间注入第一导电类型的离子，形成JFET源极；光刻并刻蚀接触孔，向所述接触孔内注入第二导电类型的离子，在所述第一阱内以及所述第二阱底部形成钳位区，所述钳位区的离子浓度大于所述第一阱的离子浓度；淀积金属层并填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图；
图2是仿真得到的图1所示器件在不同漏极电压Vd下的夹断电压比较曲线；
图3是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图；
图4a～4e是图2所述的制造方法在制造器件的过程中的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，功率器件为VDMOS。如图1中所述，将器件按结构分为JFET区和VDMOS区，设于器件背面(即图1中朝下的面)的N型的漏极201部分用于形成JFET区、部分用于形成VDMOS区。同样的，设于漏极201正面(即图1中朝上的面)的N型区214部分用于形成JFET区、部分用于形成VDMOS区。在本实施例中，漏极201为N+漏极，N型区214为N-外延层，作为VDMOS的漂移区(在其他实施例中也可以直接使用N型衬底)。
在本实施例中，JFET区包括JFET源极208、JFET源极的金属电极212、JFET金属栅极213、第一阱202以及钳位区210。
P-的第一阱202设于N型区214内且形成于N+的JFET源极208的两侧，在图1所示实施例中，JFET源极208伸入两侧的JFET源极208内。JFET源极的金属电极212形成于JFET源极208上，与JFET源极208接触。JFET金属栅极213设于JFET源极208两侧的第一阱202上。P型的钳位区210位于JFET金属栅极213的下方、第一阱202之内，且离子浓度大于第一阱202的离子浓度。
上述集成有结型场效应晶体管的器件，通过钳位区210提高了第一阱202的离子浓度，增强了沟道区的耗尽能力，使得JFET夹断电压稳定性会有一定程度的提高。同时钳位区210的存在会增强该处电场强度，改变雪崩电流的路径，提升了器件的稳定性。
钳位区210采用高能的P型离子注入，以获得足够的注入深度。在其中一个实施例中注入能量为480keV左右。钳位区210能够固化击穿点。
在图1所示实施例中，JFET区和VDMOS区交界处形成有一个第一阱202，作为隔离阱，用于将JFET区和VDMOS区隔离。利用P-的第一阱202辅助耗尽隔离，通过较深的第一阱202隔离，可以完全阻断电流的流通路径，防止JFET和VDMOS间的漏电，且在器件反偏耐压时可以辅助下方的N-外延层(即N型区214)参与耗尽，提升局部区域的击穿电压来固化击穿点作用。同时，该第一阱202作为结终端扩展技术中终端的耗尽结构，能够有效缩短高压VDMOS的芯片面积。另外由于该结终端扩展的结工艺存在，P-阱结深大大超过了传统技术中VDMOS的P型衬底的结深，从而有了较长的纵向电流沟道。相较于传统结构，器件的夹断电压稳定性会提高较多，同时夹断电压也会显著降低。在其中一个实施例中，第一阱202的阱深为8.5微米～13.5微米。
在图1所示实施例中，VDMOS区包括栅极(栅极包括栅氧层203和多晶硅栅204)、第二阱205、设于第二阱205内的N+的VDMOS源极206，且 VDMOS区同样包括P型的钳位区210，其设于第二阱205的底部。
在图1所示实施例中，VDMOS区的第二阱205和JFET区的第一阱202内形成有沟槽，VDMOS区设有VDMOS源极的金属接触211，各第二阱205内与沟槽的底部接触处以及各第一阱202内与沟槽的底部接触处形成有P型的欧姆接触区209，VDMOS源极的金属接触211填充于VDMOS区的沟槽内、向下贯穿VDMOS源极206并延伸至欧姆接触区209。JFET金属栅极213填充于JFET区的沟槽内并向下延伸至欧姆接触区209。欧姆接触区209的离子浓度大于第二阱205的离子浓度。
在图1所示实施例中，在VDMOS区的第二阱205内、VDMOS源极206和欧姆接触区209之间，还形成有P型的非钳位感性开关(Unclamped Inductive Switching，UIS)区207。非钳位感性开关区207的离子浓度大于第二阱205的离子浓度。
图2是仿真得到的图1所示器件在不同漏极电压Vd下的夹断电压比较曲线其中横坐标为源极电压，纵坐标为漏极电流。通过SILVACO软件对不同漏极电压Vd下进行仿真，可以看出当漏极电压Vd分别为50V、100V、200V和600V时的夹断电压变化。从50V到200V的区间内夹断电压变化维持在线性0.5V左右的变化。当漏极电压Vd升高为600V时，夹断电压增加了5V，这是由于热模型添加，高电压情况下器件内载流子有较高温度，动量加大，运动速率加快，单位时间内通过截面的电荷数增加，电流变大，所以在夹断时电流会表现增加，这是正常现象。图4的仿真中针对的是击穿电压为650V器件，上述结型场效应晶体管基本做到了在正常使用范围内夹断电压可控。上述结型场效应晶体管同样适用于外延层加厚之后的超高压器件，以及低压的沟槽栅器件。
上述集成有结型场效应晶体管的器件的主要优势在于提高了原始集成JFET沟道夹断的稳定性。以其较深的纵向沟道的特点，降低了漏极电压Vd对源极表面电势的影响，提高了夹断电压的稳定性，所以结深的增加是本发明结构的其中一个关键所在。第一阱202同时作为VDMOS的结终端扩展环， 最深的深度由它的终端技术所限制，但此时已大大超过了耗尽型JFET的P阱所需要的深度，所以二者可以兼容。
图3是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图，以下以功率器件是VDMOS，第一导电类型是N型，第二导电类型是P型为例，介绍集成有结型场效应晶体管的器件的制造方法：
步骤S510，提供第一导电类型的衬底，衬底上形成有第一导电类型区。
在本实施例中，是在N+衬底上外延形成N型区214，衬底后续将会作为器件的漏极201。
步骤S520，注入第二导电类型的离子并推阱，在第一导电类型区内形成第一阱。
在本实施例中，是向N型区214中注入P型离子并推阱，在N型区214内形成第一阱202。图4a是步骤S520完成后器件的剖面结构示意图。
步骤S530，生长场氧层和栅氧层，形成多晶硅层，注入第二导电类型的离子并推阱形成多个第二阱。
在N型区214的表面生长厚的场氧层然后生长栅氧层，并在N型区214表面形成多晶硅层604，再以场氧层和多晶硅层604为掩膜向N型区214注入P型离子，推阱形成多个第二阱205。第二阱205的离子浓度大于第一阱202的离子浓度。图4b是步骤S530完成后器件的剖面结构示意图。
步骤S540，向功率器件区的第二阱中注入第一导电类型的离子，形成功率器件源极。
向VDMOS区的第二阱205注入N型离子，形成VDMOS源极206。
参见图4c，在本实施例中，注入N型离子形成VDMOS源极206的步骤之后，还包括向功率器件区的第二阱205中注入P型离子的步骤，以在第二阱205内的VDMOS源极206的下方形成非钳位感性开关区207。为了防止向第二阱205中注入的P型离子对沟道区造成不利影响，本实施例中在注入P型离子形成非钳位感性开关区207的步骤之前，还包括形成注入阻挡层的步骤。在本实施例中形成注入阻挡层是通过再形成一层氧化层，由于注入P 型离子形成非钳位感性开关区207的注入窗口处的氧化层较薄，因此高能注入的P型离子可以穿过氧化层形成非钳位感性开关区207。而其他位置处的氧化层形成于场氧层、多晶硅层604等结构上，因此整个注入阻挡层的厚度较厚，P型离子难以穿过注入阻挡层进入N型区214内。
S550，向JFET区的两相邻第二阱之间注入第一导电类型的离子，形成JFET源极。
在本实施例中，是通过光刻和刻蚀去除JFET源极208上方的介质和多晶硅层604，然后注入N型杂质，在N型区214的表面形成JFET源极208。多余的多晶硅层604被去除后形成图4d所示的多晶硅栅204。图4d是步骤S550完成后器件的剖面结构示意图。
S560，光刻并刻蚀接触孔，向接触孔内注入第二导电类型的离子形成钳位区。
参见图4e，在本实施例中，步骤S560之前还包括在各第二阱205和第一阱202内刻蚀出沟槽602的步骤。本步骤需要分两次向第二阱205注入P型离子，其中第一次注入在栅极两侧的第二阱205内与沟槽602的底部接触处、以及在源极208两侧的第一阱202内与沟槽602的底部接触处形成P型的欧姆接触区209，第二次注入在栅极两侧的第二阱205的底部、以及源极208两侧的第一阱202内形成P型的钳位区210。
S570，淀积金属层并填入接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
淀积的金属层填入JFET区的第二阱205内的沟槽602，形成JFET金属栅极213，填入功率器件区的第二阱205内的沟槽602，形成VDMOS源极的金属接触211。淀积金属层后在器件表面形成钝化层，完成后器件的剖面如图1所示。
在其中一个实施例中，注入形成P型的钳位区210为高能P型注入，注入能量为480keV左右。
在VDMOS部分引入深槽(沟槽602)加P+注入(形成非钳位感性开关 区207)的结构，其目的是提升VDMOS器件的UIS特性。在传统的高压VDMOS工艺中，通过UIS注入来加强器件UIS能力，但受限于注入深度和浓度分散，效果不甚理想。深槽刻蚀VDMOS的cell区，去除了多余的N型杂质，并集中注入了P型离子，增加了UIS过程中电子泄放路径，大大加强了器件的UIS能力。
上述集成有结型场效应晶体管的器件的制造方法，器件中的第二阱205可以是VDMOS中cell区的P型衬底，但P型衬底的浓度受限于VDMOS中cell设计参数，因而在需精确调整的情况下是还需加入专门调节第二阱205的光刻，此光刻与DMOS工艺兼容，所以在整个工艺中的光刻总层数是不变的。
综合上述优势，上述集成有结型场效应晶体管的器件在传统技术的基础上提升了夹断电压的稳定性，固化了击穿点，加强了UIS能力，工艺上完全匹配，并且实现了夹断电压大小的可调性。
在其中一个实施例中，步骤S520包括在JFET区和功率器件区交界处形成一个第一阱202作为隔离阱，用于将JFET区和功率器件区的隔离。
在其中一个实施例中，步骤S520的第一阱202的注入浓度为1.5E13cm-2～2.2E13cm-2，形成的第一阱202的阱深为8.5微米～13.5微米。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：
    漏极，具有第一导电类型，所述漏极的一部分位于所述JFET区、另一部分位于所述功率器件区；及
    第一导电类型区，设于所述漏极的正面，所述第一导电类型区的一部分位于所述JFET区、另一部分位于所述功率器件区；所述JFET区还包括：
    JFET源极，具有第一导电类型；
    第一阱，具有第二导电类型，设于所述第一导电类型区内且形成于所述JFET源极两侧；所述第一导电类型和第二导电类型相反；
    金属电极，形成于所述JFET源极上并与所述JFET源极接触；
    JFET金属栅极，设于所述JFET源极两侧的所述第一阱上；及
    第一钳位区，位于所述JFET金属栅极的下方、所述第一阱内，为第二导电类型且其离子浓度大于所述第一阱的离子浓度。
  2. 根据权利要求1所述的器件，其特征在于，还包括隔离阱，位于所述JFET区和功率器件区交界处，用于将所述JFET区和功率器件区隔离。
  3. 根据权利要求1所述的器件，其特征在于，所述JFET区形成有：
    沟槽，所述沟槽的内壁覆盖有氧化硅，所述JFET金属栅极填充于覆盖有所述氧化硅的沟槽内；及
    欧姆接触区，形成于第一阱内的与所述沟槽的底部接触处，具有第二导电类型，且与所述JFET金属栅极相接触。
  4. 根据权利要求1所述的器件，其特征在于，所述器件是VDMOS。
  5. 根据权利要求4所述的器件，其特征在于，所述功率器件区形成有：
    栅极；
    第二阱，具有第二导电类型；
    VDMOS源极，具有第一导电类型，设于所述第二阱内；及
    第二钳位区，设于所述第二阱的底部。
  6. 根据权利要求5所述的器件，其特征在于，各所述第二阱内形成有沟槽，各第二阱内与所述沟槽的底部接触处形成有第二导电类型的欧姆接触区，所述器件还包括VDMOS源极的金属接触，所述VDMOS源极的金属接触填充于所述功率器件区的沟槽内、贯穿所述VDMOS源极并延伸至所述欧姆接触区，所述欧姆接触区的离子浓度大于所述第二阱的离子浓度。
  7. 根据权利要求6所述的器件，其特征在于，在所述功率器件区的第二阱内，所述VDMOS源极和所述欧姆接触区之间还形成有第二导电类型的非钳位感性开关区，所述非钳位感性开关区的离子浓度大于所述第二阱的离子浓度。
  8. 根据权利要求1所述的器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
  9. 一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：
    提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；
    向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；
    在所述第一导电类型区的表面先后生长场氧层和栅氧层，在所述第一导电类型区表面形成多晶硅层，向所述功率器件区的所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱；
    向所述功率器件区的第二阱中注入第一导电类型的离子，形成功率器件源极；
    向所述JFET区的两相邻第二阱之间注入第一导电类型的离子，形成JFET源极；
    光刻并刻蚀接触孔，向所述接触孔内注入第二导电类型的离子，在所述第一阱内以及所述第二阱底部形成钳位区，所述钳位区的离子浓度大于所述 第一阱的离子浓度；及
    淀积金属层并填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
  10. 根据权利要求9所述的方法，其特征在于，所述在所述第一导电类型区内形成隔离阱的步骤，包括在所述JFET区和功率器件区交界处形成隔离阱，作为JFET区和功率器件区的隔离。
  11. 根据权利要求9所述的方法，其特征在于，所述向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱的步骤中，是以所述场氧层和多晶硅层为掩膜进行注入。
  12. 根据权利要求11所述的方法，其特征在于，所述形成功率器件源极的步骤和所述形成JFET源极的步骤之间，还包括步骤：
    形成注入阻挡层，所述场氧层和多晶硅层的表面也叠加上所述注入阻挡层；及
    向所述功率器件区的所述第二阱中注入第二导电类型的离子，以在所述第二阱内所述功率器件源极的下方形成非钳位感性开关区，注入能量大于所述向所述功率器件区的第二阱中注入第一导电类型的离子的步骤的注入能量，叠加有所述注入阻挡层的场氧层和多晶硅层将注入的第二导电类型的离子阻挡。
  13. 根据权利要求9所述的方法，其特征在于，所述光刻并刻蚀接触孔的步骤之前，还包括步骤：
    在各所述第一阱和各所述第二阱内刻蚀出沟槽；其中，所述JFET金属栅极由填入所述第一阱内的沟槽的金属层形成，所述功率器件源极的金属接触由填入所述第二阱内的沟槽的金属层形成。
  14. 根据权利要求13所述的方法，其特征在于，所述在各所述第二阱内刻蚀出沟槽的步骤之后，所述方法还包括：向所述沟槽注入第二导电类型的离子，在每一第二阱内与所述沟槽的底部接触处，以及在每一第一阱内与所述沟槽的底部接触处形成第二导电类型的欧姆接触区。
  15. 根据权利要求14所述的方法，其特征在于，还包括再次注入第二导电类型的离子，在所述第二阱的底部、以及所述JFET源极两侧的第一阱内形成第二导电类型的钳位区的步骤。
  16. 根据权利要求15所述的方法，其特征在于，所述再次注入第二导电类型的离子的步骤中注入能量为480keV。
  17. 根据权利要求9所述的方法，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
  18. 根据权利要求9所述的方法，其特征在于，所述器件是VDMOS。
  19. 根据权利要求9所述的方法，其特征在于，所述向第一导电类型区中注入第二导电类型的离子并推阱的步骤，注入浓度为1.5E13cm-2～2.2E13cm-2；
    所述在所述第一导电类型区内形成第一阱的步骤，形成的所述第一阱的阱深为8.5微米～13.5微米。
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